Ray Jui | 61ca7b0 | 2015-05-05 11:13:21 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2014 Broadcom Corporation |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License as |
| 6 | * published by the Free Software Foundation version 2. |
| 7 | * |
| 8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 9 | * kind, whether express or implied; without even the implied warranty |
| 10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/clk-provider.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/of.h> |
| 19 | #include <linux/clkdev.h> |
| 20 | #include <linux/of_address.h> |
| 21 | #include <linux/delay.h> |
| 22 | |
| 23 | #include <dt-bindings/clock/bcm-cygnus.h> |
| 24 | #include "clk-iproc.h" |
| 25 | |
| 26 | #define reg_val(o, s, w) { .offset = o, .shift = s, .width = w, } |
| 27 | |
| 28 | #define aon_val(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ |
| 29 | .pwr_shift = ps, .iso_shift = is } |
| 30 | |
| 31 | #define sw_ctrl_val(o, s) { .offset = o, .shift = s, } |
| 32 | |
| 33 | #define asiu_div_val(o, es, hs, hw, ls, lw) \ |
| 34 | { .offset = o, .en_shift = es, .high_shift = hs, \ |
| 35 | .high_width = hw, .low_shift = ls, .low_width = lw } |
| 36 | |
| 37 | #define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ |
| 38 | .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ |
| 39 | .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ |
| 40 | .ka_width = kaw } |
| 41 | |
| 42 | #define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo } |
| 43 | |
| 44 | #define enable_val(o, es, hs, bs) { .offset = o, .enable_shift = es, \ |
| 45 | .hold_shift = hs, .bypass_shift = bs } |
| 46 | |
| 47 | #define asiu_gate_val(o, es) { .offset = o, .en_shift = es } |
| 48 | |
| 49 | static void __init cygnus_armpll_init(struct device_node *node) |
| 50 | { |
| 51 | iproc_armpll_setup(node); |
| 52 | } |
| 53 | CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init); |
| 54 | |
| 55 | static const struct iproc_pll_ctrl genpll = { |
| 56 | .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | |
| 57 | IPROC_CLK_PLL_NEEDS_SW_CFG, |
| 58 | .aon = aon_val(0x0, 2, 1, 0), |
| 59 | .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3), |
| 60 | .sw_ctrl = sw_ctrl_val(0x10, 31), |
| 61 | .ndiv_int = reg_val(0x10, 20, 10), |
| 62 | .ndiv_frac = reg_val(0x10, 0, 20), |
| 63 | .pdiv = reg_val(0x14, 0, 4), |
| 64 | .vco_ctrl = vco_ctrl_val(0x18, 0x1c), |
| 65 | .status = reg_val(0x28, 12, 1), |
| 66 | }; |
| 67 | |
| 68 | static const struct iproc_clk_ctrl genpll_clk[] = { |
| 69 | [BCM_CYGNUS_GENPLL_AXI21_CLK] = { |
| 70 | .channel = BCM_CYGNUS_GENPLL_AXI21_CLK, |
| 71 | .flags = IPROC_CLK_AON, |
| 72 | .enable = enable_val(0x4, 6, 0, 12), |
| 73 | .mdiv = reg_val(0x20, 0, 8), |
| 74 | }, |
| 75 | [BCM_CYGNUS_GENPLL_250MHZ_CLK] = { |
| 76 | .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK, |
| 77 | .flags = IPROC_CLK_AON, |
| 78 | .enable = enable_val(0x4, 7, 1, 13), |
| 79 | .mdiv = reg_val(0x20, 10, 8), |
| 80 | }, |
| 81 | [BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = { |
| 82 | .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK, |
| 83 | .flags = IPROC_CLK_AON, |
| 84 | .enable = enable_val(0x4, 8, 2, 14), |
| 85 | .mdiv = reg_val(0x20, 20, 8), |
| 86 | }, |
| 87 | [BCM_CYGNUS_GENPLL_ENET_SW_CLK] = { |
| 88 | .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK, |
| 89 | .flags = IPROC_CLK_AON, |
| 90 | .enable = enable_val(0x4, 9, 3, 15), |
| 91 | .mdiv = reg_val(0x24, 0, 8), |
| 92 | }, |
| 93 | [BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = { |
| 94 | .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK, |
| 95 | .flags = IPROC_CLK_AON, |
| 96 | .enable = enable_val(0x4, 10, 4, 16), |
| 97 | .mdiv = reg_val(0x24, 10, 8), |
| 98 | }, |
| 99 | [BCM_CYGNUS_GENPLL_CAN_CLK] = { |
| 100 | .channel = BCM_CYGNUS_GENPLL_CAN_CLK, |
| 101 | .flags = IPROC_CLK_AON, |
| 102 | .enable = enable_val(0x4, 11, 5, 17), |
| 103 | .mdiv = reg_val(0x24, 20, 8), |
| 104 | }, |
| 105 | }; |
| 106 | |
| 107 | static void __init cygnus_genpll_clk_init(struct device_node *node) |
| 108 | { |
| 109 | iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk, |
| 110 | ARRAY_SIZE(genpll_clk)); |
| 111 | } |
| 112 | CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init); |
| 113 | |
| 114 | static const struct iproc_pll_ctrl lcpll0 = { |
| 115 | .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG, |
| 116 | .aon = aon_val(0x0, 2, 5, 4), |
| 117 | .reset = reset_val(0x0, 31, 30, 27, 3, 23, 4, 19, 4), |
| 118 | .sw_ctrl = sw_ctrl_val(0x4, 31), |
| 119 | .ndiv_int = reg_val(0x4, 16, 10), |
| 120 | .pdiv = reg_val(0x4, 26, 4), |
| 121 | .vco_ctrl = vco_ctrl_val(0x10, 0x14), |
| 122 | .status = reg_val(0x18, 12, 1), |
| 123 | }; |
| 124 | |
| 125 | static const struct iproc_clk_ctrl lcpll0_clk[] = { |
| 126 | [BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK] = { |
| 127 | .channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK, |
| 128 | .flags = IPROC_CLK_AON, |
| 129 | .enable = enable_val(0x0, 7, 1, 13), |
| 130 | .mdiv = reg_val(0x8, 0, 8), |
| 131 | }, |
| 132 | [BCM_CYGNUS_LCPLL0_DDR_PHY_CLK] = { |
| 133 | .channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK, |
| 134 | .flags = IPROC_CLK_AON, |
| 135 | .enable = enable_val(0x0, 8, 2, 14), |
| 136 | .mdiv = reg_val(0x8, 10, 8), |
| 137 | }, |
| 138 | [BCM_CYGNUS_LCPLL0_SDIO_CLK] = { |
| 139 | .channel = BCM_CYGNUS_LCPLL0_SDIO_CLK, |
| 140 | .flags = IPROC_CLK_AON, |
| 141 | .enable = enable_val(0x0, 9, 3, 15), |
| 142 | .mdiv = reg_val(0x8, 20, 8), |
| 143 | }, |
| 144 | [BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK] = { |
| 145 | .channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK, |
| 146 | .flags = IPROC_CLK_AON, |
| 147 | .enable = enable_val(0x0, 10, 4, 16), |
| 148 | .mdiv = reg_val(0xc, 0, 8), |
| 149 | }, |
| 150 | [BCM_CYGNUS_LCPLL0_SMART_CARD_CLK] = { |
| 151 | .channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK, |
| 152 | .flags = IPROC_CLK_AON, |
| 153 | .enable = enable_val(0x0, 11, 5, 17), |
| 154 | .mdiv = reg_val(0xc, 10, 8), |
| 155 | }, |
| 156 | [BCM_CYGNUS_LCPLL0_CH5_UNUSED] = { |
| 157 | .channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED, |
| 158 | .flags = IPROC_CLK_AON, |
| 159 | .enable = enable_val(0x0, 12, 6, 18), |
| 160 | .mdiv = reg_val(0xc, 20, 8), |
| 161 | }, |
| 162 | }; |
| 163 | |
| 164 | static void __init cygnus_lcpll0_clk_init(struct device_node *node) |
| 165 | { |
| 166 | iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk, |
| 167 | ARRAY_SIZE(lcpll0_clk)); |
| 168 | } |
| 169 | CLK_OF_DECLARE(cygnus_lcpll0, "brcm,cygnus-lcpll0", cygnus_lcpll0_clk_init); |
| 170 | |
| 171 | /* |
| 172 | * MIPI PLL VCO frequency parameter table |
| 173 | */ |
| 174 | static const struct iproc_pll_vco_param mipipll_vco_params[] = { |
| 175 | /* rate (Hz) ndiv_int ndiv_frac pdiv */ |
| 176 | { 750000000UL, 30, 0, 1 }, |
| 177 | { 1000000000UL, 40, 0, 1 }, |
| 178 | { 1350000000ul, 54, 0, 1 }, |
| 179 | { 2000000000UL, 80, 0, 1 }, |
| 180 | { 2100000000UL, 84, 0, 1 }, |
| 181 | { 2250000000UL, 90, 0, 1 }, |
| 182 | { 2500000000UL, 100, 0, 1 }, |
| 183 | { 2700000000UL, 54, 0, 0 }, |
| 184 | { 2975000000UL, 119, 0, 1 }, |
| 185 | { 3100000000UL, 124, 0, 1 }, |
| 186 | { 3150000000UL, 126, 0, 1 }, |
| 187 | }; |
| 188 | |
| 189 | static const struct iproc_pll_ctrl mipipll = { |
| 190 | .flags = IPROC_CLK_PLL_ASIU | IPROC_CLK_PLL_HAS_NDIV_FRAC | |
| 191 | IPROC_CLK_NEEDS_READ_BACK, |
| 192 | .aon = aon_val(0x0, 4, 17, 16), |
| 193 | .asiu = asiu_gate_val(0x0, 3), |
| 194 | .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 4), |
| 195 | .ndiv_int = reg_val(0x10, 20, 10), |
| 196 | .ndiv_frac = reg_val(0x10, 0, 20), |
| 197 | .pdiv = reg_val(0x14, 0, 4), |
| 198 | .vco_ctrl = vco_ctrl_val(0x18, 0x1c), |
| 199 | .status = reg_val(0x28, 12, 1), |
| 200 | }; |
| 201 | |
| 202 | static const struct iproc_clk_ctrl mipipll_clk[] = { |
| 203 | [BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = { |
| 204 | .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED, |
| 205 | .flags = IPROC_CLK_NEEDS_READ_BACK, |
| 206 | .enable = enable_val(0x4, 12, 6, 18), |
| 207 | .mdiv = reg_val(0x20, 0, 8), |
| 208 | }, |
| 209 | [BCM_CYGNUS_MIPIPLL_CH1_LCD] = { |
| 210 | .channel = BCM_CYGNUS_MIPIPLL_CH1_LCD, |
| 211 | .flags = IPROC_CLK_NEEDS_READ_BACK, |
| 212 | .enable = enable_val(0x4, 13, 7, 19), |
| 213 | .mdiv = reg_val(0x20, 10, 8), |
| 214 | }, |
| 215 | [BCM_CYGNUS_MIPIPLL_CH2_V3D] = { |
| 216 | .channel = BCM_CYGNUS_MIPIPLL_CH2_V3D, |
| 217 | .flags = IPROC_CLK_NEEDS_READ_BACK, |
| 218 | .enable = enable_val(0x4, 14, 8, 20), |
| 219 | .mdiv = reg_val(0x20, 20, 8), |
| 220 | }, |
| 221 | [BCM_CYGNUS_MIPIPLL_CH3_UNUSED] = { |
| 222 | .channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED, |
| 223 | .flags = IPROC_CLK_NEEDS_READ_BACK, |
| 224 | .enable = enable_val(0x4, 15, 9, 21), |
| 225 | .mdiv = reg_val(0x24, 0, 8), |
| 226 | }, |
| 227 | [BCM_CYGNUS_MIPIPLL_CH4_UNUSED] = { |
| 228 | .channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED, |
| 229 | .flags = IPROC_CLK_NEEDS_READ_BACK, |
| 230 | .enable = enable_val(0x4, 16, 10, 22), |
| 231 | .mdiv = reg_val(0x24, 10, 8), |
| 232 | }, |
| 233 | [BCM_CYGNUS_MIPIPLL_CH5_UNUSED] = { |
| 234 | .channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED, |
| 235 | .flags = IPROC_CLK_NEEDS_READ_BACK, |
| 236 | .enable = enable_val(0x4, 17, 11, 23), |
| 237 | .mdiv = reg_val(0x24, 20, 8), |
| 238 | }, |
| 239 | }; |
| 240 | |
| 241 | static void __init cygnus_mipipll_clk_init(struct device_node *node) |
| 242 | { |
| 243 | iproc_pll_clk_setup(node, &mipipll, mipipll_vco_params, |
| 244 | ARRAY_SIZE(mipipll_vco_params), mipipll_clk, |
| 245 | ARRAY_SIZE(mipipll_clk)); |
| 246 | } |
| 247 | CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init); |
| 248 | |
| 249 | static const struct iproc_asiu_div asiu_div[] = { |
| 250 | [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_div_val(0x0, 31, 16, 10, 0, 10), |
| 251 | [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_div_val(0x4, 31, 16, 10, 0, 10), |
| 252 | [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_div_val(0x8, 31, 16, 10, 0, 10), |
| 253 | }; |
| 254 | |
| 255 | static const struct iproc_asiu_gate asiu_gate[] = { |
| 256 | [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_gate_val(0x0, 7), |
| 257 | [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_gate_val(0x0, 9), |
| 258 | [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_gate_val(IPROC_CLK_INVALID_OFFSET, 0), |
| 259 | }; |
| 260 | |
| 261 | static void __init cygnus_asiu_init(struct device_node *node) |
| 262 | { |
| 263 | iproc_asiu_setup(node, asiu_div, asiu_gate, ARRAY_SIZE(asiu_div)); |
| 264 | } |
| 265 | CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init); |