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Gabor Juhosd4a67d92011-01-04 21:28:14 +01001/*
2 * Atheros AR71XX/AR724X/AR913X common routines
3 *
Gabor Juhos88896122012-03-14 10:45:22 +01004 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
Gabor Juhosd4a67d92011-01-04 21:28:14 +01005 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
6 *
Gabor Juhos88896122012-03-14 10:45:22 +01007 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
8 *
Gabor Juhosd4a67d92011-01-04 21:28:14 +01009 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/err.h>
18#include <linux/clk.h>
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020019#include <linux/clkdev.h>
Gabor Juhosd4a67d92011-01-04 21:28:14 +010020
Gabor Juhos97541cc2012-09-08 14:02:21 +020021#include <asm/div64.h>
22
Gabor Juhosd4a67d92011-01-04 21:28:14 +010023#include <asm/mach-ath79/ath79.h>
24#include <asm/mach-ath79/ar71xx_regs.h>
25#include "common.h"
26
27#define AR71XX_BASE_FREQ 40000000
28#define AR724X_BASE_FREQ 5000000
29#define AR913X_BASE_FREQ 5000000
30
31struct clk {
32 unsigned long rate;
33};
34
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020035static void __init ath79_add_sys_clkdev(const char *id, unsigned long rate)
36{
37 struct clk *clk;
38 int err;
39
40 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
41 if (!clk)
42 panic("failed to allocate %s clock structure", id);
43
44 clk->rate = rate;
45
46 err = clk_register_clkdev(clk, id, NULL);
47 if (err)
48 panic("unable to register %s clock device", id);
49}
Gabor Juhosd4a67d92011-01-04 21:28:14 +010050
51static void __init ar71xx_clocks_init(void)
52{
Gabor Juhos6612a682013-08-28 10:41:46 +020053 unsigned long ref_rate;
54 unsigned long cpu_rate;
55 unsigned long ddr_rate;
56 unsigned long ahb_rate;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010057 u32 pll;
58 u32 freq;
59 u32 div;
60
Gabor Juhos6612a682013-08-28 10:41:46 +020061 ref_rate = AR71XX_BASE_FREQ;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010062
63 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
64
Alban Bedel626a0692015-04-19 14:30:02 +020065 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +020066 freq = div * ref_rate;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010067
68 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +020069 cpu_rate = freq / div;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010070
71 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +020072 ddr_rate = freq / div;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010073
74 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
Gabor Juhos6612a682013-08-28 10:41:46 +020075 ahb_rate = cpu_rate / div;
76
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020077 ath79_add_sys_clkdev("ref", ref_rate);
78 ath79_add_sys_clkdev("cpu", cpu_rate);
79 ath79_add_sys_clkdev("ddr", ddr_rate);
80 ath79_add_sys_clkdev("ahb", ahb_rate);
Gabor Juhosd4a67d92011-01-04 21:28:14 +010081
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020082 clk_add_alias("wdt", NULL, "ahb", NULL);
83 clk_add_alias("uart", NULL, "ahb", NULL);
Gabor Juhosd4a67d92011-01-04 21:28:14 +010084}
85
86static void __init ar724x_clocks_init(void)
87{
Gabor Juhos6612a682013-08-28 10:41:46 +020088 unsigned long ref_rate;
89 unsigned long cpu_rate;
90 unsigned long ddr_rate;
91 unsigned long ahb_rate;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010092 u32 pll;
93 u32 freq;
94 u32 div;
95
Gabor Juhos6612a682013-08-28 10:41:46 +020096 ref_rate = AR724X_BASE_FREQ;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010097 pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
98
Alban Bedel626a0692015-04-19 14:30:02 +020099 div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
Gabor Juhos6612a682013-08-28 10:41:46 +0200100 freq = div * ref_rate;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100101
102 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
103 freq *= div;
104
Gabor Juhos6612a682013-08-28 10:41:46 +0200105 cpu_rate = freq;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100106
107 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +0200108 ddr_rate = freq / div;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100109
110 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
Gabor Juhos6612a682013-08-28 10:41:46 +0200111 ahb_rate = cpu_rate / div;
112
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200113 ath79_add_sys_clkdev("ref", ref_rate);
114 ath79_add_sys_clkdev("cpu", cpu_rate);
115 ath79_add_sys_clkdev("ddr", ddr_rate);
116 ath79_add_sys_clkdev("ahb", ahb_rate);
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100117
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200118 clk_add_alias("wdt", NULL, "ahb", NULL);
119 clk_add_alias("uart", NULL, "ahb", NULL);
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100120}
121
122static void __init ar913x_clocks_init(void)
123{
Gabor Juhos6612a682013-08-28 10:41:46 +0200124 unsigned long ref_rate;
125 unsigned long cpu_rate;
126 unsigned long ddr_rate;
127 unsigned long ahb_rate;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100128 u32 pll;
129 u32 freq;
130 u32 div;
131
Gabor Juhos6612a682013-08-28 10:41:46 +0200132 ref_rate = AR913X_BASE_FREQ;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100133 pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
134
Alban Bedel626a0692015-04-19 14:30:02 +0200135 div = ((pll >> AR913X_PLL_FB_SHIFT) & AR913X_PLL_FB_MASK);
Gabor Juhos6612a682013-08-28 10:41:46 +0200136 freq = div * ref_rate;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100137
Gabor Juhos6612a682013-08-28 10:41:46 +0200138 cpu_rate = freq;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100139
140 div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +0200141 ddr_rate = freq / div;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100142
143 div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
Gabor Juhos6612a682013-08-28 10:41:46 +0200144 ahb_rate = cpu_rate / div;
145
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200146 ath79_add_sys_clkdev("ref", ref_rate);
147 ath79_add_sys_clkdev("cpu", cpu_rate);
148 ath79_add_sys_clkdev("ddr", ddr_rate);
149 ath79_add_sys_clkdev("ahb", ahb_rate);
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100150
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200151 clk_add_alias("wdt", NULL, "ahb", NULL);
152 clk_add_alias("uart", NULL, "ahb", NULL);
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100153}
154
Gabor Juhos04225e12011-06-20 21:26:04 +0200155static void __init ar933x_clocks_init(void)
156{
Gabor Juhos6612a682013-08-28 10:41:46 +0200157 unsigned long ref_rate;
158 unsigned long cpu_rate;
159 unsigned long ddr_rate;
160 unsigned long ahb_rate;
Gabor Juhos04225e12011-06-20 21:26:04 +0200161 u32 clock_ctrl;
162 u32 cpu_config;
163 u32 freq;
164 u32 t;
165
166 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
167 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
Gabor Juhos6612a682013-08-28 10:41:46 +0200168 ref_rate = (40 * 1000 * 1000);
Gabor Juhos04225e12011-06-20 21:26:04 +0200169 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200170 ref_rate = (25 * 1000 * 1000);
Gabor Juhos04225e12011-06-20 21:26:04 +0200171
172 clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
173 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
Gabor Juhos6612a682013-08-28 10:41:46 +0200174 cpu_rate = ref_rate;
175 ahb_rate = ref_rate;
176 ddr_rate = ref_rate;
Gabor Juhos04225e12011-06-20 21:26:04 +0200177 } else {
178 cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
179
180 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
181 AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
Gabor Juhos6612a682013-08-28 10:41:46 +0200182 freq = ref_rate / t;
Gabor Juhos04225e12011-06-20 21:26:04 +0200183
184 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
185 AR933X_PLL_CPU_CONFIG_NINT_MASK;
186 freq *= t;
187
188 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
189 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
190 if (t == 0)
191 t = 1;
192
193 freq >>= t;
194
195 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
196 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +0200197 cpu_rate = freq / t;
Gabor Juhos04225e12011-06-20 21:26:04 +0200198
199 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
200 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +0200201 ddr_rate = freq / t;
Gabor Juhos04225e12011-06-20 21:26:04 +0200202
203 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
204 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +0200205 ahb_rate = freq / t;
Gabor Juhos04225e12011-06-20 21:26:04 +0200206 }
207
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200208 ath79_add_sys_clkdev("ref", ref_rate);
209 ath79_add_sys_clkdev("cpu", cpu_rate);
210 ath79_add_sys_clkdev("ddr", ddr_rate);
211 ath79_add_sys_clkdev("ahb", ahb_rate);
Gabor Juhos6612a682013-08-28 10:41:46 +0200212
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200213 clk_add_alias("wdt", NULL, "ahb", NULL);
214 clk_add_alias("uart", NULL, "ref", NULL);
Gabor Juhos04225e12011-06-20 21:26:04 +0200215}
216
Gabor Juhos97541cc2012-09-08 14:02:21 +0200217static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
218 u32 frac, u32 out_div)
219{
220 u64 t;
221 u32 ret;
222
Gabor Juhos837f0362013-08-28 10:41:43 +0200223 t = ref;
Gabor Juhos97541cc2012-09-08 14:02:21 +0200224 t *= nint;
225 do_div(t, ref_div);
226 ret = t;
227
Gabor Juhos837f0362013-08-28 10:41:43 +0200228 t = ref;
Gabor Juhos97541cc2012-09-08 14:02:21 +0200229 t *= nfrac;
230 do_div(t, ref_div * frac);
231 ret += t;
232
233 ret /= (1 << out_div);
234 return ret;
235}
236
Gabor Juhos88896122012-03-14 10:45:22 +0100237static void __init ar934x_clocks_init(void)
238{
Gabor Juhos6612a682013-08-28 10:41:46 +0200239 unsigned long ref_rate;
240 unsigned long cpu_rate;
241 unsigned long ddr_rate;
242 unsigned long ahb_rate;
Gabor Juhos97541cc2012-09-08 14:02:21 +0200243 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
Gabor Juhos88896122012-03-14 10:45:22 +0100244 u32 cpu_pll, ddr_pll;
245 u32 bootstrap;
Gabor Juhos97541cc2012-09-08 14:02:21 +0200246 void __iomem *dpll_base;
247
248 dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
Gabor Juhos88896122012-03-14 10:45:22 +0100249
250 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
Ralf Baechle70342282013-01-22 12:59:30 +0100251 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
Gabor Juhos6612a682013-08-28 10:41:46 +0200252 ref_rate = 40 * 1000 * 1000;
Gabor Juhos88896122012-03-14 10:45:22 +0100253 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200254 ref_rate = 25 * 1000 * 1000;
Gabor Juhos88896122012-03-14 10:45:22 +0100255
Gabor Juhos97541cc2012-09-08 14:02:21 +0200256 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
257 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
258 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
259 AR934X_SRIF_DPLL2_OUTDIV_MASK;
260 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
261 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
262 AR934X_SRIF_DPLL1_NINT_MASK;
263 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
264 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
265 AR934X_SRIF_DPLL1_REFDIV_MASK;
266 frac = 1 << 18;
267 } else {
268 pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
269 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
270 AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
271 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
272 AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
273 nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
274 AR934X_PLL_CPU_CONFIG_NINT_MASK;
275 nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
276 AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
277 frac = 1 << 6;
278 }
Gabor Juhos88896122012-03-14 10:45:22 +0100279
Gabor Juhos6612a682013-08-28 10:41:46 +0200280 cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
Gabor Juhos97541cc2012-09-08 14:02:21 +0200281 nfrac, frac, out_div);
Gabor Juhos88896122012-03-14 10:45:22 +0100282
Gabor Juhos97541cc2012-09-08 14:02:21 +0200283 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
284 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
285 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
286 AR934X_SRIF_DPLL2_OUTDIV_MASK;
287 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
288 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
289 AR934X_SRIF_DPLL1_NINT_MASK;
290 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
291 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
292 AR934X_SRIF_DPLL1_REFDIV_MASK;
293 frac = 1 << 18;
294 } else {
295 pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
296 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
297 AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
298 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
299 AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
300 nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
301 AR934X_PLL_DDR_CONFIG_NINT_MASK;
302 nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
303 AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
304 frac = 1 << 10;
305 }
Gabor Juhos88896122012-03-14 10:45:22 +0100306
Gabor Juhos6612a682013-08-28 10:41:46 +0200307 ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
Gabor Juhos97541cc2012-09-08 14:02:21 +0200308 nfrac, frac, out_div);
Gabor Juhos88896122012-03-14 10:45:22 +0100309
310 clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
311
312 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
313 AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
314
315 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200316 cpu_rate = ref_rate;
Gabor Juhos88896122012-03-14 10:45:22 +0100317 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200318 cpu_rate = cpu_pll / (postdiv + 1);
Gabor Juhos88896122012-03-14 10:45:22 +0100319 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200320 cpu_rate = ddr_pll / (postdiv + 1);
Gabor Juhos88896122012-03-14 10:45:22 +0100321
322 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
323 AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
324
325 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200326 ddr_rate = ref_rate;
Gabor Juhos88896122012-03-14 10:45:22 +0100327 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200328 ddr_rate = ddr_pll / (postdiv + 1);
Gabor Juhos88896122012-03-14 10:45:22 +0100329 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200330 ddr_rate = cpu_pll / (postdiv + 1);
Gabor Juhos88896122012-03-14 10:45:22 +0100331
332 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
333 AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
334
335 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200336 ahb_rate = ref_rate;
Gabor Juhos88896122012-03-14 10:45:22 +0100337 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200338 ahb_rate = ddr_pll / (postdiv + 1);
Gabor Juhos88896122012-03-14 10:45:22 +0100339 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200340 ahb_rate = cpu_pll / (postdiv + 1);
341
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200342 ath79_add_sys_clkdev("ref", ref_rate);
343 ath79_add_sys_clkdev("cpu", cpu_rate);
344 ath79_add_sys_clkdev("ddr", ddr_rate);
345 ath79_add_sys_clkdev("ahb", ahb_rate);
Gabor Juhos88896122012-03-14 10:45:22 +0100346
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200347 clk_add_alias("wdt", NULL, "ref", NULL);
348 clk_add_alias("uart", NULL, "ref", NULL);
Gabor Juhos97541cc2012-09-08 14:02:21 +0200349
350 iounmap(dpll_base);
Gabor Juhos88896122012-03-14 10:45:22 +0100351}
352
Gabor Juhos41583c02013-02-15 13:38:17 +0000353static void __init qca955x_clocks_init(void)
354{
Gabor Juhos6612a682013-08-28 10:41:46 +0200355 unsigned long ref_rate;
356 unsigned long cpu_rate;
357 unsigned long ddr_rate;
358 unsigned long ahb_rate;
Gabor Juhos41583c02013-02-15 13:38:17 +0000359 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
360 u32 cpu_pll, ddr_pll;
361 u32 bootstrap;
362
363 bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
364 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
Gabor Juhos6612a682013-08-28 10:41:46 +0200365 ref_rate = 40 * 1000 * 1000;
Gabor Juhos41583c02013-02-15 13:38:17 +0000366 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200367 ref_rate = 25 * 1000 * 1000;
Gabor Juhos41583c02013-02-15 13:38:17 +0000368
369 pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
370 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
371 QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
372 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
373 QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
374 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
375 QCA955X_PLL_CPU_CONFIG_NINT_MASK;
376 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
377 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
378
Gabor Juhos6612a682013-08-28 10:41:46 +0200379 cpu_pll = nint * ref_rate / ref_div;
380 cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
Gabor Juhos41583c02013-02-15 13:38:17 +0000381 cpu_pll /= (1 << out_div);
382
383 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
384 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
385 QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
386 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
387 QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
388 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
389 QCA955X_PLL_DDR_CONFIG_NINT_MASK;
390 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
391 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
392
Gabor Juhos6612a682013-08-28 10:41:46 +0200393 ddr_pll = nint * ref_rate / ref_div;
394 ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
Gabor Juhos41583c02013-02-15 13:38:17 +0000395 ddr_pll /= (1 << out_div);
396
397 clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
398
399 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
400 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
401
402 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200403 cpu_rate = ref_rate;
Gabor Juhos41583c02013-02-15 13:38:17 +0000404 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200405 cpu_rate = ddr_pll / (postdiv + 1);
Gabor Juhos41583c02013-02-15 13:38:17 +0000406 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200407 cpu_rate = cpu_pll / (postdiv + 1);
Gabor Juhos41583c02013-02-15 13:38:17 +0000408
409 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
410 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
411
412 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200413 ddr_rate = ref_rate;
Gabor Juhos41583c02013-02-15 13:38:17 +0000414 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200415 ddr_rate = cpu_pll / (postdiv + 1);
Gabor Juhos41583c02013-02-15 13:38:17 +0000416 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200417 ddr_rate = ddr_pll / (postdiv + 1);
Gabor Juhos41583c02013-02-15 13:38:17 +0000418
419 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
420 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
421
422 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200423 ahb_rate = ref_rate;
Gabor Juhos41583c02013-02-15 13:38:17 +0000424 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200425 ahb_rate = ddr_pll / (postdiv + 1);
Gabor Juhos41583c02013-02-15 13:38:17 +0000426 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200427 ahb_rate = cpu_pll / (postdiv + 1);
428
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200429 ath79_add_sys_clkdev("ref", ref_rate);
430 ath79_add_sys_clkdev("cpu", cpu_rate);
431 ath79_add_sys_clkdev("ddr", ddr_rate);
432 ath79_add_sys_clkdev("ahb", ahb_rate);
Gabor Juhos41583c02013-02-15 13:38:17 +0000433
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200434 clk_add_alias("wdt", NULL, "ref", NULL);
435 clk_add_alias("uart", NULL, "ref", NULL);
Gabor Juhos41583c02013-02-15 13:38:17 +0000436}
437
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100438void __init ath79_clocks_init(void)
439{
440 if (soc_is_ar71xx())
441 ar71xx_clocks_init();
442 else if (soc_is_ar724x())
443 ar724x_clocks_init();
444 else if (soc_is_ar913x())
445 ar913x_clocks_init();
Gabor Juhos04225e12011-06-20 21:26:04 +0200446 else if (soc_is_ar933x())
447 ar933x_clocks_init();
Gabor Juhos88896122012-03-14 10:45:22 +0100448 else if (soc_is_ar934x())
449 ar934x_clocks_init();
Gabor Juhos41583c02013-02-15 13:38:17 +0000450 else if (soc_is_qca955x())
451 qca955x_clocks_init();
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100452 else
453 BUG();
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100454}
455
Gabor Juhos23107802013-08-28 10:41:44 +0200456unsigned long __init
457ath79_get_sys_clk_rate(const char *id)
458{
459 struct clk *clk;
460 unsigned long rate;
461
462 clk = clk_get(NULL, id);
463 if (IS_ERR(clk))
464 panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
465
466 rate = clk_get_rate(clk);
467 clk_put(clk);
468
469 return rate;
470}
471
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100472/*
473 * Linux clock API
474 */
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100475int clk_enable(struct clk *clk)
476{
477 return 0;
478}
479EXPORT_SYMBOL(clk_enable);
480
481void clk_disable(struct clk *clk)
482{
483}
484EXPORT_SYMBOL(clk_disable);
485
486unsigned long clk_get_rate(struct clk *clk)
487{
488 return clk->rate;
489}
490EXPORT_SYMBOL(clk_get_rate);