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gerrit-public.fairphone.software / kernel / msm-4.9 / 636e97b0fb0a063dc89773b13064647f5da632cb / . / sound / soc / codecs / max98088.c
blob: ee660e2d3df3ba0ced0587ee13bab59fc86de6f9 [file] [log] [blame]
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1/*
2 * max98088.c -- MAX98088 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]18#include <linux/regmap.h>
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]19#include <sound/core.h>
20#include <sound/pcm.h>
21#include <sound/pcm_params.h>
22#include <sound/soc.h>
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]23#include <sound/initval.h>
24#include <sound/tlv.h>
25#include <linux/slab.h>
26#include <asm/div64.h>
27#include <sound/max98088.h>
28#include "max98088.h"
29
Jesse Marroquinfb762a52010-11-17 14:26:40 -0600[diff] [blame]30enum max98088_type {
31 MAX98088,
32 MAX98089,
33};
34
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]35struct max98088_cdata {
36 unsigned int rate;
37 unsigned int fmt;
38 int eq_sel;
39};
40
41struct max98088_priv {
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]42 struct regmap *regmap;
Mark Brown356d86e2013-09-23 17:22:17 +0100[diff] [blame]43 enum max98088_type devtype;
44 struct max98088_pdata *pdata;
45 unsigned int sysclk;
46 struct max98088_cdata dai[2];
47 int eq_textcnt;
48 const char **eq_texts;
49 struct soc_enum eq_enum;
50 u8 ina_state;
51 u8 inb_state;
52 unsigned int ex_mode;
53 unsigned int digmic;
54 unsigned int mic1pre;
55 unsigned int mic2pre;
56 unsigned int extmic_mode;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]57};
58
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]59static const struct reg_default max98088_reg[] = {
60 { 0xf, 0x00 }, /* 0F interrupt enable */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]61
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]62 { 0x10, 0x00 }, /* 10 master clock */
63 { 0x11, 0x00 }, /* 11 DAI1 clock mode */
64 { 0x12, 0x00 }, /* 12 DAI1 clock control */
65 { 0x13, 0x00 }, /* 13 DAI1 clock control */
66 { 0x14, 0x00 }, /* 14 DAI1 format */
67 { 0x15, 0x00 }, /* 15 DAI1 clock */
68 { 0x16, 0x00 }, /* 16 DAI1 config */
69 { 0x17, 0x00 }, /* 17 DAI1 TDM */
70 { 0x18, 0x00 }, /* 18 DAI1 filters */
71 { 0x19, 0x00 }, /* 19 DAI2 clock mode */
72 { 0x1a, 0x00 }, /* 1A DAI2 clock control */
73 { 0x1b, 0x00 }, /* 1B DAI2 clock control */
74 { 0x1c, 0x00 }, /* 1C DAI2 format */
75 { 0x1d, 0x00 }, /* 1D DAI2 clock */
76 { 0x1e, 0x00 }, /* 1E DAI2 config */
77 { 0x1f, 0x00 }, /* 1F DAI2 TDM */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]78
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]79 { 0x20, 0x00 }, /* 20 DAI2 filters */
80 { 0x21, 0x00 }, /* 21 data config */
81 { 0x22, 0x00 }, /* 22 DAC mixer */
82 { 0x23, 0x00 }, /* 23 left ADC mixer */
83 { 0x24, 0x00 }, /* 24 right ADC mixer */
84 { 0x25, 0x00 }, /* 25 left HP mixer */
85 { 0x26, 0x00 }, /* 26 right HP mixer */
86 { 0x27, 0x00 }, /* 27 HP control */
87 { 0x28, 0x00 }, /* 28 left REC mixer */
88 { 0x29, 0x00 }, /* 29 right REC mixer */
89 { 0x2a, 0x00 }, /* 2A REC control */
90 { 0x2b, 0x00 }, /* 2B left SPK mixer */
91 { 0x2c, 0x00 }, /* 2C right SPK mixer */
92 { 0x2d, 0x00 }, /* 2D SPK control */
93 { 0x2e, 0x00 }, /* 2E sidetone */
94 { 0x2f, 0x00 }, /* 2F DAI1 playback level */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]95
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]96 { 0x30, 0x00 }, /* 30 DAI1 playback level */
97 { 0x31, 0x00 }, /* 31 DAI2 playback level */
98 { 0x32, 0x00 }, /* 32 DAI2 playbakc level */
99 { 0x33, 0x00 }, /* 33 left ADC level */
100 { 0x34, 0x00 }, /* 34 right ADC level */
101 { 0x35, 0x00 }, /* 35 MIC1 level */
102 { 0x36, 0x00 }, /* 36 MIC2 level */
103 { 0x37, 0x00 }, /* 37 INA level */
104 { 0x38, 0x00 }, /* 38 INB level */
105 { 0x39, 0x00 }, /* 39 left HP volume */
106 { 0x3a, 0x00 }, /* 3A right HP volume */
107 { 0x3b, 0x00 }, /* 3B left REC volume */
108 { 0x3c, 0x00 }, /* 3C right REC volume */
109 { 0x3d, 0x00 }, /* 3D left SPK volume */
110 { 0x3e, 0x00 }, /* 3E right SPK volume */
111 { 0x3f, 0x00 }, /* 3F MIC config */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]112
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]113 { 0x40, 0x00 }, /* 40 MIC threshold */
114 { 0x41, 0x00 }, /* 41 excursion limiter filter */
115 { 0x42, 0x00 }, /* 42 excursion limiter threshold */
116 { 0x43, 0x00 }, /* 43 ALC */
117 { 0x44, 0x00 }, /* 44 power limiter threshold */
118 { 0x45, 0x00 }, /* 45 power limiter config */
119 { 0x46, 0x00 }, /* 46 distortion limiter config */
120 { 0x47, 0x00 }, /* 47 audio input */
121 { 0x48, 0x00 }, /* 48 microphone */
122 { 0x49, 0x00 }, /* 49 level control */
123 { 0x4a, 0x00 }, /* 4A bypass switches */
124 { 0x4b, 0x00 }, /* 4B jack detect */
125 { 0x4c, 0x00 }, /* 4C input enable */
126 { 0x4d, 0x00 }, /* 4D output enable */
127 { 0x4e, 0xF0 }, /* 4E bias control */
128 { 0x4f, 0x00 }, /* 4F DAC power */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]129
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]130 { 0x50, 0x0F }, /* 50 DAC power */
131 { 0x51, 0x00 }, /* 51 system */
132 { 0x52, 0x00 }, /* 52 DAI1 EQ1 */
133 { 0x53, 0x00 }, /* 53 DAI1 EQ1 */
134 { 0x54, 0x00 }, /* 54 DAI1 EQ1 */
135 { 0x55, 0x00 }, /* 55 DAI1 EQ1 */
136 { 0x56, 0x00 }, /* 56 DAI1 EQ1 */
137 { 0x57, 0x00 }, /* 57 DAI1 EQ1 */
138 { 0x58, 0x00 }, /* 58 DAI1 EQ1 */
139 { 0x59, 0x00 }, /* 59 DAI1 EQ1 */
140 { 0x5a, 0x00 }, /* 5A DAI1 EQ1 */
141 { 0x5b, 0x00 }, /* 5B DAI1 EQ1 */
142 { 0x5c, 0x00 }, /* 5C DAI1 EQ2 */
143 { 0x5d, 0x00 }, /* 5D DAI1 EQ2 */
144 { 0x5e, 0x00 }, /* 5E DAI1 EQ2 */
145 { 0x5f, 0x00 }, /* 5F DAI1 EQ2 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]146
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]147 { 0x60, 0x00 }, /* 60 DAI1 EQ2 */
148 { 0x61, 0x00 }, /* 61 DAI1 EQ2 */
149 { 0x62, 0x00 }, /* 62 DAI1 EQ2 */
150 { 0x63, 0x00 }, /* 63 DAI1 EQ2 */
151 { 0x64, 0x00 }, /* 64 DAI1 EQ2 */
152 { 0x65, 0x00 }, /* 65 DAI1 EQ2 */
153 { 0x66, 0x00 }, /* 66 DAI1 EQ3 */
154 { 0x67, 0x00 }, /* 67 DAI1 EQ3 */
155 { 0x68, 0x00 }, /* 68 DAI1 EQ3 */
156 { 0x69, 0x00 }, /* 69 DAI1 EQ3 */
157 { 0x6a, 0x00 }, /* 6A DAI1 EQ3 */
158 { 0x6b, 0x00 }, /* 6B DAI1 EQ3 */
159 { 0x6c, 0x00 }, /* 6C DAI1 EQ3 */
160 { 0x6d, 0x00 }, /* 6D DAI1 EQ3 */
161 { 0x6e, 0x00 }, /* 6E DAI1 EQ3 */
162 { 0x6f, 0x00 }, /* 6F DAI1 EQ3 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]163
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]164 { 0x70, 0x00 }, /* 70 DAI1 EQ4 */
165 { 0x71, 0x00 }, /* 71 DAI1 EQ4 */
166 { 0x72, 0x00 }, /* 72 DAI1 EQ4 */
167 { 0x73, 0x00 }, /* 73 DAI1 EQ4 */
168 { 0x74, 0x00 }, /* 74 DAI1 EQ4 */
169 { 0x75, 0x00 }, /* 75 DAI1 EQ4 */
170 { 0x76, 0x00 }, /* 76 DAI1 EQ4 */
171 { 0x77, 0x00 }, /* 77 DAI1 EQ4 */
172 { 0x78, 0x00 }, /* 78 DAI1 EQ4 */
173 { 0x79, 0x00 }, /* 79 DAI1 EQ4 */
174 { 0x7a, 0x00 }, /* 7A DAI1 EQ5 */
175 { 0x7b, 0x00 }, /* 7B DAI1 EQ5 */
176 { 0x7c, 0x00 }, /* 7C DAI1 EQ5 */
177 { 0x7d, 0x00 }, /* 7D DAI1 EQ5 */
178 { 0x7e, 0x00 }, /* 7E DAI1 EQ5 */
179 { 0x7f, 0x00 }, /* 7F DAI1 EQ5 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]180
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]181 { 0x80, 0x00 }, /* 80 DAI1 EQ5 */
182 { 0x81, 0x00 }, /* 81 DAI1 EQ5 */
183 { 0x82, 0x00 }, /* 82 DAI1 EQ5 */
184 { 0x83, 0x00 }, /* 83 DAI1 EQ5 */
185 { 0x84, 0x00 }, /* 84 DAI2 EQ1 */
186 { 0x85, 0x00 }, /* 85 DAI2 EQ1 */
187 { 0x86, 0x00 }, /* 86 DAI2 EQ1 */
188 { 0x87, 0x00 }, /* 87 DAI2 EQ1 */
189 { 0x88, 0x00 }, /* 88 DAI2 EQ1 */
190 { 0x89, 0x00 }, /* 89 DAI2 EQ1 */
191 { 0x8a, 0x00 }, /* 8A DAI2 EQ1 */
192 { 0x8b, 0x00 }, /* 8B DAI2 EQ1 */
193 { 0x8c, 0x00 }, /* 8C DAI2 EQ1 */
194 { 0x8d, 0x00 }, /* 8D DAI2 EQ1 */
195 { 0x8e, 0x00 }, /* 8E DAI2 EQ2 */
196 { 0x8f, 0x00 }, /* 8F DAI2 EQ2 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]197
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]198 { 0x90, 0x00 }, /* 90 DAI2 EQ2 */
199 { 0x91, 0x00 }, /* 91 DAI2 EQ2 */
200 { 0x92, 0x00 }, /* 92 DAI2 EQ2 */
201 { 0x93, 0x00 }, /* 93 DAI2 EQ2 */
202 { 0x94, 0x00 }, /* 94 DAI2 EQ2 */
203 { 0x95, 0x00 }, /* 95 DAI2 EQ2 */
204 { 0x96, 0x00 }, /* 96 DAI2 EQ2 */
205 { 0x97, 0x00 }, /* 97 DAI2 EQ2 */
206 { 0x98, 0x00 }, /* 98 DAI2 EQ3 */
207 { 0x99, 0x00 }, /* 99 DAI2 EQ3 */
208 { 0x9a, 0x00 }, /* 9A DAI2 EQ3 */
209 { 0x9b, 0x00 }, /* 9B DAI2 EQ3 */
210 { 0x9c, 0x00 }, /* 9C DAI2 EQ3 */
211 { 0x9d, 0x00 }, /* 9D DAI2 EQ3 */
212 { 0x9e, 0x00 }, /* 9E DAI2 EQ3 */
213 { 0x9f, 0x00 }, /* 9F DAI2 EQ3 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]214
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]215 { 0xa0, 0x00 }, /* A0 DAI2 EQ3 */
216 { 0xa1, 0x00 }, /* A1 DAI2 EQ3 */
217 { 0xa2, 0x00 }, /* A2 DAI2 EQ4 */
218 { 0xa3, 0x00 }, /* A3 DAI2 EQ4 */
219 { 0xa4, 0x00 }, /* A4 DAI2 EQ4 */
220 { 0xa5, 0x00 }, /* A5 DAI2 EQ4 */
221 { 0xa6, 0x00 }, /* A6 DAI2 EQ4 */
222 { 0xa7, 0x00 }, /* A7 DAI2 EQ4 */
223 { 0xa8, 0x00 }, /* A8 DAI2 EQ4 */
224 { 0xa9, 0x00 }, /* A9 DAI2 EQ4 */
225 { 0xaa, 0x00 }, /* AA DAI2 EQ4 */
226 { 0xab, 0x00 }, /* AB DAI2 EQ4 */
227 { 0xac, 0x00 }, /* AC DAI2 EQ5 */
228 { 0xad, 0x00 }, /* AD DAI2 EQ5 */
229 { 0xae, 0x00 }, /* AE DAI2 EQ5 */
230 { 0xaf, 0x00 }, /* AF DAI2 EQ5 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]231
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]232 { 0xb0, 0x00 }, /* B0 DAI2 EQ5 */
233 { 0xb1, 0x00 }, /* B1 DAI2 EQ5 */
234 { 0xb2, 0x00 }, /* B2 DAI2 EQ5 */
235 { 0xb3, 0x00 }, /* B3 DAI2 EQ5 */
236 { 0xb4, 0x00 }, /* B4 DAI2 EQ5 */
237 { 0xb5, 0x00 }, /* B5 DAI2 EQ5 */
238 { 0xb6, 0x00 }, /* B6 DAI1 biquad */
239 { 0xb7, 0x00 }, /* B7 DAI1 biquad */
240 { 0xb8 ,0x00 }, /* B8 DAI1 biquad */
241 { 0xb9, 0x00 }, /* B9 DAI1 biquad */
242 { 0xba, 0x00 }, /* BA DAI1 biquad */
243 { 0xbb, 0x00 }, /* BB DAI1 biquad */
244 { 0xbc, 0x00 }, /* BC DAI1 biquad */
245 { 0xbd, 0x00 }, /* BD DAI1 biquad */
246 { 0xbe, 0x00 }, /* BE DAI1 biquad */
247 { 0xbf, 0x00 }, /* BF DAI1 biquad */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]248
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]249 { 0xc0, 0x00 }, /* C0 DAI2 biquad */
250 { 0xc1, 0x00 }, /* C1 DAI2 biquad */
251 { 0xc2, 0x00 }, /* C2 DAI2 biquad */
252 { 0xc3, 0x00 }, /* C3 DAI2 biquad */
253 { 0xc4, 0x00 }, /* C4 DAI2 biquad */
254 { 0xc5, 0x00 }, /* C5 DAI2 biquad */
255 { 0xc6, 0x00 }, /* C6 DAI2 biquad */
256 { 0xc7, 0x00 }, /* C7 DAI2 biquad */
257 { 0xc8, 0x00 }, /* C8 DAI2 biquad */
258 { 0xc9, 0x00 }, /* C9 DAI2 biquad */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]259};
260
261static struct {
262 int readable;
263 int writable;
264 int vol;
265} max98088_access[M98088_REG_CNT] = {
266 { 0xFF, 0xFF, 1 }, /* 00 IRQ status */
267 { 0xFF, 0x00, 1 }, /* 01 MIC status */
268 { 0xFF, 0x00, 1 }, /* 02 jack status */
269 { 0x1F, 0x1F, 1 }, /* 03 battery voltage */
270 { 0xFF, 0xFF, 0 }, /* 04 */
271 { 0xFF, 0xFF, 0 }, /* 05 */
272 { 0xFF, 0xFF, 0 }, /* 06 */
273 { 0xFF, 0xFF, 0 }, /* 07 */
274 { 0xFF, 0xFF, 0 }, /* 08 */
275 { 0xFF, 0xFF, 0 }, /* 09 */
276 { 0xFF, 0xFF, 0 }, /* 0A */
277 { 0xFF, 0xFF, 0 }, /* 0B */
278 { 0xFF, 0xFF, 0 }, /* 0C */
279 { 0xFF, 0xFF, 0 }, /* 0D */
280 { 0xFF, 0xFF, 0 }, /* 0E */
281 { 0xFF, 0xFF, 0 }, /* 0F interrupt enable */
282
283 { 0xFF, 0xFF, 0 }, /* 10 master clock */
284 { 0xFF, 0xFF, 0 }, /* 11 DAI1 clock mode */
285 { 0xFF, 0xFF, 0 }, /* 12 DAI1 clock control */
286 { 0xFF, 0xFF, 0 }, /* 13 DAI1 clock control */
287 { 0xFF, 0xFF, 0 }, /* 14 DAI1 format */
288 { 0xFF, 0xFF, 0 }, /* 15 DAI1 clock */
289 { 0xFF, 0xFF, 0 }, /* 16 DAI1 config */
290 { 0xFF, 0xFF, 0 }, /* 17 DAI1 TDM */
291 { 0xFF, 0xFF, 0 }, /* 18 DAI1 filters */
292 { 0xFF, 0xFF, 0 }, /* 19 DAI2 clock mode */
293 { 0xFF, 0xFF, 0 }, /* 1A DAI2 clock control */
294 { 0xFF, 0xFF, 0 }, /* 1B DAI2 clock control */
295 { 0xFF, 0xFF, 0 }, /* 1C DAI2 format */
296 { 0xFF, 0xFF, 0 }, /* 1D DAI2 clock */
297 { 0xFF, 0xFF, 0 }, /* 1E DAI2 config */
298 { 0xFF, 0xFF, 0 }, /* 1F DAI2 TDM */
299
300 { 0xFF, 0xFF, 0 }, /* 20 DAI2 filters */
301 { 0xFF, 0xFF, 0 }, /* 21 data config */
302 { 0xFF, 0xFF, 0 }, /* 22 DAC mixer */
303 { 0xFF, 0xFF, 0 }, /* 23 left ADC mixer */
304 { 0xFF, 0xFF, 0 }, /* 24 right ADC mixer */
305 { 0xFF, 0xFF, 0 }, /* 25 left HP mixer */
306 { 0xFF, 0xFF, 0 }, /* 26 right HP mixer */
307 { 0xFF, 0xFF, 0 }, /* 27 HP control */
308 { 0xFF, 0xFF, 0 }, /* 28 left REC mixer */
309 { 0xFF, 0xFF, 0 }, /* 29 right REC mixer */
310 { 0xFF, 0xFF, 0 }, /* 2A REC control */
311 { 0xFF, 0xFF, 0 }, /* 2B left SPK mixer */
312 { 0xFF, 0xFF, 0 }, /* 2C right SPK mixer */
313 { 0xFF, 0xFF, 0 }, /* 2D SPK control */
314 { 0xFF, 0xFF, 0 }, /* 2E sidetone */
315 { 0xFF, 0xFF, 0 }, /* 2F DAI1 playback level */
316
317 { 0xFF, 0xFF, 0 }, /* 30 DAI1 playback level */
318 { 0xFF, 0xFF, 0 }, /* 31 DAI2 playback level */
319 { 0xFF, 0xFF, 0 }, /* 32 DAI2 playbakc level */
320 { 0xFF, 0xFF, 0 }, /* 33 left ADC level */
321 { 0xFF, 0xFF, 0 }, /* 34 right ADC level */
322 { 0xFF, 0xFF, 0 }, /* 35 MIC1 level */
323 { 0xFF, 0xFF, 0 }, /* 36 MIC2 level */
324 { 0xFF, 0xFF, 0 }, /* 37 INA level */
325 { 0xFF, 0xFF, 0 }, /* 38 INB level */
326 { 0xFF, 0xFF, 0 }, /* 39 left HP volume */
327 { 0xFF, 0xFF, 0 }, /* 3A right HP volume */
328 { 0xFF, 0xFF, 0 }, /* 3B left REC volume */
329 { 0xFF, 0xFF, 0 }, /* 3C right REC volume */
330 { 0xFF, 0xFF, 0 }, /* 3D left SPK volume */
331 { 0xFF, 0xFF, 0 }, /* 3E right SPK volume */
332 { 0xFF, 0xFF, 0 }, /* 3F MIC config */
333
334 { 0xFF, 0xFF, 0 }, /* 40 MIC threshold */
335 { 0xFF, 0xFF, 0 }, /* 41 excursion limiter filter */
336 { 0xFF, 0xFF, 0 }, /* 42 excursion limiter threshold */
337 { 0xFF, 0xFF, 0 }, /* 43 ALC */
338 { 0xFF, 0xFF, 0 }, /* 44 power limiter threshold */
339 { 0xFF, 0xFF, 0 }, /* 45 power limiter config */
340 { 0xFF, 0xFF, 0 }, /* 46 distortion limiter config */
341 { 0xFF, 0xFF, 0 }, /* 47 audio input */
342 { 0xFF, 0xFF, 0 }, /* 48 microphone */
343 { 0xFF, 0xFF, 0 }, /* 49 level control */
344 { 0xFF, 0xFF, 0 }, /* 4A bypass switches */
345 { 0xFF, 0xFF, 0 }, /* 4B jack detect */
346 { 0xFF, 0xFF, 0 }, /* 4C input enable */
347 { 0xFF, 0xFF, 0 }, /* 4D output enable */
348 { 0xFF, 0xFF, 0 }, /* 4E bias control */
349 { 0xFF, 0xFF, 0 }, /* 4F DAC power */
350
351 { 0xFF, 0xFF, 0 }, /* 50 DAC power */
352 { 0xFF, 0xFF, 0 }, /* 51 system */
353 { 0xFF, 0xFF, 0 }, /* 52 DAI1 EQ1 */
354 { 0xFF, 0xFF, 0 }, /* 53 DAI1 EQ1 */
355 { 0xFF, 0xFF, 0 }, /* 54 DAI1 EQ1 */
356 { 0xFF, 0xFF, 0 }, /* 55 DAI1 EQ1 */
357 { 0xFF, 0xFF, 0 }, /* 56 DAI1 EQ1 */
358 { 0xFF, 0xFF, 0 }, /* 57 DAI1 EQ1 */
359 { 0xFF, 0xFF, 0 }, /* 58 DAI1 EQ1 */
360 { 0xFF, 0xFF, 0 }, /* 59 DAI1 EQ1 */
361 { 0xFF, 0xFF, 0 }, /* 5A DAI1 EQ1 */
362 { 0xFF, 0xFF, 0 }, /* 5B DAI1 EQ1 */
363 { 0xFF, 0xFF, 0 }, /* 5C DAI1 EQ2 */
364 { 0xFF, 0xFF, 0 }, /* 5D DAI1 EQ2 */
365 { 0xFF, 0xFF, 0 }, /* 5E DAI1 EQ2 */
366 { 0xFF, 0xFF, 0 }, /* 5F DAI1 EQ2 */
367
368 { 0xFF, 0xFF, 0 }, /* 60 DAI1 EQ2 */
369 { 0xFF, 0xFF, 0 }, /* 61 DAI1 EQ2 */
370 { 0xFF, 0xFF, 0 }, /* 62 DAI1 EQ2 */
371 { 0xFF, 0xFF, 0 }, /* 63 DAI1 EQ2 */
372 { 0xFF, 0xFF, 0 }, /* 64 DAI1 EQ2 */
373 { 0xFF, 0xFF, 0 }, /* 65 DAI1 EQ2 */
374 { 0xFF, 0xFF, 0 }, /* 66 DAI1 EQ3 */
375 { 0xFF, 0xFF, 0 }, /* 67 DAI1 EQ3 */
376 { 0xFF, 0xFF, 0 }, /* 68 DAI1 EQ3 */
377 { 0xFF, 0xFF, 0 }, /* 69 DAI1 EQ3 */
378 { 0xFF, 0xFF, 0 }, /* 6A DAI1 EQ3 */
379 { 0xFF, 0xFF, 0 }, /* 6B DAI1 EQ3 */
380 { 0xFF, 0xFF, 0 }, /* 6C DAI1 EQ3 */
381 { 0xFF, 0xFF, 0 }, /* 6D DAI1 EQ3 */
382 { 0xFF, 0xFF, 0 }, /* 6E DAI1 EQ3 */
383 { 0xFF, 0xFF, 0 }, /* 6F DAI1 EQ3 */
384
385 { 0xFF, 0xFF, 0 }, /* 70 DAI1 EQ4 */
386 { 0xFF, 0xFF, 0 }, /* 71 DAI1 EQ4 */
387 { 0xFF, 0xFF, 0 }, /* 72 DAI1 EQ4 */
388 { 0xFF, 0xFF, 0 }, /* 73 DAI1 EQ4 */
389 { 0xFF, 0xFF, 0 }, /* 74 DAI1 EQ4 */
390 { 0xFF, 0xFF, 0 }, /* 75 DAI1 EQ4 */
391 { 0xFF, 0xFF, 0 }, /* 76 DAI1 EQ4 */
392 { 0xFF, 0xFF, 0 }, /* 77 DAI1 EQ4 */
393 { 0xFF, 0xFF, 0 }, /* 78 DAI1 EQ4 */
394 { 0xFF, 0xFF, 0 }, /* 79 DAI1 EQ4 */
395 { 0xFF, 0xFF, 0 }, /* 7A DAI1 EQ5 */
396 { 0xFF, 0xFF, 0 }, /* 7B DAI1 EQ5 */
397 { 0xFF, 0xFF, 0 }, /* 7C DAI1 EQ5 */
398 { 0xFF, 0xFF, 0 }, /* 7D DAI1 EQ5 */
399 { 0xFF, 0xFF, 0 }, /* 7E DAI1 EQ5 */
400 { 0xFF, 0xFF, 0 }, /* 7F DAI1 EQ5 */
401
402 { 0xFF, 0xFF, 0 }, /* 80 DAI1 EQ5 */
403 { 0xFF, 0xFF, 0 }, /* 81 DAI1 EQ5 */
404 { 0xFF, 0xFF, 0 }, /* 82 DAI1 EQ5 */
405 { 0xFF, 0xFF, 0 }, /* 83 DAI1 EQ5 */
406 { 0xFF, 0xFF, 0 }, /* 84 DAI2 EQ1 */
407 { 0xFF, 0xFF, 0 }, /* 85 DAI2 EQ1 */
408 { 0xFF, 0xFF, 0 }, /* 86 DAI2 EQ1 */
409 { 0xFF, 0xFF, 0 }, /* 87 DAI2 EQ1 */
410 { 0xFF, 0xFF, 0 }, /* 88 DAI2 EQ1 */
411 { 0xFF, 0xFF, 0 }, /* 89 DAI2 EQ1 */
412 { 0xFF, 0xFF, 0 }, /* 8A DAI2 EQ1 */
413 { 0xFF, 0xFF, 0 }, /* 8B DAI2 EQ1 */
414 { 0xFF, 0xFF, 0 }, /* 8C DAI2 EQ1 */
415 { 0xFF, 0xFF, 0 }, /* 8D DAI2 EQ1 */
416 { 0xFF, 0xFF, 0 }, /* 8E DAI2 EQ2 */
417 { 0xFF, 0xFF, 0 }, /* 8F DAI2 EQ2 */
418
419 { 0xFF, 0xFF, 0 }, /* 90 DAI2 EQ2 */
420 { 0xFF, 0xFF, 0 }, /* 91 DAI2 EQ2 */
421 { 0xFF, 0xFF, 0 }, /* 92 DAI2 EQ2 */
422 { 0xFF, 0xFF, 0 }, /* 93 DAI2 EQ2 */
423 { 0xFF, 0xFF, 0 }, /* 94 DAI2 EQ2 */
424 { 0xFF, 0xFF, 0 }, /* 95 DAI2 EQ2 */
425 { 0xFF, 0xFF, 0 }, /* 96 DAI2 EQ2 */
426 { 0xFF, 0xFF, 0 }, /* 97 DAI2 EQ2 */
427 { 0xFF, 0xFF, 0 }, /* 98 DAI2 EQ3 */
428 { 0xFF, 0xFF, 0 }, /* 99 DAI2 EQ3 */
429 { 0xFF, 0xFF, 0 }, /* 9A DAI2 EQ3 */
430 { 0xFF, 0xFF, 0 }, /* 9B DAI2 EQ3 */
431 { 0xFF, 0xFF, 0 }, /* 9C DAI2 EQ3 */
432 { 0xFF, 0xFF, 0 }, /* 9D DAI2 EQ3 */
433 { 0xFF, 0xFF, 0 }, /* 9E DAI2 EQ3 */
434 { 0xFF, 0xFF, 0 }, /* 9F DAI2 EQ3 */
435
436 { 0xFF, 0xFF, 0 }, /* A0 DAI2 EQ3 */
437 { 0xFF, 0xFF, 0 }, /* A1 DAI2 EQ3 */
438 { 0xFF, 0xFF, 0 }, /* A2 DAI2 EQ4 */
439 { 0xFF, 0xFF, 0 }, /* A3 DAI2 EQ4 */
440 { 0xFF, 0xFF, 0 }, /* A4 DAI2 EQ4 */
441 { 0xFF, 0xFF, 0 }, /* A5 DAI2 EQ4 */
442 { 0xFF, 0xFF, 0 }, /* A6 DAI2 EQ4 */
443 { 0xFF, 0xFF, 0 }, /* A7 DAI2 EQ4 */
444 { 0xFF, 0xFF, 0 }, /* A8 DAI2 EQ4 */
445 { 0xFF, 0xFF, 0 }, /* A9 DAI2 EQ4 */
446 { 0xFF, 0xFF, 0 }, /* AA DAI2 EQ4 */
447 { 0xFF, 0xFF, 0 }, /* AB DAI2 EQ4 */
448 { 0xFF, 0xFF, 0 }, /* AC DAI2 EQ5 */
449 { 0xFF, 0xFF, 0 }, /* AD DAI2 EQ5 */
450 { 0xFF, 0xFF, 0 }, /* AE DAI2 EQ5 */
451 { 0xFF, 0xFF, 0 }, /* AF DAI2 EQ5 */
452
453 { 0xFF, 0xFF, 0 }, /* B0 DAI2 EQ5 */
454 { 0xFF, 0xFF, 0 }, /* B1 DAI2 EQ5 */
455 { 0xFF, 0xFF, 0 }, /* B2 DAI2 EQ5 */
456 { 0xFF, 0xFF, 0 }, /* B3 DAI2 EQ5 */
457 { 0xFF, 0xFF, 0 }, /* B4 DAI2 EQ5 */
458 { 0xFF, 0xFF, 0 }, /* B5 DAI2 EQ5 */
459 { 0xFF, 0xFF, 0 }, /* B6 DAI1 biquad */
460 { 0xFF, 0xFF, 0 }, /* B7 DAI1 biquad */
461 { 0xFF, 0xFF, 0 }, /* B8 DAI1 biquad */
462 { 0xFF, 0xFF, 0 }, /* B9 DAI1 biquad */
463 { 0xFF, 0xFF, 0 }, /* BA DAI1 biquad */
464 { 0xFF, 0xFF, 0 }, /* BB DAI1 biquad */
465 { 0xFF, 0xFF, 0 }, /* BC DAI1 biquad */
466 { 0xFF, 0xFF, 0 }, /* BD DAI1 biquad */
467 { 0xFF, 0xFF, 0 }, /* BE DAI1 biquad */
468 { 0xFF, 0xFF, 0 }, /* BF DAI1 biquad */
469
470 { 0xFF, 0xFF, 0 }, /* C0 DAI2 biquad */
471 { 0xFF, 0xFF, 0 }, /* C1 DAI2 biquad */
472 { 0xFF, 0xFF, 0 }, /* C2 DAI2 biquad */
473 { 0xFF, 0xFF, 0 }, /* C3 DAI2 biquad */
474 { 0xFF, 0xFF, 0 }, /* C4 DAI2 biquad */
475 { 0xFF, 0xFF, 0 }, /* C5 DAI2 biquad */
476 { 0xFF, 0xFF, 0 }, /* C6 DAI2 biquad */
477 { 0xFF, 0xFF, 0 }, /* C7 DAI2 biquad */
478 { 0xFF, 0xFF, 0 }, /* C8 DAI2 biquad */
479 { 0xFF, 0xFF, 0 }, /* C9 DAI2 biquad */
480 { 0x00, 0x00, 0 }, /* CA */
481 { 0x00, 0x00, 0 }, /* CB */
482 { 0x00, 0x00, 0 }, /* CC */
483 { 0x00, 0x00, 0 }, /* CD */
484 { 0x00, 0x00, 0 }, /* CE */
485 { 0x00, 0x00, 0 }, /* CF */
486
487 { 0x00, 0x00, 0 }, /* D0 */
488 { 0x00, 0x00, 0 }, /* D1 */
489 { 0x00, 0x00, 0 }, /* D2 */
490 { 0x00, 0x00, 0 }, /* D3 */
491 { 0x00, 0x00, 0 }, /* D4 */
492 { 0x00, 0x00, 0 }, /* D5 */
493 { 0x00, 0x00, 0 }, /* D6 */
494 { 0x00, 0x00, 0 }, /* D7 */
495 { 0x00, 0x00, 0 }, /* D8 */
496 { 0x00, 0x00, 0 }, /* D9 */
497 { 0x00, 0x00, 0 }, /* DA */
498 { 0x00, 0x00, 0 }, /* DB */
499 { 0x00, 0x00, 0 }, /* DC */
500 { 0x00, 0x00, 0 }, /* DD */
501 { 0x00, 0x00, 0 }, /* DE */
502 { 0x00, 0x00, 0 }, /* DF */
503
504 { 0x00, 0x00, 0 }, /* E0 */
505 { 0x00, 0x00, 0 }, /* E1 */
506 { 0x00, 0x00, 0 }, /* E2 */
507 { 0x00, 0x00, 0 }, /* E3 */
508 { 0x00, 0x00, 0 }, /* E4 */
509 { 0x00, 0x00, 0 }, /* E5 */
510 { 0x00, 0x00, 0 }, /* E6 */
511 { 0x00, 0x00, 0 }, /* E7 */
512 { 0x00, 0x00, 0 }, /* E8 */
513 { 0x00, 0x00, 0 }, /* E9 */
514 { 0x00, 0x00, 0 }, /* EA */
515 { 0x00, 0x00, 0 }, /* EB */
516 { 0x00, 0x00, 0 }, /* EC */
517 { 0x00, 0x00, 0 }, /* ED */
518 { 0x00, 0x00, 0 }, /* EE */
519 { 0x00, 0x00, 0 }, /* EF */
520
521 { 0x00, 0x00, 0 }, /* F0 */
522 { 0x00, 0x00, 0 }, /* F1 */
523 { 0x00, 0x00, 0 }, /* F2 */
524 { 0x00, 0x00, 0 }, /* F3 */
525 { 0x00, 0x00, 0 }, /* F4 */
526 { 0x00, 0x00, 0 }, /* F5 */
527 { 0x00, 0x00, 0 }, /* F6 */
528 { 0x00, 0x00, 0 }, /* F7 */
529 { 0x00, 0x00, 0 }, /* F8 */
530 { 0x00, 0x00, 0 }, /* F9 */
531 { 0x00, 0x00, 0 }, /* FA */
532 { 0x00, 0x00, 0 }, /* FB */
533 { 0x00, 0x00, 0 }, /* FC */
534 { 0x00, 0x00, 0 }, /* FD */
535 { 0x00, 0x00, 0 }, /* FE */
536 { 0xFF, 0x00, 1 }, /* FF */
537};
538
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]539static bool max98088_readable_register(struct device *dev, unsigned int reg)
540{
541 return max98088_access[reg].readable;
542}
543
544static bool max98088_volatile_register(struct device *dev, unsigned int reg)
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]545{
546 return max98088_access[reg].vol;
547}
548
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]549static const struct regmap_config max98088_regmap = {
550 .reg_bits = 8,
551 .val_bits = 8,
552
553 .readable_reg = max98088_readable_register,
554 .volatile_reg = max98088_volatile_register,
Mark Brown19ab2a72013-09-24 11:14:39 +0100[diff] [blame]555 .max_register = 0xff,
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]556
557 .reg_defaults = max98088_reg,
558 .num_reg_defaults = ARRAY_SIZE(max98088_reg),
559 .cache_type = REGCACHE_RBTREE,
560};
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]561
562/*
563 * Load equalizer DSP coefficient configurations registers
564 */
Dimitris Papastamos4428bc02010-10-21 12:15:56 +0100[diff] [blame]565static void m98088_eq_band(struct snd_soc_codec *codec, unsigned int dai,
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]566 unsigned int band, u16 *coefs)
567{
568 unsigned int eq_reg;
569 unsigned int i;
570
Takashi Iwaibee026d2013-11-05 18:39:49 +0100[diff] [blame]571 if (WARN_ON(band > 4) ||
572 WARN_ON(dai > 1))
573 return;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]574
575 /* Load the base register address */
576 eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE;
577
578 /* Add the band address offset, note adjustment for word address */
579 eq_reg += band * (M98088_COEFS_PER_BAND << 1);
580
581 /* Step through the registers and coefs */
582 for (i = 0; i < M98088_COEFS_PER_BAND; i++) {
583 snd_soc_write(codec, eq_reg++, M98088_BYTE1(coefs[i]));
584 snd_soc_write(codec, eq_reg++, M98088_BYTE0(coefs[i]));
585 }
586}
587
588/*
589 * Excursion limiter modes
590 */
591static const char *max98088_exmode_texts[] = {
592 "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz",
593 "400-600Hz", "400-800Hz",
594};
595
596static const unsigned int max98088_exmode_values[] = {
597 0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32
598};
599
600static const struct soc_enum max98088_exmode_enum =
601 SOC_VALUE_ENUM_SINGLE(M98088_REG_41_SPKDHP, 0, 127,
602 ARRAY_SIZE(max98088_exmode_texts),
603 max98088_exmode_texts,
604 max98088_exmode_values);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]605
606static const char *max98088_ex_thresh[] = { /* volts PP */
607 "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"};
608static const struct soc_enum max98088_ex_thresh_enum[] = {
609 SOC_ENUM_SINGLE(M98088_REG_42_SPKDHP_THRESH, 0, 8,
610 max98088_ex_thresh),
611};
612
613static const char *max98088_fltr_mode[] = {"Voice", "Music" };
614static const struct soc_enum max98088_filter_mode_enum[] = {
615 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 7, 2, max98088_fltr_mode),
616};
617
618static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" };
619
620static const struct soc_enum max98088_extmic_enum =
621 SOC_ENUM_SINGLE(M98088_REG_48_CFG_MIC, 0, 3, max98088_extmic_text);
622
623static const struct snd_kcontrol_new max98088_extmic_mux =
624 SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum);
625
626static const char *max98088_dai1_fltr[] = {
627 "Off", "fc=258/fs=16k", "fc=500/fs=16k",
628 "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"};
629static const struct soc_enum max98088_dai1_dac_filter_enum[] = {
630 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 0, 6, max98088_dai1_fltr),
631};
632static const struct soc_enum max98088_dai1_adc_filter_enum[] = {
633 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 4, 6, max98088_dai1_fltr),
634};
635
636static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol,
637 struct snd_ctl_elem_value *ucontrol)
638{
639 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
640 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
641 unsigned int sel = ucontrol->value.integer.value[0];
642
643 max98088->mic1pre = sel;
644 snd_soc_update_bits(codec, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK,
645 (1+sel)<<M98088_MICPRE_SHIFT);
646
647 return 0;
648}
649
650static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol,
651 struct snd_ctl_elem_value *ucontrol)
652{
653 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
654 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
655
656 ucontrol->value.integer.value[0] = max98088->mic1pre;
657 return 0;
658}
659
660static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol,
661 struct snd_ctl_elem_value *ucontrol)
662{
663 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
664 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
665 unsigned int sel = ucontrol->value.integer.value[0];
666
667 max98088->mic2pre = sel;
668 snd_soc_update_bits(codec, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK,
669 (1+sel)<<M98088_MICPRE_SHIFT);
670
671 return 0;
672}
673
674static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol,
675 struct snd_ctl_elem_value *ucontrol)
676{
677 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
678 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
679
680 ucontrol->value.integer.value[0] = max98088->mic2pre;
681 return 0;
682}
683
684static const unsigned int max98088_micboost_tlv[] = {
685 TLV_DB_RANGE_HEAD(2),
686 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
687 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
688};
689
Dylan Reidc751a1f2013-02-15 08:55:10 -0800[diff] [blame]690static const unsigned int max98088_hp_tlv[] = {
691 TLV_DB_RANGE_HEAD(5),
692 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
693 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
694 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
695 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
696 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
697};
698
699static const unsigned int max98088_spk_tlv[] = {
700 TLV_DB_RANGE_HEAD(5),
701 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
702 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
703 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
704 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
705 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
706};
707
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]708static const struct snd_kcontrol_new max98088_snd_controls[] = {
709
Dylan Reidc751a1f2013-02-15 08:55:10 -0800[diff] [blame]710 SOC_DOUBLE_R_TLV("Headphone Volume", M98088_REG_39_LVL_HP_L,
711 M98088_REG_3A_LVL_HP_R, 0, 31, 0, max98088_hp_tlv),
712 SOC_DOUBLE_R_TLV("Speaker Volume", M98088_REG_3D_LVL_SPK_L,
713 M98088_REG_3E_LVL_SPK_R, 0, 31, 0, max98088_spk_tlv),
714 SOC_DOUBLE_R_TLV("Receiver Volume", M98088_REG_3B_LVL_REC_L,
715 M98088_REG_3C_LVL_REC_R, 0, 31, 0, max98088_spk_tlv),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]716
717 SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L,
718 M98088_REG_3A_LVL_HP_R, 7, 1, 1),
719 SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L,
720 M98088_REG_3E_LVL_SPK_R, 7, 1, 1),
721 SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L,
722 M98088_REG_3C_LVL_REC_R, 7, 1, 1),
723
724 SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1),
725 SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1),
726
727 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
728 M98088_REG_35_LVL_MIC1, 5, 2, 0,
729 max98088_mic1pre_get, max98088_mic1pre_set,
730 max98088_micboost_tlv),
731 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
732 M98088_REG_36_LVL_MIC2, 5, 2, 0,
733 max98088_mic2pre_get, max98088_mic2pre_set,
734 max98088_micboost_tlv),
735
736 SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1),
737 SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1),
738
739 SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0),
740 SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0),
741
742 SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0),
743 SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0),
744
745 SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0),
746 SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0),
747
Jin Park938b4fb2011-05-12 14:58:37 +0900[diff] [blame]748 SOC_ENUM("EX Limiter Mode", max98088_exmode_enum),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]749 SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum),
750
751 SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum),
752 SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum),
753 SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum),
754 SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS,
755 0, 1, 0),
756
757 SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0),
758 SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0),
759 SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0),
760 SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0),
761
762 SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG,
763 4, 15, 0),
764 SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0),
765 SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0),
766 SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0),
767
768 SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0),
769 SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0),
770};
771
772/* Left speaker mixer switch */
773static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = {
Jin Park770939c2011-05-12 14:58:36 +0900[diff] [blame]774 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
775 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
776 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
777 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]778 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0),
779 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0),
780 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0),
781 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0),
782 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0),
783 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0),
784};
785
786/* Right speaker mixer switch */
787static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = {
788 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
789 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
790 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
791 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
792 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0),
793 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0),
794 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0),
795 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0),
796 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0),
797 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0),
798};
799
800/* Left headphone mixer switch */
801static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = {
Jin Park770939c2011-05-12 14:58:36 +0900[diff] [blame]802 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
803 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
804 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
805 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]806 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0),
807 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0),
808 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0),
809 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0),
810 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0),
811 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0),
812};
813
814/* Right headphone mixer switch */
815static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = {
816 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
817 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
818 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
819 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
820 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0),
821 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0),
822 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0),
823 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0),
824 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0),
825 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0),
826};
827
828/* Left earpiece/receiver mixer switch */
829static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = {
Jin Park770939c2011-05-12 14:58:36 +0900[diff] [blame]830 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
831 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
832 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
833 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]834 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0),
835 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0),
836 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0),
837 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0),
838 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0),
839 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0),
840};
841
842/* Right earpiece/receiver mixer switch */
843static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = {
844 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
845 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
846 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
847 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
848 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0),
849 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0),
850 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0),
851 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0),
852 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0),
853 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0),
854};
855
856/* Left ADC mixer switch */
857static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = {
858 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0),
859 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0),
860 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0),
861 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0),
862 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0),
863 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0),
864};
865
866/* Right ADC mixer switch */
867static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = {
868 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0),
869 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0),
870 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0),
871 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0),
872 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0),
873 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0),
874};
875
876static int max98088_mic_event(struct snd_soc_dapm_widget *w,
877 struct snd_kcontrol *kcontrol, int event)
878{
879 struct snd_soc_codec *codec = w->codec;
880 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
881
882 switch (event) {
883 case SND_SOC_DAPM_POST_PMU:
884 if (w->reg == M98088_REG_35_LVL_MIC1) {
885 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK,
886 (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT);
887 } else {
888 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK,
889 (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT);
890 }
891 break;
892 case SND_SOC_DAPM_POST_PMD:
893 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 0);
894 break;
895 default:
896 return -EINVAL;
897 }
898
899 return 0;
900}
901
902/*
903 * The line inputs are 2-channel stereo inputs with the left
904 * and right channels sharing a common PGA power control signal.
905 */
906static int max98088_line_pga(struct snd_soc_dapm_widget *w,
907 int event, int line, u8 channel)
908{
909 struct snd_soc_codec *codec = w->codec;
910 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
911 u8 *state;
912
Takashi Iwaibee026d2013-11-05 18:39:49 +0100[diff] [blame]913 if (WARN_ON(!(channel == 1 || channel == 2)))
914 return -EINVAL;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]915
916 switch (line) {
917 case LINE_INA:
918 state = &max98088->ina_state;
919 break;
920 case LINE_INB:
921 state = &max98088->inb_state;
922 break;
923 default:
924 return -EINVAL;
925 }
926
927 switch (event) {
928 case SND_SOC_DAPM_POST_PMU:
929 *state |= channel;
930 snd_soc_update_bits(codec, w->reg,
931 (1 << w->shift), (1 << w->shift));
932 break;
933 case SND_SOC_DAPM_POST_PMD:
934 *state &= ~channel;
935 if (*state == 0) {
936 snd_soc_update_bits(codec, w->reg,
937 (1 << w->shift), 0);
938 }
939 break;
940 default:
941 return -EINVAL;
942 }
943
944 return 0;
945}
946
947static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w,
948 struct snd_kcontrol *k, int event)
949{
950 return max98088_line_pga(w, event, LINE_INA, 1);
951}
952
953static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w,
954 struct snd_kcontrol *k, int event)
955{
956 return max98088_line_pga(w, event, LINE_INA, 2);
957}
958
959static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w,
960 struct snd_kcontrol *k, int event)
961{
962 return max98088_line_pga(w, event, LINE_INB, 1);
963}
964
965static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w,
966 struct snd_kcontrol *k, int event)
967{
968 return max98088_line_pga(w, event, LINE_INB, 2);
969}
970
971static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = {
972
973 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0),
974 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0),
975
976 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
977 M98088_REG_4D_PWR_EN_OUT, 1, 0),
978 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
979 M98088_REG_4D_PWR_EN_OUT, 0, 0),
980 SND_SOC_DAPM_DAC("DACL2", "Aux Playback",
981 M98088_REG_4D_PWR_EN_OUT, 1, 0),
982 SND_SOC_DAPM_DAC("DACR2", "Aux Playback",
983 M98088_REG_4D_PWR_EN_OUT, 0, 0),
984
985 SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT,
986 7, 0, NULL, 0),
987 SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT,
988 6, 0, NULL, 0),
989
990 SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT,
991 5, 0, NULL, 0),
992 SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT,
993 4, 0, NULL, 0),
994
995 SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT,
996 3, 0, NULL, 0),
997 SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT,
998 2, 0, NULL, 0),
999
1000 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
1001 &max98088_extmic_mux),
1002
1003 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
1004 &max98088_left_hp_mixer_controls[0],
1005 ARRAY_SIZE(max98088_left_hp_mixer_controls)),
1006
1007 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
1008 &max98088_right_hp_mixer_controls[0],
1009 ARRAY_SIZE(max98088_right_hp_mixer_controls)),
1010
1011 SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0,
1012 &max98088_left_speaker_mixer_controls[0],
1013 ARRAY_SIZE(max98088_left_speaker_mixer_controls)),
1014
1015 SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0,
1016 &max98088_right_speaker_mixer_controls[0],
1017 ARRAY_SIZE(max98088_right_speaker_mixer_controls)),
1018
1019 SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0,
1020 &max98088_left_rec_mixer_controls[0],
1021 ARRAY_SIZE(max98088_left_rec_mixer_controls)),
1022
1023 SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0,
1024 &max98088_right_rec_mixer_controls[0],
1025 ARRAY_SIZE(max98088_right_rec_mixer_controls)),
1026
1027 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1028 &max98088_left_ADC_mixer_controls[0],
1029 ARRAY_SIZE(max98088_left_ADC_mixer_controls)),
1030
1031 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1032 &max98088_right_ADC_mixer_controls[0],
1033 ARRAY_SIZE(max98088_right_ADC_mixer_controls)),
1034
1035 SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1,
1036 5, 0, NULL, 0, max98088_mic_event,
1037 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1038
1039 SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2,
1040 5, 0, NULL, 0, max98088_mic_event,
1041 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1042
1043 SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN,
1044 7, 0, NULL, 0, max98088_pga_ina1_event,
1045 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1046
1047 SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN,
1048 7, 0, NULL, 0, max98088_pga_ina2_event,
1049 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1050
1051 SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN,
1052 6, 0, NULL, 0, max98088_pga_inb1_event,
1053 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1054
1055 SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN,
1056 6, 0, NULL, 0, max98088_pga_inb2_event,
1057 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1058
1059 SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0),
1060
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1061 SND_SOC_DAPM_OUTPUT("HPL"),
1062 SND_SOC_DAPM_OUTPUT("HPR"),
1063 SND_SOC_DAPM_OUTPUT("SPKL"),
1064 SND_SOC_DAPM_OUTPUT("SPKR"),
1065 SND_SOC_DAPM_OUTPUT("RECL"),
1066 SND_SOC_DAPM_OUTPUT("RECR"),
1067
1068 SND_SOC_DAPM_INPUT("MIC1"),
1069 SND_SOC_DAPM_INPUT("MIC2"),
1070 SND_SOC_DAPM_INPUT("INA1"),
1071 SND_SOC_DAPM_INPUT("INA2"),
1072 SND_SOC_DAPM_INPUT("INB1"),
1073 SND_SOC_DAPM_INPUT("INB2"),
1074};
1075
Lu Guanqundc6fc492011-03-30 21:53:10 +0800[diff] [blame]1076static const struct snd_soc_dapm_route max98088_audio_map[] = {
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1077 /* Left headphone output mixer */
1078 {"Left HP Mixer", "Left DAC1 Switch", "DACL1"},
1079 {"Left HP Mixer", "Left DAC2 Switch", "DACL2"},
1080 {"Left HP Mixer", "Right DAC1 Switch", "DACR1"},
1081 {"Left HP Mixer", "Right DAC2 Switch", "DACR2"},
1082 {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"},
1083 {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"},
1084 {"Left HP Mixer", "INA1 Switch", "INA1 Input"},
1085 {"Left HP Mixer", "INA2 Switch", "INA2 Input"},
1086 {"Left HP Mixer", "INB1 Switch", "INB1 Input"},
1087 {"Left HP Mixer", "INB2 Switch", "INB2 Input"},
1088
1089 /* Right headphone output mixer */
1090 {"Right HP Mixer", "Left DAC1 Switch", "DACL1"},
1091 {"Right HP Mixer", "Left DAC2 Switch", "DACL2" },
1092 {"Right HP Mixer", "Right DAC1 Switch", "DACR1"},
1093 {"Right HP Mixer", "Right DAC2 Switch", "DACR2"},
1094 {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"},
1095 {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"},
1096 {"Right HP Mixer", "INA1 Switch", "INA1 Input"},
1097 {"Right HP Mixer", "INA2 Switch", "INA2 Input"},
1098 {"Right HP Mixer", "INB1 Switch", "INB1 Input"},
1099 {"Right HP Mixer", "INB2 Switch", "INB2 Input"},
1100
1101 /* Left speaker output mixer */
1102 {"Left SPK Mixer", "Left DAC1 Switch", "DACL1"},
1103 {"Left SPK Mixer", "Left DAC2 Switch", "DACL2"},
1104 {"Left SPK Mixer", "Right DAC1 Switch", "DACR1"},
1105 {"Left SPK Mixer", "Right DAC2 Switch", "DACR2"},
1106 {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"},
1107 {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"},
1108 {"Left SPK Mixer", "INA1 Switch", "INA1 Input"},
1109 {"Left SPK Mixer", "INA2 Switch", "INA2 Input"},
1110 {"Left SPK Mixer", "INB1 Switch", "INB1 Input"},
1111 {"Left SPK Mixer", "INB2 Switch", "INB2 Input"},
1112
1113 /* Right speaker output mixer */
1114 {"Right SPK Mixer", "Left DAC1 Switch", "DACL1"},
1115 {"Right SPK Mixer", "Left DAC2 Switch", "DACL2"},
1116 {"Right SPK Mixer", "Right DAC1 Switch", "DACR1"},
1117 {"Right SPK Mixer", "Right DAC2 Switch", "DACR2"},
1118 {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"},
1119 {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"},
1120 {"Right SPK Mixer", "INA1 Switch", "INA1 Input"},
1121 {"Right SPK Mixer", "INA2 Switch", "INA2 Input"},
1122 {"Right SPK Mixer", "INB1 Switch", "INB1 Input"},
1123 {"Right SPK Mixer", "INB2 Switch", "INB2 Input"},
1124
1125 /* Earpiece/Receiver output mixer */
1126 {"Left REC Mixer", "Left DAC1 Switch", "DACL1"},
1127 {"Left REC Mixer", "Left DAC2 Switch", "DACL2"},
1128 {"Left REC Mixer", "Right DAC1 Switch", "DACR1"},
1129 {"Left REC Mixer", "Right DAC2 Switch", "DACR2"},
1130 {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"},
1131 {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"},
1132 {"Left REC Mixer", "INA1 Switch", "INA1 Input"},
1133 {"Left REC Mixer", "INA2 Switch", "INA2 Input"},
1134 {"Left REC Mixer", "INB1 Switch", "INB1 Input"},
1135 {"Left REC Mixer", "INB2 Switch", "INB2 Input"},
1136
1137 /* Earpiece/Receiver output mixer */
1138 {"Right REC Mixer", "Left DAC1 Switch", "DACL1"},
1139 {"Right REC Mixer", "Left DAC2 Switch", "DACL2"},
1140 {"Right REC Mixer", "Right DAC1 Switch", "DACR1"},
1141 {"Right REC Mixer", "Right DAC2 Switch", "DACR2"},
1142 {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"},
1143 {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"},
1144 {"Right REC Mixer", "INA1 Switch", "INA1 Input"},
1145 {"Right REC Mixer", "INA2 Switch", "INA2 Input"},
1146 {"Right REC Mixer", "INB1 Switch", "INB1 Input"},
1147 {"Right REC Mixer", "INB2 Switch", "INB2 Input"},
1148
1149 {"HP Left Out", NULL, "Left HP Mixer"},
1150 {"HP Right Out", NULL, "Right HP Mixer"},
1151 {"SPK Left Out", NULL, "Left SPK Mixer"},
1152 {"SPK Right Out", NULL, "Right SPK Mixer"},
1153 {"REC Left Out", NULL, "Left REC Mixer"},
1154 {"REC Right Out", NULL, "Right REC Mixer"},
1155
1156 {"HPL", NULL, "HP Left Out"},
1157 {"HPR", NULL, "HP Right Out"},
1158 {"SPKL", NULL, "SPK Left Out"},
1159 {"SPKR", NULL, "SPK Right Out"},
1160 {"RECL", NULL, "REC Left Out"},
1161 {"RECR", NULL, "REC Right Out"},
1162
1163 /* Left ADC input mixer */
1164 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1165 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1166 {"Left ADC Mixer", "INA1 Switch", "INA1 Input"},
1167 {"Left ADC Mixer", "INA2 Switch", "INA2 Input"},
1168 {"Left ADC Mixer", "INB1 Switch", "INB1 Input"},
1169 {"Left ADC Mixer", "INB2 Switch", "INB2 Input"},
1170
1171 /* Right ADC input mixer */
1172 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1173 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1174 {"Right ADC Mixer", "INA1 Switch", "INA1 Input"},
1175 {"Right ADC Mixer", "INA2 Switch", "INA2 Input"},
1176 {"Right ADC Mixer", "INB1 Switch", "INB1 Input"},
1177 {"Right ADC Mixer", "INB2 Switch", "INB2 Input"},
1178
1179 /* Inputs */
1180 {"ADCL", NULL, "Left ADC Mixer"},
1181 {"ADCR", NULL, "Right ADC Mixer"},
1182 {"INA1 Input", NULL, "INA1"},
1183 {"INA2 Input", NULL, "INA2"},
1184 {"INB1 Input", NULL, "INB1"},
1185 {"INB2 Input", NULL, "INB2"},
1186 {"MIC1 Input", NULL, "MIC1"},
1187 {"MIC2 Input", NULL, "MIC2"},
1188};
1189
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1190/* codec mclk clock divider coefficients */
1191static const struct {
1192 u32 rate;
1193 u8 sr;
1194} rate_table[] = {
1195 {8000, 0x10},
1196 {11025, 0x20},
1197 {16000, 0x30},
1198 {22050, 0x40},
1199 {24000, 0x50},
1200 {32000, 0x60},
1201 {44100, 0x70},
1202 {48000, 0x80},
1203 {88200, 0x90},
1204 {96000, 0xA0},
1205};
1206
1207static inline int rate_value(int rate, u8 *value)
1208{
1209 int i;
1210
1211 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
1212 if (rate_table[i].rate >= rate) {
1213 *value = rate_table[i].sr;
1214 return 0;
1215 }
1216 }
1217 *value = rate_table[0].sr;
1218 return -EINVAL;
1219}
1220
1221static int max98088_dai1_hw_params(struct snd_pcm_substream *substream,
1222 struct snd_pcm_hw_params *params,
1223 struct snd_soc_dai *dai)
1224{
1225 struct snd_soc_codec *codec = dai->codec;
1226 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1227 struct max98088_cdata *cdata;
1228 unsigned long long ni;
1229 unsigned int rate;
1230 u8 regval;
1231
1232 cdata = &max98088->dai[0];
1233
1234 rate = params_rate(params);
1235
Mark Brown793f7702014-01-08 20:39:22 +0000[diff] [blame]1236 switch (params_width(params)) {
1237 case 16:
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1238 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1239 M98088_DAI_WS, 0);
1240 break;
Mark Brown793f7702014-01-08 20:39:22 +0000[diff] [blame]1241 case 24:
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1242 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1243 M98088_DAI_WS, M98088_DAI_WS);
1244 break;
1245 default:
1246 return -EINVAL;
1247 }
1248
1249 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1250
1251 if (rate_value(rate, &regval))
1252 return -EINVAL;
1253
1254 snd_soc_update_bits(codec, M98088_REG_11_DAI1_CLKMODE,
1255 M98088_CLKMODE_MASK, regval);
1256 cdata->rate = rate;
1257
1258 /* Configure NI when operating as master */
1259 if (snd_soc_read(codec, M98088_REG_14_DAI1_FORMAT)
1260 & M98088_DAI_MAS) {
1261 if (max98088->sysclk == 0) {
1262 dev_err(codec->dev, "Invalid system clock frequency\n");
1263 return -EINVAL;
1264 }
1265 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1266 * (unsigned long long int)rate;
1267 do_div(ni, (unsigned long long int)max98088->sysclk);
1268 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI,
1269 (ni >> 8) & 0x7F);
1270 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO,
1271 ni & 0xFF);
1272 }
1273
1274 /* Update sample rate mode */
1275 if (rate < 50000)
1276 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS,
1277 M98088_DAI_DHF, 0);
1278 else
1279 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS,
1280 M98088_DAI_DHF, M98088_DAI_DHF);
1281
1282 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1283 M98088_SHDNRUN);
1284
1285 return 0;
1286}
1287
1288static int max98088_dai2_hw_params(struct snd_pcm_substream *substream,
1289 struct snd_pcm_hw_params *params,
1290 struct snd_soc_dai *dai)
1291{
1292 struct snd_soc_codec *codec = dai->codec;
1293 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1294 struct max98088_cdata *cdata;
1295 unsigned long long ni;
1296 unsigned int rate;
1297 u8 regval;
1298
1299 cdata = &max98088->dai[1];
1300
1301 rate = params_rate(params);
1302
1303 switch (params_format(params)) {
1304 case SNDRV_PCM_FORMAT_S16_LE:
1305 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1306 M98088_DAI_WS, 0);
1307 break;
1308 case SNDRV_PCM_FORMAT_S24_LE:
1309 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1310 M98088_DAI_WS, M98088_DAI_WS);
1311 break;
1312 default:
1313 return -EINVAL;
1314 }
1315
1316 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1317
1318 if (rate_value(rate, &regval))
1319 return -EINVAL;
1320
1321 snd_soc_update_bits(codec, M98088_REG_19_DAI2_CLKMODE,
1322 M98088_CLKMODE_MASK, regval);
1323 cdata->rate = rate;
1324
1325 /* Configure NI when operating as master */
1326 if (snd_soc_read(codec, M98088_REG_1C_DAI2_FORMAT)
1327 & M98088_DAI_MAS) {
1328 if (max98088->sysclk == 0) {
1329 dev_err(codec->dev, "Invalid system clock frequency\n");
1330 return -EINVAL;
1331 }
1332 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1333 * (unsigned long long int)rate;
1334 do_div(ni, (unsigned long long int)max98088->sysclk);
1335 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI,
1336 (ni >> 8) & 0x7F);
1337 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO,
1338 ni & 0xFF);
1339 }
1340
1341 /* Update sample rate mode */
1342 if (rate < 50000)
1343 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS,
1344 M98088_DAI_DHF, 0);
1345 else
1346 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS,
1347 M98088_DAI_DHF, M98088_DAI_DHF);
1348
1349 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1350 M98088_SHDNRUN);
1351
1352 return 0;
1353}
1354
1355static int max98088_dai_set_sysclk(struct snd_soc_dai *dai,
1356 int clk_id, unsigned int freq, int dir)
1357{
1358 struct snd_soc_codec *codec = dai->codec;
1359 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1360
1361 /* Requested clock frequency is already setup */
1362 if (freq == max98088->sysclk)
1363 return 0;
1364
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1365 /* Setup clocks for slave mode, and using the PLL
1366 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1367 * 0x02 (when master clk is 20MHz to 30MHz)..
1368 */
1369 if ((freq >= 10000000) && (freq < 20000000)) {
1370 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x10);
1371 } else if ((freq >= 20000000) && (freq < 30000000)) {
1372 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x20);
1373 } else {
1374 dev_err(codec->dev, "Invalid master clock frequency\n");
1375 return -EINVAL;
1376 }
1377
1378 if (snd_soc_read(codec, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) {
1379 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS,
1380 M98088_SHDNRUN, 0);
1381 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS,
1382 M98088_SHDNRUN, M98088_SHDNRUN);
1383 }
1384
1385 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1386
1387 max98088->sysclk = freq;
1388 return 0;
1389}
1390
1391static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1392 unsigned int fmt)
1393{
1394 struct snd_soc_codec *codec = codec_dai->codec;
1395 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1396 struct max98088_cdata *cdata;
1397 u8 reg15val;
1398 u8 reg14val = 0;
1399
1400 cdata = &max98088->dai[0];
1401
1402 if (fmt != cdata->fmt) {
1403 cdata->fmt = fmt;
1404
1405 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1406 case SND_SOC_DAIFMT_CBS_CFS:
1407 /* Slave mode PLL */
1408 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI,
1409 0x80);
1410 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO,
1411 0x00);
1412 break;
1413 case SND_SOC_DAIFMT_CBM_CFM:
1414 /* Set to master mode */
1415 reg14val |= M98088_DAI_MAS;
1416 break;
1417 case SND_SOC_DAIFMT_CBS_CFM:
1418 case SND_SOC_DAIFMT_CBM_CFS:
1419 default:
1420 dev_err(codec->dev, "Clock mode unsupported");
1421 return -EINVAL;
1422 }
1423
1424 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1425 case SND_SOC_DAIFMT_I2S:
1426 reg14val |= M98088_DAI_DLY;
1427 break;
1428 case SND_SOC_DAIFMT_LEFT_J:
1429 break;
1430 default:
1431 return -EINVAL;
1432 }
1433
1434 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1435 case SND_SOC_DAIFMT_NB_NF:
1436 break;
1437 case SND_SOC_DAIFMT_NB_IF:
1438 reg14val |= M98088_DAI_WCI;
1439 break;
1440 case SND_SOC_DAIFMT_IB_NF:
1441 reg14val |= M98088_DAI_BCI;
1442 break;
1443 case SND_SOC_DAIFMT_IB_IF:
1444 reg14val |= M98088_DAI_BCI|M98088_DAI_WCI;
1445 break;
1446 default:
1447 return -EINVAL;
1448 }
1449
1450 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1451 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1452 M98088_DAI_WCI, reg14val);
1453
1454 reg15val = M98088_DAI_BSEL64;
1455 if (max98088->digmic)
1456 reg15val |= M98088_DAI_OSR64;
1457 snd_soc_write(codec, M98088_REG_15_DAI1_CLOCK, reg15val);
1458 }
1459
1460 return 0;
1461}
1462
1463static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1464 unsigned int fmt)
1465{
1466 struct snd_soc_codec *codec = codec_dai->codec;
1467 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1468 struct max98088_cdata *cdata;
1469 u8 reg1Cval = 0;
1470
1471 cdata = &max98088->dai[1];
1472
1473 if (fmt != cdata->fmt) {
1474 cdata->fmt = fmt;
1475
1476 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1477 case SND_SOC_DAIFMT_CBS_CFS:
1478 /* Slave mode PLL */
1479 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI,
1480 0x80);
1481 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO,
1482 0x00);
1483 break;
1484 case SND_SOC_DAIFMT_CBM_CFM:
1485 /* Set to master mode */
1486 reg1Cval |= M98088_DAI_MAS;
1487 break;
1488 case SND_SOC_DAIFMT_CBS_CFM:
1489 case SND_SOC_DAIFMT_CBM_CFS:
1490 default:
1491 dev_err(codec->dev, "Clock mode unsupported");
1492 return -EINVAL;
1493 }
1494
1495 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1496 case SND_SOC_DAIFMT_I2S:
1497 reg1Cval |= M98088_DAI_DLY;
1498 break;
1499 case SND_SOC_DAIFMT_LEFT_J:
1500 break;
1501 default:
1502 return -EINVAL;
1503 }
1504
1505 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1506 case SND_SOC_DAIFMT_NB_NF:
1507 break;
1508 case SND_SOC_DAIFMT_NB_IF:
1509 reg1Cval |= M98088_DAI_WCI;
1510 break;
1511 case SND_SOC_DAIFMT_IB_NF:
1512 reg1Cval |= M98088_DAI_BCI;
1513 break;
1514 case SND_SOC_DAIFMT_IB_IF:
1515 reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI;
1516 break;
1517 default:
1518 return -EINVAL;
1519 }
1520
1521 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1522 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1523 M98088_DAI_WCI, reg1Cval);
1524
1525 snd_soc_write(codec, M98088_REG_1D_DAI2_CLOCK,
1526 M98088_DAI_BSEL64);
1527 }
1528
1529 return 0;
1530}
1531
Jin Park25709f62011-05-12 14:58:38 +0900[diff] [blame]1532static int max98088_dai1_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1533{
1534 struct snd_soc_codec *codec = codec_dai->codec;
1535 int reg;
1536
1537 if (mute)
1538 reg = M98088_DAI_MUTE;
1539 else
1540 reg = 0;
1541
1542 snd_soc_update_bits(codec, M98088_REG_2F_LVL_DAI1_PLAY,
1543 M98088_DAI_MUTE_MASK, reg);
1544 return 0;
1545}
1546
1547static int max98088_dai2_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1548{
1549 struct snd_soc_codec *codec = codec_dai->codec;
1550 int reg;
1551
1552 if (mute)
1553 reg = M98088_DAI_MUTE;
1554 else
1555 reg = 0;
1556
1557 snd_soc_update_bits(codec, M98088_REG_31_LVL_DAI2_PLAY,
1558 M98088_DAI_MUTE_MASK, reg);
1559 return 0;
1560}
1561
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1562static int max98088_set_bias_level(struct snd_soc_codec *codec,
1563 enum snd_soc_bias_level level)
1564{
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1565 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1566
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1567 switch (level) {
1568 case SND_SOC_BIAS_ON:
1569 break;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1570
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1571 case SND_SOC_BIAS_PREPARE:
1572 break;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1573
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1574 case SND_SOC_BIAS_STANDBY:
1575 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1576 regcache_sync(max98088->regmap);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1577
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1578 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
1579 M98088_MBEN, M98088_MBEN);
1580 break;
1581
1582 case SND_SOC_BIAS_OFF:
1583 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
1584 M98088_MBEN, 0);
1585 regcache_mark_dirty(max98088->regmap);
1586 break;
1587 }
1588 codec->dapm.bias_level = level;
1589 return 0;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1590}
1591
1592#define MAX98088_RATES SNDRV_PCM_RATE_8000_96000
1593#define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1594
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100[diff] [blame]1595static const struct snd_soc_dai_ops max98088_dai1_ops = {
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1596 .set_sysclk = max98088_dai_set_sysclk,
1597 .set_fmt = max98088_dai1_set_fmt,
1598 .hw_params = max98088_dai1_hw_params,
Jin Park25709f62011-05-12 14:58:38 +0900[diff] [blame]1599 .digital_mute = max98088_dai1_digital_mute,
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1600};
1601
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100[diff] [blame]1602static const struct snd_soc_dai_ops max98088_dai2_ops = {
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1603 .set_sysclk = max98088_dai_set_sysclk,
1604 .set_fmt = max98088_dai2_set_fmt,
1605 .hw_params = max98088_dai2_hw_params,
Jin Park25709f62011-05-12 14:58:38 +0900[diff] [blame]1606 .digital_mute = max98088_dai2_digital_mute,
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1607};
1608
1609static struct snd_soc_dai_driver max98088_dai[] = {
1610{
1611 .name = "HiFi",
1612 .playback = {
1613 .stream_name = "HiFi Playback",
1614 .channels_min = 1,
1615 .channels_max = 2,
1616 .rates = MAX98088_RATES,
1617 .formats = MAX98088_FORMATS,
1618 },
1619 .capture = {
1620 .stream_name = "HiFi Capture",
1621 .channels_min = 1,
1622 .channels_max = 2,
1623 .rates = MAX98088_RATES,
1624 .formats = MAX98088_FORMATS,
1625 },
1626 .ops = &max98088_dai1_ops,
1627},
1628{
1629 .name = "Aux",
1630 .playback = {
1631 .stream_name = "Aux Playback",
1632 .channels_min = 1,
1633 .channels_max = 2,
1634 .rates = MAX98088_RATES,
1635 .formats = MAX98088_FORMATS,
1636 },
1637 .ops = &max98088_dai2_ops,
1638}
1639};
1640
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1641static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"};
1642
1643static int max98088_get_channel(struct snd_soc_codec *codec, const char *name)
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1644{
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1645 int i;
1646
1647 for (i = 0; i < ARRAY_SIZE(eq_mode_name); i++)
1648 if (strcmp(name, eq_mode_name[i]) == 0)
1649 return i;
1650
1651 /* Shouldn't happen */
1652 dev_err(codec->dev, "Bad EQ channel name '%s'\n", name);
1653 return -EINVAL;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1654}
1655
1656static void max98088_setup_eq1(struct snd_soc_codec *codec)
1657{
1658 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1659 struct max98088_pdata *pdata = max98088->pdata;
1660 struct max98088_eq_cfg *coef_set;
1661 int best, best_val, save, i, sel, fs;
1662 struct max98088_cdata *cdata;
1663
1664 cdata = &max98088->dai[0];
1665
1666 if (!pdata || !max98088->eq_textcnt)
1667 return;
1668
1669 /* Find the selected configuration with nearest sample rate */
1670 fs = cdata->rate;
1671 sel = cdata->eq_sel;
1672
1673 best = 0;
1674 best_val = INT_MAX;
1675 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1676 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1677 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1678 best = i;
1679 best_val = abs(pdata->eq_cfg[i].rate - fs);
1680 }
1681 }
1682
1683 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1684 pdata->eq_cfg[best].name,
1685 pdata->eq_cfg[best].rate, fs);
1686
1687 /* Disable EQ while configuring, and save current on/off state */
1688 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL);
1689 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0);
1690
1691 coef_set = &pdata->eq_cfg[sel];
1692
1693 m98088_eq_band(codec, 0, 0, coef_set->band1);
1694 m98088_eq_band(codec, 0, 1, coef_set->band2);
1695 m98088_eq_band(codec, 0, 2, coef_set->band3);
1696 m98088_eq_band(codec, 0, 3, coef_set->band4);
1697 m98088_eq_band(codec, 0, 4, coef_set->band5);
1698
1699 /* Restore the original on/off state */
1700 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save);
1701}
1702
1703static void max98088_setup_eq2(struct snd_soc_codec *codec)
1704{
1705 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1706 struct max98088_pdata *pdata = max98088->pdata;
1707 struct max98088_eq_cfg *coef_set;
1708 int best, best_val, save, i, sel, fs;
1709 struct max98088_cdata *cdata;
1710
1711 cdata = &max98088->dai[1];
1712
1713 if (!pdata || !max98088->eq_textcnt)
1714 return;
1715
1716 /* Find the selected configuration with nearest sample rate */
1717 fs = cdata->rate;
1718
1719 sel = cdata->eq_sel;
1720 best = 0;
1721 best_val = INT_MAX;
1722 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1723 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1724 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1725 best = i;
1726 best_val = abs(pdata->eq_cfg[i].rate - fs);
1727 }
1728 }
1729
1730 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1731 pdata->eq_cfg[best].name,
1732 pdata->eq_cfg[best].rate, fs);
1733
1734 /* Disable EQ while configuring, and save current on/off state */
1735 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL);
1736 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0);
1737
1738 coef_set = &pdata->eq_cfg[sel];
1739
1740 m98088_eq_band(codec, 1, 0, coef_set->band1);
1741 m98088_eq_band(codec, 1, 1, coef_set->band2);
1742 m98088_eq_band(codec, 1, 2, coef_set->band3);
1743 m98088_eq_band(codec, 1, 3, coef_set->band4);
1744 m98088_eq_band(codec, 1, 4, coef_set->band5);
1745
1746 /* Restore the original on/off state */
1747 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN,
1748 save);
1749}
1750
1751static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol,
1752 struct snd_ctl_elem_value *ucontrol)
1753{
1754 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1755 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1756 struct max98088_pdata *pdata = max98088->pdata;
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1757 int channel = max98088_get_channel(codec, kcontrol->id.name);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1758 struct max98088_cdata *cdata;
1759 int sel = ucontrol->value.integer.value[0];
1760
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1761 if (channel < 0)
1762 return channel;
1763
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1764 cdata = &max98088->dai[channel];
1765
1766 if (sel >= pdata->eq_cfgcnt)
1767 return -EINVAL;
1768
1769 cdata->eq_sel = sel;
1770
1771 switch (channel) {
1772 case 0:
1773 max98088_setup_eq1(codec);
1774 break;
1775 case 1:
1776 max98088_setup_eq2(codec);
1777 break;
1778 }
1779
1780 return 0;
1781}
1782
1783static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol,
1784 struct snd_ctl_elem_value *ucontrol)
1785{
1786 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1787 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1788 int channel = max98088_get_channel(codec, kcontrol->id.name);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1789 struct max98088_cdata *cdata;
1790
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1791 if (channel < 0)
1792 return channel;
1793
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1794 cdata = &max98088->dai[channel];
1795 ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1796 return 0;
1797}
1798
1799static void max98088_handle_eq_pdata(struct snd_soc_codec *codec)
1800{
1801 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1802 struct max98088_pdata *pdata = max98088->pdata;
1803 struct max98088_eq_cfg *cfg;
1804 unsigned int cfgcnt;
1805 int i, j;
1806 const char **t;
1807 int ret;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1808 struct snd_kcontrol_new controls[] = {
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1809 SOC_ENUM_EXT((char *)eq_mode_name[0],
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1810 max98088->eq_enum,
1811 max98088_get_eq_enum,
1812 max98088_put_eq_enum),
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1813 SOC_ENUM_EXT((char *)eq_mode_name[1],
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1814 max98088->eq_enum,
1815 max98088_get_eq_enum,
1816 max98088_put_eq_enum),
1817 };
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1818 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(eq_mode_name));
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1819
1820 cfg = pdata->eq_cfg;
1821 cfgcnt = pdata->eq_cfgcnt;
1822
1823 /* Setup an array of texts for the equalizer enum.
1824 * This is based on Mark Brown's equalizer driver code.
1825 */
1826 max98088->eq_textcnt = 0;
1827 max98088->eq_texts = NULL;
1828 for (i = 0; i < cfgcnt; i++) {
1829 for (j = 0; j < max98088->eq_textcnt; j++) {
1830 if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0)
1831 break;
1832 }
1833
1834 if (j != max98088->eq_textcnt)
1835 continue;
1836
1837 /* Expand the array */
1838 t = krealloc(max98088->eq_texts,
1839 sizeof(char *) * (max98088->eq_textcnt + 1),
1840 GFP_KERNEL);
1841 if (t == NULL)
1842 continue;
1843
1844 /* Store the new entry */
1845 t[max98088->eq_textcnt] = cfg[i].name;
1846 max98088->eq_textcnt++;
1847 max98088->eq_texts = t;
1848 }
1849
1850 /* Now point the soc_enum to .texts array items */
1851 max98088->eq_enum.texts = max98088->eq_texts;
1852 max98088->eq_enum.max = max98088->eq_textcnt;
1853
Liam Girdwood022658b2012-02-03 17:43:09 +0000[diff] [blame]1854 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1855 if (ret != 0)
1856 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret);
1857}
1858
1859static void max98088_handle_pdata(struct snd_soc_codec *codec)
1860{
1861 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1862 struct max98088_pdata *pdata = max98088->pdata;
1863 u8 regval = 0;
1864
1865 if (!pdata) {
1866 dev_dbg(codec->dev, "No platform data\n");
1867 return;
1868 }
1869
1870 /* Configure mic for analog/digital mic mode */
1871 if (pdata->digmic_left_mode)
1872 regval |= M98088_DIGMIC_L;
1873
1874 if (pdata->digmic_right_mode)
1875 regval |= M98088_DIGMIC_R;
1876
1877 max98088->digmic = (regval ? 1 : 0);
1878
1879 snd_soc_write(codec, M98088_REG_48_CFG_MIC, regval);
1880
1881 /* Configure receiver output */
1882 regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0);
1883 snd_soc_update_bits(codec, M98088_REG_2A_MIC_REC_CNTL,
1884 M98088_REC_LINEMODE_MASK, regval);
1885
1886 /* Configure equalizers */
1887 if (pdata->eq_cfgcnt)
1888 max98088_handle_eq_pdata(codec);
1889}
1890
1891#ifdef CONFIG_PM
Lars-Peter Clausen84b315e2011-12-02 10:18:28 +0100[diff] [blame]1892static int max98088_suspend(struct snd_soc_codec *codec)
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1893{
1894 max98088_set_bias_level(codec, SND_SOC_BIAS_OFF);
1895
1896 return 0;
1897}
1898
1899static int max98088_resume(struct snd_soc_codec *codec)
1900{
1901 max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1902
1903 return 0;
1904}
1905#else
1906#define max98088_suspend NULL
1907#define max98088_resume NULL
1908#endif
1909
1910static int max98088_probe(struct snd_soc_codec *codec)
1911{
1912 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1913 struct max98088_cdata *cdata;
1914 int ret = 0;
1915
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1916 regcache_mark_dirty(max98088->regmap);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1917
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1918 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1919 if (ret != 0) {
1920 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1921 return ret;
1922 }
1923
Uwe Kleine-Königb5950762010-11-01 15:38:34 -0400[diff] [blame]1924 /* initialize private data */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1925
1926 max98088->sysclk = (unsigned)-1;
1927 max98088->eq_textcnt = 0;
1928
1929 cdata = &max98088->dai[0];
1930 cdata->rate = (unsigned)-1;
1931 cdata->fmt = (unsigned)-1;
1932 cdata->eq_sel = 0;
1933
1934 cdata = &max98088->dai[1];
1935 cdata->rate = (unsigned)-1;
1936 cdata->fmt = (unsigned)-1;
1937 cdata->eq_sel = 0;
1938
1939 max98088->ina_state = 0;
1940 max98088->inb_state = 0;
1941 max98088->ex_mode = 0;
1942 max98088->digmic = 0;
1943 max98088->mic1pre = 0;
1944 max98088->mic2pre = 0;
1945
1946 ret = snd_soc_read(codec, M98088_REG_FF_REV_ID);
1947 if (ret < 0) {
1948 dev_err(codec->dev, "Failed to read device revision: %d\n",
1949 ret);
1950 goto err_access;
1951 }
Dylan Reid98682062013-04-16 20:02:34 -0700[diff] [blame]1952 dev_info(codec->dev, "revision %c\n", ret - 0x40 + 'A');
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1953
1954 snd_soc_write(codec, M98088_REG_51_PWR_SYS, M98088_PWRSV);
1955
1956 /* initialize registers cache to hardware default */
1957 max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1958
1959 snd_soc_write(codec, M98088_REG_0F_IRQ_ENABLE, 0x00);
1960
1961 snd_soc_write(codec, M98088_REG_22_MIX_DAC,
1962 M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL|
1963 M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR);
1964
1965 snd_soc_write(codec, M98088_REG_4E_BIAS_CNTL, 0xF0);
1966 snd_soc_write(codec, M98088_REG_50_DAC_BIAS2, 0x0F);
1967
1968 snd_soc_write(codec, M98088_REG_16_DAI1_IOCFG,
1969 M98088_S1NORMAL|M98088_SDATA);
1970
1971 snd_soc_write(codec, M98088_REG_1E_DAI2_IOCFG,
1972 M98088_S2NORMAL|M98088_SDATA);
1973
1974 max98088_handle_pdata(codec);
1975
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1976err_access:
1977 return ret;
1978}
1979
1980static int max98088_remove(struct snd_soc_codec *codec)
1981{
Axel Linbc5954f2010-11-23 15:56:21 +0800[diff] [blame]1982 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1983
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1984 max98088_set_bias_level(codec, SND_SOC_BIAS_OFF);
Axel Linbc5954f2010-11-23 15:56:21 +0800[diff] [blame]1985 kfree(max98088->eq_texts);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1986
1987 return 0;
1988}
1989
1990static struct snd_soc_codec_driver soc_codec_dev_max98088 = {
Mark Brown356d86e2013-09-23 17:22:17 +0100[diff] [blame]1991 .probe = max98088_probe,
1992 .remove = max98088_remove,
1993 .suspend = max98088_suspend,
1994 .resume = max98088_resume,
1995 .set_bias_level = max98088_set_bias_level,
Mark Brownad65adf2013-09-23 17:54:02 +0100[diff] [blame]1996 .controls = max98088_snd_controls,
1997 .num_controls = ARRAY_SIZE(max98088_snd_controls),
Lu Guanqundc6fc492011-03-30 21:53:10 +0800[diff] [blame]1998 .dapm_widgets = max98088_dapm_widgets,
1999 .num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets),
2000 .dapm_routes = max98088_audio_map,
2001 .num_dapm_routes = ARRAY_SIZE(max98088_audio_map),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2002};
2003
2004static int max98088_i2c_probe(struct i2c_client *i2c,
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]2005 const struct i2c_device_id *id)
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2006{
2007 struct max98088_priv *max98088;
2008 int ret;
2009
Axel Lin49ba7672011-12-29 12:01:07 +0800[diff] [blame]2010 max98088 = devm_kzalloc(&i2c->dev, sizeof(struct max98088_priv),
2011 GFP_KERNEL);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2012 if (max98088 == NULL)
2013 return -ENOMEM;
2014
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]2015 max98088->regmap = devm_regmap_init_i2c(i2c, &max98088_regmap);
2016 if (IS_ERR(max98088->regmap))
2017 return PTR_ERR(max98088->regmap);
2018
Jesse Marroquinfb762a52010-11-17 14:26:40 -0600[diff] [blame]2019 max98088->devtype = id->driver_data;
2020
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2021 i2c_set_clientdata(i2c, max98088);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2022 max98088->pdata = i2c->dev.platform_data;
2023
2024 ret = snd_soc_register_codec(&i2c->dev,
2025 &soc_codec_dev_max98088, &max98088_dai[0], 2);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2026 return ret;
2027}
2028
Bill Pemberton7a79e942012-12-07 09:26:37 -0500[diff] [blame]2029static int max98088_i2c_remove(struct i2c_client *client)
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2030{
2031 snd_soc_unregister_codec(&client->dev);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2032 return 0;
2033}
2034
2035static const struct i2c_device_id max98088_i2c_id[] = {
Jesse Marroquinfb762a52010-11-17 14:26:40 -0600[diff] [blame]2036 { "max98088", MAX98088 },
2037 { "max98089", MAX98089 },
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2038 { }
2039};
2040MODULE_DEVICE_TABLE(i2c, max98088_i2c_id);
2041
2042static struct i2c_driver max98088_i2c_driver = {
Bill Pemberton69395652012-11-19 13:19:39 -0500[diff] [blame]2043 .driver = {
2044 .name = "max98088",
2045 .owner = THIS_MODULE,
2046 },
2047 .probe = max98088_i2c_probe,
2048 .remove = max98088_i2c_remove,
2049 .id_table = max98088_i2c_id,
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2050};
2051
Sachin Kamat2342a072012-08-06 17:25:51 +0530[diff] [blame]2052module_i2c_driver(max98088_i2c_driver);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2053
2054MODULE_DESCRIPTION("ALSA SoC MAX98088 driver");
2055MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin");
2056MODULE_LICENSE("GPL");