Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * s3c2443-ac97.c -- ALSA Soc Audio Layer |
| 3 | * |
| 4 | * (c) 2007 Wolfson Microelectronics PLC. |
| 5 | * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com |
| 6 | * |
| 7 | * Copyright (C) 2005, Sean Choi <sh428.choi@samsung.com> |
| 8 | * All rights reserved. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/interrupt.h> |
Mark Brown | ccfdd6c | 2008-04-30 17:19:07 +0200 | [diff] [blame] | 19 | #include <linux/io.h> |
Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 20 | #include <linux/wait.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/clk.h> |
| 23 | |
Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 24 | #include <sound/core.h> |
| 25 | #include <sound/pcm.h> |
| 26 | #include <sound/ac97_codec.h> |
| 27 | #include <sound/initval.h> |
| 28 | #include <sound/soc.h> |
| 29 | |
| 30 | #include <asm/hardware.h> |
Krzysztof Helt | 1700139 | 2007-10-19 08:23:00 +0200 | [diff] [blame] | 31 | #include <asm/plat-s3c/regs-ac97.h> |
Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 32 | #include <asm/arch/regs-gpio.h> |
| 33 | #include <asm/arch/regs-clock.h> |
| 34 | #include <asm/arch/audio.h> |
| 35 | #include <asm/dma.h> |
| 36 | #include <asm/arch/dma.h> |
| 37 | |
| 38 | #include "s3c24xx-pcm.h" |
| 39 | #include "s3c24xx-ac97.h" |
| 40 | |
| 41 | struct s3c24xx_ac97_info { |
| 42 | void __iomem *regs; |
| 43 | struct clk *ac97_clk; |
| 44 | }; |
| 45 | static struct s3c24xx_ac97_info s3c24xx_ac97; |
| 46 | |
Mark Brown | ccfdd6c | 2008-04-30 17:19:07 +0200 | [diff] [blame] | 47 | static DECLARE_COMPLETION(ac97_completion); |
Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 48 | static u32 codec_ready; |
| 49 | static DECLARE_MUTEX(ac97_mutex); |
| 50 | |
| 51 | static unsigned short s3c2443_ac97_read(struct snd_ac97 *ac97, |
| 52 | unsigned short reg) |
| 53 | { |
| 54 | u32 ac_glbctrl; |
| 55 | u32 ac_codec_cmd; |
| 56 | u32 stat, addr, data; |
| 57 | |
| 58 | down(&ac97_mutex); |
| 59 | |
| 60 | codec_ready = S3C_AC97_GLBSTAT_CODECREADY; |
| 61 | ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); |
| 62 | ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg); |
| 63 | writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); |
| 64 | |
| 65 | udelay(50); |
| 66 | |
| 67 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 68 | ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE; |
| 69 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 70 | |
| 71 | wait_for_completion(&ac97_completion); |
| 72 | |
| 73 | stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT); |
| 74 | addr = (stat >> 16) & 0x7f; |
| 75 | data = (stat & 0xffff); |
| 76 | |
| 77 | if (addr != reg) |
| 78 | printk(KERN_ERR "s3c24xx-ac97: req addr = %02x," |
| 79 | " rep addr = %02x\n", reg, addr); |
| 80 | |
| 81 | up(&ac97_mutex); |
| 82 | |
| 83 | return (unsigned short)data; |
| 84 | } |
| 85 | |
| 86 | static void s3c2443_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
| 87 | unsigned short val) |
| 88 | { |
| 89 | u32 ac_glbctrl; |
| 90 | u32 ac_codec_cmd; |
| 91 | |
| 92 | down(&ac97_mutex); |
| 93 | |
| 94 | codec_ready = S3C_AC97_GLBSTAT_CODECREADY; |
| 95 | ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); |
| 96 | ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val); |
| 97 | writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); |
| 98 | |
| 99 | udelay(50); |
| 100 | |
| 101 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 102 | ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE; |
| 103 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 104 | |
| 105 | wait_for_completion(&ac97_completion); |
| 106 | |
| 107 | ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); |
| 108 | ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ; |
| 109 | writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); |
| 110 | |
| 111 | up(&ac97_mutex); |
| 112 | |
| 113 | } |
| 114 | |
| 115 | static void s3c2443_ac97_warm_reset(struct snd_ac97 *ac97) |
| 116 | { |
| 117 | u32 ac_glbctrl; |
| 118 | |
| 119 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 120 | ac_glbctrl = S3C_AC97_GLBCTRL_WARMRESET; |
| 121 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 122 | msleep(1); |
| 123 | |
| 124 | ac_glbctrl = 0; |
| 125 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 126 | msleep(1); |
| 127 | } |
| 128 | |
| 129 | static void s3c2443_ac97_cold_reset(struct snd_ac97 *ac97) |
| 130 | { |
| 131 | u32 ac_glbctrl; |
| 132 | |
| 133 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 134 | ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET; |
| 135 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 136 | msleep(1); |
| 137 | |
| 138 | ac_glbctrl = 0; |
| 139 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 140 | msleep(1); |
| 141 | |
| 142 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 143 | ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON; |
| 144 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 145 | msleep(1); |
| 146 | |
| 147 | ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE; |
| 148 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 149 | msleep(1); |
| 150 | |
| 151 | ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA | |
| 152 | S3C_AC97_GLBCTRL_PCMINTM_DMA | S3C_AC97_GLBCTRL_MICINTM_DMA; |
| 153 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 154 | } |
| 155 | |
| 156 | static irqreturn_t s3c2443_ac97_irq(int irq, void *dev_id) |
| 157 | { |
| 158 | int status; |
| 159 | u32 ac_glbctrl; |
| 160 | |
| 161 | status = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT) & codec_ready; |
| 162 | |
| 163 | if (status) { |
| 164 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 165 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE; |
| 166 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 167 | complete(&ac97_completion); |
| 168 | } |
| 169 | return IRQ_HANDLED; |
| 170 | } |
| 171 | |
| 172 | struct snd_ac97_bus_ops soc_ac97_ops = { |
| 173 | .read = s3c2443_ac97_read, |
| 174 | .write = s3c2443_ac97_write, |
| 175 | .warm_reset = s3c2443_ac97_warm_reset, |
| 176 | .reset = s3c2443_ac97_cold_reset, |
| 177 | }; |
| 178 | |
| 179 | static struct s3c2410_dma_client s3c2443_dma_client_out = { |
| 180 | .name = "AC97 PCM Stereo out" |
| 181 | }; |
| 182 | |
| 183 | static struct s3c2410_dma_client s3c2443_dma_client_in = { |
| 184 | .name = "AC97 PCM Stereo in" |
| 185 | }; |
| 186 | |
| 187 | static struct s3c2410_dma_client s3c2443_dma_client_micin = { |
| 188 | .name = "AC97 Mic Mono in" |
| 189 | }; |
| 190 | |
| 191 | static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_out = { |
| 192 | .client = &s3c2443_dma_client_out, |
| 193 | .channel = DMACH_PCM_OUT, |
| 194 | .dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA, |
| 195 | .dma_size = 4, |
| 196 | }; |
| 197 | |
| 198 | static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_in = { |
| 199 | .client = &s3c2443_dma_client_in, |
| 200 | .channel = DMACH_PCM_IN, |
| 201 | .dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA, |
| 202 | .dma_size = 4, |
| 203 | }; |
| 204 | |
| 205 | static struct s3c24xx_pcm_dma_params s3c2443_ac97_mic_mono_in = { |
| 206 | .client = &s3c2443_dma_client_micin, |
| 207 | .channel = DMACH_MIC_IN, |
| 208 | .dma_addr = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA, |
| 209 | .dma_size = 4, |
| 210 | }; |
| 211 | |
Mark Brown | bdb9287 | 2008-06-11 13:47:10 +0100 | [diff] [blame] | 212 | static int s3c2443_ac97_probe(struct platform_device *pdev, |
Liam Girdwood | 1992a6f | 2008-07-07 16:08:24 +0100 | [diff] [blame] | 213 | struct snd_soc_dai *dai) |
Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 214 | { |
| 215 | int ret; |
| 216 | u32 ac_glbctrl; |
| 217 | |
| 218 | s3c24xx_ac97.regs = ioremap(S3C2440_PA_AC97, 0x100); |
| 219 | if (s3c24xx_ac97.regs == NULL) |
| 220 | return -ENXIO; |
| 221 | |
| 222 | s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97"); |
| 223 | if (s3c24xx_ac97.ac97_clk == NULL) { |
| 224 | printk(KERN_ERR "s3c2443-ac97 failed to get ac97_clock\n"); |
| 225 | iounmap(s3c24xx_ac97.regs); |
| 226 | return -ENODEV; |
| 227 | } |
| 228 | clk_enable(s3c24xx_ac97.ac97_clk); |
| 229 | |
| 230 | s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2443_GPE0_AC_nRESET); |
| 231 | s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2443_GPE1_AC_SYNC); |
| 232 | s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2443_GPE2_AC_BITCLK); |
| 233 | s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2443_GPE3_AC_SDI); |
| 234 | s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2443_GPE4_AC_SDO); |
| 235 | |
| 236 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 237 | ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET; |
| 238 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 239 | msleep(1); |
| 240 | |
| 241 | ac_glbctrl = 0; |
| 242 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 243 | msleep(1); |
| 244 | |
| 245 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 246 | ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON; |
| 247 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 248 | msleep(1); |
| 249 | |
| 250 | ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE; |
| 251 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 252 | |
Ivan Kuten | 040956f | 2007-10-26 14:53:47 +0200 | [diff] [blame] | 253 | ret = request_irq(IRQ_S3C244x_AC97, s3c2443_ac97_irq, |
Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 254 | IRQF_DISABLED, "AC97", NULL); |
| 255 | if (ret < 0) { |
| 256 | printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n"); |
| 257 | clk_disable(s3c24xx_ac97.ac97_clk); |
| 258 | clk_put(s3c24xx_ac97.ac97_clk); |
| 259 | iounmap(s3c24xx_ac97.regs); |
| 260 | } |
| 261 | return ret; |
| 262 | } |
| 263 | |
Mark Brown | bdb9287 | 2008-06-11 13:47:10 +0100 | [diff] [blame] | 264 | static void s3c2443_ac97_remove(struct platform_device *pdev, |
Liam Girdwood | 1992a6f | 2008-07-07 16:08:24 +0100 | [diff] [blame] | 265 | struct snd_soc_dai *dai) |
Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 266 | { |
Ivan Kuten | 040956f | 2007-10-26 14:53:47 +0200 | [diff] [blame] | 267 | free_irq(IRQ_S3C244x_AC97, NULL); |
Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 268 | clk_disable(s3c24xx_ac97.ac97_clk); |
| 269 | clk_put(s3c24xx_ac97.ac97_clk); |
| 270 | iounmap(s3c24xx_ac97.regs); |
| 271 | } |
| 272 | |
| 273 | static int s3c2443_ac97_hw_params(struct snd_pcm_substream *substream, |
| 274 | struct snd_pcm_hw_params *params) |
| 275 | { |
| 276 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
Liam Girdwood | 1992a6f | 2008-07-07 16:08:24 +0100 | [diff] [blame] | 277 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 278 | |
| 279 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 280 | cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_out; |
| 281 | else |
| 282 | cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_in; |
| 283 | |
| 284 | return 0; |
| 285 | } |
| 286 | |
| 287 | static int s3c2443_ac97_trigger(struct snd_pcm_substream *substream, int cmd) |
| 288 | { |
| 289 | u32 ac_glbctrl; |
| 290 | |
| 291 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
Mark Brown | ccfdd6c | 2008-04-30 17:19:07 +0200 | [diff] [blame] | 292 | switch (cmd) { |
Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 293 | case SNDRV_PCM_TRIGGER_START: |
| 294 | case SNDRV_PCM_TRIGGER_RESUME: |
| 295 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
| 296 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
| 297 | ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA; |
| 298 | else |
| 299 | ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA; |
| 300 | break; |
| 301 | case SNDRV_PCM_TRIGGER_STOP: |
| 302 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 303 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
| 304 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
| 305 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK; |
| 306 | else |
| 307 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK; |
| 308 | break; |
| 309 | } |
| 310 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 311 | |
| 312 | return 0; |
| 313 | } |
| 314 | |
| 315 | static int s3c2443_ac97_hw_mic_params(struct snd_pcm_substream *substream, |
| 316 | struct snd_pcm_hw_params *params) |
| 317 | { |
| 318 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
Liam Girdwood | 1992a6f | 2008-07-07 16:08:24 +0100 | [diff] [blame] | 319 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 320 | |
| 321 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 322 | return -ENODEV; |
| 323 | else |
| 324 | cpu_dai->dma_data = &s3c2443_ac97_mic_mono_in; |
| 325 | |
| 326 | return 0; |
| 327 | } |
| 328 | |
| 329 | static int s3c2443_ac97_mic_trigger(struct snd_pcm_substream *substream, |
| 330 | int cmd) |
| 331 | { |
| 332 | u32 ac_glbctrl; |
| 333 | |
| 334 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
Mark Brown | ccfdd6c | 2008-04-30 17:19:07 +0200 | [diff] [blame] | 335 | switch (cmd) { |
Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 336 | case SNDRV_PCM_TRIGGER_START: |
| 337 | case SNDRV_PCM_TRIGGER_RESUME: |
| 338 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
| 339 | ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA; |
| 340 | break; |
| 341 | case SNDRV_PCM_TRIGGER_STOP: |
| 342 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 343 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
| 344 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK; |
| 345 | } |
| 346 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); |
| 347 | |
| 348 | return 0; |
| 349 | } |
| 350 | |
| 351 | #define s3c2443_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ |
| 352 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ |
| 353 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) |
| 354 | |
Liam Girdwood | 1992a6f | 2008-07-07 16:08:24 +0100 | [diff] [blame] | 355 | struct snd_soc_dai s3c2443_ac97_dai[] = { |
Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 356 | { |
| 357 | .name = "s3c2443-ac97", |
| 358 | .id = 0, |
| 359 | .type = SND_SOC_DAI_AC97, |
| 360 | .probe = s3c2443_ac97_probe, |
| 361 | .remove = s3c2443_ac97_remove, |
| 362 | .playback = { |
| 363 | .stream_name = "AC97 Playback", |
| 364 | .channels_min = 2, |
| 365 | .channels_max = 2, |
| 366 | .rates = s3c2443_AC97_RATES, |
| 367 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, |
| 368 | .capture = { |
| 369 | .stream_name = "AC97 Capture", |
| 370 | .channels_min = 2, |
| 371 | .channels_max = 2, |
| 372 | .rates = s3c2443_AC97_RATES, |
| 373 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, |
| 374 | .ops = { |
| 375 | .hw_params = s3c2443_ac97_hw_params, |
| 376 | .trigger = s3c2443_ac97_trigger}, |
| 377 | }, |
| 378 | { |
| 379 | .name = "pxa2xx-ac97-mic", |
| 380 | .id = 1, |
| 381 | .type = SND_SOC_DAI_AC97, |
| 382 | .capture = { |
| 383 | .stream_name = "AC97 Mic Capture", |
| 384 | .channels_min = 1, |
| 385 | .channels_max = 1, |
| 386 | .rates = s3c2443_AC97_RATES, |
| 387 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, |
| 388 | .ops = { |
| 389 | .hw_params = s3c2443_ac97_hw_mic_params, |
| 390 | .trigger = s3c2443_ac97_mic_trigger,}, |
| 391 | }, |
| 392 | }; |
Graeme Gregory | 050f05e | 2007-05-14 11:02:51 +0200 | [diff] [blame] | 393 | EXPORT_SYMBOL_GPL(s3c2443_ac97_dai); |
| 394 | EXPORT_SYMBOL_GPL(soc_ac97_ops); |
| 395 | |
| 396 | MODULE_AUTHOR("Graeme Gregory"); |
| 397 | MODULE_DESCRIPTION("AC97 driver for the Samsung s3c2443 chip"); |
| 398 | MODULE_LICENSE("GPL"); |