Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 1 | #ifndef WILC_WLAN_H |
| 2 | #define WILC_WLAN_H |
| 3 | |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 4 | |
| 5 | |
| 6 | #define ISWILC1000(id) (((id & 0xfffff000) == 0x100000) ? 1 : 0) |
| 7 | |
| 8 | |
| 9 | /******************************************** |
| 10 | * |
| 11 | * Mac eth header length |
| 12 | * |
| 13 | ********************************************/ |
| 14 | #define DRIVER_HANDLER_SIZE 4 |
| 15 | #define MAX_MAC_HDR_LEN 26 /* QOS_MAC_HDR_LEN */ |
| 16 | #define SUB_MSDU_HEADER_LENGTH 14 |
| 17 | #define SNAP_HDR_LEN 8 |
| 18 | #define ETHERNET_HDR_LEN 14 |
| 19 | #define WORD_ALIGNMENT_PAD 0 |
| 20 | |
| 21 | #define ETH_ETHERNET_HDR_OFFSET (MAX_MAC_HDR_LEN + SUB_MSDU_HEADER_LENGTH + \ |
| 22 | SNAP_HDR_LEN - ETHERNET_HDR_LEN + WORD_ALIGNMENT_PAD) |
| 23 | |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 24 | #define HOST_HDR_OFFSET 4 |
| 25 | #define ETHERNET_HDR_LEN 14 |
| 26 | #define IP_HDR_LEN 20 |
| 27 | #define IP_HDR_OFFSET ETHERNET_HDR_LEN |
| 28 | #define UDP_HDR_OFFSET (IP_HDR_LEN + IP_HDR_OFFSET) |
| 29 | #define UDP_HDR_LEN 8 |
| 30 | #define UDP_DATA_OFFSET (UDP_HDR_OFFSET + UDP_HDR_LEN) |
| 31 | #define ETH_CONFIG_PKT_HDR_LEN UDP_DATA_OFFSET |
| 32 | |
| 33 | #define ETH_CONFIG_PKT_HDR_OFFSET (ETH_ETHERNET_HDR_OFFSET + \ |
| 34 | ETH_CONFIG_PKT_HDR_LEN) |
| 35 | #define ACTION 0xD0 |
| 36 | #define PROBE_REQ 0x40 |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 37 | |
| 38 | /******************************************** |
| 39 | * |
| 40 | * Endian Conversion |
| 41 | * |
| 42 | ********************************************/ |
| 43 | |
| 44 | #define BYTE_SWAP(val) ((((val) & 0x000000FF) << 24) + \ |
| 45 | (((val) & 0x0000FF00) << 8) + \ |
| 46 | (((val) & 0x00FF0000) >> 8) + \ |
| 47 | (((val) & 0xFF000000) >> 24)) |
| 48 | |
| 49 | /******************************************** |
| 50 | * |
| 51 | * Register Defines |
| 52 | * |
| 53 | ********************************************/ |
| 54 | #define WILC_PERIPH_REG_BASE 0x1000 |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 55 | #define WILC_CHANGING_VIR_IF (0x108c) |
| 56 | #define WILC_CHIPID (WILC_PERIPH_REG_BASE) |
| 57 | #define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400) |
| 58 | #define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408) |
| 59 | #define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c) |
| 60 | #define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70) |
| 61 | #define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74) |
| 62 | #define WILC_HOST_VMM_CTL (WILC_PERIPH_REG_BASE + 0x78) |
| 63 | #define WILC_HOST_RX_CTRL (WILC_PERIPH_REG_BASE + 0x80) |
| 64 | #define WILC_HOST_RX_EXTRA_SIZE (WILC_PERIPH_REG_BASE + 0x84) |
| 65 | #define WILC_HOST_TX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x88) |
| 66 | #define WILC_MISC (WILC_PERIPH_REG_BASE + 0x428) |
| 67 | #define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00) |
| 68 | #define WILC_INTR_ENABLE (WILC_INTR_REG_BASE) |
| 69 | #define WILC_INTR2_ENABLE (WILC_INTR_REG_BASE + 4) |
| 70 | |
| 71 | #define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10) |
| 72 | #define WILC_INTR_TYPE (WILC_INTR_REG_BASE + 0x20) |
| 73 | #define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30) |
| 74 | #define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40) |
| 75 | |
| 76 | #define WILC_VMM_TBL_SIZE 64 |
| 77 | #define WILC_VMM_TX_TBL_BASE (0x150400) |
| 78 | #define WILC_VMM_RX_TBL_BASE (0x150500) |
| 79 | |
| 80 | #define WILC_VMM_BASE 0x150000 |
| 81 | #define WILC_VMM_CORE_CTL (WILC_VMM_BASE) |
| 82 | #define WILC_VMM_TBL_CTL (WILC_VMM_BASE + 0x4) |
| 83 | #define WILC_VMM_TBL_ENTRY (WILC_VMM_BASE + 0x8) |
| 84 | #define WILC_VMM_TBL0_SIZE (WILC_VMM_BASE + 0xc) |
| 85 | #define WILC_VMM_TO_HOST_SIZE (WILC_VMM_BASE + 0x10) |
| 86 | #define WILC_VMM_CORE_CFG (WILC_VMM_BASE + 0x14) |
| 87 | #define WILC_VMM_TBL_ACTIVE (WILC_VMM_BASE + 040) |
| 88 | #define WILC_VMM_TBL_STATUS (WILC_VMM_BASE + 0x44) |
| 89 | |
| 90 | #define WILC_SPI_REG_BASE 0xe800 |
| 91 | #define WILC_SPI_CTL (WILC_SPI_REG_BASE) |
| 92 | #define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4) |
| 93 | #define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8) |
| 94 | #define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc) |
| 95 | #define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10) |
| 96 | #define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20) |
| 97 | #define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24) |
| 98 | #define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c) |
| 99 | |
| 100 | #define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - WILC_SPI_REG_BASE) |
| 101 | |
| 102 | #define WILC_AHB_DATA_MEM_BASE 0x30000 |
| 103 | #define WILC_AHB_SHARE_MEM_BASE 0xd0000 |
| 104 | |
Chaehyun Lim | c3ca637 | 2015-09-20 15:51:19 +0900 | [diff] [blame] | 105 | #define WILC_VMM_TBL_RX_SHADOW_BASE WILC_AHB_SHARE_MEM_BASE |
| 106 | #define WILC_VMM_TBL_RX_SHADOW_SIZE (256) |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 107 | |
| 108 | #define WILC_GP_REG_0 0x149c |
| 109 | #define WILC_GP_REG_1 0x14a0 |
| 110 | |
| 111 | #define rHAVE_SDIO_IRQ_GPIO_BIT (0) |
| 112 | #define rHAVE_USE_PMU_BIT (1) |
| 113 | #define rHAVE_SLEEP_CLK_SRC_RTC_BIT (2) |
| 114 | #define rHAVE_SLEEP_CLK_SRC_XO_BIT (3) |
| 115 | #define rHAVE_EXT_PA_INV_TX_RX_BIT (4) |
| 116 | #define rHAVE_LEGACY_RF_SETTINGS_BIT (5) |
| 117 | #define rHAVE_XTAL_24_BIT (6) |
| 118 | #define rHAVE_DISABLE_WILC_UART_BIT (7) |
| 119 | |
| 120 | |
| 121 | #define WILC_HAVE_SDIO_IRQ_GPIO (1 << rHAVE_SDIO_IRQ_GPIO_BIT) |
| 122 | #define WILC_HAVE_USE_PMU (1 << rHAVE_USE_PMU_BIT) |
| 123 | #define WILC_HAVE_SLEEP_CLK_SRC_RTC (1 << rHAVE_SLEEP_CLK_SRC_RTC_BIT) |
| 124 | #define WILC_HAVE_SLEEP_CLK_SRC_XO (1 << rHAVE_SLEEP_CLK_SRC_XO_BIT) |
| 125 | #define WILC_HAVE_EXT_PA_INV_TX_RX (1 << rHAVE_EXT_PA_INV_TX_RX_BIT) |
| 126 | #define WILC_HAVE_LEGACY_RF_SETTINGS (1 << rHAVE_LEGACY_RF_SETTINGS_BIT) |
| 127 | #define WILC_HAVE_XTAL_24 (1 << rHAVE_XTAL_24_BIT) |
| 128 | #define WILC_HAVE_DISABLE_WILC_UART (1 << rHAVE_DISABLE_WILC_UART_BIT) |
| 129 | |
| 130 | |
| 131 | /******************************************** |
| 132 | * |
| 133 | * Wlan Defines |
| 134 | * |
| 135 | ********************************************/ |
| 136 | #define WILC_CFG_PKT 1 |
| 137 | #define WILC_NET_PKT 0 |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 138 | #define WILC_MGMT_PKT 2 |
| 139 | |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 140 | #define WILC_CFG_SET 1 |
| 141 | #define WILC_CFG_QUERY 0 |
| 142 | |
| 143 | #define WILC_CFG_RSP 1 |
| 144 | #define WILC_CFG_RSP_STATUS 2 |
| 145 | #define WILC_CFG_RSP_SCAN 3 |
| 146 | |
| 147 | #ifdef WILC_SDIO |
| 148 | #define WILC_PLL_TO 4 |
| 149 | #else |
| 150 | #define WILC_PLL_TO 2 |
| 151 | #endif |
| 152 | |
| 153 | |
Anish Bhatt | ffda203 | 2015-09-29 12:15:49 -0700 | [diff] [blame] | 154 | #define ABORT_INT BIT(31) |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 155 | |
| 156 | /*******************************************/ |
| 157 | /* E0 and later Interrupt flags. */ |
| 158 | /*******************************************/ |
| 159 | /*******************************************/ |
| 160 | /* E0 and later Interrupt flags. */ |
| 161 | /* IRQ Status word */ |
| 162 | /* 15:0 = DMA count in words. */ |
| 163 | /* 16: INT0 flag */ |
| 164 | /* 17: INT1 flag */ |
| 165 | /* 18: INT2 flag */ |
| 166 | /* 19: INT3 flag */ |
| 167 | /* 20: INT4 flag */ |
| 168 | /* 21: INT5 flag */ |
| 169 | /*******************************************/ |
| 170 | #define IRG_FLAGS_OFFSET 16 |
| 171 | #define IRQ_DMA_WD_CNT_MASK ((1ul << IRG_FLAGS_OFFSET) - 1) |
| 172 | #define INT_0 (1 << (IRG_FLAGS_OFFSET)) |
| 173 | #define INT_1 (1 << (IRG_FLAGS_OFFSET + 1)) |
| 174 | #define INT_2 (1 << (IRG_FLAGS_OFFSET + 2)) |
| 175 | #define INT_3 (1 << (IRG_FLAGS_OFFSET + 3)) |
| 176 | #define INT_4 (1 << (IRG_FLAGS_OFFSET + 4)) |
| 177 | #define INT_5 (1 << (IRG_FLAGS_OFFSET + 5)) |
| 178 | #define MAX_NUM_INT (6) |
| 179 | |
| 180 | /*******************************************/ |
| 181 | /* E0 and later Interrupt flags. */ |
| 182 | /* IRQ Clear word */ |
| 183 | /* 0: Clear INT0 */ |
| 184 | /* 1: Clear INT1 */ |
| 185 | /* 2: Clear INT2 */ |
| 186 | /* 3: Clear INT3 */ |
| 187 | /* 4: Clear INT4 */ |
| 188 | /* 5: Clear INT5 */ |
| 189 | /* 6: Select VMM table 1 */ |
| 190 | /* 7: Select VMM table 2 */ |
| 191 | /* 8: Enable VMM */ |
| 192 | /*******************************************/ |
Anish Bhatt | ffda203 | 2015-09-29 12:15:49 -0700 | [diff] [blame] | 193 | #define CLR_INT0 BIT(0) |
| 194 | #define CLR_INT1 BIT(1) |
| 195 | #define CLR_INT2 BIT(2) |
| 196 | #define CLR_INT3 BIT(3) |
| 197 | #define CLR_INT4 BIT(4) |
| 198 | #define CLR_INT5 BIT(5) |
| 199 | #define SEL_VMM_TBL0 BIT(6) |
| 200 | #define SEL_VMM_TBL1 BIT(7) |
| 201 | #define EN_VMM BIT(8) |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 202 | |
| 203 | #define DATA_INT_EXT INT_0 |
| 204 | #define PLL_INT_EXT INT_1 |
| 205 | #define SLEEP_INT_EXT INT_2 |
| 206 | #define ALL_INT_EXT (DATA_INT_EXT | PLL_INT_EXT | SLEEP_INT_EXT) |
| 207 | #define NUM_INT_EXT (3) |
| 208 | |
| 209 | #define DATA_INT_CLR CLR_INT0 |
| 210 | #define PLL_INT_CLR CLR_INT1 |
| 211 | #define SLEEP_INT_CLR CLR_INT2 |
| 212 | |
| 213 | #define ENABLE_RX_VMM (SEL_VMM_TBL1 | EN_VMM) |
| 214 | #define ENABLE_TX_VMM (SEL_VMM_TBL0 | EN_VMM) |
| 215 | |
| 216 | |
| 217 | /*time for expiring the semaphores of cfg packets*/ |
| 218 | #define CFG_PKTS_TIMEOUT 2000 |
| 219 | /******************************************** |
| 220 | * |
| 221 | * Debug Type |
| 222 | * |
| 223 | ********************************************/ |
Chaehyun Lim | fbc2fe1 | 2015-09-15 14:06:16 +0900 | [diff] [blame] | 224 | typedef void (*wilc_debug_func)(u32, char *, ...); |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 225 | |
| 226 | /******************************************** |
| 227 | * |
| 228 | * Tx/Rx Queue Structure |
| 229 | * |
| 230 | ********************************************/ |
| 231 | |
| 232 | struct txq_entry_t { |
| 233 | struct txq_entry_t *next; |
| 234 | struct txq_entry_t *prev; |
| 235 | int type; |
| 236 | int tcp_PendingAck_index; |
Chaehyun Lim | 51e825f | 2015-09-15 14:06:14 +0900 | [diff] [blame] | 237 | u8 *buffer; |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 238 | int buffer_size; |
| 239 | void *priv; |
| 240 | int status; |
| 241 | void (*tx_complete_func)(void *, int); |
| 242 | }; |
| 243 | |
| 244 | struct rxq_entry_t { |
| 245 | struct rxq_entry_t *next; |
Chaehyun Lim | 51e825f | 2015-09-15 14:06:14 +0900 | [diff] [blame] | 246 | u8 *buffer; |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 247 | int buffer_size; |
| 248 | }; |
| 249 | |
| 250 | /******************************************** |
| 251 | * |
| 252 | * Host IF Structure |
| 253 | * |
| 254 | ********************************************/ |
| 255 | |
| 256 | typedef struct { |
| 257 | int (*hif_init)(wilc_wlan_inp_t *, wilc_debug_func); |
| 258 | int (*hif_deinit)(void *); |
Chaehyun Lim | fbc2fe1 | 2015-09-15 14:06:16 +0900 | [diff] [blame] | 259 | int (*hif_read_reg)(u32, u32 *); |
| 260 | int (*hif_write_reg)(u32, u32); |
| 261 | int (*hif_block_rx)(u32, u8 *, u32); |
| 262 | int (*hif_block_tx)(u32, u8 *, u32); |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 263 | int (*hif_sync)(void); |
| 264 | int (*hif_clear_int)(void); |
Chaehyun Lim | fbc2fe1 | 2015-09-15 14:06:16 +0900 | [diff] [blame] | 265 | int (*hif_read_int)(u32 *); |
| 266 | int (*hif_clear_int_ext)(u32); |
| 267 | int (*hif_read_size)(u32 *); |
| 268 | int (*hif_block_tx_ext)(u32, u8 *, u32); |
| 269 | int (*hif_block_rx_ext)(u32, u8 *, u32); |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 270 | int (*hif_sync_ext)(int); |
| 271 | void (*hif_set_max_bus_speed)(void); |
| 272 | void (*hif_set_default_bus_speed)(void); |
| 273 | } wilc_hif_func_t; |
| 274 | |
| 275 | /******************************************** |
| 276 | * |
| 277 | * Configuration Structure |
| 278 | * |
| 279 | ********************************************/ |
| 280 | |
| 281 | #define MAX_CFG_FRAME_SIZE 1468 |
| 282 | |
| 283 | typedef struct { |
Chaehyun Lim | 51e825f | 2015-09-15 14:06:14 +0900 | [diff] [blame] | 284 | u8 ether_header[14]; |
| 285 | u8 ip_header[20]; |
| 286 | u8 udp_header[8]; |
| 287 | u8 wid_header[8]; |
| 288 | u8 frame[MAX_CFG_FRAME_SIZE]; |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 289 | } wilc_cfg_frame_t; |
| 290 | |
| 291 | typedef struct { |
Chaehyun Lim | fbc2fe1 | 2015-09-15 14:06:16 +0900 | [diff] [blame] | 292 | int (*wlan_tx)(u8 *, u32, wilc_tx_complete_func_t); |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 293 | } wilc_wlan_cfg_func_t; |
| 294 | |
| 295 | typedef struct { |
| 296 | int type; |
Chaehyun Lim | fbc2fe1 | 2015-09-15 14:06:16 +0900 | [diff] [blame] | 297 | u32 seq_no; |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 298 | } wilc_cfg_rsp_t; |
| 299 | |
| 300 | typedef struct { |
Chaehyun Lim | fbc2fe1 | 2015-09-15 14:06:16 +0900 | [diff] [blame] | 301 | int (*cfg_wid_set)(u8 *, u32, u16, u8 *, int); |
| 302 | int (*cfg_wid_get)(u8 *, u32, u16); |
| 303 | int (*cfg_wid_get_val)(u16, u8 *, u32); |
Chaehyun Lim | 51e825f | 2015-09-15 14:06:14 +0900 | [diff] [blame] | 304 | int (*rx_indicate)(u8 *, int, wilc_cfg_rsp_t *); |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 305 | int (*cfg_init)(wilc_debug_func); |
| 306 | } wilc_cfg_func_t; |
| 307 | |
Glen Lee | 63d7ab8 | 2015-10-01 16:03:32 +0900 | [diff] [blame^] | 308 | int wilc_wlan_firmware_download(const u8 *buffer, u32 buffer_size); |
Johnny Kim | c5c77ba | 2015-05-11 14:30:56 +0900 | [diff] [blame] | 309 | #endif |