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gerrit-public.fairphone.software / kernel / msm-4.9 / 640a7f3f0fd54dd12bd20c43e32da0ff3993bf05 / . / arch / arm / boot / dts / imx6sl.dtsi
blob: f295290d29fc904b8c70bf29ff3e5c3e8f2f2fe4 [file] [log] [blame]
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include "skeleton.dtsi"
11#include "imx6sl-pinfunc.h"
12#include <dt-bindings/clock/imx6sl-clock.h>
13
14/ {
15 aliases {
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]16 gpio0 = &gpio1;
17 gpio1 = &gpio2;
18 gpio2 = &gpio3;
19 gpio3 = &gpio4;
20 gpio4 = &gpio5;
Fabio Estevam640a7f32013-09-13 18:13:00 -0300[diff] [blame^]21 serial0 = &uart1;
22 serial1 = &uart2;
23 serial2 = &uart3;
24 serial3 = &uart4;
25 serial4 = &uart5;
26 spi0 = &ecspi1;
27 spi1 = &ecspi2;
28 spi2 = &ecspi3;
29 spi3 = &ecspi4;
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 cpu@0 {
37 compatible = "arm,cortex-a9";
38 device_type = "cpu";
39 reg = <0x0>;
40 next-level-cache = <&L2>;
41 };
42 };
43
44 intc: interrupt-controller@00a01000 {
45 compatible = "arm,cortex-a9-gic";
46 #interrupt-cells = <3>;
47 #address-cells = <1>;
48 #size-cells = <1>;
49 interrupt-controller;
50 reg = <0x00a01000 0x1000>,
51 <0x00a00100 0x100>;
52 };
53
54 clocks {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 ckil {
59 compatible = "fixed-clock";
60 clock-frequency = <32768>;
61 };
62
63 osc {
64 compatible = "fixed-clock";
65 clock-frequency = <24000000>;
66 };
67 };
68
69 soc {
70 #address-cells = <1>;
71 #size-cells = <1>;
72 compatible = "simple-bus";
73 interrupt-parent = <&intc>;
74 ranges;
75
76 L2: l2-cache@00a02000 {
77 compatible = "arm,pl310-cache";
78 reg = <0x00a02000 0x1000>;
79 interrupts = <0 92 0x04>;
80 cache-unified;
81 cache-level = <2>;
82 arm,tag-latency = <4 2 3>;
83 arm,data-latency = <4 2 3>;
84 };
85
86 pmu {
87 compatible = "arm,cortex-a9-pmu";
88 interrupts = <0 94 0x04>;
89 };
90
91 aips1: aips-bus@02000000 {
92 compatible = "fsl,aips-bus", "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 reg = <0x02000000 0x100000>;
96 ranges;
97
98 spba: spba-bus@02000000 {
99 compatible = "fsl,spba-bus", "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 reg = <0x02000000 0x40000>;
103 ranges;
104
105 spdif: spdif@02004000 {
106 reg = <0x02004000 0x4000>;
107 interrupts = <0 52 0x04>;
108 };
109
110 ecspi1: ecspi@02008000 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
114 reg = <0x02008000 0x4000>;
115 interrupts = <0 31 0x04>;
116 clocks = <&clks IMX6SL_CLK_ECSPI1>,
117 <&clks IMX6SL_CLK_ECSPI1>;
118 clock-names = "ipg", "per";
119 status = "disabled";
120 };
121
122 ecspi2: ecspi@0200c000 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
126 reg = <0x0200c000 0x4000>;
127 interrupts = <0 32 0x04>;
128 clocks = <&clks IMX6SL_CLK_ECSPI2>,
129 <&clks IMX6SL_CLK_ECSPI2>;
130 clock-names = "ipg", "per";
131 status = "disabled";
132 };
133
134 ecspi3: ecspi@02010000 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
138 reg = <0x02010000 0x4000>;
139 interrupts = <0 33 0x04>;
140 clocks = <&clks IMX6SL_CLK_ECSPI3>,
141 <&clks IMX6SL_CLK_ECSPI3>;
142 clock-names = "ipg", "per";
143 status = "disabled";
144 };
145
146 ecspi4: ecspi@02014000 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
150 reg = <0x02014000 0x4000>;
151 interrupts = <0 34 0x04>;
152 clocks = <&clks IMX6SL_CLK_ECSPI4>,
153 <&clks IMX6SL_CLK_ECSPI4>;
154 clock-names = "ipg", "per";
155 status = "disabled";
156 };
157
158 uart5: serial@02018000 {
Huang Shijie6eb85f92013-07-08 17:14:19 +0800[diff] [blame]159 compatible = "fsl,imx6sl-uart",
160 "fsl,imx6q-uart", "fsl,imx21-uart";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]161 reg = <0x02018000 0x4000>;
162 interrupts = <0 30 0x04>;
163 clocks = <&clks IMX6SL_CLK_UART>,
164 <&clks IMX6SL_CLK_UART_SERIAL>;
165 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]166 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
167 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]168 status = "disabled";
169 };
170
171 uart1: serial@02020000 {
Huang Shijie6eb85f92013-07-08 17:14:19 +0800[diff] [blame]172 compatible = "fsl,imx6sl-uart",
173 "fsl,imx6q-uart", "fsl,imx21-uart";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]174 reg = <0x02020000 0x4000>;
175 interrupts = <0 26 0x04>;
176 clocks = <&clks IMX6SL_CLK_UART>,
177 <&clks IMX6SL_CLK_UART_SERIAL>;
178 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]179 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
180 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]181 status = "disabled";
182 };
183
184 uart2: serial@02024000 {
Huang Shijie6eb85f92013-07-08 17:14:19 +0800[diff] [blame]185 compatible = "fsl,imx6sl-uart",
186 "fsl,imx6q-uart", "fsl,imx21-uart";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]187 reg = <0x02024000 0x4000>;
188 interrupts = <0 27 0x04>;
189 clocks = <&clks IMX6SL_CLK_UART>,
190 <&clks IMX6SL_CLK_UART_SERIAL>;
191 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]192 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
193 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]194 status = "disabled";
195 };
196
197 ssi1: ssi@02028000 {
198 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
199 reg = <0x02028000 0x4000>;
200 interrupts = <0 46 0x04>;
201 clocks = <&clks IMX6SL_CLK_SSI1>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800[diff] [blame]202 dmas = <&sdma 37 1 0>,
203 <&sdma 38 1 0>;
204 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]205 fsl,fifo-depth = <15>;
206 status = "disabled";
207 };
208
209 ssi2: ssi@0202c000 {
210 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
211 reg = <0x0202c000 0x4000>;
212 interrupts = <0 47 0x04>;
213 clocks = <&clks IMX6SL_CLK_SSI2>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800[diff] [blame]214 dmas = <&sdma 41 1 0>,
215 <&sdma 42 1 0>;
216 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]217 fsl,fifo-depth = <15>;
218 status = "disabled";
219 };
220
221 ssi3: ssi@02030000 {
222 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
223 reg = <0x02030000 0x4000>;
224 interrupts = <0 48 0x04>;
225 clocks = <&clks IMX6SL_CLK_SSI3>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800[diff] [blame]226 dmas = <&sdma 45 1 0>,
227 <&sdma 46 1 0>;
228 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]229 fsl,fifo-depth = <15>;
230 status = "disabled";
231 };
232
233 uart3: serial@02034000 {
Huang Shijie6eb85f92013-07-08 17:14:19 +0800[diff] [blame]234 compatible = "fsl,imx6sl-uart",
235 "fsl,imx6q-uart", "fsl,imx21-uart";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]236 reg = <0x02034000 0x4000>;
237 interrupts = <0 28 0x04>;
238 clocks = <&clks IMX6SL_CLK_UART>,
239 <&clks IMX6SL_CLK_UART_SERIAL>;
240 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]241 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
242 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]243 status = "disabled";
244 };
245
246 uart4: serial@02038000 {
Huang Shijie6eb85f92013-07-08 17:14:19 +0800[diff] [blame]247 compatible = "fsl,imx6sl-uart",
248 "fsl,imx6q-uart", "fsl,imx21-uart";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]249 reg = <0x02038000 0x4000>;
250 interrupts = <0 29 0x04>;
251 clocks = <&clks IMX6SL_CLK_UART>,
252 <&clks IMX6SL_CLK_UART_SERIAL>;
253 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]254 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
255 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]256 status = "disabled";
257 };
258 };
259
260 pwm1: pwm@02080000 {
261 #pwm-cells = <2>;
262 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
263 reg = <0x02080000 0x4000>;
264 interrupts = <0 83 0x04>;
265 clocks = <&clks IMX6SL_CLK_PWM1>,
266 <&clks IMX6SL_CLK_PWM1>;
267 clock-names = "ipg", "per";
268 };
269
270 pwm2: pwm@02084000 {
271 #pwm-cells = <2>;
272 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
273 reg = <0x02084000 0x4000>;
274 interrupts = <0 84 0x04>;
275 clocks = <&clks IMX6SL_CLK_PWM2>,
276 <&clks IMX6SL_CLK_PWM2>;
277 clock-names = "ipg", "per";
278 };
279
280 pwm3: pwm@02088000 {
281 #pwm-cells = <2>;
282 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
283 reg = <0x02088000 0x4000>;
284 interrupts = <0 85 0x04>;
285 clocks = <&clks IMX6SL_CLK_PWM3>,
286 <&clks IMX6SL_CLK_PWM3>;
287 clock-names = "ipg", "per";
288 };
289
290 pwm4: pwm@0208c000 {
291 #pwm-cells = <2>;
292 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
293 reg = <0x0208c000 0x4000>;
294 interrupts = <0 86 0x04>;
295 clocks = <&clks IMX6SL_CLK_PWM4>,
296 <&clks IMX6SL_CLK_PWM4>;
297 clock-names = "ipg", "per";
298 };
299
300 gpt: gpt@02098000 {
301 compatible = "fsl,imx6sl-gpt";
302 reg = <0x02098000 0x4000>;
303 interrupts = <0 55 0x04>;
304 clocks = <&clks IMX6SL_CLK_GPT>,
305 <&clks IMX6SL_CLK_GPT_SERIAL>;
306 clock-names = "ipg", "per";
307 };
308
309 gpio1: gpio@0209c000 {
310 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
311 reg = <0x0209c000 0x4000>;
312 interrupts = <0 66 0x04 0 67 0x04>;
313 gpio-controller;
314 #gpio-cells = <2>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
317 };
318
319 gpio2: gpio@020a0000 {
320 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
321 reg = <0x020a0000 0x4000>;
322 interrupts = <0 68 0x04 0 69 0x04>;
323 gpio-controller;
324 #gpio-cells = <2>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 };
328
329 gpio3: gpio@020a4000 {
330 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
331 reg = <0x020a4000 0x4000>;
332 interrupts = <0 70 0x04 0 71 0x04>;
333 gpio-controller;
334 #gpio-cells = <2>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 };
338
339 gpio4: gpio@020a8000 {
340 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
341 reg = <0x020a8000 0x4000>;
342 interrupts = <0 72 0x04 0 73 0x04>;
343 gpio-controller;
344 #gpio-cells = <2>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
347 };
348
349 gpio5: gpio@020ac000 {
350 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
351 reg = <0x020ac000 0x4000>;
352 interrupts = <0 74 0x04 0 75 0x04>;
353 gpio-controller;
354 #gpio-cells = <2>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 };
358
359 kpp: kpp@020b8000 {
360 reg = <0x020b8000 0x4000>;
361 interrupts = <0 82 0x04>;
362 };
363
364 wdog1: wdog@020bc000 {
365 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
366 reg = <0x020bc000 0x4000>;
367 interrupts = <0 80 0x04>;
368 clocks = <&clks IMX6SL_CLK_DUMMY>;
369 };
370
371 wdog2: wdog@020c0000 {
372 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
373 reg = <0x020c0000 0x4000>;
374 interrupts = <0 81 0x04>;
375 clocks = <&clks IMX6SL_CLK_DUMMY>;
376 status = "disabled";
377 };
378
379 clks: ccm@020c4000 {
380 compatible = "fsl,imx6sl-ccm";
381 reg = <0x020c4000 0x4000>;
382 interrupts = <0 87 0x04 0 88 0x04>;
383 #clock-cells = <1>;
384 };
385
386 anatop: anatop@020c8000 {
387 compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus";
388 reg = <0x020c8000 0x1000>;
389 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
390
391 regulator-1p1@110 {
392 compatible = "fsl,anatop-regulator";
393 regulator-name = "vdd1p1";
394 regulator-min-microvolt = <800000>;
395 regulator-max-microvolt = <1375000>;
396 regulator-always-on;
397 anatop-reg-offset = <0x110>;
398 anatop-vol-bit-shift = <8>;
399 anatop-vol-bit-width = <5>;
400 anatop-min-bit-val = <4>;
401 anatop-min-voltage = <800000>;
402 anatop-max-voltage = <1375000>;
403 };
404
405 regulator-3p0@120 {
406 compatible = "fsl,anatop-regulator";
407 regulator-name = "vdd3p0";
408 regulator-min-microvolt = <2800000>;
409 regulator-max-microvolt = <3150000>;
410 regulator-always-on;
411 anatop-reg-offset = <0x120>;
412 anatop-vol-bit-shift = <8>;
413 anatop-vol-bit-width = <5>;
414 anatop-min-bit-val = <0>;
415 anatop-min-voltage = <2625000>;
416 anatop-max-voltage = <3400000>;
417 };
418
419 regulator-2p5@130 {
420 compatible = "fsl,anatop-regulator";
421 regulator-name = "vdd2p5";
422 regulator-min-microvolt = <2100000>;
423 regulator-max-microvolt = <2850000>;
424 regulator-always-on;
425 anatop-reg-offset = <0x130>;
426 anatop-vol-bit-shift = <8>;
427 anatop-vol-bit-width = <5>;
428 anatop-min-bit-val = <0>;
429 anatop-min-voltage = <2100000>;
430 anatop-max-voltage = <2850000>;
431 };
432
433 reg_arm: regulator-vddcore@140 {
434 compatible = "fsl,anatop-regulator";
435 regulator-name = "cpu";
436 regulator-min-microvolt = <725000>;
437 regulator-max-microvolt = <1450000>;
438 regulator-always-on;
439 anatop-reg-offset = <0x140>;
440 anatop-vol-bit-shift = <0>;
441 anatop-vol-bit-width = <5>;
442 anatop-delay-reg-offset = <0x170>;
443 anatop-delay-bit-shift = <24>;
444 anatop-delay-bit-width = <2>;
445 anatop-min-bit-val = <1>;
446 anatop-min-voltage = <725000>;
447 anatop-max-voltage = <1450000>;
448 };
449
450 reg_pu: regulator-vddpu@140 {
451 compatible = "fsl,anatop-regulator";
452 regulator-name = "vddpu";
453 regulator-min-microvolt = <725000>;
454 regulator-max-microvolt = <1450000>;
455 regulator-always-on;
456 anatop-reg-offset = <0x140>;
457 anatop-vol-bit-shift = <9>;
458 anatop-vol-bit-width = <5>;
459 anatop-delay-reg-offset = <0x170>;
460 anatop-delay-bit-shift = <26>;
461 anatop-delay-bit-width = <2>;
462 anatop-min-bit-val = <1>;
463 anatop-min-voltage = <725000>;
464 anatop-max-voltage = <1450000>;
465 };
466
467 reg_soc: regulator-vddsoc@140 {
468 compatible = "fsl,anatop-regulator";
469 regulator-name = "vddsoc";
470 regulator-min-microvolt = <725000>;
471 regulator-max-microvolt = <1450000>;
472 regulator-always-on;
473 anatop-reg-offset = <0x140>;
474 anatop-vol-bit-shift = <18>;
475 anatop-vol-bit-width = <5>;
476 anatop-delay-reg-offset = <0x170>;
477 anatop-delay-bit-shift = <28>;
478 anatop-delay-bit-width = <2>;
479 anatop-min-bit-val = <1>;
480 anatop-min-voltage = <725000>;
481 anatop-max-voltage = <1450000>;
482 };
483 };
484
485 usbphy1: usbphy@020c9000 {
486 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
487 reg = <0x020c9000 0x1000>;
488 interrupts = <0 44 0x04>;
489 clocks = <&clks IMX6SL_CLK_USBPHY1>;
490 };
491
492 usbphy2: usbphy@020ca000 {
493 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
494 reg = <0x020ca000 0x1000>;
495 interrupts = <0 45 0x04>;
496 clocks = <&clks IMX6SL_CLK_USBPHY2>;
497 };
498
499 snvs@020cc000 {
500 compatible = "fsl,sec-v4.0-mon", "simple-bus";
501 #address-cells = <1>;
502 #size-cells = <1>;
503 ranges = <0 0x020cc000 0x4000>;
504
505 snvs-rtc-lp@34 {
506 compatible = "fsl,sec-v4.0-mon-rtc-lp";
507 reg = <0x34 0x58>;
508 interrupts = <0 19 0x04 0 20 0x04>;
509 };
510 };
511
512 epit1: epit@020d0000 {
513 reg = <0x020d0000 0x4000>;
514 interrupts = <0 56 0x04>;
515 };
516
517 epit2: epit@020d4000 {
518 reg = <0x020d4000 0x4000>;
519 interrupts = <0 57 0x04>;
520 };
521
522 src: src@020d8000 {
523 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
524 reg = <0x020d8000 0x4000>;
525 interrupts = <0 91 0x04 0 96 0x04>;
526 #reset-cells = <1>;
527 };
528
529 gpc: gpc@020dc000 {
530 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
531 reg = <0x020dc000 0x4000>;
532 interrupts = <0 89 0x04>;
533 };
534
Fugang Duane03d10f2013-09-03 12:26:22 +0800[diff] [blame]535 gpr: iomuxc-gpr@020e0000 {
536 compatible = "fsl,imx6sl-iomuxc-gpr", "syscon";
537 reg = <0x020e0000 0x38>;
538 };
539
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]540 iomuxc: iomuxc@020e0000 {
541 compatible = "fsl,imx6sl-iomuxc";
542 reg = <0x020e0000 0x4000>;
543
544 fec {
545 pinctrl_fec_1: fecgrp-1 {
546 fsl,pins = <
547 MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
548 MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
549 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
550 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
551 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
552 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
553 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
554 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
555 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
556 >;
557 };
558 };
559
560 uart1 {
561 pinctrl_uart1_1: uart1grp-1 {
562 fsl,pins = <
563 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
564 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
565 >;
566 };
567 };
568
Peter Chen60222322013-09-10 10:23:16 +0800[diff] [blame]569 usbotg1 {
570 pinctrl_usbotg1_1: usbotg1grp-1 {
571 fsl,pins = <
572 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
573 >;
574 };
575
576 pinctrl_usbotg1_2: usbotg1grp-2 {
577 fsl,pins = <
578 MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059
579 >;
580 };
581
582 pinctrl_usbotg1_3: usbotg1grp-3 {
583 fsl,pins = <
584 MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059
585 >;
586 };
587
588 pinctrl_usbotg1_4: usbotg1grp-4 {
589 fsl,pins = <
590 MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059
591 >;
592 };
593
594 pinctrl_usbotg1_5: usbotg1grp-5 {
595 fsl,pins = <
596 MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059
597 >;
598 };
599 };
600
601 usbotg2 {
602 pinctrl_usbotg2_1: usbotg2grp-1 {
603 fsl,pins = <
604 MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059
605 >;
606 };
607
608 pinctrl_usbotg2_2: usbotg2grp-2 {
609 fsl,pins = <
610 MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059
611 >;
612 };
613
614 pinctrl_usbotg2_3: usbotg2grp-3 {
615 fsl,pins = <
616 MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059
617 >;
618 };
619
620 pinctrl_usbotg2_4: usbotg2grp-4 {
621 fsl,pins = <
622 MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059
623 >;
624 };
625 };
626
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]627 usdhc1 {
628 pinctrl_usdhc1_1: usdhc1grp-1 {
629 fsl,pins = <
630 MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
631 MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
632 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
633 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
634 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
635 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
636 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
637 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
638 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
639 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
640 >;
641 };
642 };
643
644 usdhc2 {
645 pinctrl_usdhc2_1: usdhc2grp-1 {
646 fsl,pins = <
647 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
648 MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
649 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
650 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
651 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
652 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
653 >;
654 };
655 };
656
657 usdhc3 {
658 pinctrl_usdhc3_1: usdhc3grp-1 {
659 fsl,pins = <
660 MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
661 MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
662 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
663 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
664 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
665 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
666 >;
667 };
668 };
669 };
670
671 csi: csi@020e4000 {
672 reg = <0x020e4000 0x4000>;
673 interrupts = <0 7 0x04>;
674 };
675
676 spdc: spdc@020e8000 {
677 reg = <0x020e8000 0x4000>;
678 interrupts = <0 6 0x04>;
679 };
680
681 sdma: sdma@020ec000 {
682 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
683 reg = <0x020ec000 0x4000>;
684 interrupts = <0 2 0x04>;
685 clocks = <&clks IMX6SL_CLK_SDMA>,
686 <&clks IMX6SL_CLK_SDMA>;
687 clock-names = "ipg", "ahb";
Huang Shijiefb72bb22013-07-02 10:15:29 +0800[diff] [blame]688 #dma-cells = <3>;
Shawn Guo44a26872013-08-13 08:55:02 +0800[diff] [blame]689 /* imx6sl reuses imx6q sdma firmware */
690 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]691 };
692
693 pxp: pxp@020f0000 {
694 reg = <0x020f0000 0x4000>;
695 interrupts = <0 98 0x04>;
696 };
697
698 epdc: epdc@020f4000 {
699 reg = <0x020f4000 0x4000>;
700 interrupts = <0 97 0x04>;
701 };
702
703 lcdif: lcdif@020f8000 {
704 reg = <0x020f8000 0x4000>;
705 interrupts = <0 39 0x04>;
706 };
707
708 dcp: dcp@020fc000 {
709 reg = <0x020fc000 0x4000>;
710 interrupts = <0 99 0x04>;
711 };
712 };
713
714 aips2: aips-bus@02100000 {
715 compatible = "fsl,aips-bus", "simple-bus";
716 #address-cells = <1>;
717 #size-cells = <1>;
718 reg = <0x02100000 0x100000>;
719 ranges;
720
721 usbotg1: usb@02184000 {
722 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
723 reg = <0x02184000 0x200>;
724 interrupts = <0 43 0x04>;
725 clocks = <&clks IMX6SL_CLK_USBOH3>;
726 fsl,usbphy = <&usbphy1>;
727 fsl,usbmisc = <&usbmisc 0>;
728 status = "disabled";
729 };
730
731 usbotg2: usb@02184200 {
732 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
733 reg = <0x02184200 0x200>;
Peter Chen60222322013-09-10 10:23:16 +0800[diff] [blame]734 interrupts = <0 42 0x04>;
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]735 clocks = <&clks IMX6SL_CLK_USBOH3>;
736 fsl,usbphy = <&usbphy2>;
737 fsl,usbmisc = <&usbmisc 1>;
738 status = "disabled";
739 };
740
741 usbh: usb@02184400 {
742 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
743 reg = <0x02184400 0x200>;
Peter Chen60222322013-09-10 10:23:16 +0800[diff] [blame]744 interrupts = <0 40 0x04>;
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]745 clocks = <&clks IMX6SL_CLK_USBOH3>;
746 fsl,usbmisc = <&usbmisc 2>;
747 status = "disabled";
748 };
749
750 usbmisc: usbmisc@02184800 {
751 #index-cells = <1>;
752 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
753 reg = <0x02184800 0x200>;
754 clocks = <&clks IMX6SL_CLK_USBOH3>;
755 };
756
757 fec: ethernet@02188000 {
758 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
759 reg = <0x02188000 0x4000>;
760 interrupts = <0 114 0x04>;
761 clocks = <&clks IMX6SL_CLK_ENET_REF>,
762 <&clks IMX6SL_CLK_ENET_REF>;
763 clock-names = "ipg", "ahb";
764 status = "disabled";
765 };
766
767 usdhc1: usdhc@02190000 {
768 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
769 reg = <0x02190000 0x4000>;
770 interrupts = <0 22 0x04>;
771 clocks = <&clks IMX6SL_CLK_USDHC1>,
772 <&clks IMX6SL_CLK_USDHC1>,
773 <&clks IMX6SL_CLK_USDHC1>;
774 clock-names = "ipg", "ahb", "per";
775 bus-width = <4>;
776 status = "disabled";
777 };
778
779 usdhc2: usdhc@02194000 {
780 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
781 reg = <0x02194000 0x4000>;
782 interrupts = <0 23 0x04>;
783 clocks = <&clks IMX6SL_CLK_USDHC2>,
784 <&clks IMX6SL_CLK_USDHC2>,
785 <&clks IMX6SL_CLK_USDHC2>;
786 clock-names = "ipg", "ahb", "per";
787 bus-width = <4>;
788 status = "disabled";
789 };
790
791 usdhc3: usdhc@02198000 {
792 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
793 reg = <0x02198000 0x4000>;
794 interrupts = <0 24 0x04>;
795 clocks = <&clks IMX6SL_CLK_USDHC3>,
796 <&clks IMX6SL_CLK_USDHC3>,
797 <&clks IMX6SL_CLK_USDHC3>;
798 clock-names = "ipg", "ahb", "per";
799 bus-width = <4>;
800 status = "disabled";
801 };
802
803 usdhc4: usdhc@0219c000 {
804 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
805 reg = <0x0219c000 0x4000>;
806 interrupts = <0 25 0x04>;
807 clocks = <&clks IMX6SL_CLK_USDHC4>,
808 <&clks IMX6SL_CLK_USDHC4>,
809 <&clks IMX6SL_CLK_USDHC4>;
810 clock-names = "ipg", "ahb", "per";
811 bus-width = <4>;
812 status = "disabled";
813 };
814
815 i2c1: i2c@021a0000 {
816 #address-cells = <1>;
817 #size-cells = <0>;
818 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
819 reg = <0x021a0000 0x4000>;
820 interrupts = <0 36 0x04>;
821 clocks = <&clks IMX6SL_CLK_I2C1>;
822 status = "disabled";
823 };
824
825 i2c2: i2c@021a4000 {
826 #address-cells = <1>;
827 #size-cells = <0>;
828 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
829 reg = <0x021a4000 0x4000>;
830 interrupts = <0 37 0x04>;
831 clocks = <&clks IMX6SL_CLK_I2C2>;
832 status = "disabled";
833 };
834
835 i2c3: i2c@021a8000 {
836 #address-cells = <1>;
837 #size-cells = <0>;
838 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
839 reg = <0x021a8000 0x4000>;
840 interrupts = <0 38 0x04>;
841 clocks = <&clks IMX6SL_CLK_I2C3>;
842 status = "disabled";
843 };
844
845 mmdc: mmdc@021b0000 {
846 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
847 reg = <0x021b0000 0x4000>;
848 };
849
850 rngb: rngb@021b4000 {
851 reg = <0x021b4000 0x4000>;
852 interrupts = <0 5 0x04>;
853 };
854
855 weim: weim@021b8000 {
856 reg = <0x021b8000 0x4000>;
857 interrupts = <0 14 0x04>;
858 };
859
860 ocotp: ocotp@021bc000 {
861 compatible = "fsl,imx6sl-ocotp";
862 reg = <0x021bc000 0x4000>;
863 };
864
865 audmux: audmux@021d8000 {
866 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
867 reg = <0x021d8000 0x4000>;
868 status = "disabled";
869 };
870 };
871 };
872};