Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * TAS5086 ASoC codec driver |
| 3 | * |
| 4 | * Copyright (c) 2013 Daniel Mack <zonque@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * TODO: |
| 17 | * - implement DAPM and input muxing |
| 18 | * - implement modulation limit |
| 19 | * - implement non-default PWM start |
| 20 | * |
| 21 | * Note that this chip has a very unusual register layout, specifically |
| 22 | * because the registers are of unequal size, and multi-byte registers |
| 23 | * require bulk writes to take effect. Regmap does not support that kind |
| 24 | * of devices. |
| 25 | * |
| 26 | * Currently, the driver does not touch any of the registers >= 0x20, so |
| 27 | * it doesn't matter because the entire map can be accessed as 8-bit |
| 28 | * array. In case more features will be added in the future |
| 29 | * that require access to higher registers, the entire regmap H/W I/O |
| 30 | * routines have to be open-coded. |
| 31 | */ |
| 32 | |
| 33 | #include <linux/module.h> |
| 34 | #include <linux/slab.h> |
| 35 | #include <linux/delay.h> |
| 36 | #include <linux/gpio.h> |
| 37 | #include <linux/i2c.h> |
| 38 | #include <linux/regmap.h> |
| 39 | #include <linux/spi/spi.h> |
| 40 | #include <linux/of_device.h> |
| 41 | #include <linux/of_gpio.h> |
| 42 | #include <sound/pcm.h> |
| 43 | #include <sound/pcm_params.h> |
| 44 | #include <sound/soc.h> |
| 45 | #include <sound/tlv.h> |
| 46 | #include <sound/tas5086.h> |
| 47 | |
| 48 | #define TAS5086_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ |
| 49 | SNDRV_PCM_FMTBIT_S20_3LE | \ |
| 50 | SNDRV_PCM_FMTBIT_S24_3LE) |
| 51 | |
| 52 | #define TAS5086_PCM_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ |
| 53 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \ |
| 54 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \ |
| 55 | SNDRV_PCM_RATE_192000) |
| 56 | |
| 57 | /* |
| 58 | * TAS5086 registers |
| 59 | */ |
| 60 | #define TAS5086_CLOCK_CONTROL 0x00 /* Clock control register */ |
| 61 | #define TAS5086_CLOCK_RATE(val) (val << 5) |
| 62 | #define TAS5086_CLOCK_RATE_MASK (0x7 << 5) |
| 63 | #define TAS5086_CLOCK_RATIO(val) (val << 2) |
| 64 | #define TAS5086_CLOCK_RATIO_MASK (0x7 << 2) |
| 65 | #define TAS5086_CLOCK_SCLK_RATIO_48 (1 << 1) |
| 66 | #define TAS5086_CLOCK_VALID (1 << 0) |
| 67 | |
| 68 | #define TAS5086_DEEMPH_MASK 0x03 |
| 69 | #define TAS5086_SOFT_MUTE_ALL 0x3f |
| 70 | |
| 71 | #define TAS5086_DEV_ID 0x01 /* Device ID register */ |
| 72 | #define TAS5086_ERROR_STATUS 0x02 /* Error status register */ |
| 73 | #define TAS5086_SYS_CONTROL_1 0x03 /* System control register 1 */ |
| 74 | #define TAS5086_SERIAL_DATA_IF 0x04 /* Serial data interface register */ |
| 75 | #define TAS5086_SYS_CONTROL_2 0x05 /* System control register 2 */ |
| 76 | #define TAS5086_SOFT_MUTE 0x06 /* Soft mute register */ |
| 77 | #define TAS5086_MASTER_VOL 0x07 /* Master volume */ |
| 78 | #define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */ |
| 79 | #define TAS5086_VOLUME_CONTROL 0x09 /* Volume control register */ |
| 80 | #define TAS5086_MOD_LIMIT 0x10 /* Modulation limit register */ |
| 81 | #define TAS5086_PWM_START 0x18 /* PWM start register */ |
| 82 | #define TAS5086_SURROUND 0x19 /* Surround register */ |
| 83 | #define TAS5086_SPLIT_CAP_CHARGE 0x1a /* Split cap charge period register */ |
| 84 | #define TAS5086_OSC_TRIM 0x1b /* Oscillator trim register */ |
| 85 | #define TAS5086_BKNDERR 0x1c |
Daniel Mack | 8892d47 | 2013-06-24 16:25:30 +0200 | [diff] [blame] | 86 | #define TAS5086_INPUT_MUX 0x20 |
| 87 | #define TAS5086_PWM_OUTPUT_MUX 0x25 |
| 88 | |
| 89 | #define TAS5086_MAX_REGISTER TAS5086_PWM_OUTPUT_MUX |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 90 | |
Daniel Mack | 79b23b5 | 2013-06-24 16:25:32 +0200 | [diff] [blame] | 91 | #define TAS5086_PWM_START_MIDZ_FOR_START_1 (1 << 7) |
| 92 | #define TAS5086_PWM_START_MIDZ_FOR_START_2 (1 << 6) |
| 93 | #define TAS5086_PWM_START_CHANNEL_MASK (0x3f) |
| 94 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 95 | /* |
| 96 | * Default TAS5086 power-up configuration |
| 97 | */ |
| 98 | static const struct reg_default tas5086_reg_defaults[] = { |
| 99 | { 0x00, 0x6c }, |
| 100 | { 0x01, 0x03 }, |
| 101 | { 0x02, 0x00 }, |
| 102 | { 0x03, 0xa0 }, |
| 103 | { 0x04, 0x05 }, |
| 104 | { 0x05, 0x60 }, |
| 105 | { 0x06, 0x00 }, |
| 106 | { 0x07, 0xff }, |
| 107 | { 0x08, 0x30 }, |
| 108 | { 0x09, 0x30 }, |
| 109 | { 0x0a, 0x30 }, |
| 110 | { 0x0b, 0x30 }, |
| 111 | { 0x0c, 0x30 }, |
| 112 | { 0x0d, 0x30 }, |
| 113 | { 0x0e, 0xb1 }, |
| 114 | { 0x0f, 0x00 }, |
| 115 | { 0x10, 0x02 }, |
| 116 | { 0x11, 0x00 }, |
| 117 | { 0x12, 0x00 }, |
| 118 | { 0x13, 0x00 }, |
| 119 | { 0x14, 0x00 }, |
| 120 | { 0x15, 0x00 }, |
| 121 | { 0x16, 0x00 }, |
| 122 | { 0x17, 0x00 }, |
| 123 | { 0x18, 0x3f }, |
| 124 | { 0x19, 0x00 }, |
| 125 | { 0x1a, 0x18 }, |
| 126 | { 0x1b, 0x82 }, |
| 127 | { 0x1c, 0x05 }, |
| 128 | }; |
| 129 | |
Daniel Mack | 6b36d37 | 2013-06-24 16:25:29 +0200 | [diff] [blame] | 130 | static int tas5086_register_size(struct device *dev, unsigned int reg) |
| 131 | { |
| 132 | switch (reg) { |
Daniel Mack | 9f24dc8 | 2013-06-27 21:59:10 +0200 | [diff] [blame] | 133 | case TAS5086_CLOCK_CONTROL ... TAS5086_BKNDERR: |
Daniel Mack | 6b36d37 | 2013-06-24 16:25:29 +0200 | [diff] [blame] | 134 | return 1; |
Daniel Mack | 8892d47 | 2013-06-24 16:25:30 +0200 | [diff] [blame] | 135 | case TAS5086_INPUT_MUX: |
| 136 | case TAS5086_PWM_OUTPUT_MUX: |
| 137 | return 4; |
Daniel Mack | 6b36d37 | 2013-06-24 16:25:29 +0200 | [diff] [blame] | 138 | } |
| 139 | |
| 140 | dev_err(dev, "Unsupported register address: %d\n", reg); |
| 141 | return 0; |
| 142 | } |
| 143 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 144 | static bool tas5086_accessible_reg(struct device *dev, unsigned int reg) |
| 145 | { |
Daniel Mack | 8892d47 | 2013-06-24 16:25:30 +0200 | [diff] [blame] | 146 | switch (reg) { |
| 147 | case 0x0f: |
| 148 | case 0x11 ... 0x17: |
| 149 | case 0x1d ... 0x1f: |
| 150 | return false; |
| 151 | default: |
| 152 | return true; |
| 153 | } |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | static bool tas5086_volatile_reg(struct device *dev, unsigned int reg) |
| 157 | { |
| 158 | switch (reg) { |
| 159 | case TAS5086_DEV_ID: |
| 160 | case TAS5086_ERROR_STATUS: |
| 161 | return true; |
| 162 | } |
| 163 | |
| 164 | return false; |
| 165 | } |
| 166 | |
| 167 | static bool tas5086_writeable_reg(struct device *dev, unsigned int reg) |
| 168 | { |
| 169 | return tas5086_accessible_reg(dev, reg) && (reg != TAS5086_DEV_ID); |
| 170 | } |
| 171 | |
Daniel Mack | 6b36d37 | 2013-06-24 16:25:29 +0200 | [diff] [blame] | 172 | static int tas5086_reg_write(void *context, unsigned int reg, |
| 173 | unsigned int value) |
| 174 | { |
| 175 | struct i2c_client *client = context; |
| 176 | unsigned int i, size; |
| 177 | uint8_t buf[5]; |
| 178 | int ret; |
| 179 | |
| 180 | size = tas5086_register_size(&client->dev, reg); |
| 181 | if (size == 0) |
| 182 | return -EINVAL; |
| 183 | |
| 184 | buf[0] = reg; |
| 185 | |
| 186 | for (i = size; i >= 1; --i) { |
| 187 | buf[i] = value; |
| 188 | value >>= 8; |
| 189 | } |
| 190 | |
| 191 | ret = i2c_master_send(client, buf, size + 1); |
| 192 | if (ret == size + 1) |
| 193 | return 0; |
| 194 | else if (ret < 0) |
| 195 | return ret; |
| 196 | else |
| 197 | return -EIO; |
| 198 | } |
| 199 | |
| 200 | static int tas5086_reg_read(void *context, unsigned int reg, |
| 201 | unsigned int *value) |
| 202 | { |
| 203 | struct i2c_client *client = context; |
| 204 | uint8_t send_buf, recv_buf[4]; |
| 205 | struct i2c_msg msgs[2]; |
| 206 | unsigned int size; |
| 207 | unsigned int i; |
| 208 | int ret; |
| 209 | |
| 210 | size = tas5086_register_size(&client->dev, reg); |
| 211 | if (size == 0) |
| 212 | return -EINVAL; |
| 213 | |
| 214 | send_buf = reg; |
| 215 | |
| 216 | msgs[0].addr = client->addr; |
| 217 | msgs[0].len = sizeof(send_buf); |
| 218 | msgs[0].buf = &send_buf; |
| 219 | msgs[0].flags = 0; |
| 220 | |
| 221 | msgs[1].addr = client->addr; |
| 222 | msgs[1].len = size; |
| 223 | msgs[1].buf = recv_buf; |
| 224 | msgs[1].flags = I2C_M_RD; |
| 225 | |
| 226 | ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); |
| 227 | if (ret < 0) |
| 228 | return ret; |
| 229 | else if (ret != ARRAY_SIZE(msgs)) |
| 230 | return -EIO; |
| 231 | |
| 232 | *value = 0; |
| 233 | |
| 234 | for (i = 0; i < size; i++) { |
| 235 | *value <<= 8; |
| 236 | *value |= recv_buf[i]; |
| 237 | } |
| 238 | |
| 239 | return 0; |
| 240 | } |
| 241 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 242 | struct tas5086_private { |
| 243 | struct regmap *regmap; |
| 244 | unsigned int mclk, sclk; |
| 245 | unsigned int format; |
| 246 | bool deemph; |
Daniel Mack | 648c538 | 2013-10-01 14:48:24 +0200 | [diff] [blame^] | 247 | unsigned int charge_period; |
| 248 | unsigned int pwm_start_mid_z; |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 249 | /* Current sample rate for de-emphasis control */ |
| 250 | int rate; |
| 251 | /* GPIO driving Reset pin, if any */ |
| 252 | int gpio_nreset; |
| 253 | }; |
| 254 | |
| 255 | static int tas5086_deemph[] = { 0, 32000, 44100, 48000 }; |
| 256 | |
| 257 | static int tas5086_set_deemph(struct snd_soc_codec *codec) |
| 258 | { |
| 259 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 260 | int i, val = 0; |
| 261 | |
| 262 | if (priv->deemph) |
| 263 | for (i = 0; i < ARRAY_SIZE(tas5086_deemph); i++) |
| 264 | if (tas5086_deemph[i] == priv->rate) |
| 265 | val = i; |
| 266 | |
| 267 | return regmap_update_bits(priv->regmap, TAS5086_SYS_CONTROL_1, |
| 268 | TAS5086_DEEMPH_MASK, val); |
| 269 | } |
| 270 | |
| 271 | static int tas5086_get_deemph(struct snd_kcontrol *kcontrol, |
| 272 | struct snd_ctl_elem_value *ucontrol) |
| 273 | { |
| 274 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 275 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 276 | |
| 277 | ucontrol->value.enumerated.item[0] = priv->deemph; |
| 278 | |
| 279 | return 0; |
| 280 | } |
| 281 | |
| 282 | static int tas5086_put_deemph(struct snd_kcontrol *kcontrol, |
| 283 | struct snd_ctl_elem_value *ucontrol) |
| 284 | { |
| 285 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 286 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 287 | |
| 288 | priv->deemph = ucontrol->value.enumerated.item[0]; |
| 289 | |
| 290 | return tas5086_set_deemph(codec); |
| 291 | } |
| 292 | |
| 293 | |
| 294 | static int tas5086_set_dai_sysclk(struct snd_soc_dai *codec_dai, |
| 295 | int clk_id, unsigned int freq, int dir) |
| 296 | { |
| 297 | struct snd_soc_codec *codec = codec_dai->codec; |
| 298 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 299 | |
| 300 | switch (clk_id) { |
| 301 | case TAS5086_CLK_IDX_MCLK: |
| 302 | priv->mclk = freq; |
| 303 | break; |
| 304 | case TAS5086_CLK_IDX_SCLK: |
| 305 | priv->sclk = freq; |
| 306 | break; |
| 307 | } |
| 308 | |
| 309 | return 0; |
| 310 | } |
| 311 | |
| 312 | static int tas5086_set_dai_fmt(struct snd_soc_dai *codec_dai, |
| 313 | unsigned int format) |
| 314 | { |
| 315 | struct snd_soc_codec *codec = codec_dai->codec; |
| 316 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 317 | |
| 318 | /* The TAS5086 can only be slave to all clocks */ |
| 319 | if ((format & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) { |
| 320 | dev_err(codec->dev, "Invalid clocking mode\n"); |
| 321 | return -EINVAL; |
| 322 | } |
| 323 | |
| 324 | /* we need to refer to the data format from hw_params() */ |
| 325 | priv->format = format; |
| 326 | |
| 327 | return 0; |
| 328 | } |
| 329 | |
| 330 | static const int tas5086_sample_rates[] = { |
| 331 | 32000, 38000, 44100, 48000, 88200, 96000, 176400, 192000 |
| 332 | }; |
| 333 | |
| 334 | static const int tas5086_ratios[] = { |
| 335 | 64, 128, 192, 256, 384, 512 |
| 336 | }; |
| 337 | |
| 338 | static int index_in_array(const int *array, int len, int needle) |
| 339 | { |
| 340 | int i; |
| 341 | |
| 342 | for (i = 0; i < len; i++) |
| 343 | if (array[i] == needle) |
| 344 | return i; |
| 345 | |
| 346 | return -ENOENT; |
| 347 | } |
| 348 | |
| 349 | static int tas5086_hw_params(struct snd_pcm_substream *substream, |
| 350 | struct snd_pcm_hw_params *params, |
| 351 | struct snd_soc_dai *dai) |
| 352 | { |
| 353 | struct snd_soc_codec *codec = dai->codec; |
| 354 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
Dan Carpenter | 28dbd16 | 2013-03-13 08:32:53 +0300 | [diff] [blame] | 355 | int val; |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 356 | int ret; |
| 357 | |
| 358 | priv->rate = params_rate(params); |
| 359 | |
| 360 | /* Look up the sample rate and refer to the offset in the list */ |
| 361 | val = index_in_array(tas5086_sample_rates, |
| 362 | ARRAY_SIZE(tas5086_sample_rates), priv->rate); |
| 363 | |
| 364 | if (val < 0) { |
| 365 | dev_err(codec->dev, "Invalid sample rate\n"); |
| 366 | return -EINVAL; |
| 367 | } |
| 368 | |
| 369 | ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, |
| 370 | TAS5086_CLOCK_RATE_MASK, |
| 371 | TAS5086_CLOCK_RATE(val)); |
| 372 | if (ret < 0) |
| 373 | return ret; |
| 374 | |
| 375 | /* MCLK / Fs ratio */ |
| 376 | val = index_in_array(tas5086_ratios, ARRAY_SIZE(tas5086_ratios), |
| 377 | priv->mclk / priv->rate); |
| 378 | if (val < 0) { |
| 379 | dev_err(codec->dev, "Inavlid MCLK / Fs ratio\n"); |
| 380 | return -EINVAL; |
| 381 | } |
| 382 | |
| 383 | ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, |
| 384 | TAS5086_CLOCK_RATIO_MASK, |
| 385 | TAS5086_CLOCK_RATIO(val)); |
| 386 | if (ret < 0) |
| 387 | return ret; |
| 388 | |
| 389 | |
| 390 | ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, |
| 391 | TAS5086_CLOCK_SCLK_RATIO_48, |
| 392 | (priv->sclk == 48 * priv->rate) ? |
| 393 | TAS5086_CLOCK_SCLK_RATIO_48 : 0); |
| 394 | if (ret < 0) |
| 395 | return ret; |
| 396 | |
| 397 | /* |
| 398 | * The chip has a very unituitive register mapping and muxes information |
| 399 | * about data format and sample depth into the same register, but not on |
| 400 | * a logical bit-boundary. Hence, we have to refer to the format passed |
| 401 | * in the set_dai_fmt() callback and set up everything from here. |
| 402 | * |
| 403 | * First, determine the 'base' value, using the format ... |
| 404 | */ |
| 405 | switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 406 | case SND_SOC_DAIFMT_RIGHT_J: |
| 407 | val = 0x00; |
| 408 | break; |
| 409 | case SND_SOC_DAIFMT_I2S: |
| 410 | val = 0x03; |
| 411 | break; |
| 412 | case SND_SOC_DAIFMT_LEFT_J: |
| 413 | val = 0x06; |
| 414 | break; |
| 415 | default: |
| 416 | dev_err(codec->dev, "Invalid DAI format\n"); |
| 417 | return -EINVAL; |
| 418 | } |
| 419 | |
| 420 | /* ... then add the offset for the sample bit depth. */ |
| 421 | switch (params_format(params)) { |
| 422 | case SNDRV_PCM_FORMAT_S16_LE: |
| 423 | val += 0; |
| 424 | break; |
| 425 | case SNDRV_PCM_FORMAT_S20_3LE: |
| 426 | val += 1; |
| 427 | break; |
| 428 | case SNDRV_PCM_FORMAT_S24_3LE: |
| 429 | val += 2; |
| 430 | break; |
| 431 | default: |
| 432 | dev_err(codec->dev, "Invalid bit width\n"); |
| 433 | return -EINVAL; |
| 434 | }; |
| 435 | |
| 436 | ret = regmap_write(priv->regmap, TAS5086_SERIAL_DATA_IF, val); |
| 437 | if (ret < 0) |
| 438 | return ret; |
| 439 | |
| 440 | /* clock is considered valid now */ |
| 441 | ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, |
| 442 | TAS5086_CLOCK_VALID, TAS5086_CLOCK_VALID); |
| 443 | if (ret < 0) |
| 444 | return ret; |
| 445 | |
| 446 | return tas5086_set_deemph(codec); |
| 447 | } |
| 448 | |
| 449 | static int tas5086_mute_stream(struct snd_soc_dai *dai, int mute, int stream) |
| 450 | { |
| 451 | struct snd_soc_codec *codec = dai->codec; |
| 452 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 453 | unsigned int val = 0; |
| 454 | |
| 455 | if (mute) |
| 456 | val = TAS5086_SOFT_MUTE_ALL; |
| 457 | |
| 458 | return regmap_write(priv->regmap, TAS5086_SOFT_MUTE, val); |
| 459 | } |
| 460 | |
| 461 | /* TAS5086 controls */ |
| 462 | static const DECLARE_TLV_DB_SCALE(tas5086_dac_tlv, -10350, 50, 1); |
| 463 | |
| 464 | static const struct snd_kcontrol_new tas5086_controls[] = { |
| 465 | SOC_SINGLE_TLV("Master Playback Volume", TAS5086_MASTER_VOL, |
| 466 | 0, 0xff, 1, tas5086_dac_tlv), |
| 467 | SOC_DOUBLE_R_TLV("Channel 1/2 Playback Volume", |
| 468 | TAS5086_CHANNEL_VOL(0), TAS5086_CHANNEL_VOL(1), |
| 469 | 0, 0xff, 1, tas5086_dac_tlv), |
| 470 | SOC_DOUBLE_R_TLV("Channel 3/4 Playback Volume", |
| 471 | TAS5086_CHANNEL_VOL(2), TAS5086_CHANNEL_VOL(3), |
| 472 | 0, 0xff, 1, tas5086_dac_tlv), |
| 473 | SOC_DOUBLE_R_TLV("Channel 5/6 Playback Volume", |
| 474 | TAS5086_CHANNEL_VOL(4), TAS5086_CHANNEL_VOL(5), |
| 475 | 0, 0xff, 1, tas5086_dac_tlv), |
| 476 | SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0, |
| 477 | tas5086_get_deemph, tas5086_put_deemph), |
| 478 | }; |
| 479 | |
Daniel Mack | 18710ac | 2013-06-24 16:25:31 +0200 | [diff] [blame] | 480 | /* Input mux controls */ |
| 481 | static const char *tas5086_dapm_sdin_texts[] = |
| 482 | { |
| 483 | "SDIN1-L", "SDIN1-R", "SDIN2-L", "SDIN2-R", |
| 484 | "SDIN3-L", "SDIN3-R", "Ground (0)", "nc" |
| 485 | }; |
| 486 | |
| 487 | static const struct soc_enum tas5086_dapm_input_mux_enum[] = { |
| 488 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 20, 8, tas5086_dapm_sdin_texts), |
| 489 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 16, 8, tas5086_dapm_sdin_texts), |
| 490 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 12, 8, tas5086_dapm_sdin_texts), |
| 491 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 8, 8, tas5086_dapm_sdin_texts), |
| 492 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 4, 8, tas5086_dapm_sdin_texts), |
| 493 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 0, 8, tas5086_dapm_sdin_texts), |
| 494 | }; |
| 495 | |
| 496 | static const struct snd_kcontrol_new tas5086_dapm_input_mux_controls[] = { |
| 497 | SOC_DAPM_ENUM("Channel 1 input", tas5086_dapm_input_mux_enum[0]), |
| 498 | SOC_DAPM_ENUM("Channel 2 input", tas5086_dapm_input_mux_enum[1]), |
| 499 | SOC_DAPM_ENUM("Channel 3 input", tas5086_dapm_input_mux_enum[2]), |
| 500 | SOC_DAPM_ENUM("Channel 4 input", tas5086_dapm_input_mux_enum[3]), |
| 501 | SOC_DAPM_ENUM("Channel 5 input", tas5086_dapm_input_mux_enum[4]), |
| 502 | SOC_DAPM_ENUM("Channel 6 input", tas5086_dapm_input_mux_enum[5]), |
| 503 | }; |
| 504 | |
| 505 | /* Output mux controls */ |
| 506 | static const char *tas5086_dapm_channel_texts[] = |
| 507 | { "Channel 1 Mux", "Channel 2 Mux", "Channel 3 Mux", |
| 508 | "Channel 4 Mux", "Channel 5 Mux", "Channel 6 Mux" }; |
| 509 | |
| 510 | static const struct soc_enum tas5086_dapm_output_mux_enum[] = { |
| 511 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 20, 6, tas5086_dapm_channel_texts), |
| 512 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 16, 6, tas5086_dapm_channel_texts), |
| 513 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 12, 6, tas5086_dapm_channel_texts), |
| 514 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 8, 6, tas5086_dapm_channel_texts), |
| 515 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 4, 6, tas5086_dapm_channel_texts), |
| 516 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 0, 6, tas5086_dapm_channel_texts), |
| 517 | }; |
| 518 | |
| 519 | static const struct snd_kcontrol_new tas5086_dapm_output_mux_controls[] = { |
| 520 | SOC_DAPM_ENUM("PWM1 Output", tas5086_dapm_output_mux_enum[0]), |
| 521 | SOC_DAPM_ENUM("PWM2 Output", tas5086_dapm_output_mux_enum[1]), |
| 522 | SOC_DAPM_ENUM("PWM3 Output", tas5086_dapm_output_mux_enum[2]), |
| 523 | SOC_DAPM_ENUM("PWM4 Output", tas5086_dapm_output_mux_enum[3]), |
| 524 | SOC_DAPM_ENUM("PWM5 Output", tas5086_dapm_output_mux_enum[4]), |
| 525 | SOC_DAPM_ENUM("PWM6 Output", tas5086_dapm_output_mux_enum[5]), |
| 526 | }; |
| 527 | |
| 528 | static const struct snd_soc_dapm_widget tas5086_dapm_widgets[] = { |
| 529 | SND_SOC_DAPM_INPUT("SDIN1-L"), |
| 530 | SND_SOC_DAPM_INPUT("SDIN1-R"), |
| 531 | SND_SOC_DAPM_INPUT("SDIN2-L"), |
| 532 | SND_SOC_DAPM_INPUT("SDIN2-R"), |
| 533 | SND_SOC_DAPM_INPUT("SDIN3-L"), |
| 534 | SND_SOC_DAPM_INPUT("SDIN3-R"), |
| 535 | SND_SOC_DAPM_INPUT("SDIN4-L"), |
| 536 | SND_SOC_DAPM_INPUT("SDIN4-R"), |
| 537 | |
| 538 | SND_SOC_DAPM_OUTPUT("PWM1"), |
| 539 | SND_SOC_DAPM_OUTPUT("PWM2"), |
| 540 | SND_SOC_DAPM_OUTPUT("PWM3"), |
| 541 | SND_SOC_DAPM_OUTPUT("PWM4"), |
| 542 | SND_SOC_DAPM_OUTPUT("PWM5"), |
| 543 | SND_SOC_DAPM_OUTPUT("PWM6"), |
| 544 | |
| 545 | SND_SOC_DAPM_MUX("Channel 1 Mux", SND_SOC_NOPM, 0, 0, |
| 546 | &tas5086_dapm_input_mux_controls[0]), |
| 547 | SND_SOC_DAPM_MUX("Channel 2 Mux", SND_SOC_NOPM, 0, 0, |
| 548 | &tas5086_dapm_input_mux_controls[1]), |
| 549 | SND_SOC_DAPM_MUX("Channel 3 Mux", SND_SOC_NOPM, 0, 0, |
| 550 | &tas5086_dapm_input_mux_controls[2]), |
| 551 | SND_SOC_DAPM_MUX("Channel 4 Mux", SND_SOC_NOPM, 0, 0, |
| 552 | &tas5086_dapm_input_mux_controls[3]), |
| 553 | SND_SOC_DAPM_MUX("Channel 5 Mux", SND_SOC_NOPM, 0, 0, |
| 554 | &tas5086_dapm_input_mux_controls[4]), |
| 555 | SND_SOC_DAPM_MUX("Channel 6 Mux", SND_SOC_NOPM, 0, 0, |
| 556 | &tas5086_dapm_input_mux_controls[5]), |
| 557 | |
| 558 | SND_SOC_DAPM_MUX("PWM1 Mux", SND_SOC_NOPM, 0, 0, |
| 559 | &tas5086_dapm_output_mux_controls[0]), |
| 560 | SND_SOC_DAPM_MUX("PWM2 Mux", SND_SOC_NOPM, 0, 0, |
| 561 | &tas5086_dapm_output_mux_controls[1]), |
| 562 | SND_SOC_DAPM_MUX("PWM3 Mux", SND_SOC_NOPM, 0, 0, |
| 563 | &tas5086_dapm_output_mux_controls[2]), |
| 564 | SND_SOC_DAPM_MUX("PWM4 Mux", SND_SOC_NOPM, 0, 0, |
| 565 | &tas5086_dapm_output_mux_controls[3]), |
| 566 | SND_SOC_DAPM_MUX("PWM5 Mux", SND_SOC_NOPM, 0, 0, |
| 567 | &tas5086_dapm_output_mux_controls[4]), |
| 568 | SND_SOC_DAPM_MUX("PWM6 Mux", SND_SOC_NOPM, 0, 0, |
| 569 | &tas5086_dapm_output_mux_controls[5]), |
| 570 | }; |
| 571 | |
| 572 | static const struct snd_soc_dapm_route tas5086_dapm_routes[] = { |
| 573 | /* SDIN inputs -> channel muxes */ |
| 574 | { "Channel 1 Mux", "SDIN1-L", "SDIN1-L" }, |
| 575 | { "Channel 1 Mux", "SDIN1-R", "SDIN1-R" }, |
| 576 | { "Channel 1 Mux", "SDIN2-L", "SDIN2-L" }, |
| 577 | { "Channel 1 Mux", "SDIN2-R", "SDIN2-R" }, |
| 578 | { "Channel 1 Mux", "SDIN3-L", "SDIN3-L" }, |
| 579 | { "Channel 1 Mux", "SDIN3-R", "SDIN3-R" }, |
| 580 | |
| 581 | { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" }, |
| 582 | { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" }, |
| 583 | { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" }, |
| 584 | { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" }, |
| 585 | { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" }, |
| 586 | { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" }, |
| 587 | |
| 588 | { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" }, |
| 589 | { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" }, |
| 590 | { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" }, |
| 591 | { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" }, |
| 592 | { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" }, |
| 593 | { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" }, |
| 594 | |
| 595 | { "Channel 3 Mux", "SDIN1-L", "SDIN1-L" }, |
| 596 | { "Channel 3 Mux", "SDIN1-R", "SDIN1-R" }, |
| 597 | { "Channel 3 Mux", "SDIN2-L", "SDIN2-L" }, |
| 598 | { "Channel 3 Mux", "SDIN2-R", "SDIN2-R" }, |
| 599 | { "Channel 3 Mux", "SDIN3-L", "SDIN3-L" }, |
| 600 | { "Channel 3 Mux", "SDIN3-R", "SDIN3-R" }, |
| 601 | |
| 602 | { "Channel 4 Mux", "SDIN1-L", "SDIN1-L" }, |
| 603 | { "Channel 4 Mux", "SDIN1-R", "SDIN1-R" }, |
| 604 | { "Channel 4 Mux", "SDIN2-L", "SDIN2-L" }, |
| 605 | { "Channel 4 Mux", "SDIN2-R", "SDIN2-R" }, |
| 606 | { "Channel 4 Mux", "SDIN3-L", "SDIN3-L" }, |
| 607 | { "Channel 4 Mux", "SDIN3-R", "SDIN3-R" }, |
| 608 | |
| 609 | { "Channel 5 Mux", "SDIN1-L", "SDIN1-L" }, |
| 610 | { "Channel 5 Mux", "SDIN1-R", "SDIN1-R" }, |
| 611 | { "Channel 5 Mux", "SDIN2-L", "SDIN2-L" }, |
| 612 | { "Channel 5 Mux", "SDIN2-R", "SDIN2-R" }, |
| 613 | { "Channel 5 Mux", "SDIN3-L", "SDIN3-L" }, |
| 614 | { "Channel 5 Mux", "SDIN3-R", "SDIN3-R" }, |
| 615 | |
| 616 | { "Channel 6 Mux", "SDIN1-L", "SDIN1-L" }, |
| 617 | { "Channel 6 Mux", "SDIN1-R", "SDIN1-R" }, |
| 618 | { "Channel 6 Mux", "SDIN2-L", "SDIN2-L" }, |
| 619 | { "Channel 6 Mux", "SDIN2-R", "SDIN2-R" }, |
| 620 | { "Channel 6 Mux", "SDIN3-L", "SDIN3-L" }, |
| 621 | { "Channel 6 Mux", "SDIN3-R", "SDIN3-R" }, |
| 622 | |
| 623 | /* Channel muxes -> PWM muxes */ |
| 624 | { "PWM1 Mux", "Channel 1 Mux", "Channel 1 Mux" }, |
| 625 | { "PWM2 Mux", "Channel 1 Mux", "Channel 1 Mux" }, |
| 626 | { "PWM3 Mux", "Channel 1 Mux", "Channel 1 Mux" }, |
| 627 | { "PWM4 Mux", "Channel 1 Mux", "Channel 1 Mux" }, |
| 628 | { "PWM5 Mux", "Channel 1 Mux", "Channel 1 Mux" }, |
| 629 | { "PWM6 Mux", "Channel 1 Mux", "Channel 1 Mux" }, |
| 630 | |
| 631 | { "PWM1 Mux", "Channel 2 Mux", "Channel 2 Mux" }, |
| 632 | { "PWM2 Mux", "Channel 2 Mux", "Channel 2 Mux" }, |
| 633 | { "PWM3 Mux", "Channel 2 Mux", "Channel 2 Mux" }, |
| 634 | { "PWM4 Mux", "Channel 2 Mux", "Channel 2 Mux" }, |
| 635 | { "PWM5 Mux", "Channel 2 Mux", "Channel 2 Mux" }, |
| 636 | { "PWM6 Mux", "Channel 2 Mux", "Channel 2 Mux" }, |
| 637 | |
| 638 | { "PWM1 Mux", "Channel 3 Mux", "Channel 3 Mux" }, |
| 639 | { "PWM2 Mux", "Channel 3 Mux", "Channel 3 Mux" }, |
| 640 | { "PWM3 Mux", "Channel 3 Mux", "Channel 3 Mux" }, |
| 641 | { "PWM4 Mux", "Channel 3 Mux", "Channel 3 Mux" }, |
| 642 | { "PWM5 Mux", "Channel 3 Mux", "Channel 3 Mux" }, |
| 643 | { "PWM6 Mux", "Channel 3 Mux", "Channel 3 Mux" }, |
| 644 | |
| 645 | { "PWM1 Mux", "Channel 4 Mux", "Channel 4 Mux" }, |
| 646 | { "PWM2 Mux", "Channel 4 Mux", "Channel 4 Mux" }, |
| 647 | { "PWM3 Mux", "Channel 4 Mux", "Channel 4 Mux" }, |
| 648 | { "PWM4 Mux", "Channel 4 Mux", "Channel 4 Mux" }, |
| 649 | { "PWM5 Mux", "Channel 4 Mux", "Channel 4 Mux" }, |
| 650 | { "PWM6 Mux", "Channel 4 Mux", "Channel 4 Mux" }, |
| 651 | |
| 652 | { "PWM1 Mux", "Channel 5 Mux", "Channel 5 Mux" }, |
| 653 | { "PWM2 Mux", "Channel 5 Mux", "Channel 5 Mux" }, |
| 654 | { "PWM3 Mux", "Channel 5 Mux", "Channel 5 Mux" }, |
| 655 | { "PWM4 Mux", "Channel 5 Mux", "Channel 5 Mux" }, |
| 656 | { "PWM5 Mux", "Channel 5 Mux", "Channel 5 Mux" }, |
| 657 | { "PWM6 Mux", "Channel 5 Mux", "Channel 5 Mux" }, |
| 658 | |
| 659 | { "PWM1 Mux", "Channel 6 Mux", "Channel 6 Mux" }, |
| 660 | { "PWM2 Mux", "Channel 6 Mux", "Channel 6 Mux" }, |
| 661 | { "PWM3 Mux", "Channel 6 Mux", "Channel 6 Mux" }, |
| 662 | { "PWM4 Mux", "Channel 6 Mux", "Channel 6 Mux" }, |
| 663 | { "PWM5 Mux", "Channel 6 Mux", "Channel 6 Mux" }, |
| 664 | { "PWM6 Mux", "Channel 6 Mux", "Channel 6 Mux" }, |
| 665 | |
| 666 | /* The PWM muxes are directly connected to the PWM outputs */ |
| 667 | { "PWM1", NULL, "PWM1 Mux" }, |
| 668 | { "PWM2", NULL, "PWM2 Mux" }, |
| 669 | { "PWM3", NULL, "PWM3 Mux" }, |
| 670 | { "PWM4", NULL, "PWM4 Mux" }, |
| 671 | { "PWM5", NULL, "PWM5 Mux" }, |
| 672 | { "PWM6", NULL, "PWM6 Mux" }, |
| 673 | |
| 674 | }; |
| 675 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 676 | static const struct snd_soc_dai_ops tas5086_dai_ops = { |
| 677 | .hw_params = tas5086_hw_params, |
| 678 | .set_sysclk = tas5086_set_dai_sysclk, |
| 679 | .set_fmt = tas5086_set_dai_fmt, |
| 680 | .mute_stream = tas5086_mute_stream, |
| 681 | }; |
| 682 | |
| 683 | static struct snd_soc_dai_driver tas5086_dai = { |
| 684 | .name = "tas5086-hifi", |
| 685 | .playback = { |
| 686 | .stream_name = "Playback", |
| 687 | .channels_min = 2, |
| 688 | .channels_max = 6, |
| 689 | .rates = TAS5086_PCM_RATES, |
| 690 | .formats = TAS5086_PCM_FORMATS, |
| 691 | }, |
| 692 | .ops = &tas5086_dai_ops, |
| 693 | }; |
| 694 | |
| 695 | #ifdef CONFIG_PM |
| 696 | static int tas5086_soc_resume(struct snd_soc_codec *codec) |
| 697 | { |
| 698 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 699 | |
| 700 | /* Restore codec state */ |
| 701 | return regcache_sync(priv->regmap); |
| 702 | } |
| 703 | #else |
| 704 | #define tas5086_soc_resume NULL |
| 705 | #endif /* CONFIG_PM */ |
| 706 | |
| 707 | #ifdef CONFIG_OF |
| 708 | static const struct of_device_id tas5086_dt_ids[] = { |
| 709 | { .compatible = "ti,tas5086", }, |
| 710 | { } |
| 711 | }; |
| 712 | MODULE_DEVICE_TABLE(of, tas5086_dt_ids); |
| 713 | #endif |
| 714 | |
| 715 | /* charge period values in microseconds */ |
| 716 | static const int tas5086_charge_period[] = { |
| 717 | 13000, 16900, 23400, 31200, 41600, 54600, 72800, 96200, |
| 718 | 130000, 156000, 234000, 312000, 416000, 546000, 728000, 962000, |
| 719 | 1300000, 169000, 2340000, 3120000, 4160000, 5460000, 7280000, 9620000, |
| 720 | }; |
| 721 | |
| 722 | static int tas5086_probe(struct snd_soc_codec *codec) |
| 723 | { |
| 724 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 725 | int i, ret; |
| 726 | |
Daniel Mack | 648c538 | 2013-10-01 14:48:24 +0200 | [diff] [blame^] | 727 | priv->pwm_start_mid_z = 0; |
| 728 | priv->charge_period = 1300000; /* hardware default is 1300 ms */ |
| 729 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 730 | if (of_match_device(of_match_ptr(tas5086_dt_ids), codec->dev)) { |
| 731 | struct device_node *of_node = codec->dev->of_node; |
Daniel Mack | 648c538 | 2013-10-01 14:48:24 +0200 | [diff] [blame^] | 732 | of_property_read_u32(of_node, "ti,charge-period", |
| 733 | &priv->charge_period); |
Daniel Mack | 79b23b5 | 2013-06-24 16:25:32 +0200 | [diff] [blame] | 734 | |
| 735 | for (i = 0; i < 6; i++) { |
| 736 | char name[25]; |
| 737 | |
| 738 | snprintf(name, sizeof(name), |
| 739 | "ti,mid-z-channel-%d", i + 1); |
| 740 | |
| 741 | if (of_get_property(of_node, name, NULL) != NULL) |
Daniel Mack | 648c538 | 2013-10-01 14:48:24 +0200 | [diff] [blame^] | 742 | priv->pwm_start_mid_z |= 1 << i; |
Daniel Mack | 79b23b5 | 2013-06-24 16:25:32 +0200 | [diff] [blame] | 743 | } |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 744 | } |
| 745 | |
Daniel Mack | 79b23b5 | 2013-06-24 16:25:32 +0200 | [diff] [blame] | 746 | /* |
Daniel Mack | a975873 | 2013-06-27 21:59:11 +0200 | [diff] [blame] | 747 | * If any of the channels is configured to start in Mid-Z mode, |
| 748 | * configure 'part 1' of the PWM starts to use Mid-Z, and tell |
| 749 | * all configured mid-z channels to start start under 'part 1'. |
Daniel Mack | 79b23b5 | 2013-06-24 16:25:32 +0200 | [diff] [blame] | 750 | */ |
Daniel Mack | 648c538 | 2013-10-01 14:48:24 +0200 | [diff] [blame^] | 751 | if (priv->pwm_start_mid_z) |
Daniel Mack | a975873 | 2013-06-27 21:59:11 +0200 | [diff] [blame] | 752 | regmap_write(priv->regmap, TAS5086_PWM_START, |
| 753 | TAS5086_PWM_START_MIDZ_FOR_START_1 | |
Daniel Mack | 648c538 | 2013-10-01 14:48:24 +0200 | [diff] [blame^] | 754 | priv->pwm_start_mid_z); |
Daniel Mack | 79b23b5 | 2013-06-24 16:25:32 +0200 | [diff] [blame] | 755 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 756 | /* lookup and set split-capacitor charge period */ |
Daniel Mack | 648c538 | 2013-10-01 14:48:24 +0200 | [diff] [blame^] | 757 | if (priv->charge_period == 0) { |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 758 | regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, 0); |
| 759 | } else { |
| 760 | i = index_in_array(tas5086_charge_period, |
| 761 | ARRAY_SIZE(tas5086_charge_period), |
Daniel Mack | 648c538 | 2013-10-01 14:48:24 +0200 | [diff] [blame^] | 762 | priv->charge_period); |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 763 | if (i >= 0) |
| 764 | regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, |
| 765 | i + 0x08); |
| 766 | else |
| 767 | dev_warn(codec->dev, |
| 768 | "Invalid split-cap charge period of %d ns.\n", |
Daniel Mack | 648c538 | 2013-10-01 14:48:24 +0200 | [diff] [blame^] | 769 | priv->charge_period); |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 770 | } |
| 771 | |
| 772 | /* enable factory trim */ |
| 773 | ret = regmap_write(priv->regmap, TAS5086_OSC_TRIM, 0x00); |
| 774 | if (ret < 0) |
| 775 | return ret; |
| 776 | |
| 777 | /* start all channels */ |
| 778 | ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x20); |
| 779 | if (ret < 0) |
| 780 | return ret; |
| 781 | |
| 782 | /* set master volume to 0 dB */ |
| 783 | ret = regmap_write(priv->regmap, TAS5086_MASTER_VOL, 0x30); |
| 784 | if (ret < 0) |
| 785 | return ret; |
| 786 | |
| 787 | /* mute all channels for now */ |
| 788 | ret = regmap_write(priv->regmap, TAS5086_SOFT_MUTE, |
| 789 | TAS5086_SOFT_MUTE_ALL); |
| 790 | if (ret < 0) |
| 791 | return ret; |
| 792 | |
| 793 | return 0; |
| 794 | } |
| 795 | |
| 796 | static int tas5086_remove(struct snd_soc_codec *codec) |
| 797 | { |
| 798 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 799 | |
| 800 | if (gpio_is_valid(priv->gpio_nreset)) |
| 801 | /* Set codec to the reset state */ |
| 802 | gpio_set_value(priv->gpio_nreset, 0); |
| 803 | |
| 804 | return 0; |
| 805 | }; |
| 806 | |
| 807 | static struct snd_soc_codec_driver soc_codec_dev_tas5086 = { |
| 808 | .probe = tas5086_probe, |
| 809 | .remove = tas5086_remove, |
| 810 | .resume = tas5086_soc_resume, |
| 811 | .controls = tas5086_controls, |
| 812 | .num_controls = ARRAY_SIZE(tas5086_controls), |
Daniel Mack | 18710ac | 2013-06-24 16:25:31 +0200 | [diff] [blame] | 813 | .dapm_widgets = tas5086_dapm_widgets, |
| 814 | .num_dapm_widgets = ARRAY_SIZE(tas5086_dapm_widgets), |
| 815 | .dapm_routes = tas5086_dapm_routes, |
| 816 | .num_dapm_routes = ARRAY_SIZE(tas5086_dapm_routes), |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 817 | }; |
| 818 | |
| 819 | static const struct i2c_device_id tas5086_i2c_id[] = { |
| 820 | { "tas5086", 0 }, |
| 821 | { } |
| 822 | }; |
| 823 | MODULE_DEVICE_TABLE(i2c, tas5086_i2c_id); |
| 824 | |
| 825 | static const struct regmap_config tas5086_regmap = { |
| 826 | .reg_bits = 8, |
Daniel Mack | 8892d47 | 2013-06-24 16:25:30 +0200 | [diff] [blame] | 827 | .val_bits = 32, |
| 828 | .max_register = TAS5086_MAX_REGISTER, |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 829 | .reg_defaults = tas5086_reg_defaults, |
| 830 | .num_reg_defaults = ARRAY_SIZE(tas5086_reg_defaults), |
| 831 | .cache_type = REGCACHE_RBTREE, |
| 832 | .volatile_reg = tas5086_volatile_reg, |
| 833 | .writeable_reg = tas5086_writeable_reg, |
| 834 | .readable_reg = tas5086_accessible_reg, |
Daniel Mack | 6b36d37 | 2013-06-24 16:25:29 +0200 | [diff] [blame] | 835 | .reg_read = tas5086_reg_read, |
| 836 | .reg_write = tas5086_reg_write, |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 837 | }; |
| 838 | |
| 839 | static int tas5086_i2c_probe(struct i2c_client *i2c, |
| 840 | const struct i2c_device_id *id) |
| 841 | { |
| 842 | struct tas5086_private *priv; |
| 843 | struct device *dev = &i2c->dev; |
| 844 | int gpio_nreset = -EINVAL; |
| 845 | int i, ret; |
| 846 | |
| 847 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
| 848 | if (!priv) |
| 849 | return -ENOMEM; |
| 850 | |
Daniel Mack | 6b36d37 | 2013-06-24 16:25:29 +0200 | [diff] [blame] | 851 | priv->regmap = devm_regmap_init(dev, NULL, i2c, &tas5086_regmap); |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 852 | if (IS_ERR(priv->regmap)) { |
| 853 | ret = PTR_ERR(priv->regmap); |
| 854 | dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret); |
| 855 | return ret; |
| 856 | } |
| 857 | |
| 858 | i2c_set_clientdata(i2c, priv); |
| 859 | |
| 860 | if (of_match_device(of_match_ptr(tas5086_dt_ids), dev)) { |
| 861 | struct device_node *of_node = dev->of_node; |
| 862 | gpio_nreset = of_get_named_gpio(of_node, "reset-gpio", 0); |
| 863 | } |
| 864 | |
| 865 | if (gpio_is_valid(gpio_nreset)) |
| 866 | if (devm_gpio_request(dev, gpio_nreset, "TAS5086 Reset")) |
| 867 | gpio_nreset = -EINVAL; |
| 868 | |
| 869 | if (gpio_is_valid(gpio_nreset)) { |
| 870 | /* Reset codec - minimum assertion time is 400ns */ |
| 871 | gpio_direction_output(gpio_nreset, 0); |
| 872 | udelay(1); |
| 873 | gpio_set_value(gpio_nreset, 1); |
| 874 | |
| 875 | /* Codec needs ~15ms to wake up */ |
| 876 | msleep(15); |
| 877 | } |
| 878 | |
| 879 | priv->gpio_nreset = gpio_nreset; |
| 880 | |
| 881 | /* The TAS5086 always returns 0x03 in its TAS5086_DEV_ID register */ |
| 882 | ret = regmap_read(priv->regmap, TAS5086_DEV_ID, &i); |
| 883 | if (ret < 0) |
| 884 | return ret; |
| 885 | |
| 886 | if (i != 0x3) { |
| 887 | dev_err(dev, |
| 888 | "Failed to identify TAS5086 codec (got %02x)\n", i); |
| 889 | return -ENODEV; |
| 890 | } |
| 891 | |
| 892 | return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_tas5086, |
| 893 | &tas5086_dai, 1); |
| 894 | } |
| 895 | |
| 896 | static int tas5086_i2c_remove(struct i2c_client *i2c) |
| 897 | { |
| 898 | snd_soc_unregister_codec(&i2c->dev); |
| 899 | return 0; |
| 900 | } |
| 901 | |
| 902 | static struct i2c_driver tas5086_i2c_driver = { |
| 903 | .driver = { |
| 904 | .name = "tas5086", |
| 905 | .owner = THIS_MODULE, |
| 906 | .of_match_table = of_match_ptr(tas5086_dt_ids), |
| 907 | }, |
| 908 | .id_table = tas5086_i2c_id, |
| 909 | .probe = tas5086_i2c_probe, |
| 910 | .remove = tas5086_i2c_remove, |
| 911 | }; |
| 912 | |
Wei Yongjun | c300d6d | 2013-03-12 21:36:24 +0800 | [diff] [blame] | 913 | module_i2c_driver(tas5086_i2c_driver); |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 914 | |
| 915 | MODULE_AUTHOR("Daniel Mack <zonque@gmail.com>"); |
| 916 | MODULE_DESCRIPTION("Texas Instruments TAS5086 ALSA SoC Codec Driver"); |
| 917 | MODULE_LICENSE("GPL"); |