Micky Ching | fa590c2 | 2013-11-12 17:16:08 +0800 | [diff] [blame] | 1 | /* Driver for Realtek PCI-Express card reader |
| 2 | * |
| 3 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation; either version 2, or (at your option) any |
| 8 | * later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, but |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 13 | * General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along |
| 16 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 17 | * |
| 18 | * Author: |
| 19 | * Wei WANG (wei_wang@realsil.com.cn) |
| 20 | * Micky Ching (micky_ching@realsil.com.cn) |
| 21 | */ |
| 22 | |
| 23 | #include <linux/blkdev.h> |
| 24 | #include <linux/kthread.h> |
| 25 | #include <linux/sched.h> |
| 26 | #include <linux/workqueue.h> |
| 27 | #include <linux/vmalloc.h> |
| 28 | |
| 29 | #include "rtsx.h" |
| 30 | #include "rtsx_transport.h" |
| 31 | #include "rtsx_scsi.h" |
| 32 | #include "rtsx_card.h" |
| 33 | #include "rtsx_chip.h" |
| 34 | #include "rtsx_sys.h" |
| 35 | #include "general.h" |
| 36 | |
| 37 | #include "sd.h" |
| 38 | #include "xd.h" |
| 39 | #include "ms.h" |
| 40 | |
| 41 | static void rtsx_calibration(struct rtsx_chip *chip) |
| 42 | { |
| 43 | rtsx_write_phy_register(chip, 0x1B, 0x135E); |
| 44 | wait_timeout(10); |
| 45 | rtsx_write_phy_register(chip, 0x00, 0x0280); |
| 46 | rtsx_write_phy_register(chip, 0x01, 0x7112); |
| 47 | rtsx_write_phy_register(chip, 0x01, 0x7110); |
| 48 | rtsx_write_phy_register(chip, 0x01, 0x7112); |
| 49 | rtsx_write_phy_register(chip, 0x01, 0x7113); |
| 50 | rtsx_write_phy_register(chip, 0x00, 0x0288); |
| 51 | } |
| 52 | |
| 53 | void rtsx_disable_card_int(struct rtsx_chip *chip) |
| 54 | { |
| 55 | u32 reg = rtsx_readl(chip, RTSX_BIER); |
| 56 | |
| 57 | reg &= ~(XD_INT_EN | SD_INT_EN | MS_INT_EN); |
| 58 | rtsx_writel(chip, RTSX_BIER, reg); |
| 59 | } |
| 60 | |
| 61 | void rtsx_enable_card_int(struct rtsx_chip *chip) |
| 62 | { |
| 63 | u32 reg = rtsx_readl(chip, RTSX_BIER); |
| 64 | int i; |
| 65 | |
| 66 | for (i = 0; i <= chip->max_lun; i++) { |
| 67 | if (chip->lun2card[i] & XD_CARD) |
| 68 | reg |= XD_INT_EN; |
| 69 | if (chip->lun2card[i] & SD_CARD) |
| 70 | reg |= SD_INT_EN; |
| 71 | if (chip->lun2card[i] & MS_CARD) |
| 72 | reg |= MS_INT_EN; |
| 73 | } |
| 74 | if (chip->hw_bypass_sd) |
| 75 | reg &= ~((u32)SD_INT_EN); |
| 76 | |
| 77 | rtsx_writel(chip, RTSX_BIER, reg); |
| 78 | } |
| 79 | |
| 80 | void rtsx_enable_bus_int(struct rtsx_chip *chip) |
| 81 | { |
| 82 | u32 reg = 0; |
| 83 | #ifndef DISABLE_CARD_INT |
| 84 | int i; |
| 85 | #endif |
| 86 | |
| 87 | reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN; |
| 88 | |
| 89 | #ifndef DISABLE_CARD_INT |
| 90 | for (i = 0; i <= chip->max_lun; i++) { |
| 91 | RTSX_DEBUGP("lun2card[%d] = 0x%02x\n", i, chip->lun2card[i]); |
| 92 | |
| 93 | if (chip->lun2card[i] & XD_CARD) |
| 94 | reg |= XD_INT_EN; |
| 95 | if (chip->lun2card[i] & SD_CARD) |
| 96 | reg |= SD_INT_EN; |
| 97 | if (chip->lun2card[i] & MS_CARD) |
| 98 | reg |= MS_INT_EN; |
| 99 | } |
| 100 | if (chip->hw_bypass_sd) |
| 101 | reg &= ~((u32)SD_INT_EN); |
| 102 | #endif |
| 103 | |
| 104 | if (chip->ic_version >= IC_VER_C) |
| 105 | reg |= DELINK_INT_EN; |
| 106 | #ifdef SUPPORT_OCP |
| 107 | reg |= OC_INT_EN; |
| 108 | #endif |
| 109 | if (!chip->adma_mode) |
| 110 | reg |= DATA_DONE_INT_EN; |
| 111 | |
| 112 | /* Enable Bus Interrupt */ |
| 113 | rtsx_writel(chip, RTSX_BIER, reg); |
| 114 | |
| 115 | RTSX_DEBUGP("RTSX_BIER: 0x%08x\n", reg); |
| 116 | } |
| 117 | |
| 118 | void rtsx_disable_bus_int(struct rtsx_chip *chip) |
| 119 | { |
| 120 | rtsx_writel(chip, RTSX_BIER, 0); |
| 121 | } |
| 122 | |
| 123 | static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip) |
| 124 | { |
| 125 | if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) { |
| 126 | if (chip->asic_code) { |
| 127 | RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, |
| 128 | MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU); |
| 129 | } else { |
| 130 | RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, |
| 131 | FPGA_SD_PULL_CTL_EN); |
| 132 | } |
| 133 | RTSX_WRITE_REG(chip, CARD_SHARE_MODE, 0xFF, CARD_SHARE_48_SD); |
| 134 | |
| 135 | /* Enable SDIO internal clock */ |
| 136 | RTSX_WRITE_REG(chip, 0xFF2C, 0x01, 0x01); |
| 137 | |
| 138 | RTSX_WRITE_REG(chip, SDIO_CTRL, 0xFF, |
| 139 | SDIO_BUS_CTRL | SDIO_CD_CTRL); |
| 140 | |
| 141 | chip->sd_int = 1; |
| 142 | chip->sd_io = 1; |
| 143 | } else { |
| 144 | chip->need_reset |= SD_CARD; |
| 145 | } |
| 146 | |
| 147 | return STATUS_SUCCESS; |
| 148 | } |
| 149 | |
| 150 | #ifdef HW_AUTO_SWITCH_SD_BUS |
| 151 | static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip) |
| 152 | { |
| 153 | u8 tmp; |
| 154 | int sw_bypass_sd = 0; |
| 155 | int retval; |
| 156 | |
| 157 | if (chip->driver_first_load) { |
| 158 | if (CHECK_PID(chip, 0x5288)) { |
| 159 | RTSX_READ_REG(chip, 0xFE5A, &tmp); |
| 160 | if (tmp & 0x08) |
| 161 | sw_bypass_sd = 1; |
| 162 | } else if (CHECK_PID(chip, 0x5208)) { |
| 163 | RTSX_READ_REG(chip, 0xFE70, &tmp); |
| 164 | if (tmp & 0x80) |
| 165 | sw_bypass_sd = 1; |
| 166 | } |
| 167 | } else { |
| 168 | if (chip->sdio_in_charge) |
| 169 | sw_bypass_sd = 1; |
| 170 | } |
| 171 | RTSX_DEBUGP("chip->sdio_in_charge = %d\n", chip->sdio_in_charge); |
| 172 | RTSX_DEBUGP("chip->driver_first_load = %d\n", chip->driver_first_load); |
| 173 | RTSX_DEBUGP("sw_bypass_sd = %d\n", sw_bypass_sd); |
| 174 | |
| 175 | if (sw_bypass_sd) { |
| 176 | u8 cd_toggle_mask = 0; |
| 177 | |
| 178 | RTSX_READ_REG(chip, TLPTISTAT, &tmp); |
| 179 | cd_toggle_mask = 0x08; |
| 180 | |
| 181 | if (tmp & cd_toggle_mask) { |
| 182 | /* Disable sdio_bus_auto_switch */ |
| 183 | if (CHECK_PID(chip, 0x5288)) |
| 184 | RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x00); |
| 185 | else if (CHECK_PID(chip, 0x5208)) |
| 186 | RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x00); |
| 187 | |
| 188 | RTSX_WRITE_REG(chip, TLPTISTAT, 0xFF, tmp); |
| 189 | |
| 190 | chip->need_reset |= SD_CARD; |
| 191 | } else { |
| 192 | RTSX_DEBUGP("Chip inserted with SDIO!\n"); |
| 193 | |
| 194 | if (chip->asic_code) { |
| 195 | retval = sd_pull_ctl_enable(chip); |
| 196 | if (retval != STATUS_SUCCESS) |
| 197 | TRACE_RET(chip, STATUS_FAIL); |
| 198 | } else { |
| 199 | RTSX_WRITE_REG(chip, FPGA_PULL_CTL, |
| 200 | FPGA_SD_PULL_CTL_BIT | 0x20, 0); |
| 201 | } |
| 202 | retval = card_share_mode(chip, SD_CARD); |
| 203 | if (retval != STATUS_SUCCESS) |
| 204 | TRACE_RET(chip, STATUS_FAIL); |
| 205 | |
| 206 | /* Enable sdio_bus_auto_switch */ |
| 207 | if (CHECK_PID(chip, 0x5288)) |
| 208 | RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x08); |
| 209 | else if (CHECK_PID(chip, 0x5208)) |
| 210 | RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x80); |
| 211 | |
| 212 | chip->chip_insert_with_sdio = 1; |
| 213 | chip->sd_io = 1; |
| 214 | } |
| 215 | } else { |
| 216 | RTSX_WRITE_REG(chip, TLPTISTAT, 0x08, 0x08); |
| 217 | |
| 218 | chip->need_reset |= SD_CARD; |
| 219 | } |
| 220 | |
| 221 | return STATUS_SUCCESS; |
| 222 | } |
| 223 | #endif |
| 224 | |
| 225 | int rtsx_reset_chip(struct rtsx_chip *chip) |
| 226 | { |
| 227 | int retval; |
| 228 | |
| 229 | rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr); |
| 230 | |
| 231 | rtsx_disable_aspm(chip); |
| 232 | |
| 233 | RTSX_WRITE_REG(chip, HOST_SLEEP_STATE, 0x03, 0x00); |
| 234 | |
| 235 | /* Disable card clock */ |
| 236 | RTSX_WRITE_REG(chip, CARD_CLK_EN, 0x1E, 0); |
| 237 | |
| 238 | #ifdef SUPPORT_OCP |
| 239 | /* SSC power on, OCD power on */ |
| 240 | if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) |
| 241 | RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, 0); |
| 242 | else |
| 243 | RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, MS_OC_POWER_DOWN); |
| 244 | |
| 245 | RTSX_WRITE_REG(chip, OCPPARA1, OCP_TIME_MASK, OCP_TIME_800); |
| 246 | RTSX_WRITE_REG(chip, OCPPARA2, OCP_THD_MASK, OCP_THD_244_946); |
| 247 | RTSX_WRITE_REG(chip, OCPCTL, 0xFF, CARD_OC_INT_EN | CARD_DETECT_EN); |
| 248 | #else |
| 249 | /* OC power down */ |
| 250 | RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, OC_POWER_DOWN); |
| 251 | #endif |
| 252 | |
| 253 | if (!CHECK_PID(chip, 0x5288)) |
| 254 | RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0xFF, 0x03); |
| 255 | |
| 256 | /* Turn off LED */ |
| 257 | RTSX_WRITE_REG(chip, CARD_GPIO, 0xFF, 0x03); |
| 258 | |
| 259 | /* Reset delink mode */ |
| 260 | RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x0A, 0); |
| 261 | |
| 262 | /* Card driving select */ |
| 263 | RTSX_WRITE_REG(chip, CARD_DRIVE_SEL, 0xFF, chip->card_drive_sel); |
| 264 | |
| 265 | #ifdef LED_AUTO_BLINK |
| 266 | RTSX_WRITE_REG(chip, CARD_AUTO_BLINK, 0xFF, |
| 267 | LED_BLINK_SPEED | BLINK_EN | LED_GPIO0); |
| 268 | #endif |
| 269 | |
| 270 | if (chip->asic_code) { |
| 271 | /* Enable SSC Clock */ |
| 272 | RTSX_WRITE_REG(chip, SSC_CTL1, 0xFF, SSC_8X_EN | SSC_SEL_4M); |
| 273 | RTSX_WRITE_REG(chip, SSC_CTL2, 0xFF, 0x12); |
| 274 | } |
| 275 | |
| 276 | /* Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0) |
| 277 | 0xFE5B |
| 278 | bit[1] u_cd_rst_core_en rst_value = 0 |
| 279 | bit[2] u_force_rst_core_en rst_value = 0 |
| 280 | bit[5] u_mac_phy_rst_n_dbg rst_value = 1 |
| 281 | bit[4] u_non_sticky_rst_n_dbg rst_value = 0 |
| 282 | */ |
| 283 | RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x16, 0x10); |
| 284 | |
| 285 | /* Enable ASPM */ |
| 286 | if (chip->aspm_l0s_l1_en) { |
| 287 | if (chip->dynamic_aspm) { |
| 288 | if (CHK_SDIO_EXIST(chip)) { |
| 289 | if (CHECK_PID(chip, 0x5288)) { |
| 290 | retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, chip->aspm_l0s_l1_en); |
| 291 | if (retval != STATUS_SUCCESS) |
| 292 | TRACE_RET(chip, STATUS_FAIL); |
| 293 | } |
| 294 | } |
| 295 | } else { |
| 296 | if (CHECK_PID(chip, 0x5208)) |
| 297 | RTSX_WRITE_REG(chip, ASPM_FORCE_CTL, |
| 298 | 0xFF, 0x3F); |
| 299 | |
| 300 | retval = rtsx_write_config_byte(chip, LCTLR, |
| 301 | chip->aspm_l0s_l1_en); |
| 302 | if (retval != STATUS_SUCCESS) |
| 303 | TRACE_RET(chip, STATUS_FAIL); |
| 304 | |
| 305 | chip->aspm_level[0] = chip->aspm_l0s_l1_en; |
| 306 | if (CHK_SDIO_EXIST(chip)) { |
| 307 | chip->aspm_level[1] = chip->aspm_l0s_l1_en; |
| 308 | if (CHECK_PID(chip, 0x5288)) |
| 309 | retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, chip->aspm_l0s_l1_en); |
| 310 | else |
| 311 | retval = rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF, chip->aspm_l0s_l1_en); |
| 312 | |
| 313 | if (retval != STATUS_SUCCESS) |
| 314 | TRACE_RET(chip, STATUS_FAIL); |
| 315 | |
| 316 | } |
| 317 | |
| 318 | chip->aspm_enabled = 1; |
| 319 | } |
| 320 | } else { |
| 321 | if (chip->asic_code && CHECK_PID(chip, 0x5208)) { |
| 322 | retval = rtsx_write_phy_register(chip, 0x07, 0x0129); |
| 323 | if (retval != STATUS_SUCCESS) |
| 324 | TRACE_RET(chip, STATUS_FAIL); |
| 325 | } |
| 326 | retval = rtsx_write_config_byte(chip, LCTLR, |
| 327 | chip->aspm_l0s_l1_en); |
| 328 | if (retval != STATUS_SUCCESS) |
| 329 | TRACE_RET(chip, STATUS_FAIL); |
| 330 | } |
| 331 | |
| 332 | retval = rtsx_write_config_byte(chip, 0x81, 1); |
| 333 | if (retval != STATUS_SUCCESS) |
| 334 | TRACE_RET(chip, STATUS_FAIL); |
| 335 | |
| 336 | if (CHK_SDIO_EXIST(chip)) { |
| 337 | if (CHECK_PID(chip, 0x5288)) |
| 338 | retval = rtsx_write_cfg_dw(chip, 2, 0xC0, |
| 339 | 0xFF00, 0x0100); |
| 340 | else |
| 341 | retval = rtsx_write_cfg_dw(chip, 1, 0xC0, |
| 342 | 0xFF00, 0x0100); |
| 343 | |
| 344 | if (retval != STATUS_SUCCESS) |
| 345 | TRACE_RET(chip, STATUS_FAIL); |
| 346 | |
| 347 | } |
| 348 | |
| 349 | if (CHECK_PID(chip, 0x5288)) { |
| 350 | if (!CHK_SDIO_EXIST(chip)) { |
| 351 | retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, |
| 352 | 0x0103); |
| 353 | if (retval != STATUS_SUCCESS) |
| 354 | TRACE_RET(chip, STATUS_FAIL); |
| 355 | |
| 356 | retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03); |
| 357 | if (retval != STATUS_SUCCESS) |
| 358 | TRACE_RET(chip, STATUS_FAIL); |
| 359 | |
| 360 | } |
| 361 | } |
| 362 | |
| 363 | RTSX_WRITE_REG(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT); |
| 364 | |
| 365 | RTSX_WRITE_REG(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80); |
| 366 | |
| 367 | /* Enable PCIE interrupt */ |
| 368 | if (chip->asic_code) { |
| 369 | if (CHECK_PID(chip, 0x5208)) { |
| 370 | if (chip->phy_debug_mode) { |
| 371 | RTSX_WRITE_REG(chip, CDRESUMECTL, 0x77, 0); |
| 372 | rtsx_disable_bus_int(chip); |
| 373 | } else { |
| 374 | rtsx_enable_bus_int(chip); |
| 375 | } |
| 376 | |
| 377 | if (chip->ic_version >= IC_VER_D) { |
| 378 | u16 reg; |
| 379 | retval = rtsx_read_phy_register(chip, 0x00, |
| 380 | ®); |
| 381 | if (retval != STATUS_SUCCESS) |
| 382 | TRACE_RET(chip, STATUS_FAIL); |
| 383 | |
| 384 | reg &= 0xFE7F; |
| 385 | reg |= 0x80; |
| 386 | retval = rtsx_write_phy_register(chip, 0x00, |
| 387 | reg); |
| 388 | if (retval != STATUS_SUCCESS) |
| 389 | TRACE_RET(chip, STATUS_FAIL); |
| 390 | |
| 391 | retval = rtsx_read_phy_register(chip, 0x1C, |
| 392 | ®); |
| 393 | if (retval != STATUS_SUCCESS) |
| 394 | TRACE_RET(chip, STATUS_FAIL); |
| 395 | |
| 396 | reg &= 0xFFF7; |
| 397 | retval = rtsx_write_phy_register(chip, 0x1C, |
| 398 | reg); |
| 399 | if (retval != STATUS_SUCCESS) |
| 400 | TRACE_RET(chip, STATUS_FAIL); |
| 401 | |
| 402 | } |
| 403 | |
| 404 | if (chip->driver_first_load && |
| 405 | (chip->ic_version < IC_VER_C)) |
| 406 | rtsx_calibration(chip); |
| 407 | |
| 408 | } else { |
| 409 | rtsx_enable_bus_int(chip); |
| 410 | } |
| 411 | } else { |
| 412 | rtsx_enable_bus_int(chip); |
| 413 | } |
| 414 | |
| 415 | chip->need_reset = 0; |
| 416 | |
| 417 | chip->int_reg = rtsx_readl(chip, RTSX_BIPR); |
| 418 | |
| 419 | if (chip->hw_bypass_sd) |
| 420 | goto NextCard; |
| 421 | RTSX_DEBUGP("In rtsx_reset_chip, chip->int_reg = 0x%x\n", |
| 422 | chip->int_reg); |
| 423 | if (chip->int_reg & SD_EXIST) { |
| 424 | #ifdef HW_AUTO_SWITCH_SD_BUS |
| 425 | if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C)) |
| 426 | retval = rtsx_pre_handle_sdio_old(chip); |
| 427 | else |
| 428 | retval = rtsx_pre_handle_sdio_new(chip); |
| 429 | |
| 430 | RTSX_DEBUGP("chip->need_reset = 0x%x (rtsx_reset_chip)\n", |
| 431 | (unsigned int)(chip->need_reset)); |
| 432 | #else /* HW_AUTO_SWITCH_SD_BUS */ |
| 433 | retval = rtsx_pre_handle_sdio_old(chip); |
| 434 | #endif /* HW_AUTO_SWITCH_SD_BUS */ |
| 435 | if (retval != STATUS_SUCCESS) |
| 436 | TRACE_RET(chip, STATUS_FAIL); |
| 437 | |
| 438 | } else { |
| 439 | chip->sd_io = 0; |
| 440 | RTSX_WRITE_REG(chip, SDIO_CTRL, SDIO_BUS_CTRL | SDIO_CD_CTRL, |
| 441 | 0); |
| 442 | } |
| 443 | |
| 444 | NextCard: |
| 445 | if (chip->int_reg & XD_EXIST) |
| 446 | chip->need_reset |= XD_CARD; |
| 447 | if (chip->int_reg & MS_EXIST) |
| 448 | chip->need_reset |= MS_CARD; |
| 449 | if (chip->int_reg & CARD_EXIST) |
| 450 | RTSX_WRITE_REG(chip, SSC_CTL1, SSC_RSTB, SSC_RSTB); |
| 451 | |
| 452 | RTSX_DEBUGP("In rtsx_init_chip, chip->need_reset = 0x%x\n", |
| 453 | (unsigned int)(chip->need_reset)); |
| 454 | |
| 455 | RTSX_WRITE_REG(chip, RCCTL, 0x01, 0x00); |
| 456 | |
| 457 | if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) { |
| 458 | /* Turn off main power when entering S3/S4 state */ |
| 459 | RTSX_WRITE_REG(chip, MAIN_PWR_OFF_CTL, 0x03, 0x03); |
| 460 | } |
| 461 | |
| 462 | if (chip->remote_wakeup_en && !chip->auto_delink_en) { |
| 463 | RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x07); |
| 464 | if (chip->aux_pwr_exist) |
| 465 | RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x33); |
| 466 | } else { |
| 467 | RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x04); |
| 468 | RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x30); |
| 469 | } |
| 470 | |
| 471 | if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) |
| 472 | RTSX_WRITE_REG(chip, PETXCFG, 0x1C, 0x14); |
| 473 | |
| 474 | if (chip->asic_code && CHECK_PID(chip, 0x5208)) { |
| 475 | retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2); |
| 476 | if (retval != STATUS_SUCCESS) |
| 477 | TRACE_RET(chip, STATUS_FAIL); |
| 478 | } |
| 479 | |
| 480 | if (chip->ft2_fast_mode) { |
| 481 | RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF, |
| 482 | MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON); |
| 483 | udelay(chip->pmos_pwr_on_interval); |
| 484 | RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF, |
| 485 | MS_POWER_ON | SD_POWER_ON); |
| 486 | |
| 487 | wait_timeout(200); |
| 488 | } |
| 489 | |
| 490 | /* Reset card */ |
| 491 | rtsx_reset_detected_cards(chip, 0); |
| 492 | |
| 493 | chip->driver_first_load = 0; |
| 494 | |
| 495 | return STATUS_SUCCESS; |
| 496 | } |
| 497 | |
| 498 | static inline int check_sd_speed_prior(u32 sd_speed_prior) |
| 499 | { |
| 500 | int i, fake_para = 0; |
| 501 | |
| 502 | for (i = 0; i < 4; i++) { |
| 503 | u8 tmp = (u8)(sd_speed_prior >> (i*8)); |
| 504 | if ((tmp < 0x01) || (tmp > 0x04)) { |
| 505 | fake_para = 1; |
| 506 | break; |
| 507 | } |
| 508 | } |
| 509 | |
| 510 | return !fake_para; |
| 511 | } |
| 512 | |
| 513 | static inline int check_sd_current_prior(u32 sd_current_prior) |
| 514 | { |
| 515 | int i, fake_para = 0; |
| 516 | |
| 517 | for (i = 0; i < 4; i++) { |
| 518 | u8 tmp = (u8)(sd_current_prior >> (i*8)); |
| 519 | if (tmp > 0x03) { |
| 520 | fake_para = 1; |
| 521 | break; |
| 522 | } |
| 523 | } |
| 524 | |
| 525 | return !fake_para; |
| 526 | } |
| 527 | |
| 528 | static int rts5208_init(struct rtsx_chip *chip) |
| 529 | { |
| 530 | int retval; |
| 531 | u16 reg = 0; |
| 532 | u8 val = 0; |
| 533 | |
| 534 | RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03); |
| 535 | RTSX_READ_REG(chip, CLK_SEL, &val); |
| 536 | if (val == 0) |
| 537 | chip->asic_code = 1; |
| 538 | else |
| 539 | chip->asic_code = 0; |
| 540 | |
| 541 | if (chip->asic_code) { |
| 542 | retval = rtsx_read_phy_register(chip, 0x1C, ®); |
| 543 | if (retval != STATUS_SUCCESS) |
| 544 | TRACE_RET(chip, STATUS_FAIL); |
| 545 | |
| 546 | RTSX_DEBUGP("Value of phy register 0x1C is 0x%x\n", reg); |
| 547 | chip->ic_version = (reg >> 4) & 0x07; |
| 548 | if (reg & PHY_DEBUG_MODE) |
| 549 | chip->phy_debug_mode = 1; |
| 550 | else |
| 551 | chip->phy_debug_mode = 0; |
| 552 | |
| 553 | } else { |
| 554 | RTSX_READ_REG(chip, 0xFE80, &val); |
| 555 | chip->ic_version = val; |
| 556 | chip->phy_debug_mode = 0; |
| 557 | } |
| 558 | |
| 559 | RTSX_READ_REG(chip, PDINFO, &val); |
| 560 | RTSX_DEBUGP("PDINFO: 0x%x\n", val); |
| 561 | if (val & AUX_PWR_DETECTED) |
| 562 | chip->aux_pwr_exist = 1; |
| 563 | else |
| 564 | chip->aux_pwr_exist = 0; |
| 565 | |
| 566 | RTSX_READ_REG(chip, 0xFE50, &val); |
| 567 | if (val & 0x01) |
| 568 | chip->hw_bypass_sd = 1; |
| 569 | else |
| 570 | chip->hw_bypass_sd = 0; |
| 571 | |
| 572 | rtsx_read_config_byte(chip, 0x0E, &val); |
| 573 | if (val & 0x80) |
| 574 | SET_SDIO_EXIST(chip); |
| 575 | else |
| 576 | CLR_SDIO_EXIST(chip); |
| 577 | |
| 578 | if (chip->use_hw_setting) { |
| 579 | RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val); |
| 580 | if (val & 0x80) |
| 581 | chip->auto_delink_en = 1; |
| 582 | else |
| 583 | chip->auto_delink_en = 0; |
| 584 | } |
| 585 | |
| 586 | return STATUS_SUCCESS; |
| 587 | } |
| 588 | |
| 589 | static int rts5288_init(struct rtsx_chip *chip) |
| 590 | { |
| 591 | int retval; |
| 592 | u8 val = 0, max_func; |
| 593 | u32 lval = 0; |
| 594 | |
| 595 | RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03); |
| 596 | RTSX_READ_REG(chip, CLK_SEL, &val); |
| 597 | if (val == 0) |
| 598 | chip->asic_code = 1; |
| 599 | else |
| 600 | chip->asic_code = 0; |
| 601 | |
| 602 | chip->ic_version = 0; |
| 603 | chip->phy_debug_mode = 0; |
| 604 | |
| 605 | RTSX_READ_REG(chip, PDINFO, &val); |
| 606 | RTSX_DEBUGP("PDINFO: 0x%x\n", val); |
| 607 | if (val & AUX_PWR_DETECTED) |
| 608 | chip->aux_pwr_exist = 1; |
| 609 | else |
| 610 | chip->aux_pwr_exist = 0; |
| 611 | |
| 612 | RTSX_READ_REG(chip, CARD_SHARE_MODE, &val); |
| 613 | RTSX_DEBUGP("CARD_SHARE_MODE: 0x%x\n", val); |
| 614 | if (val & 0x04) |
| 615 | chip->baro_pkg = QFN; |
| 616 | else |
| 617 | chip->baro_pkg = LQFP; |
| 618 | |
| 619 | RTSX_READ_REG(chip, 0xFE5A, &val); |
| 620 | if (val & 0x10) |
| 621 | chip->hw_bypass_sd = 1; |
| 622 | else |
| 623 | chip->hw_bypass_sd = 0; |
| 624 | |
| 625 | retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval); |
| 626 | if (retval != STATUS_SUCCESS) |
| 627 | TRACE_RET(chip, STATUS_FAIL); |
| 628 | |
| 629 | max_func = (u8)((lval >> 29) & 0x07); |
| 630 | RTSX_DEBUGP("Max function number: %d\n", max_func); |
| 631 | if (max_func == 0x02) |
| 632 | SET_SDIO_EXIST(chip); |
| 633 | else |
| 634 | CLR_SDIO_EXIST(chip); |
| 635 | |
| 636 | if (chip->use_hw_setting) { |
| 637 | RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val); |
| 638 | if (val & 0x80) |
| 639 | chip->auto_delink_en = 1; |
| 640 | else |
| 641 | chip->auto_delink_en = 0; |
| 642 | |
| 643 | if (CHECK_BARO_PKG(chip, LQFP)) |
| 644 | chip->lun_mode = SD_MS_1LUN; |
| 645 | else |
| 646 | chip->lun_mode = DEFAULT_SINGLE; |
| 647 | |
| 648 | } |
| 649 | |
| 650 | return STATUS_SUCCESS; |
| 651 | } |
| 652 | |
| 653 | int rtsx_init_chip(struct rtsx_chip *chip) |
| 654 | { |
| 655 | struct sd_info *sd_card = &(chip->sd_card); |
| 656 | struct xd_info *xd_card = &(chip->xd_card); |
| 657 | struct ms_info *ms_card = &(chip->ms_card); |
| 658 | int retval; |
| 659 | unsigned int i; |
| 660 | |
| 661 | RTSX_DEBUGP("Vendor ID: 0x%04x, Product ID: 0x%04x\n", |
| 662 | chip->vendor_id, chip->product_id); |
| 663 | |
| 664 | chip->ic_version = 0; |
| 665 | |
| 666 | #ifdef _MSG_TRACE |
| 667 | chip->msg_idx = 0; |
| 668 | #endif |
| 669 | |
| 670 | memset(xd_card, 0, sizeof(struct xd_info)); |
| 671 | memset(sd_card, 0, sizeof(struct sd_info)); |
| 672 | memset(ms_card, 0, sizeof(struct ms_info)); |
| 673 | |
| 674 | chip->xd_reset_counter = 0; |
| 675 | chip->sd_reset_counter = 0; |
| 676 | chip->ms_reset_counter = 0; |
| 677 | |
| 678 | chip->xd_show_cnt = MAX_SHOW_CNT; |
| 679 | chip->sd_show_cnt = MAX_SHOW_CNT; |
| 680 | chip->ms_show_cnt = MAX_SHOW_CNT; |
| 681 | |
| 682 | chip->sd_io = 0; |
| 683 | chip->auto_delink_cnt = 0; |
| 684 | chip->auto_delink_allowed = 1; |
| 685 | rtsx_set_stat(chip, RTSX_STAT_INIT); |
| 686 | |
| 687 | chip->aspm_enabled = 0; |
| 688 | chip->chip_insert_with_sdio = 0; |
| 689 | chip->sdio_aspm = 0; |
| 690 | chip->sdio_idle = 0; |
| 691 | chip->sdio_counter = 0; |
| 692 | chip->cur_card = 0; |
| 693 | chip->phy_debug_mode = 0; |
| 694 | chip->sdio_func_exist = 0; |
| 695 | memset(chip->sdio_raw_data, 0, 12); |
| 696 | |
| 697 | for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) { |
| 698 | set_sense_type(chip, i, SENSE_TYPE_NO_SENSE); |
| 699 | chip->rw_fail_cnt[i] = 0; |
| 700 | } |
| 701 | |
| 702 | if (!check_sd_speed_prior(chip->sd_speed_prior)) |
| 703 | chip->sd_speed_prior = 0x01040203; |
| 704 | |
| 705 | RTSX_DEBUGP("sd_speed_prior = 0x%08x\n", chip->sd_speed_prior); |
| 706 | |
| 707 | if (!check_sd_current_prior(chip->sd_current_prior)) |
| 708 | chip->sd_current_prior = 0x00010203; |
| 709 | |
| 710 | RTSX_DEBUGP("sd_current_prior = 0x%08x\n", chip->sd_current_prior); |
| 711 | |
| 712 | if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0)) |
| 713 | chip->sd_ddr_tx_phase = 0; |
| 714 | |
| 715 | if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0)) |
| 716 | chip->mmc_ddr_tx_phase = 0; |
| 717 | |
| 718 | RTSX_WRITE_REG(chip, FPDCTL, SSC_POWER_DOWN, 0); |
| 719 | wait_timeout(200); |
| 720 | RTSX_WRITE_REG(chip, CLK_DIV, 0x07, 0x07); |
| 721 | RTSX_DEBUGP("chip->use_hw_setting = %d\n", chip->use_hw_setting); |
| 722 | |
| 723 | if (CHECK_PID(chip, 0x5208)) { |
| 724 | retval = rts5208_init(chip); |
| 725 | if (retval != STATUS_SUCCESS) |
| 726 | TRACE_RET(chip, STATUS_FAIL); |
| 727 | |
| 728 | } else if (CHECK_PID(chip, 0x5288)) { |
| 729 | retval = rts5288_init(chip); |
| 730 | if (retval != STATUS_SUCCESS) |
| 731 | TRACE_RET(chip, STATUS_FAIL); |
| 732 | |
| 733 | } |
| 734 | |
| 735 | if (chip->ss_en == 2) |
| 736 | chip->ss_en = 0; |
| 737 | |
| 738 | RTSX_DEBUGP("chip->asic_code = %d\n", chip->asic_code); |
| 739 | RTSX_DEBUGP("chip->ic_version = 0x%x\n", chip->ic_version); |
| 740 | RTSX_DEBUGP("chip->phy_debug_mode = %d\n", chip->phy_debug_mode); |
| 741 | RTSX_DEBUGP("chip->aux_pwr_exist = %d\n", chip->aux_pwr_exist); |
| 742 | RTSX_DEBUGP("chip->sdio_func_exist = %d\n", chip->sdio_func_exist); |
| 743 | RTSX_DEBUGP("chip->hw_bypass_sd = %d\n", chip->hw_bypass_sd); |
| 744 | RTSX_DEBUGP("chip->aspm_l0s_l1_en = %d\n", chip->aspm_l0s_l1_en); |
| 745 | RTSX_DEBUGP("chip->lun_mode = %d\n", chip->lun_mode); |
| 746 | RTSX_DEBUGP("chip->auto_delink_en = %d\n", chip->auto_delink_en); |
| 747 | RTSX_DEBUGP("chip->ss_en = %d\n", chip->ss_en); |
| 748 | RTSX_DEBUGP("chip->baro_pkg = %d\n", chip->baro_pkg); |
| 749 | |
| 750 | if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { |
| 751 | chip->card2lun[SD_CARD] = 0; |
| 752 | chip->card2lun[MS_CARD] = 1; |
| 753 | chip->card2lun[XD_CARD] = 0xFF; |
| 754 | chip->lun2card[0] = SD_CARD; |
| 755 | chip->lun2card[1] = MS_CARD; |
| 756 | chip->max_lun = 1; |
| 757 | SET_SDIO_IGNORED(chip); |
| 758 | } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) { |
| 759 | chip->card2lun[SD_CARD] = 0; |
| 760 | chip->card2lun[MS_CARD] = 0; |
| 761 | chip->card2lun[XD_CARD] = 0xFF; |
| 762 | chip->lun2card[0] = SD_CARD | MS_CARD; |
| 763 | chip->max_lun = 0; |
| 764 | } else { |
| 765 | chip->card2lun[XD_CARD] = 0; |
| 766 | chip->card2lun[SD_CARD] = 0; |
| 767 | chip->card2lun[MS_CARD] = 0; |
| 768 | chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD; |
| 769 | chip->max_lun = 0; |
| 770 | } |
| 771 | |
| 772 | retval = rtsx_reset_chip(chip); |
| 773 | if (retval != STATUS_SUCCESS) |
| 774 | TRACE_RET(chip, STATUS_FAIL); |
| 775 | |
| 776 | return STATUS_SUCCESS; |
| 777 | } |
| 778 | |
| 779 | void rtsx_release_chip(struct rtsx_chip *chip) |
| 780 | { |
| 781 | xd_free_l2p_tbl(chip); |
| 782 | ms_free_l2p_tbl(chip); |
| 783 | chip->card_exist = 0; |
| 784 | chip->card_ready = 0; |
| 785 | } |
| 786 | |
| 787 | #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK) |
| 788 | static inline void rtsx_blink_led(struct rtsx_chip *chip) |
| 789 | { |
| 790 | if (chip->card_exist && chip->blink_led) { |
| 791 | if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) { |
| 792 | chip->led_toggle_counter++; |
| 793 | } else { |
| 794 | chip->led_toggle_counter = 0; |
| 795 | toggle_gpio(chip, LED_GPIO); |
| 796 | } |
| 797 | } |
| 798 | } |
| 799 | #endif |
| 800 | |
| 801 | static void rtsx_monitor_aspm_config(struct rtsx_chip *chip) |
| 802 | { |
| 803 | int maybe_support_aspm, reg_changed; |
| 804 | u32 tmp = 0; |
| 805 | u8 reg0 = 0, reg1 = 0; |
| 806 | |
| 807 | maybe_support_aspm = 0; |
| 808 | reg_changed = 0; |
| 809 | rtsx_read_config_byte(chip, LCTLR, ®0); |
| 810 | if (chip->aspm_level[0] != reg0) { |
| 811 | reg_changed = 1; |
| 812 | chip->aspm_level[0] = reg0; |
| 813 | } |
| 814 | if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) { |
| 815 | rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp); |
| 816 | reg1 = (u8)tmp; |
| 817 | if (chip->aspm_level[1] != reg1) { |
| 818 | reg_changed = 1; |
| 819 | chip->aspm_level[1] = reg1; |
| 820 | } |
| 821 | |
| 822 | if ((reg0 & 0x03) && (reg1 & 0x03)) |
| 823 | maybe_support_aspm = 1; |
| 824 | |
| 825 | } else { |
| 826 | if (reg0 & 0x03) |
| 827 | maybe_support_aspm = 1; |
| 828 | |
| 829 | } |
| 830 | |
| 831 | if (reg_changed) { |
| 832 | if (maybe_support_aspm) |
| 833 | chip->aspm_l0s_l1_en = 0x03; |
| 834 | |
| 835 | RTSX_DEBUGP("aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n", |
| 836 | chip->aspm_level[0], chip->aspm_level[1]); |
| 837 | |
| 838 | if (chip->aspm_l0s_l1_en) { |
| 839 | chip->aspm_enabled = 1; |
| 840 | } else { |
| 841 | chip->aspm_enabled = 0; |
| 842 | chip->sdio_aspm = 0; |
| 843 | } |
| 844 | rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, |
| 845 | 0x30 | chip->aspm_level[0] | |
| 846 | (chip->aspm_level[1] << 2)); |
| 847 | } |
| 848 | } |
| 849 | |
| 850 | void rtsx_polling_func(struct rtsx_chip *chip) |
| 851 | { |
| 852 | #ifdef SUPPORT_SD_LOCK |
| 853 | struct sd_info *sd_card = &(chip->sd_card); |
| 854 | #endif |
| 855 | int ss_allowed; |
| 856 | |
| 857 | if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND)) |
| 858 | return; |
| 859 | |
| 860 | if (rtsx_chk_stat(chip, RTSX_STAT_DELINK)) |
| 861 | goto Delink_Stage; |
| 862 | |
| 863 | if (chip->polling_config) { |
| 864 | u8 val; |
| 865 | rtsx_read_config_byte(chip, 0, &val); |
| 866 | } |
| 867 | |
| 868 | if (rtsx_chk_stat(chip, RTSX_STAT_SS)) |
| 869 | return; |
| 870 | |
| 871 | #ifdef SUPPORT_OCP |
| 872 | if (chip->ocp_int) { |
| 873 | rtsx_read_register(chip, OCPSTAT, &(chip->ocp_stat)); |
| 874 | |
| 875 | if (chip->card_exist & SD_CARD) |
| 876 | sd_power_off_card3v3(chip); |
| 877 | else if (chip->card_exist & MS_CARD) |
| 878 | ms_power_off_card3v3(chip); |
| 879 | else if (chip->card_exist & XD_CARD) |
| 880 | xd_power_off_card3v3(chip); |
| 881 | |
| 882 | chip->ocp_int = 0; |
| 883 | } |
| 884 | #endif |
| 885 | |
| 886 | #ifdef SUPPORT_SD_LOCK |
| 887 | if (sd_card->sd_erase_status) { |
| 888 | if (chip->card_exist & SD_CARD) { |
| 889 | u8 val; |
| 890 | rtsx_read_register(chip, 0xFD30, &val); |
| 891 | if (val & 0x02) { |
| 892 | sd_card->sd_erase_status = SD_NOT_ERASE; |
| 893 | sd_card->sd_lock_notify = 1; |
| 894 | chip->need_reinit |= SD_CARD; |
| 895 | } |
| 896 | } else { |
| 897 | sd_card->sd_erase_status = SD_NOT_ERASE; |
| 898 | } |
| 899 | } |
| 900 | #endif |
| 901 | |
| 902 | rtsx_init_cards(chip); |
| 903 | |
| 904 | if (chip->ss_en) { |
| 905 | ss_allowed = 1; |
| 906 | |
| 907 | if (CHECK_PID(chip, 0x5288)) { |
| 908 | ss_allowed = 0; |
| 909 | } else { |
| 910 | if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) { |
| 911 | u32 val; |
| 912 | rtsx_read_cfg_dw(chip, 1, 0x04, &val); |
| 913 | if (val & 0x07) |
| 914 | ss_allowed = 0; |
| 915 | |
| 916 | } |
| 917 | } |
| 918 | } else { |
| 919 | ss_allowed = 0; |
| 920 | } |
| 921 | |
| 922 | if (ss_allowed && !chip->sd_io) { |
| 923 | if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) { |
| 924 | chip->ss_counter = 0; |
| 925 | } else { |
| 926 | if (chip->ss_counter < |
| 927 | (chip->ss_idle_period / POLLING_INTERVAL)) { |
| 928 | chip->ss_counter++; |
| 929 | } else { |
| 930 | rtsx_exclusive_enter_ss(chip); |
| 931 | return; |
| 932 | } |
| 933 | } |
| 934 | } |
| 935 | |
| 936 | if (CHECK_PID(chip, 0x5208)) { |
| 937 | rtsx_monitor_aspm_config(chip); |
| 938 | |
| 939 | #ifdef SUPPORT_SDIO_ASPM |
| 940 | if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && |
| 941 | chip->aspm_l0s_l1_en && chip->dynamic_aspm) { |
| 942 | if (chip->sd_io) { |
| 943 | dynamic_configure_sdio_aspm(chip); |
| 944 | } else { |
| 945 | if (!chip->sdio_aspm) { |
| 946 | RTSX_DEBUGP("SDIO enter ASPM!\n"); |
| 947 | rtsx_write_register(chip, |
| 948 | ASPM_FORCE_CTL, 0xFC, |
| 949 | 0x30 | (chip->aspm_level[1] << 2)); |
| 950 | chip->sdio_aspm = 1; |
| 951 | } |
| 952 | } |
| 953 | } |
| 954 | #endif |
| 955 | } |
| 956 | |
| 957 | if (chip->idle_counter < IDLE_MAX_COUNT) { |
| 958 | chip->idle_counter++; |
| 959 | } else { |
| 960 | if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) { |
| 961 | RTSX_DEBUGP("Idle state!\n"); |
| 962 | rtsx_set_stat(chip, RTSX_STAT_IDLE); |
| 963 | |
| 964 | #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK) |
| 965 | chip->led_toggle_counter = 0; |
| 966 | #endif |
| 967 | rtsx_force_power_on(chip, SSC_PDCTL); |
| 968 | |
| 969 | turn_off_led(chip, LED_GPIO); |
| 970 | |
| 971 | if (chip->auto_power_down && !chip->card_ready && !chip->sd_io) |
| 972 | rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL); |
| 973 | |
| 974 | } |
| 975 | } |
| 976 | |
| 977 | switch (rtsx_get_stat(chip)) { |
| 978 | case RTSX_STAT_RUN: |
| 979 | #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK) |
| 980 | rtsx_blink_led(chip); |
| 981 | #endif |
| 982 | do_remaining_work(chip); |
| 983 | break; |
| 984 | |
| 985 | case RTSX_STAT_IDLE: |
| 986 | if (chip->sd_io && !chip->sd_int) |
| 987 | try_to_switch_sdio_ctrl(chip); |
| 988 | |
| 989 | rtsx_enable_aspm(chip); |
| 990 | break; |
| 991 | |
| 992 | default: |
| 993 | break; |
| 994 | } |
| 995 | |
| 996 | |
| 997 | #ifdef SUPPORT_OCP |
| 998 | if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { |
| 999 | #ifdef CONFIG_RTS5208_DEBUG |
| 1000 | if (chip->ocp_stat & |
| 1001 | (SD_OC_NOW | SD_OC_EVER | MS_OC_NOW | MS_OC_EVER)) |
| 1002 | RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", |
| 1003 | chip->ocp_stat); |
| 1004 | #endif |
| 1005 | |
| 1006 | if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { |
| 1007 | if (chip->card_exist & SD_CARD) { |
| 1008 | rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, |
| 1009 | 0); |
| 1010 | card_power_off(chip, SD_CARD); |
| 1011 | chip->card_fail |= SD_CARD; |
| 1012 | } |
| 1013 | } |
| 1014 | if (chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER)) { |
| 1015 | if (chip->card_exist & MS_CARD) { |
| 1016 | rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, |
| 1017 | 0); |
| 1018 | card_power_off(chip, MS_CARD); |
| 1019 | chip->card_fail |= MS_CARD; |
| 1020 | } |
| 1021 | } |
| 1022 | } else { |
| 1023 | if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { |
| 1024 | RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", |
| 1025 | chip->ocp_stat); |
| 1026 | if (chip->card_exist & SD_CARD) { |
| 1027 | rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, |
| 1028 | 0); |
| 1029 | chip->card_fail |= SD_CARD; |
| 1030 | } else if (chip->card_exist & MS_CARD) { |
| 1031 | rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, |
| 1032 | 0); |
| 1033 | chip->card_fail |= MS_CARD; |
| 1034 | } else if (chip->card_exist & XD_CARD) { |
| 1035 | rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, |
| 1036 | 0); |
| 1037 | chip->card_fail |= XD_CARD; |
| 1038 | } |
| 1039 | card_power_off(chip, SD_CARD); |
| 1040 | } |
| 1041 | } |
| 1042 | #endif |
| 1043 | |
| 1044 | Delink_Stage: |
| 1045 | if (chip->auto_delink_en && chip->auto_delink_allowed && |
| 1046 | !chip->card_ready && !chip->card_ejected && !chip->sd_io) { |
| 1047 | int enter_L1 = chip->auto_delink_in_L1 && ( |
| 1048 | chip->aspm_l0s_l1_en || chip->ss_en); |
| 1049 | int delink_stage1_cnt = chip->delink_stage1_step; |
| 1050 | int delink_stage2_cnt = delink_stage1_cnt + |
| 1051 | chip->delink_stage2_step; |
| 1052 | int delink_stage3_cnt = delink_stage2_cnt + |
| 1053 | chip->delink_stage3_step; |
| 1054 | |
| 1055 | if (chip->auto_delink_cnt <= delink_stage3_cnt) { |
| 1056 | if (chip->auto_delink_cnt == delink_stage1_cnt) { |
| 1057 | rtsx_set_stat(chip, RTSX_STAT_DELINK); |
| 1058 | |
| 1059 | if (chip->asic_code && CHECK_PID(chip, 0x5208)) |
| 1060 | rtsx_set_phy_reg_bit(chip, 0x1C, 2); |
| 1061 | |
| 1062 | if (chip->card_exist) { |
| 1063 | RTSX_DEBUGP("False card inserted, do force delink\n"); |
| 1064 | |
| 1065 | if (enter_L1) |
| 1066 | rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1); |
| 1067 | |
| 1068 | rtsx_write_register(chip, |
| 1069 | CHANGE_LINK_STATE, 0x0A, |
| 1070 | 0x0A); |
| 1071 | |
| 1072 | if (enter_L1) |
| 1073 | rtsx_enter_L1(chip); |
| 1074 | |
| 1075 | chip->auto_delink_cnt = delink_stage3_cnt + 1; |
| 1076 | } else { |
| 1077 | RTSX_DEBUGP("No card inserted, do delink\n"); |
| 1078 | |
| 1079 | if (enter_L1) |
| 1080 | rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1); |
| 1081 | |
| 1082 | rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0x02); |
| 1083 | |
| 1084 | if (enter_L1) |
| 1085 | rtsx_enter_L1(chip); |
| 1086 | |
| 1087 | } |
| 1088 | } |
| 1089 | |
| 1090 | if (chip->auto_delink_cnt == delink_stage2_cnt) { |
| 1091 | RTSX_DEBUGP("Try to do force delink\n"); |
| 1092 | |
| 1093 | if (enter_L1) |
| 1094 | rtsx_exit_L1(chip); |
| 1095 | |
| 1096 | if (chip->asic_code && CHECK_PID(chip, 0x5208)) |
| 1097 | rtsx_set_phy_reg_bit(chip, 0x1C, 2); |
| 1098 | |
| 1099 | rtsx_write_register(chip, CHANGE_LINK_STATE, |
| 1100 | 0x0A, 0x0A); |
| 1101 | } |
| 1102 | |
| 1103 | chip->auto_delink_cnt++; |
| 1104 | } |
| 1105 | } else { |
| 1106 | chip->auto_delink_cnt = 0; |
| 1107 | } |
| 1108 | } |
| 1109 | |
| 1110 | void rtsx_undo_delink(struct rtsx_chip *chip) |
| 1111 | { |
| 1112 | chip->auto_delink_allowed = 0; |
| 1113 | rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x00); |
| 1114 | } |
| 1115 | |
| 1116 | /** |
| 1117 | * rtsx_stop_cmd - stop command transfer and DMA transfer |
| 1118 | * @chip: Realtek's card reader chip |
| 1119 | * @card: flash card type |
| 1120 | * |
| 1121 | * Stop command transfer and DMA transfer. |
| 1122 | * This function is called in error handler. |
| 1123 | */ |
| 1124 | void rtsx_stop_cmd(struct rtsx_chip *chip, int card) |
| 1125 | { |
| 1126 | int i; |
| 1127 | |
| 1128 | for (i = 0; i <= 8; i++) { |
| 1129 | int addr = RTSX_HCBAR + i * 4; |
| 1130 | u32 reg; |
| 1131 | reg = rtsx_readl(chip, addr); |
| 1132 | RTSX_DEBUGP("BAR (0x%02x): 0x%08x\n", addr, reg); |
| 1133 | } |
| 1134 | rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD); |
| 1135 | rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA); |
| 1136 | |
| 1137 | for (i = 0; i < 16; i++) { |
| 1138 | u16 addr = 0xFE20 + (u16)i; |
| 1139 | u8 val; |
| 1140 | rtsx_read_register(chip, addr, &val); |
| 1141 | RTSX_DEBUGP("0x%04X: 0x%02x\n", addr, val); |
| 1142 | } |
| 1143 | |
| 1144 | rtsx_write_register(chip, DMACTL, 0x80, 0x80); |
| 1145 | rtsx_write_register(chip, RBCTL, 0x80, 0x80); |
| 1146 | } |
| 1147 | |
| 1148 | #define MAX_RW_REG_CNT 1024 |
| 1149 | |
| 1150 | int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data) |
| 1151 | { |
| 1152 | int i; |
| 1153 | u32 val = 3 << 30; |
| 1154 | |
| 1155 | val |= (u32)(addr & 0x3FFF) << 16; |
| 1156 | val |= (u32)mask << 8; |
| 1157 | val |= (u32)data; |
| 1158 | |
| 1159 | rtsx_writel(chip, RTSX_HAIMR, val); |
| 1160 | |
| 1161 | for (i = 0; i < MAX_RW_REG_CNT; i++) { |
| 1162 | val = rtsx_readl(chip, RTSX_HAIMR); |
| 1163 | if ((val & (1 << 31)) == 0) { |
| 1164 | if (data != (u8)val) |
| 1165 | TRACE_RET(chip, STATUS_FAIL); |
| 1166 | |
| 1167 | return STATUS_SUCCESS; |
| 1168 | } |
| 1169 | } |
| 1170 | |
| 1171 | TRACE_RET(chip, STATUS_TIMEDOUT); |
| 1172 | } |
| 1173 | |
| 1174 | int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data) |
| 1175 | { |
| 1176 | u32 val = 2 << 30; |
| 1177 | int i; |
| 1178 | |
| 1179 | if (data) |
| 1180 | *data = 0; |
| 1181 | |
| 1182 | val |= (u32)(addr & 0x3FFF) << 16; |
| 1183 | |
| 1184 | rtsx_writel(chip, RTSX_HAIMR, val); |
| 1185 | |
| 1186 | for (i = 0; i < MAX_RW_REG_CNT; i++) { |
| 1187 | val = rtsx_readl(chip, RTSX_HAIMR); |
| 1188 | if ((val & (1 << 31)) == 0) |
| 1189 | break; |
| 1190 | } |
| 1191 | |
| 1192 | if (i >= MAX_RW_REG_CNT) |
| 1193 | TRACE_RET(chip, STATUS_TIMEDOUT); |
| 1194 | |
| 1195 | if (data) |
| 1196 | *data = (u8)(val & 0xFF); |
| 1197 | |
| 1198 | return STATUS_SUCCESS; |
| 1199 | } |
| 1200 | |
| 1201 | int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, |
| 1202 | u32 val) |
| 1203 | { |
| 1204 | u8 mode = 0, tmp; |
| 1205 | int i; |
| 1206 | |
| 1207 | for (i = 0; i < 4; i++) { |
| 1208 | if (mask & 0xFF) { |
| 1209 | RTSX_WRITE_REG(chip, CFGDATA0 + i, |
| 1210 | 0xFF, (u8)(val & mask & 0xFF)); |
| 1211 | mode |= (1 << i); |
| 1212 | } |
| 1213 | mask >>= 8; |
| 1214 | val >>= 8; |
| 1215 | } |
| 1216 | |
| 1217 | if (mode) { |
| 1218 | RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr); |
| 1219 | RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8)); |
| 1220 | |
| 1221 | RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF, |
| 1222 | 0x80 | mode | ((func_no & 0x03) << 4)); |
| 1223 | |
| 1224 | for (i = 0; i < MAX_RW_REG_CNT; i++) { |
| 1225 | RTSX_READ_REG(chip, CFGRWCTL, &tmp); |
| 1226 | if ((tmp & 0x80) == 0) |
| 1227 | break; |
| 1228 | } |
| 1229 | } |
| 1230 | |
| 1231 | return STATUS_SUCCESS; |
| 1232 | } |
| 1233 | |
| 1234 | int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val) |
| 1235 | { |
| 1236 | int i; |
| 1237 | u8 tmp; |
| 1238 | u32 data = 0; |
| 1239 | |
| 1240 | RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr); |
| 1241 | RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8)); |
| 1242 | RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF, 0x80 | ((func_no & 0x03) << 4)); |
| 1243 | |
| 1244 | for (i = 0; i < MAX_RW_REG_CNT; i++) { |
| 1245 | RTSX_READ_REG(chip, CFGRWCTL, &tmp); |
| 1246 | if ((tmp & 0x80) == 0) |
| 1247 | break; |
| 1248 | } |
| 1249 | |
| 1250 | for (i = 0; i < 4; i++) { |
| 1251 | RTSX_READ_REG(chip, CFGDATA0 + i, &tmp); |
| 1252 | data |= (u32)tmp << (i * 8); |
| 1253 | } |
| 1254 | |
| 1255 | if (val) |
| 1256 | *val = data; |
| 1257 | |
| 1258 | return STATUS_SUCCESS; |
| 1259 | } |
| 1260 | |
| 1261 | int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, |
| 1262 | int len) |
| 1263 | { |
| 1264 | u32 *data, *mask; |
| 1265 | u16 offset = addr % 4; |
| 1266 | u16 aligned_addr = addr - offset; |
| 1267 | int dw_len, i, j; |
| 1268 | int retval; |
| 1269 | |
| 1270 | RTSX_DEBUGP("%s\n", __func__); |
| 1271 | |
| 1272 | if (!buf) |
| 1273 | TRACE_RET(chip, STATUS_NOMEM); |
| 1274 | |
| 1275 | if ((len + offset) % 4) |
| 1276 | dw_len = (len + offset) / 4 + 1; |
| 1277 | else |
| 1278 | dw_len = (len + offset) / 4; |
| 1279 | |
| 1280 | RTSX_DEBUGP("dw_len = %d\n", dw_len); |
| 1281 | |
| 1282 | data = vzalloc(dw_len * 4); |
| 1283 | if (!data) |
| 1284 | TRACE_RET(chip, STATUS_NOMEM); |
| 1285 | |
| 1286 | mask = vzalloc(dw_len * 4); |
| 1287 | if (!mask) { |
| 1288 | vfree(data); |
| 1289 | TRACE_RET(chip, STATUS_NOMEM); |
| 1290 | } |
| 1291 | |
| 1292 | j = 0; |
| 1293 | for (i = 0; i < len; i++) { |
| 1294 | mask[j] |= 0xFF << (offset * 8); |
| 1295 | data[j] |= buf[i] << (offset * 8); |
| 1296 | if (++offset == 4) { |
| 1297 | j++; |
| 1298 | offset = 0; |
| 1299 | } |
| 1300 | } |
| 1301 | |
| 1302 | RTSX_DUMP(mask, dw_len * 4); |
| 1303 | RTSX_DUMP(data, dw_len * 4); |
| 1304 | |
| 1305 | for (i = 0; i < dw_len; i++) { |
| 1306 | retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4, |
| 1307 | mask[i], data[i]); |
| 1308 | if (retval != STATUS_SUCCESS) { |
| 1309 | vfree(data); |
| 1310 | vfree(mask); |
| 1311 | TRACE_RET(chip, STATUS_FAIL); |
| 1312 | } |
| 1313 | } |
| 1314 | |
| 1315 | vfree(data); |
| 1316 | vfree(mask); |
| 1317 | |
| 1318 | return STATUS_SUCCESS; |
| 1319 | } |
| 1320 | |
| 1321 | int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, |
| 1322 | int len) |
| 1323 | { |
| 1324 | u32 *data; |
| 1325 | u16 offset = addr % 4; |
| 1326 | u16 aligned_addr = addr - offset; |
| 1327 | int dw_len, i, j; |
| 1328 | int retval; |
| 1329 | |
| 1330 | RTSX_DEBUGP("%s\n", __func__); |
| 1331 | |
| 1332 | if ((len + offset) % 4) |
| 1333 | dw_len = (len + offset) / 4 + 1; |
| 1334 | else |
| 1335 | dw_len = (len + offset) / 4; |
| 1336 | |
| 1337 | RTSX_DEBUGP("dw_len = %d\n", dw_len); |
| 1338 | |
| 1339 | data = vmalloc(dw_len * 4); |
| 1340 | if (!data) |
| 1341 | TRACE_RET(chip, STATUS_NOMEM); |
| 1342 | |
| 1343 | for (i = 0; i < dw_len; i++) { |
| 1344 | retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4, |
| 1345 | data + i); |
| 1346 | if (retval != STATUS_SUCCESS) { |
| 1347 | vfree(data); |
| 1348 | TRACE_RET(chip, STATUS_FAIL); |
| 1349 | } |
| 1350 | } |
| 1351 | |
| 1352 | if (buf) { |
| 1353 | j = 0; |
| 1354 | |
| 1355 | for (i = 0; i < len; i++) { |
| 1356 | buf[i] = (u8)(data[j] >> (offset * 8)); |
| 1357 | if (++offset == 4) { |
| 1358 | j++; |
| 1359 | offset = 0; |
| 1360 | } |
| 1361 | } |
| 1362 | } |
| 1363 | |
| 1364 | vfree(data); |
| 1365 | |
| 1366 | return STATUS_SUCCESS; |
| 1367 | } |
| 1368 | |
| 1369 | int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val) |
| 1370 | { |
| 1371 | int i, finished = 0; |
| 1372 | u8 tmp; |
| 1373 | |
| 1374 | RTSX_WRITE_REG(chip, PHYDATA0, 0xFF, (u8)val); |
| 1375 | RTSX_WRITE_REG(chip, PHYDATA1, 0xFF, (u8)(val >> 8)); |
| 1376 | RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr); |
| 1377 | RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x81); |
| 1378 | |
| 1379 | for (i = 0; i < 100000; i++) { |
| 1380 | RTSX_READ_REG(chip, PHYRWCTL, &tmp); |
| 1381 | if (!(tmp & 0x80)) { |
| 1382 | finished = 1; |
| 1383 | break; |
| 1384 | } |
| 1385 | } |
| 1386 | |
| 1387 | if (!finished) |
| 1388 | TRACE_RET(chip, STATUS_FAIL); |
| 1389 | |
| 1390 | return STATUS_SUCCESS; |
| 1391 | } |
| 1392 | |
| 1393 | int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val) |
| 1394 | { |
| 1395 | int i, finished = 0; |
| 1396 | u16 data = 0; |
| 1397 | u8 tmp; |
| 1398 | |
| 1399 | RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr); |
| 1400 | RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x80); |
| 1401 | |
| 1402 | for (i = 0; i < 100000; i++) { |
| 1403 | RTSX_READ_REG(chip, PHYRWCTL, &tmp); |
| 1404 | if (!(tmp & 0x80)) { |
| 1405 | finished = 1; |
| 1406 | break; |
| 1407 | } |
| 1408 | } |
| 1409 | |
| 1410 | if (!finished) |
| 1411 | TRACE_RET(chip, STATUS_FAIL); |
| 1412 | |
| 1413 | RTSX_READ_REG(chip, PHYDATA0, &tmp); |
| 1414 | data = tmp; |
| 1415 | RTSX_READ_REG(chip, PHYDATA1, &tmp); |
| 1416 | data |= (u16)tmp << 8; |
| 1417 | |
| 1418 | if (val) |
| 1419 | *val = data; |
| 1420 | |
| 1421 | return STATUS_SUCCESS; |
| 1422 | } |
| 1423 | |
| 1424 | int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val) |
| 1425 | { |
| 1426 | int i; |
| 1427 | u8 data = 0; |
| 1428 | |
| 1429 | RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0x80|addr); |
| 1430 | |
| 1431 | for (i = 0; i < 100; i++) { |
| 1432 | RTSX_READ_REG(chip, EFUSE_CTRL, &data); |
| 1433 | if (!(data & 0x80)) |
| 1434 | break; |
| 1435 | udelay(1); |
| 1436 | } |
| 1437 | |
| 1438 | if (data & 0x80) |
| 1439 | TRACE_RET(chip, STATUS_TIMEDOUT); |
| 1440 | |
| 1441 | RTSX_READ_REG(chip, EFUSE_DATA, &data); |
| 1442 | if (val) |
| 1443 | *val = data; |
| 1444 | |
| 1445 | return STATUS_SUCCESS; |
| 1446 | } |
| 1447 | |
| 1448 | int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val) |
| 1449 | { |
| 1450 | int i, j; |
| 1451 | u8 data = 0, tmp = 0xFF; |
| 1452 | |
| 1453 | for (i = 0; i < 8; i++) { |
| 1454 | if (val & (u8)(1 << i)) |
| 1455 | continue; |
| 1456 | |
| 1457 | tmp &= (~(u8)(1 << i)); |
| 1458 | RTSX_DEBUGP("Write 0x%x to 0x%x\n", tmp, addr); |
| 1459 | |
| 1460 | RTSX_WRITE_REG(chip, EFUSE_DATA, 0xFF, tmp); |
| 1461 | RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0xA0|addr); |
| 1462 | |
| 1463 | for (j = 0; j < 100; j++) { |
| 1464 | RTSX_READ_REG(chip, EFUSE_CTRL, &data); |
| 1465 | if (!(data & 0x80)) |
| 1466 | break; |
| 1467 | wait_timeout(3); |
| 1468 | } |
| 1469 | |
| 1470 | if (data & 0x80) |
| 1471 | TRACE_RET(chip, STATUS_TIMEDOUT); |
| 1472 | |
| 1473 | wait_timeout(5); |
| 1474 | } |
| 1475 | |
| 1476 | return STATUS_SUCCESS; |
| 1477 | } |
| 1478 | |
| 1479 | int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit) |
| 1480 | { |
| 1481 | int retval; |
| 1482 | u16 value; |
| 1483 | |
| 1484 | retval = rtsx_read_phy_register(chip, reg, &value); |
| 1485 | if (retval != STATUS_SUCCESS) |
| 1486 | TRACE_RET(chip, STATUS_FAIL); |
| 1487 | |
| 1488 | if (value & (1 << bit)) { |
| 1489 | value &= ~(1 << bit); |
| 1490 | retval = rtsx_write_phy_register(chip, reg, value); |
| 1491 | if (retval != STATUS_SUCCESS) |
| 1492 | TRACE_RET(chip, STATUS_FAIL); |
| 1493 | } |
| 1494 | |
| 1495 | return STATUS_SUCCESS; |
| 1496 | } |
| 1497 | |
| 1498 | int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit) |
| 1499 | { |
| 1500 | int retval; |
| 1501 | u16 value; |
| 1502 | |
| 1503 | retval = rtsx_read_phy_register(chip, reg, &value); |
| 1504 | if (retval != STATUS_SUCCESS) |
| 1505 | TRACE_RET(chip, STATUS_FAIL); |
| 1506 | |
| 1507 | if (0 == (value & (1 << bit))) { |
| 1508 | value |= (1 << bit); |
| 1509 | retval = rtsx_write_phy_register(chip, reg, value); |
| 1510 | if (retval != STATUS_SUCCESS) |
| 1511 | TRACE_RET(chip, STATUS_FAIL); |
| 1512 | } |
| 1513 | |
| 1514 | return STATUS_SUCCESS; |
| 1515 | } |
| 1516 | |
| 1517 | int rtsx_check_link_ready(struct rtsx_chip *chip) |
| 1518 | { |
| 1519 | u8 val; |
| 1520 | |
| 1521 | RTSX_READ_REG(chip, IRQSTAT0, &val); |
| 1522 | |
| 1523 | RTSX_DEBUGP("IRQSTAT0: 0x%x\n", val); |
| 1524 | if (val & LINK_RDY_INT) { |
| 1525 | RTSX_DEBUGP("Delinked!\n"); |
| 1526 | rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT); |
| 1527 | return STATUS_FAIL; |
| 1528 | } |
| 1529 | |
| 1530 | return STATUS_SUCCESS; |
| 1531 | } |
| 1532 | |
| 1533 | static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate) |
| 1534 | { |
| 1535 | u32 ultmp; |
| 1536 | |
| 1537 | RTSX_DEBUGP("%04x set pm_dstate to %d\n", chip->product_id, dstate); |
| 1538 | |
| 1539 | if (CHK_SDIO_EXIST(chip)) { |
| 1540 | u8 func_no; |
| 1541 | |
| 1542 | if (CHECK_PID(chip, 0x5288)) |
| 1543 | func_no = 2; |
| 1544 | else |
| 1545 | func_no = 1; |
| 1546 | |
| 1547 | rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp); |
| 1548 | RTSX_DEBUGP("pm_dstate of function %d: 0x%x\n", (int)func_no, |
| 1549 | ultmp); |
| 1550 | rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate); |
| 1551 | } |
| 1552 | |
| 1553 | rtsx_write_config_byte(chip, 0x44, dstate); |
| 1554 | rtsx_write_config_byte(chip, 0x45, 0); |
| 1555 | } |
| 1556 | |
| 1557 | void rtsx_enter_L1(struct rtsx_chip *chip) |
| 1558 | { |
| 1559 | rtsx_handle_pm_dstate(chip, 2); |
| 1560 | } |
| 1561 | |
| 1562 | void rtsx_exit_L1(struct rtsx_chip *chip) |
| 1563 | { |
| 1564 | rtsx_write_config_byte(chip, 0x44, 0); |
| 1565 | rtsx_write_config_byte(chip, 0x45, 0); |
| 1566 | } |
| 1567 | |
| 1568 | void rtsx_enter_ss(struct rtsx_chip *chip) |
| 1569 | { |
| 1570 | RTSX_DEBUGP("Enter Selective Suspend State!\n"); |
| 1571 | |
| 1572 | rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT); |
| 1573 | |
| 1574 | if (chip->power_down_in_ss) { |
| 1575 | rtsx_power_off_card(chip); |
| 1576 | rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL); |
| 1577 | } |
| 1578 | |
| 1579 | if (CHK_SDIO_EXIST(chip)) { |
| 1580 | if (CHECK_PID(chip, 0x5288)) |
| 1581 | rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF00, 0x0100); |
| 1582 | else |
| 1583 | rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF00, 0x0100); |
| 1584 | } |
| 1585 | |
| 1586 | if (chip->auto_delink_en) { |
| 1587 | rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01); |
| 1588 | } else { |
| 1589 | if (!chip->phy_debug_mode) { |
| 1590 | u32 tmp; |
| 1591 | tmp = rtsx_readl(chip, RTSX_BIER); |
| 1592 | tmp |= CARD_INT; |
| 1593 | rtsx_writel(chip, RTSX_BIER, tmp); |
| 1594 | } |
| 1595 | |
| 1596 | rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0); |
| 1597 | } |
| 1598 | |
| 1599 | rtsx_enter_L1(chip); |
| 1600 | |
| 1601 | RTSX_CLR_DELINK(chip); |
| 1602 | rtsx_set_stat(chip, RTSX_STAT_SS); |
| 1603 | } |
| 1604 | |
| 1605 | void rtsx_exit_ss(struct rtsx_chip *chip) |
| 1606 | { |
| 1607 | RTSX_DEBUGP("Exit Selective Suspend State!\n"); |
| 1608 | |
| 1609 | rtsx_exit_L1(chip); |
| 1610 | |
| 1611 | if (chip->power_down_in_ss) { |
| 1612 | rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL); |
| 1613 | udelay(1000); |
| 1614 | } |
| 1615 | |
| 1616 | if (RTSX_TST_DELINK(chip)) { |
| 1617 | chip->need_reinit = SD_CARD | MS_CARD | XD_CARD; |
| 1618 | rtsx_reinit_cards(chip, 1); |
| 1619 | RTSX_CLR_DELINK(chip); |
| 1620 | } else if (chip->power_down_in_ss) { |
| 1621 | chip->need_reinit = SD_CARD | MS_CARD | XD_CARD; |
| 1622 | rtsx_reinit_cards(chip, 0); |
| 1623 | } |
| 1624 | } |
| 1625 | |
| 1626 | int rtsx_pre_handle_interrupt(struct rtsx_chip *chip) |
| 1627 | { |
| 1628 | u32 status, int_enable; |
| 1629 | int exit_ss = 0; |
| 1630 | #ifdef SUPPORT_OCP |
| 1631 | u32 ocp_int = 0; |
| 1632 | |
| 1633 | ocp_int = OC_INT; |
| 1634 | #endif |
| 1635 | |
| 1636 | if (chip->ss_en) { |
| 1637 | chip->ss_counter = 0; |
| 1638 | if (rtsx_get_stat(chip) == RTSX_STAT_SS) { |
| 1639 | exit_ss = 1; |
| 1640 | rtsx_exit_L1(chip); |
| 1641 | rtsx_set_stat(chip, RTSX_STAT_RUN); |
| 1642 | } |
| 1643 | } |
| 1644 | |
| 1645 | int_enable = rtsx_readl(chip, RTSX_BIER); |
| 1646 | chip->int_reg = rtsx_readl(chip, RTSX_BIPR); |
| 1647 | |
| 1648 | if (((chip->int_reg & int_enable) == 0) || |
| 1649 | (chip->int_reg == 0xFFFFFFFF)) |
| 1650 | return STATUS_FAIL; |
| 1651 | |
| 1652 | status = chip->int_reg &= (int_enable | 0x7FFFFF); |
| 1653 | |
| 1654 | if (status & CARD_INT) { |
| 1655 | chip->auto_delink_cnt = 0; |
| 1656 | |
| 1657 | if (status & SD_INT) { |
| 1658 | if (status & SD_EXIST) { |
| 1659 | set_bit(SD_NR, &(chip->need_reset)); |
| 1660 | } else { |
| 1661 | set_bit(SD_NR, &(chip->need_release)); |
| 1662 | chip->sd_reset_counter = 0; |
| 1663 | chip->sd_show_cnt = 0; |
| 1664 | clear_bit(SD_NR, &(chip->need_reset)); |
| 1665 | } |
| 1666 | } else { |
| 1667 | /* If multi-luns, it's possible that |
| 1668 | when plugging/unplugging one card |
| 1669 | there is another card which still |
| 1670 | exists in the slot. In this case, |
| 1671 | all existed cards should be reset. |
| 1672 | */ |
| 1673 | if (exit_ss && (status & SD_EXIST)) |
| 1674 | set_bit(SD_NR, &(chip->need_reinit)); |
| 1675 | } |
| 1676 | if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) { |
| 1677 | if (status & XD_INT) { |
| 1678 | if (status & XD_EXIST) { |
| 1679 | set_bit(XD_NR, &(chip->need_reset)); |
| 1680 | } else { |
| 1681 | set_bit(XD_NR, &(chip->need_release)); |
| 1682 | chip->xd_reset_counter = 0; |
| 1683 | chip->xd_show_cnt = 0; |
| 1684 | clear_bit(XD_NR, &(chip->need_reset)); |
| 1685 | } |
| 1686 | } else { |
| 1687 | if (exit_ss && (status & XD_EXIST)) |
| 1688 | set_bit(XD_NR, &(chip->need_reinit)); |
| 1689 | } |
| 1690 | } |
| 1691 | if (status & MS_INT) { |
| 1692 | if (status & MS_EXIST) { |
| 1693 | set_bit(MS_NR, &(chip->need_reset)); |
| 1694 | } else { |
| 1695 | set_bit(MS_NR, &(chip->need_release)); |
| 1696 | chip->ms_reset_counter = 0; |
| 1697 | chip->ms_show_cnt = 0; |
| 1698 | clear_bit(MS_NR, &(chip->need_reset)); |
| 1699 | } |
| 1700 | } else { |
| 1701 | if (exit_ss && (status & MS_EXIST)) |
| 1702 | set_bit(MS_NR, &(chip->need_reinit)); |
| 1703 | } |
| 1704 | } |
| 1705 | |
| 1706 | #ifdef SUPPORT_OCP |
| 1707 | chip->ocp_int = ocp_int & status; |
| 1708 | #endif |
| 1709 | |
| 1710 | if (chip->sd_io) { |
| 1711 | if (chip->int_reg & DATA_DONE_INT) |
| 1712 | chip->int_reg &= ~(u32)DATA_DONE_INT; |
| 1713 | } |
| 1714 | |
| 1715 | return STATUS_SUCCESS; |
| 1716 | } |
| 1717 | |
| 1718 | void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat) |
| 1719 | { |
| 1720 | int retval; |
| 1721 | |
| 1722 | RTSX_DEBUGP("rtsx_do_before_power_down, pm_stat = %d\n", pm_stat); |
| 1723 | |
| 1724 | rtsx_set_stat(chip, RTSX_STAT_SUSPEND); |
| 1725 | |
| 1726 | retval = rtsx_force_power_on(chip, SSC_PDCTL); |
| 1727 | if (retval != STATUS_SUCCESS) |
| 1728 | return; |
| 1729 | |
| 1730 | rtsx_release_cards(chip); |
| 1731 | rtsx_disable_bus_int(chip); |
| 1732 | turn_off_led(chip, LED_GPIO); |
| 1733 | |
| 1734 | #ifdef HW_AUTO_SWITCH_SD_BUS |
| 1735 | if (chip->sd_io) { |
| 1736 | chip->sdio_in_charge = 1; |
| 1737 | if (CHECK_PID(chip, 0x5208)) { |
| 1738 | rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08); |
| 1739 | /* Enable sdio_bus_auto_switch */ |
| 1740 | rtsx_write_register(chip, 0xFE70, 0x80, 0x80); |
| 1741 | } else if (CHECK_PID(chip, 0x5288)) { |
| 1742 | rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08); |
| 1743 | /* Enable sdio_bus_auto_switch */ |
| 1744 | rtsx_write_register(chip, 0xFE5A, 0x08, 0x08); |
| 1745 | } |
| 1746 | } |
| 1747 | #endif |
| 1748 | |
| 1749 | if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) { |
| 1750 | /* u_force_clkreq_0 */ |
| 1751 | rtsx_write_register(chip, PETXCFG, 0x08, 0x08); |
| 1752 | } |
| 1753 | |
| 1754 | if (pm_stat == PM_S1) { |
| 1755 | RTSX_DEBUGP("Host enter S1\n"); |
| 1756 | rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, |
| 1757 | HOST_ENTER_S1); |
| 1758 | } else if (pm_stat == PM_S3) { |
| 1759 | if (chip->s3_pwr_off_delay > 0) |
| 1760 | wait_timeout(chip->s3_pwr_off_delay); |
| 1761 | |
| 1762 | RTSX_DEBUGP("Host enter S3\n"); |
| 1763 | rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, |
| 1764 | HOST_ENTER_S3); |
| 1765 | } |
| 1766 | |
| 1767 | if (chip->do_delink_before_power_down && chip->auto_delink_en) |
| 1768 | rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2); |
| 1769 | |
| 1770 | rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL); |
| 1771 | |
| 1772 | chip->cur_clk = 0; |
| 1773 | chip->cur_card = 0; |
| 1774 | chip->card_exist = 0; |
| 1775 | } |
| 1776 | |
| 1777 | void rtsx_enable_aspm(struct rtsx_chip *chip) |
| 1778 | { |
| 1779 | if (chip->aspm_l0s_l1_en && chip->dynamic_aspm) { |
| 1780 | if (!chip->aspm_enabled) { |
| 1781 | RTSX_DEBUGP("Try to enable ASPM\n"); |
| 1782 | chip->aspm_enabled = 1; |
| 1783 | |
| 1784 | if (chip->asic_code && CHECK_PID(chip, 0x5208)) |
| 1785 | rtsx_write_phy_register(chip, 0x07, 0); |
| 1786 | if (CHECK_PID(chip, 0x5208)) { |
| 1787 | rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3, |
| 1788 | 0x30 | chip->aspm_level[0]); |
| 1789 | } else { |
| 1790 | rtsx_write_config_byte(chip, LCTLR, |
| 1791 | chip->aspm_l0s_l1_en); |
| 1792 | } |
| 1793 | |
| 1794 | if (CHK_SDIO_EXIST(chip)) { |
| 1795 | u16 val = chip->aspm_l0s_l1_en | 0x0100; |
| 1796 | if (CHECK_PID(chip, 0x5288)) |
| 1797 | rtsx_write_cfg_dw(chip, 2, 0xC0, |
| 1798 | 0xFFFF, val); |
| 1799 | else |
| 1800 | rtsx_write_cfg_dw(chip, 1, 0xC0, |
| 1801 | 0xFFFF, val); |
| 1802 | } |
| 1803 | } |
| 1804 | } |
| 1805 | |
| 1806 | return; |
| 1807 | } |
| 1808 | |
| 1809 | void rtsx_disable_aspm(struct rtsx_chip *chip) |
| 1810 | { |
| 1811 | if (CHECK_PID(chip, 0x5208)) |
| 1812 | rtsx_monitor_aspm_config(chip); |
| 1813 | |
| 1814 | if (chip->aspm_l0s_l1_en && chip->dynamic_aspm) { |
| 1815 | if (chip->aspm_enabled) { |
| 1816 | RTSX_DEBUGP("Try to disable ASPM\n"); |
| 1817 | chip->aspm_enabled = 0; |
| 1818 | |
| 1819 | if (chip->asic_code && CHECK_PID(chip, 0x5208)) |
| 1820 | rtsx_write_phy_register(chip, 0x07, 0x0129); |
| 1821 | if (CHECK_PID(chip, 0x5208)) |
| 1822 | rtsx_write_register(chip, ASPM_FORCE_CTL, |
| 1823 | 0xF3, 0x30); |
| 1824 | else |
| 1825 | rtsx_write_config_byte(chip, LCTLR, 0x00); |
| 1826 | |
| 1827 | wait_timeout(1); |
| 1828 | } |
| 1829 | } |
| 1830 | |
| 1831 | return; |
| 1832 | } |
| 1833 | |
| 1834 | int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len) |
| 1835 | { |
| 1836 | int retval; |
| 1837 | int i, j; |
| 1838 | u16 reg_addr; |
| 1839 | u8 *ptr; |
| 1840 | |
| 1841 | if (!buf) |
| 1842 | TRACE_RET(chip, STATUS_ERROR); |
| 1843 | |
| 1844 | ptr = buf; |
| 1845 | reg_addr = PPBUF_BASE2; |
| 1846 | for (i = 0; i < buf_len/256; i++) { |
| 1847 | rtsx_init_cmd(chip); |
| 1848 | |
| 1849 | for (j = 0; j < 256; j++) |
| 1850 | rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0); |
| 1851 | |
| 1852 | retval = rtsx_send_cmd(chip, 0, 250); |
| 1853 | if (retval < 0) |
| 1854 | TRACE_RET(chip, STATUS_FAIL); |
| 1855 | |
| 1856 | memcpy(ptr, rtsx_get_cmd_data(chip), 256); |
| 1857 | ptr += 256; |
| 1858 | } |
| 1859 | |
| 1860 | if (buf_len%256) { |
| 1861 | rtsx_init_cmd(chip); |
| 1862 | |
| 1863 | for (j = 0; j < buf_len%256; j++) |
| 1864 | rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0); |
| 1865 | |
| 1866 | retval = rtsx_send_cmd(chip, 0, 250); |
| 1867 | if (retval < 0) |
| 1868 | TRACE_RET(chip, STATUS_FAIL); |
| 1869 | } |
| 1870 | |
| 1871 | memcpy(ptr, rtsx_get_cmd_data(chip), buf_len%256); |
| 1872 | |
| 1873 | return STATUS_SUCCESS; |
| 1874 | } |
| 1875 | |
| 1876 | int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len) |
| 1877 | { |
| 1878 | int retval; |
| 1879 | int i, j; |
| 1880 | u16 reg_addr; |
| 1881 | u8 *ptr; |
| 1882 | |
| 1883 | if (!buf) |
| 1884 | TRACE_RET(chip, STATUS_ERROR); |
| 1885 | |
| 1886 | ptr = buf; |
| 1887 | reg_addr = PPBUF_BASE2; |
| 1888 | for (i = 0; i < buf_len/256; i++) { |
| 1889 | rtsx_init_cmd(chip); |
| 1890 | |
| 1891 | for (j = 0; j < 256; j++) { |
| 1892 | rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, |
| 1893 | *ptr); |
| 1894 | ptr++; |
| 1895 | } |
| 1896 | |
| 1897 | retval = rtsx_send_cmd(chip, 0, 250); |
| 1898 | if (retval < 0) |
| 1899 | TRACE_RET(chip, STATUS_FAIL); |
| 1900 | } |
| 1901 | |
| 1902 | if (buf_len%256) { |
| 1903 | rtsx_init_cmd(chip); |
| 1904 | |
| 1905 | for (j = 0; j < buf_len%256; j++) { |
| 1906 | rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, |
| 1907 | *ptr); |
| 1908 | ptr++; |
| 1909 | } |
| 1910 | |
| 1911 | retval = rtsx_send_cmd(chip, 0, 250); |
| 1912 | if (retval < 0) |
| 1913 | TRACE_RET(chip, STATUS_FAIL); |
| 1914 | } |
| 1915 | |
| 1916 | return STATUS_SUCCESS; |
| 1917 | } |
| 1918 | |
| 1919 | int rtsx_check_chip_exist(struct rtsx_chip *chip) |
| 1920 | { |
| 1921 | if (rtsx_readl(chip, 0) == 0xFFFFFFFF) |
| 1922 | TRACE_RET(chip, STATUS_FAIL); |
| 1923 | |
| 1924 | return STATUS_SUCCESS; |
| 1925 | } |
| 1926 | |
| 1927 | int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl) |
| 1928 | { |
| 1929 | int retval; |
| 1930 | u8 mask = 0; |
| 1931 | |
| 1932 | if (ctl & SSC_PDCTL) |
| 1933 | mask |= SSC_POWER_DOWN; |
| 1934 | |
| 1935 | #ifdef SUPPORT_OCP |
| 1936 | if (ctl & OC_PDCTL) { |
| 1937 | mask |= SD_OC_POWER_DOWN; |
| 1938 | if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) |
| 1939 | mask |= MS_OC_POWER_DOWN; |
| 1940 | } |
| 1941 | #endif |
| 1942 | |
| 1943 | if (mask) { |
| 1944 | retval = rtsx_write_register(chip, FPDCTL, mask, 0); |
| 1945 | if (retval != STATUS_SUCCESS) |
| 1946 | TRACE_RET(chip, STATUS_FAIL); |
| 1947 | |
| 1948 | if (CHECK_PID(chip, 0x5288)) |
| 1949 | wait_timeout(200); |
| 1950 | } |
| 1951 | |
| 1952 | return STATUS_SUCCESS; |
| 1953 | } |
| 1954 | |
| 1955 | int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl) |
| 1956 | { |
| 1957 | int retval; |
| 1958 | u8 mask = 0, val = 0; |
| 1959 | |
| 1960 | if (ctl & SSC_PDCTL) |
| 1961 | mask |= SSC_POWER_DOWN; |
| 1962 | |
| 1963 | #ifdef SUPPORT_OCP |
| 1964 | if (ctl & OC_PDCTL) { |
| 1965 | mask |= SD_OC_POWER_DOWN; |
| 1966 | if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) |
| 1967 | mask |= MS_OC_POWER_DOWN; |
| 1968 | } |
| 1969 | #endif |
| 1970 | |
| 1971 | if (mask) { |
| 1972 | val = mask; |
| 1973 | retval = rtsx_write_register(chip, FPDCTL, mask, val); |
| 1974 | if (retval != STATUS_SUCCESS) |
| 1975 | TRACE_RET(chip, STATUS_FAIL); |
| 1976 | } |
| 1977 | |
| 1978 | return STATUS_SUCCESS; |
| 1979 | } |