Micky Ching | fa590c2 | 2013-11-12 17:16:08 +0800 | [diff] [blame] | 1 | /* Driver for Realtek PCI-Express card reader |
| 2 | * |
| 3 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation; either version 2, or (at your option) any |
| 8 | * later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, but |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 13 | * General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along |
| 16 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 17 | * |
| 18 | * Author: |
| 19 | * Wei WANG (wei_wang@realsil.com.cn) |
| 20 | * Micky Ching (micky_ching@realsil.com.cn) |
| 21 | */ |
| 22 | |
| 23 | #include <linux/blkdev.h> |
| 24 | #include <linux/kthread.h> |
| 25 | #include <linux/sched.h> |
| 26 | |
| 27 | #include "rtsx.h" |
| 28 | #include "rtsx_transport.h" |
| 29 | #include "rtsx_scsi.h" |
| 30 | #include "rtsx_card.h" |
| 31 | #include "sd.h" |
| 32 | |
| 33 | #define SD_MAX_RETRY_COUNT 3 |
| 34 | |
| 35 | static u16 REG_SD_CFG1; |
| 36 | static u16 REG_SD_CFG2; |
| 37 | static u16 REG_SD_CFG3; |
| 38 | static u16 REG_SD_STAT1; |
| 39 | static u16 REG_SD_STAT2; |
| 40 | static u16 REG_SD_BUS_STAT; |
| 41 | static u16 REG_SD_PAD_CTL; |
| 42 | static u16 REG_SD_SAMPLE_POINT_CTL; |
| 43 | static u16 REG_SD_PUSH_POINT_CTL; |
| 44 | static u16 REG_SD_CMD0; |
| 45 | static u16 REG_SD_CMD1; |
| 46 | static u16 REG_SD_CMD2; |
| 47 | static u16 REG_SD_CMD3; |
| 48 | static u16 REG_SD_CMD4; |
| 49 | static u16 REG_SD_CMD5; |
| 50 | static u16 REG_SD_BYTE_CNT_L; |
| 51 | static u16 REG_SD_BYTE_CNT_H; |
| 52 | static u16 REG_SD_BLOCK_CNT_L; |
| 53 | static u16 REG_SD_BLOCK_CNT_H; |
| 54 | static u16 REG_SD_TRANSFER; |
| 55 | static u16 REG_SD_VPCLK0_CTL; |
| 56 | static u16 REG_SD_VPCLK1_CTL; |
| 57 | static u16 REG_SD_DCMPS0_CTL; |
| 58 | static u16 REG_SD_DCMPS1_CTL; |
| 59 | |
| 60 | static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code) |
| 61 | { |
| 62 | struct sd_info *sd_card = &(chip->sd_card); |
| 63 | |
| 64 | sd_card->err_code |= err_code; |
| 65 | } |
| 66 | |
| 67 | static inline void sd_clr_err_code(struct rtsx_chip *chip) |
| 68 | { |
| 69 | struct sd_info *sd_card = &(chip->sd_card); |
| 70 | |
| 71 | sd_card->err_code = 0; |
| 72 | } |
| 73 | |
| 74 | static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code) |
| 75 | { |
| 76 | struct sd_info *sd_card = &(chip->sd_card); |
| 77 | |
| 78 | return sd_card->err_code & err_code; |
| 79 | } |
| 80 | |
| 81 | static void sd_init_reg_addr(struct rtsx_chip *chip) |
| 82 | { |
| 83 | REG_SD_CFG1 = 0xFD31; |
| 84 | REG_SD_CFG2 = 0xFD33; |
| 85 | REG_SD_CFG3 = 0xFD3E; |
| 86 | REG_SD_STAT1 = 0xFD30; |
| 87 | REG_SD_STAT2 = 0; |
| 88 | REG_SD_BUS_STAT = 0; |
| 89 | REG_SD_PAD_CTL = 0; |
| 90 | REG_SD_SAMPLE_POINT_CTL = 0; |
| 91 | REG_SD_PUSH_POINT_CTL = 0; |
| 92 | REG_SD_CMD0 = 0xFD34; |
| 93 | REG_SD_CMD1 = 0xFD35; |
| 94 | REG_SD_CMD2 = 0xFD36; |
| 95 | REG_SD_CMD3 = 0xFD37; |
| 96 | REG_SD_CMD4 = 0xFD38; |
| 97 | REG_SD_CMD5 = 0xFD5A; |
| 98 | REG_SD_BYTE_CNT_L = 0xFD39; |
| 99 | REG_SD_BYTE_CNT_H = 0xFD3A; |
| 100 | REG_SD_BLOCK_CNT_L = 0xFD3B; |
| 101 | REG_SD_BLOCK_CNT_H = 0xFD3C; |
| 102 | REG_SD_TRANSFER = 0xFD32; |
| 103 | REG_SD_VPCLK0_CTL = 0; |
| 104 | REG_SD_VPCLK1_CTL = 0; |
| 105 | REG_SD_DCMPS0_CTL = 0; |
| 106 | REG_SD_DCMPS1_CTL = 0; |
| 107 | } |
| 108 | |
| 109 | static int sd_check_data0_status(struct rtsx_chip *chip) |
| 110 | { |
| 111 | u8 stat; |
| 112 | |
| 113 | RTSX_READ_REG(chip, REG_SD_STAT1, &stat); |
| 114 | |
| 115 | if (!(stat & SD_DAT0_STATUS)) { |
| 116 | sd_set_err_code(chip, SD_BUSY); |
| 117 | TRACE_RET(chip, STATUS_FAIL); |
| 118 | } |
| 119 | |
| 120 | return STATUS_SUCCESS; |
| 121 | } |
| 122 | |
| 123 | static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, |
| 124 | u32 arg, u8 rsp_type, u8 *rsp, int rsp_len) |
| 125 | { |
| 126 | struct sd_info *sd_card = &(chip->sd_card); |
| 127 | int retval; |
| 128 | int timeout = 100; |
| 129 | u16 reg_addr; |
| 130 | u8 *ptr; |
| 131 | int stat_idx = 0; |
| 132 | int rty_cnt = 0; |
| 133 | |
| 134 | sd_clr_err_code(chip); |
| 135 | |
| 136 | RTSX_DEBUGP("SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg); |
| 137 | |
| 138 | if (rsp_type == SD_RSP_TYPE_R1b) |
| 139 | timeout = 3000; |
| 140 | |
| 141 | RTY_SEND_CMD: |
| 142 | |
| 143 | rtsx_init_cmd(chip); |
| 144 | |
| 145 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx); |
| 146 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24)); |
| 147 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16)); |
| 148 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8)); |
| 149 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg); |
| 150 | |
| 151 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type); |
| 152 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, |
| 153 | 0x01, PINGPONG_BUFFER); |
| 154 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, |
| 155 | 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); |
| 156 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, |
| 157 | SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END | SD_STAT_IDLE); |
| 158 | |
| 159 | if (rsp_type == SD_RSP_TYPE_R2) { |
| 160 | for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; |
| 161 | reg_addr++) |
| 162 | rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); |
| 163 | |
| 164 | stat_idx = 16; |
| 165 | } else if (rsp_type != SD_RSP_TYPE_R0) { |
| 166 | for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; |
| 167 | reg_addr++) |
| 168 | rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); |
| 169 | |
| 170 | stat_idx = 5; |
| 171 | } |
| 172 | |
| 173 | rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0); |
| 174 | |
| 175 | retval = rtsx_send_cmd(chip, SD_CARD, timeout); |
| 176 | if (retval < 0) { |
| 177 | u8 val; |
| 178 | |
| 179 | rtsx_read_register(chip, REG_SD_STAT1, &val); |
| 180 | RTSX_DEBUGP("SD_STAT1: 0x%x\n", val); |
| 181 | |
| 182 | rtsx_read_register(chip, REG_SD_CFG3, &val); |
| 183 | RTSX_DEBUGP("SD_CFG3: 0x%x\n", val); |
| 184 | |
| 185 | if (retval == -ETIMEDOUT) { |
| 186 | if (rsp_type & SD_WAIT_BUSY_END) { |
| 187 | retval = sd_check_data0_status(chip); |
| 188 | if (retval != STATUS_SUCCESS) { |
| 189 | rtsx_clear_sd_error(chip); |
| 190 | TRACE_RET(chip, retval); |
| 191 | } |
| 192 | } else { |
| 193 | sd_set_err_code(chip, SD_TO_ERR); |
| 194 | } |
| 195 | retval = STATUS_TIMEDOUT; |
| 196 | } else { |
| 197 | retval = STATUS_FAIL; |
| 198 | } |
| 199 | rtsx_clear_sd_error(chip); |
| 200 | |
| 201 | TRACE_RET(chip, retval); |
| 202 | } |
| 203 | |
| 204 | if (rsp_type == SD_RSP_TYPE_R0) |
| 205 | return STATUS_SUCCESS; |
| 206 | |
| 207 | ptr = rtsx_get_cmd_data(chip) + 1; |
| 208 | |
| 209 | if ((ptr[0] & 0xC0) != 0) { |
| 210 | sd_set_err_code(chip, SD_STS_ERR); |
| 211 | TRACE_RET(chip, STATUS_FAIL); |
| 212 | } |
| 213 | |
| 214 | if (!(rsp_type & SD_NO_CHECK_CRC7)) { |
| 215 | if (ptr[stat_idx] & SD_CRC7_ERR) { |
| 216 | if (cmd_idx == WRITE_MULTIPLE_BLOCK) { |
| 217 | sd_set_err_code(chip, SD_CRC_ERR); |
| 218 | TRACE_RET(chip, STATUS_FAIL); |
| 219 | } |
| 220 | if (rty_cnt < SD_MAX_RETRY_COUNT) { |
| 221 | wait_timeout(20); |
| 222 | rty_cnt++; |
| 223 | goto RTY_SEND_CMD; |
| 224 | } else { |
| 225 | sd_set_err_code(chip, SD_CRC_ERR); |
| 226 | TRACE_RET(chip, STATUS_FAIL); |
| 227 | } |
| 228 | } |
| 229 | } |
| 230 | |
| 231 | if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) { |
| 232 | if ((cmd_idx != SEND_RELATIVE_ADDR) && |
| 233 | (cmd_idx != SEND_IF_COND)) { |
| 234 | if (cmd_idx != STOP_TRANSMISSION) { |
| 235 | if (ptr[1] & 0x80) |
| 236 | TRACE_RET(chip, STATUS_FAIL); |
| 237 | } |
| 238 | #ifdef SUPPORT_SD_LOCK |
| 239 | if (ptr[1] & 0x7D) |
| 240 | #else |
| 241 | if (ptr[1] & 0x7F) |
| 242 | #endif |
| 243 | { |
| 244 | RTSX_DEBUGP("ptr[1]: 0x%02x\n", ptr[1]); |
| 245 | TRACE_RET(chip, STATUS_FAIL); |
| 246 | } |
| 247 | if (ptr[2] & 0xFF) { |
| 248 | RTSX_DEBUGP("ptr[2]: 0x%02x\n", ptr[2]); |
| 249 | TRACE_RET(chip, STATUS_FAIL); |
| 250 | } |
| 251 | if (ptr[3] & 0x80) { |
| 252 | RTSX_DEBUGP("ptr[3]: 0x%02x\n", ptr[3]); |
| 253 | TRACE_RET(chip, STATUS_FAIL); |
| 254 | } |
| 255 | if (ptr[3] & 0x01) |
| 256 | sd_card->sd_data_buf_ready = 1; |
| 257 | else |
| 258 | sd_card->sd_data_buf_ready = 0; |
| 259 | } |
| 260 | } |
| 261 | |
| 262 | if (rsp && rsp_len) |
| 263 | memcpy(rsp, ptr, rsp_len); |
| 264 | |
| 265 | return STATUS_SUCCESS; |
| 266 | } |
| 267 | |
| 268 | static int sd_read_data(struct rtsx_chip *chip, |
| 269 | u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt, |
| 270 | u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len, |
| 271 | int timeout) |
| 272 | { |
| 273 | struct sd_info *sd_card = &(chip->sd_card); |
| 274 | int retval; |
| 275 | int i; |
| 276 | |
| 277 | sd_clr_err_code(chip); |
| 278 | |
| 279 | if (!buf) |
| 280 | buf_len = 0; |
| 281 | |
| 282 | if (buf_len > 512) |
| 283 | TRACE_RET(chip, STATUS_FAIL); |
| 284 | |
| 285 | rtsx_init_cmd(chip); |
| 286 | |
| 287 | if (cmd_len) { |
| 288 | RTSX_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40); |
| 289 | for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) |
| 290 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i, |
| 291 | 0xFF, cmd[i]); |
| 292 | } |
| 293 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, |
| 294 | (u8)byte_cnt); |
| 295 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, |
| 296 | (u8)(byte_cnt >> 8)); |
| 297 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, |
| 298 | (u8)blk_cnt); |
| 299 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, |
| 300 | (u8)(blk_cnt >> 8)); |
| 301 | |
| 302 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width); |
| 303 | |
| 304 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, |
| 305 | SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END| |
| 306 | SD_CHECK_CRC7 | SD_RSP_LEN_6); |
| 307 | if (trans_mode != SD_TM_AUTO_TUNING) |
| 308 | rtsx_add_cmd(chip, WRITE_REG_CMD, |
| 309 | CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); |
| 310 | |
| 311 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, |
| 312 | trans_mode | SD_TRANSFER_START); |
| 313 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, |
| 314 | SD_TRANSFER_END); |
| 315 | |
| 316 | retval = rtsx_send_cmd(chip, SD_CARD, timeout); |
| 317 | if (retval < 0) { |
| 318 | if (retval == -ETIMEDOUT) { |
| 319 | sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, |
| 320 | SD_RSP_TYPE_R1, NULL, 0); |
| 321 | } |
| 322 | |
| 323 | TRACE_RET(chip, STATUS_FAIL); |
| 324 | } |
| 325 | |
| 326 | if (buf && buf_len) { |
| 327 | retval = rtsx_read_ppbuf(chip, buf, buf_len); |
| 328 | if (retval != STATUS_SUCCESS) |
| 329 | TRACE_RET(chip, STATUS_FAIL); |
| 330 | } |
| 331 | |
| 332 | return STATUS_SUCCESS; |
| 333 | } |
| 334 | |
| 335 | static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode, |
| 336 | u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt, u8 bus_width, |
| 337 | u8 *buf, int buf_len, int timeout) |
| 338 | { |
| 339 | struct sd_info *sd_card = &(chip->sd_card); |
| 340 | int retval; |
| 341 | int i; |
| 342 | |
| 343 | sd_clr_err_code(chip); |
| 344 | |
| 345 | if (!buf) |
| 346 | buf_len = 0; |
| 347 | |
| 348 | if (buf_len > 512) { |
| 349 | /* This function can't write data more than one page */ |
| 350 | TRACE_RET(chip, STATUS_FAIL); |
| 351 | } |
| 352 | |
| 353 | if (buf && buf_len) { |
| 354 | retval = rtsx_write_ppbuf(chip, buf, buf_len); |
| 355 | if (retval != STATUS_SUCCESS) |
| 356 | TRACE_RET(chip, STATUS_FAIL); |
| 357 | } |
| 358 | |
| 359 | rtsx_init_cmd(chip); |
| 360 | |
| 361 | if (cmd_len) { |
| 362 | RTSX_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40); |
| 363 | for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) { |
| 364 | rtsx_add_cmd(chip, WRITE_REG_CMD, |
| 365 | REG_SD_CMD0 + i, 0xFF, cmd[i]); |
| 366 | } |
| 367 | } |
| 368 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, |
| 369 | (u8)byte_cnt); |
| 370 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, |
| 371 | (u8)(byte_cnt >> 8)); |
| 372 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, |
| 373 | (u8)blk_cnt); |
| 374 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, |
| 375 | (u8)(blk_cnt >> 8)); |
| 376 | |
| 377 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width); |
| 378 | |
| 379 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, |
| 380 | SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END | |
| 381 | SD_CHECK_CRC7 | SD_RSP_LEN_6); |
| 382 | |
| 383 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, |
| 384 | trans_mode | SD_TRANSFER_START); |
| 385 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, |
| 386 | SD_TRANSFER_END); |
| 387 | |
| 388 | retval = rtsx_send_cmd(chip, SD_CARD, timeout); |
| 389 | if (retval < 0) { |
| 390 | if (retval == -ETIMEDOUT) { |
| 391 | sd_send_cmd_get_rsp(chip, SEND_STATUS, |
| 392 | sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); |
| 393 | } |
| 394 | |
| 395 | TRACE_RET(chip, STATUS_FAIL); |
| 396 | } |
| 397 | |
| 398 | return STATUS_SUCCESS; |
| 399 | } |
| 400 | |
| 401 | static int sd_check_csd(struct rtsx_chip *chip, char check_wp) |
| 402 | { |
| 403 | struct sd_info *sd_card = &(chip->sd_card); |
| 404 | int retval; |
| 405 | int i; |
| 406 | u8 csd_ver, trans_speed; |
| 407 | u8 rsp[16]; |
| 408 | |
| 409 | for (i = 0; i < 6; i++) { |
| 410 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { |
| 411 | sd_set_err_code(chip, SD_NO_CARD); |
| 412 | TRACE_RET(chip, STATUS_FAIL); |
| 413 | } |
| 414 | |
| 415 | retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr, |
| 416 | SD_RSP_TYPE_R2, rsp, 16); |
| 417 | if (retval == STATUS_SUCCESS) |
| 418 | break; |
| 419 | } |
| 420 | |
| 421 | if (i == 6) |
| 422 | TRACE_RET(chip, STATUS_FAIL); |
| 423 | |
| 424 | memcpy(sd_card->raw_csd, rsp + 1, 15); |
| 425 | |
| 426 | RTSX_DEBUGP("CSD Response:\n"); |
| 427 | RTSX_DUMP(sd_card->raw_csd, 16); |
| 428 | |
| 429 | csd_ver = (rsp[1] & 0xc0) >> 6; |
| 430 | RTSX_DEBUGP("csd_ver = %d\n", csd_ver); |
| 431 | |
| 432 | trans_speed = rsp[4]; |
| 433 | if ((trans_speed & 0x07) == 0x02) { |
| 434 | if ((trans_speed & 0xf8) >= 0x30) { |
| 435 | if (chip->asic_code) |
| 436 | sd_card->sd_clock = 47; |
| 437 | else |
| 438 | sd_card->sd_clock = CLK_50; |
| 439 | |
| 440 | } else if ((trans_speed & 0xf8) == 0x28) { |
| 441 | if (chip->asic_code) |
| 442 | sd_card->sd_clock = 39; |
| 443 | else |
| 444 | sd_card->sd_clock = CLK_40; |
| 445 | |
| 446 | } else if ((trans_speed & 0xf8) == 0x20) { |
| 447 | if (chip->asic_code) |
| 448 | sd_card->sd_clock = 29; |
| 449 | else |
| 450 | sd_card->sd_clock = CLK_30; |
| 451 | |
| 452 | } else if ((trans_speed & 0xf8) >= 0x10) { |
| 453 | if (chip->asic_code) |
| 454 | sd_card->sd_clock = 23; |
| 455 | else |
| 456 | sd_card->sd_clock = CLK_20; |
| 457 | |
| 458 | } else if ((trans_speed & 0x08) >= 0x08) { |
| 459 | if (chip->asic_code) |
| 460 | sd_card->sd_clock = 19; |
| 461 | else |
| 462 | sd_card->sd_clock = CLK_20; |
| 463 | } else { |
| 464 | TRACE_RET(chip, STATUS_FAIL); |
| 465 | } |
| 466 | } else { |
| 467 | TRACE_RET(chip, STATUS_FAIL); |
| 468 | } |
| 469 | |
| 470 | if (CHK_MMC_SECTOR_MODE(sd_card)) { |
| 471 | sd_card->capacity = 0; |
| 472 | } else { |
| 473 | if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) { |
| 474 | u8 blk_size, c_size_mult; |
| 475 | u16 c_size; |
| 476 | blk_size = rsp[6] & 0x0F; |
| 477 | c_size = ((u16)(rsp[7] & 0x03) << 10) |
| 478 | + ((u16)rsp[8] << 2) |
| 479 | + ((u16)(rsp[9] & 0xC0) >> 6); |
| 480 | c_size_mult = (u8)((rsp[10] & 0x03) << 1); |
| 481 | c_size_mult += (rsp[11] & 0x80) >> 7; |
| 482 | sd_card->capacity = (((u32)(c_size + 1)) * |
| 483 | (1 << (c_size_mult + 2))) |
| 484 | << (blk_size - 9); |
| 485 | } else { |
| 486 | u32 total_sector = 0; |
| 487 | total_sector = (((u32)rsp[8] & 0x3f) << 16) | |
| 488 | ((u32)rsp[9] << 8) | (u32)rsp[10]; |
| 489 | sd_card->capacity = (total_sector + 1) << 10; |
| 490 | } |
| 491 | } |
| 492 | |
| 493 | if (check_wp) { |
| 494 | if (rsp[15] & 0x30) |
| 495 | chip->card_wp |= SD_CARD; |
| 496 | |
| 497 | RTSX_DEBUGP("CSD WP Status: 0x%x\n", rsp[15]); |
| 498 | } |
| 499 | |
| 500 | return STATUS_SUCCESS; |
| 501 | } |
| 502 | |
| 503 | static int sd_set_sample_push_timing(struct rtsx_chip *chip) |
| 504 | { |
| 505 | struct sd_info *sd_card = &(chip->sd_card); |
| 506 | |
| 507 | u8 val = 0; |
| 508 | |
| 509 | if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY) |
| 510 | val |= 0x10; |
| 511 | |
| 512 | if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) { |
| 513 | if (chip->asic_code) { |
| 514 | if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) { |
| 515 | if (val & 0x10) |
| 516 | val |= 0x04; |
| 517 | else |
| 518 | val |= 0x08; |
| 519 | } |
| 520 | } else { |
| 521 | if (val & 0x10) |
| 522 | val |= 0x04; |
| 523 | else |
| 524 | val |= 0x08; |
| 525 | } |
| 526 | } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == |
| 527 | SD_SAMPLE_POINT_DELAY) { |
| 528 | if (val & 0x10) |
| 529 | val |= 0x04; |
| 530 | else |
| 531 | val |= 0x08; |
| 532 | } |
| 533 | |
| 534 | RTSX_WRITE_REG(chip, REG_SD_CFG1, 0x1C, val); |
| 535 | |
| 536 | return STATUS_SUCCESS; |
| 537 | } |
| 538 | |
| 539 | static void sd_choose_proper_clock(struct rtsx_chip *chip) |
| 540 | { |
| 541 | struct sd_info *sd_card = &(chip->sd_card); |
| 542 | |
| 543 | if (CHK_SD_SDR104(sd_card)) { |
| 544 | if (chip->asic_code) |
| 545 | sd_card->sd_clock = chip->asic_sd_sdr104_clk; |
| 546 | else |
| 547 | sd_card->sd_clock = chip->fpga_sd_sdr104_clk; |
| 548 | |
| 549 | } else if (CHK_SD_DDR50(sd_card)) { |
| 550 | if (chip->asic_code) |
| 551 | sd_card->sd_clock = chip->asic_sd_ddr50_clk; |
| 552 | else |
| 553 | sd_card->sd_clock = chip->fpga_sd_ddr50_clk; |
| 554 | |
| 555 | } else if (CHK_SD_SDR50(sd_card)) { |
| 556 | if (chip->asic_code) |
| 557 | sd_card->sd_clock = chip->asic_sd_sdr50_clk; |
| 558 | else |
| 559 | sd_card->sd_clock = chip->fpga_sd_sdr50_clk; |
| 560 | |
| 561 | } else if (CHK_SD_HS(sd_card)) { |
| 562 | if (chip->asic_code) |
| 563 | sd_card->sd_clock = chip->asic_sd_hs_clk; |
| 564 | else |
| 565 | sd_card->sd_clock = chip->fpga_sd_hs_clk; |
| 566 | |
| 567 | } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) { |
| 568 | if (chip->asic_code) |
| 569 | sd_card->sd_clock = chip->asic_mmc_52m_clk; |
| 570 | else |
| 571 | sd_card->sd_clock = chip->fpga_mmc_52m_clk; |
| 572 | |
| 573 | } else if (CHK_MMC_26M(sd_card)) { |
| 574 | if (chip->asic_code) |
| 575 | sd_card->sd_clock = 48; |
| 576 | else |
| 577 | sd_card->sd_clock = CLK_50; |
| 578 | } |
| 579 | } |
| 580 | |
| 581 | static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div) |
| 582 | { |
| 583 | u8 mask = 0, val = 0; |
| 584 | |
| 585 | mask = 0x60; |
| 586 | if (clk_div == SD_CLK_DIVIDE_0) |
| 587 | val = 0x00; |
| 588 | else if (clk_div == SD_CLK_DIVIDE_128) |
| 589 | val = 0x40; |
| 590 | else if (clk_div == SD_CLK_DIVIDE_256) |
| 591 | val = 0x20; |
| 592 | |
| 593 | RTSX_WRITE_REG(chip, REG_SD_CFG1, mask, val); |
| 594 | |
| 595 | return STATUS_SUCCESS; |
| 596 | } |
| 597 | |
| 598 | static int sd_set_init_para(struct rtsx_chip *chip) |
| 599 | { |
| 600 | struct sd_info *sd_card = &(chip->sd_card); |
| 601 | int retval; |
| 602 | |
| 603 | retval = sd_set_sample_push_timing(chip); |
| 604 | if (retval != STATUS_SUCCESS) |
| 605 | TRACE_RET(chip, STATUS_FAIL); |
| 606 | |
| 607 | sd_choose_proper_clock(chip); |
| 608 | |
| 609 | retval = switch_clock(chip, sd_card->sd_clock); |
| 610 | if (retval != STATUS_SUCCESS) |
| 611 | TRACE_RET(chip, STATUS_FAIL); |
| 612 | |
| 613 | return STATUS_SUCCESS; |
| 614 | } |
| 615 | |
| 616 | int sd_select_card(struct rtsx_chip *chip, int select) |
| 617 | { |
| 618 | struct sd_info *sd_card = &(chip->sd_card); |
| 619 | int retval; |
| 620 | u8 cmd_idx, cmd_type; |
| 621 | u32 addr; |
| 622 | |
| 623 | if (select) { |
| 624 | cmd_idx = SELECT_CARD; |
| 625 | cmd_type = SD_RSP_TYPE_R1; |
| 626 | addr = sd_card->sd_addr; |
| 627 | } else { |
| 628 | cmd_idx = DESELECT_CARD; |
| 629 | cmd_type = SD_RSP_TYPE_R0; |
| 630 | addr = 0; |
| 631 | } |
| 632 | |
| 633 | retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0); |
| 634 | if (retval != STATUS_SUCCESS) |
| 635 | TRACE_RET(chip, STATUS_FAIL); |
| 636 | |
| 637 | return STATUS_SUCCESS; |
| 638 | } |
| 639 | |
| 640 | #ifdef SUPPORT_SD_LOCK |
| 641 | static int sd_update_lock_status(struct rtsx_chip *chip) |
| 642 | { |
| 643 | struct sd_info *sd_card = &(chip->sd_card); |
| 644 | int retval; |
| 645 | u8 rsp[5]; |
| 646 | |
| 647 | retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, |
| 648 | SD_RSP_TYPE_R1, rsp, 5); |
| 649 | if (retval != STATUS_SUCCESS) |
| 650 | TRACE_RET(chip, STATUS_FAIL); |
| 651 | |
| 652 | if (rsp[1] & 0x02) |
| 653 | sd_card->sd_lock_status |= SD_LOCKED; |
| 654 | else |
| 655 | sd_card->sd_lock_status &= ~SD_LOCKED; |
| 656 | |
| 657 | RTSX_DEBUGP("sd_card->sd_lock_status = 0x%x\n", |
| 658 | sd_card->sd_lock_status); |
| 659 | |
| 660 | if (rsp[1] & 0x01) |
| 661 | TRACE_RET(chip, STATUS_FAIL); |
| 662 | |
| 663 | return STATUS_SUCCESS; |
| 664 | } |
| 665 | #endif |
| 666 | |
| 667 | static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state, |
| 668 | u8 data_ready, int polling_cnt) |
| 669 | { |
| 670 | struct sd_info *sd_card = &(chip->sd_card); |
| 671 | int retval, i; |
| 672 | u8 rsp[5]; |
| 673 | |
| 674 | for (i = 0; i < polling_cnt; i++) { |
| 675 | retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, |
| 676 | sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, |
| 677 | 5); |
| 678 | if (retval != STATUS_SUCCESS) |
| 679 | TRACE_RET(chip, STATUS_FAIL); |
| 680 | |
| 681 | if (((rsp[3] & 0x1E) == state) && |
| 682 | ((rsp[3] & 0x01) == data_ready)) |
| 683 | return STATUS_SUCCESS; |
| 684 | } |
| 685 | |
| 686 | TRACE_RET(chip, STATUS_FAIL); |
| 687 | } |
| 688 | |
| 689 | static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage) |
| 690 | { |
| 691 | int retval; |
| 692 | |
| 693 | if (voltage == SD_IO_3V3) { |
| 694 | if (chip->asic_code) { |
| 695 | retval = rtsx_write_phy_register(chip, 0x08, |
| 696 | 0x4FC0 | |
| 697 | chip->phy_voltage); |
| 698 | if (retval != STATUS_SUCCESS) |
| 699 | TRACE_RET(chip, STATUS_FAIL); |
| 700 | } else { |
| 701 | RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, 0); |
| 702 | } |
| 703 | } else if (voltage == SD_IO_1V8) { |
| 704 | if (chip->asic_code) { |
| 705 | retval = rtsx_write_phy_register(chip, 0x08, |
| 706 | 0x4C40 | |
| 707 | chip->phy_voltage); |
| 708 | if (retval != STATUS_SUCCESS) |
| 709 | TRACE_RET(chip, STATUS_FAIL); |
| 710 | } else { |
| 711 | RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, |
| 712 | SD_IO_USING_1V8); |
| 713 | } |
| 714 | } else { |
| 715 | TRACE_RET(chip, STATUS_FAIL); |
| 716 | } |
| 717 | |
| 718 | return STATUS_SUCCESS; |
| 719 | } |
| 720 | |
| 721 | static int sd_voltage_switch(struct rtsx_chip *chip) |
| 722 | { |
| 723 | int retval; |
| 724 | u8 stat; |
| 725 | |
| 726 | RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, |
| 727 | SD_CLK_TOGGLE_EN); |
| 728 | |
| 729 | retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1, |
| 730 | NULL, 0); |
| 731 | if (retval != STATUS_SUCCESS) |
| 732 | TRACE_RET(chip, STATUS_FAIL); |
| 733 | |
| 734 | udelay(chip->sd_voltage_switch_delay); |
| 735 | |
| 736 | RTSX_READ_REG(chip, SD_BUS_STAT, &stat); |
| 737 | if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | |
| 738 | SD_DAT1_STATUS | SD_DAT0_STATUS)) { |
| 739 | TRACE_RET(chip, STATUS_FAIL); |
| 740 | } |
| 741 | |
| 742 | RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_FORCE_STOP); |
| 743 | retval = sd_change_bank_voltage(chip, SD_IO_1V8); |
| 744 | if (retval != STATUS_SUCCESS) |
| 745 | TRACE_RET(chip, STATUS_FAIL); |
| 746 | |
| 747 | wait_timeout(50); |
| 748 | |
| 749 | RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); |
| 750 | wait_timeout(10); |
| 751 | |
| 752 | RTSX_READ_REG(chip, SD_BUS_STAT, &stat); |
| 753 | if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | |
| 754 | SD_DAT1_STATUS | SD_DAT0_STATUS)) != |
| 755 | (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | |
| 756 | SD_DAT1_STATUS | SD_DAT0_STATUS)) { |
| 757 | RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", stat); |
| 758 | rtsx_write_register(chip, SD_BUS_STAT, |
| 759 | SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); |
| 760 | rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0); |
| 761 | TRACE_RET(chip, STATUS_FAIL); |
| 762 | } |
| 763 | |
| 764 | RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, |
| 765 | 0); |
| 766 | |
| 767 | return STATUS_SUCCESS; |
| 768 | } |
| 769 | |
| 770 | static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir) |
| 771 | { |
| 772 | if (tune_dir == TUNE_RX) { |
| 773 | RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_RX); |
| 774 | RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RX); |
| 775 | } else { |
| 776 | RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_TX); |
| 777 | RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_TX); |
| 778 | } |
| 779 | |
| 780 | return STATUS_SUCCESS; |
| 781 | } |
| 782 | |
| 783 | static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir) |
| 784 | { |
| 785 | struct sd_info *sd_card = &(chip->sd_card); |
| 786 | u16 SD_VP_CTL, SD_DCMPS_CTL; |
| 787 | u8 val; |
| 788 | int retval; |
| 789 | int ddr_rx = 0; |
| 790 | |
| 791 | RTSX_DEBUGP("sd_change_phase (sample_point = %d, tune_dir = %d)\n", |
| 792 | sample_point, tune_dir); |
| 793 | |
| 794 | if (tune_dir == TUNE_RX) { |
| 795 | SD_VP_CTL = SD_VPRX_CTL; |
| 796 | SD_DCMPS_CTL = SD_DCMPS_RX_CTL; |
| 797 | if (CHK_SD_DDR50(sd_card)) |
| 798 | ddr_rx = 1; |
| 799 | } else { |
| 800 | SD_VP_CTL = SD_VPTX_CTL; |
| 801 | SD_DCMPS_CTL = SD_DCMPS_TX_CTL; |
| 802 | } |
| 803 | |
| 804 | if (chip->asic_code) { |
| 805 | RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK); |
| 806 | RTSX_WRITE_REG(chip, SD_VP_CTL, 0x1F, sample_point); |
| 807 | RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); |
| 808 | RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, |
| 809 | PHASE_NOT_RESET); |
| 810 | RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0); |
| 811 | } else { |
| 812 | #ifdef CONFIG_RTS5208_DEBUG |
| 813 | rtsx_read_register(chip, SD_VP_CTL, &val); |
| 814 | RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val); |
| 815 | rtsx_read_register(chip, SD_DCMPS_CTL, &val); |
| 816 | RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val); |
| 817 | #endif |
| 818 | |
| 819 | if (ddr_rx) { |
| 820 | RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, |
| 821 | PHASE_CHANGE); |
| 822 | udelay(50); |
| 823 | RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF, |
| 824 | PHASE_CHANGE | PHASE_NOT_RESET | sample_point); |
| 825 | } else { |
| 826 | RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK); |
| 827 | udelay(50); |
| 828 | RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF, |
| 829 | PHASE_NOT_RESET | sample_point); |
| 830 | } |
| 831 | udelay(100); |
| 832 | |
| 833 | rtsx_init_cmd(chip); |
| 834 | rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE, |
| 835 | DCMPS_CHANGE); |
| 836 | rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL, |
| 837 | DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE); |
| 838 | retval = rtsx_send_cmd(chip, SD_CARD, 100); |
| 839 | if (retval != STATUS_SUCCESS) |
| 840 | TRACE_GOTO(chip, Fail); |
| 841 | |
| 842 | val = *rtsx_get_cmd_data(chip); |
| 843 | if (val & DCMPS_ERROR) |
| 844 | TRACE_GOTO(chip, Fail); |
| 845 | |
| 846 | if ((val & DCMPS_CURRENT_PHASE) != sample_point) |
| 847 | TRACE_GOTO(chip, Fail); |
| 848 | |
| 849 | RTSX_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0); |
| 850 | if (ddr_rx) |
| 851 | RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, 0); |
| 852 | else |
| 853 | RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0); |
| 854 | |
| 855 | udelay(50); |
| 856 | } |
| 857 | |
| 858 | RTSX_WRITE_REG(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); |
| 859 | |
| 860 | return STATUS_SUCCESS; |
| 861 | |
| 862 | Fail: |
| 863 | #ifdef CONFIG_RTS5208_DEBUG |
| 864 | rtsx_read_register(chip, SD_VP_CTL, &val); |
| 865 | RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val); |
| 866 | rtsx_read_register(chip, SD_DCMPS_CTL, &val); |
| 867 | RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val); |
| 868 | #endif |
| 869 | |
| 870 | rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0); |
| 871 | rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0); |
| 872 | wait_timeout(10); |
| 873 | sd_reset_dcm(chip, tune_dir); |
| 874 | return STATUS_FAIL; |
| 875 | } |
| 876 | |
| 877 | static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width) |
| 878 | { |
| 879 | struct sd_info *sd_card = &(chip->sd_card); |
| 880 | int retval; |
| 881 | u8 cmd[5], buf[8]; |
| 882 | |
| 883 | retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, |
| 884 | SD_RSP_TYPE_R1, NULL, 0); |
| 885 | if (retval != STATUS_SUCCESS) |
| 886 | TRACE_RET(chip, STATUS_FAIL); |
| 887 | |
| 888 | cmd[0] = 0x40 | SEND_SCR; |
| 889 | cmd[1] = 0; |
| 890 | cmd[2] = 0; |
| 891 | cmd[3] = 0; |
| 892 | cmd[4] = 0; |
| 893 | |
| 894 | retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width, |
| 895 | buf, 8, 250); |
| 896 | if (retval != STATUS_SUCCESS) { |
| 897 | rtsx_clear_sd_error(chip); |
| 898 | TRACE_RET(chip, STATUS_FAIL); |
| 899 | } |
| 900 | |
| 901 | memcpy(sd_card->raw_scr, buf, 8); |
| 902 | |
| 903 | if ((buf[0] & 0x0F) == 0) |
| 904 | TRACE_RET(chip, STATUS_FAIL); |
| 905 | |
| 906 | return STATUS_SUCCESS; |
| 907 | } |
| 908 | |
| 909 | static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group, |
| 910 | u8 func_to_switch, u8 *buf, int buf_len) |
| 911 | { |
| 912 | u8 support_mask = 0, query_switch = 0, switch_busy = 0; |
| 913 | int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0; |
| 914 | |
| 915 | if (func_group == SD_FUNC_GROUP_1) { |
| 916 | support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET; |
| 917 | query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET; |
| 918 | check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET; |
| 919 | |
| 920 | switch (func_to_switch) { |
| 921 | case HS_SUPPORT: |
| 922 | support_mask = HS_SUPPORT_MASK; |
| 923 | query_switch = HS_QUERY_SWITCH_OK; |
| 924 | switch_busy = HS_SWITCH_BUSY; |
| 925 | break; |
| 926 | |
| 927 | case SDR50_SUPPORT: |
| 928 | support_mask = SDR50_SUPPORT_MASK; |
| 929 | query_switch = SDR50_QUERY_SWITCH_OK; |
| 930 | switch_busy = SDR50_SWITCH_BUSY; |
| 931 | break; |
| 932 | |
| 933 | case SDR104_SUPPORT: |
| 934 | support_mask = SDR104_SUPPORT_MASK; |
| 935 | query_switch = SDR104_QUERY_SWITCH_OK; |
| 936 | switch_busy = SDR104_SWITCH_BUSY; |
| 937 | break; |
| 938 | |
| 939 | case DDR50_SUPPORT: |
| 940 | support_mask = DDR50_SUPPORT_MASK; |
| 941 | query_switch = DDR50_QUERY_SWITCH_OK; |
| 942 | switch_busy = DDR50_SWITCH_BUSY; |
| 943 | break; |
| 944 | |
| 945 | default: |
| 946 | TRACE_RET(chip, STATUS_FAIL); |
| 947 | } |
| 948 | } else if (func_group == SD_FUNC_GROUP_3) { |
| 949 | support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET; |
| 950 | query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET; |
| 951 | check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET; |
| 952 | |
| 953 | switch (func_to_switch) { |
| 954 | case DRIVING_TYPE_A: |
| 955 | support_mask = DRIVING_TYPE_A_MASK; |
| 956 | query_switch = TYPE_A_QUERY_SWITCH_OK; |
| 957 | switch_busy = TYPE_A_SWITCH_BUSY; |
| 958 | break; |
| 959 | |
| 960 | case DRIVING_TYPE_C: |
| 961 | support_mask = DRIVING_TYPE_C_MASK; |
| 962 | query_switch = TYPE_C_QUERY_SWITCH_OK; |
| 963 | switch_busy = TYPE_C_SWITCH_BUSY; |
| 964 | break; |
| 965 | |
| 966 | case DRIVING_TYPE_D: |
| 967 | support_mask = DRIVING_TYPE_D_MASK; |
| 968 | query_switch = TYPE_D_QUERY_SWITCH_OK; |
| 969 | switch_busy = TYPE_D_SWITCH_BUSY; |
| 970 | break; |
| 971 | |
| 972 | default: |
| 973 | TRACE_RET(chip, STATUS_FAIL); |
| 974 | } |
| 975 | } else if (func_group == SD_FUNC_GROUP_4) { |
| 976 | support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET; |
| 977 | query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET; |
| 978 | check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET; |
| 979 | |
| 980 | switch (func_to_switch) { |
| 981 | case CURRENT_LIMIT_400: |
| 982 | support_mask = CURRENT_LIMIT_400_MASK; |
| 983 | query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK; |
| 984 | switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY; |
| 985 | break; |
| 986 | |
| 987 | case CURRENT_LIMIT_600: |
| 988 | support_mask = CURRENT_LIMIT_600_MASK; |
| 989 | query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK; |
| 990 | switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY; |
| 991 | break; |
| 992 | |
| 993 | case CURRENT_LIMIT_800: |
| 994 | support_mask = CURRENT_LIMIT_800_MASK; |
| 995 | query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK; |
| 996 | switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY; |
| 997 | break; |
| 998 | |
| 999 | default: |
| 1000 | TRACE_RET(chip, STATUS_FAIL); |
| 1001 | } |
| 1002 | } else { |
| 1003 | TRACE_RET(chip, STATUS_FAIL); |
| 1004 | } |
| 1005 | |
| 1006 | if (func_group == SD_FUNC_GROUP_1) { |
| 1007 | if (!(buf[support_offset] & support_mask) || |
| 1008 | ((buf[query_switch_offset] & 0x0F) != query_switch)) { |
| 1009 | TRACE_RET(chip, STATUS_FAIL); |
| 1010 | } |
| 1011 | } |
| 1012 | |
| 1013 | /* Check 'Busy Status' */ |
| 1014 | if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) && |
| 1015 | ((buf[check_busy_offset] & switch_busy) == switch_busy)) { |
| 1016 | TRACE_RET(chip, STATUS_FAIL); |
| 1017 | } |
| 1018 | |
| 1019 | return STATUS_SUCCESS; |
| 1020 | } |
| 1021 | |
| 1022 | static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode, |
| 1023 | u8 func_group, u8 func_to_switch, u8 bus_width) |
| 1024 | { |
| 1025 | struct sd_info *sd_card = &(chip->sd_card); |
| 1026 | int retval; |
| 1027 | u8 cmd[5], buf[64]; |
| 1028 | |
| 1029 | RTSX_DEBUGP("sd_check_switch_mode (mode = %d, func_group = %d, func_to_switch = %d)\n", |
| 1030 | mode, func_group, func_to_switch); |
| 1031 | |
| 1032 | cmd[0] = 0x40 | SWITCH; |
| 1033 | cmd[1] = mode; |
| 1034 | |
| 1035 | if (func_group == SD_FUNC_GROUP_1) { |
| 1036 | cmd[2] = 0xFF; |
| 1037 | cmd[3] = 0xFF; |
| 1038 | cmd[4] = 0xF0 + func_to_switch; |
| 1039 | } else if (func_group == SD_FUNC_GROUP_3) { |
| 1040 | cmd[2] = 0xFF; |
| 1041 | cmd[3] = 0xF0 + func_to_switch; |
| 1042 | cmd[4] = 0xFF; |
| 1043 | } else if (func_group == SD_FUNC_GROUP_4) { |
| 1044 | cmd[2] = 0xFF; |
| 1045 | cmd[3] = 0x0F + (func_to_switch << 4); |
| 1046 | cmd[4] = 0xFF; |
| 1047 | } else { |
| 1048 | cmd[1] = SD_CHECK_MODE; |
| 1049 | cmd[2] = 0xFF; |
| 1050 | cmd[3] = 0xFF; |
| 1051 | cmd[4] = 0xFF; |
| 1052 | } |
| 1053 | |
| 1054 | retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width, |
| 1055 | buf, 64, 250); |
| 1056 | if (retval != STATUS_SUCCESS) { |
| 1057 | rtsx_clear_sd_error(chip); |
| 1058 | TRACE_RET(chip, STATUS_FAIL); |
| 1059 | } |
| 1060 | |
| 1061 | RTSX_DUMP(buf, 64); |
| 1062 | |
| 1063 | if (func_group == NO_ARGUMENT) { |
| 1064 | sd_card->func_group1_mask = buf[0x0D]; |
| 1065 | sd_card->func_group2_mask = buf[0x0B]; |
| 1066 | sd_card->func_group3_mask = buf[0x09]; |
| 1067 | sd_card->func_group4_mask = buf[0x07]; |
| 1068 | |
| 1069 | RTSX_DEBUGP("func_group1_mask = 0x%02x\n", buf[0x0D]); |
| 1070 | RTSX_DEBUGP("func_group2_mask = 0x%02x\n", buf[0x0B]); |
| 1071 | RTSX_DEBUGP("func_group3_mask = 0x%02x\n", buf[0x09]); |
| 1072 | RTSX_DEBUGP("func_group4_mask = 0x%02x\n", buf[0x07]); |
| 1073 | } else { |
| 1074 | /* Maximum current consumption, check whether current is |
| 1075 | * acceptable; bit[511:496] = 0x0000 means some error happened. |
| 1076 | */ |
| 1077 | u16 cc = ((u16)buf[0] << 8) | buf[1]; |
| 1078 | RTSX_DEBUGP("Maximum current consumption: %dmA\n", cc); |
| 1079 | if ((cc == 0) || (cc > 800)) |
| 1080 | TRACE_RET(chip, STATUS_FAIL); |
| 1081 | |
| 1082 | retval = sd_query_switch_result(chip, func_group, |
| 1083 | func_to_switch, buf, 64); |
| 1084 | if (retval != STATUS_SUCCESS) |
| 1085 | TRACE_RET(chip, STATUS_FAIL); |
| 1086 | |
| 1087 | if ((cc > 400) || (func_to_switch > CURRENT_LIMIT_400)) { |
| 1088 | RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK, |
| 1089 | chip->sd_800mA_ocp_thd); |
| 1090 | RTSX_WRITE_REG(chip, CARD_PWR_CTL, PMOS_STRG_MASK, |
| 1091 | PMOS_STRG_800mA); |
| 1092 | } |
| 1093 | } |
| 1094 | |
| 1095 | return STATUS_SUCCESS; |
| 1096 | } |
| 1097 | |
| 1098 | static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch) |
| 1099 | { |
| 1100 | if (func_group == SD_FUNC_GROUP_1) { |
| 1101 | if (func_to_switch > HS_SUPPORT) |
| 1102 | func_to_switch--; |
| 1103 | |
| 1104 | } else if (func_group == SD_FUNC_GROUP_4) { |
| 1105 | if (func_to_switch > CURRENT_LIMIT_200) |
| 1106 | func_to_switch--; |
| 1107 | } |
| 1108 | |
| 1109 | return func_to_switch; |
| 1110 | } |
| 1111 | |
| 1112 | static int sd_check_switch(struct rtsx_chip *chip, |
| 1113 | u8 func_group, u8 func_to_switch, u8 bus_width) |
| 1114 | { |
| 1115 | int retval; |
| 1116 | int i; |
| 1117 | int switch_good = 0; |
| 1118 | |
| 1119 | for (i = 0; i < 3; i++) { |
| 1120 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { |
| 1121 | sd_set_err_code(chip, SD_NO_CARD); |
| 1122 | TRACE_RET(chip, STATUS_FAIL); |
| 1123 | } |
| 1124 | |
| 1125 | retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group, |
| 1126 | func_to_switch, bus_width); |
| 1127 | if (retval == STATUS_SUCCESS) { |
| 1128 | u8 stat; |
| 1129 | |
| 1130 | retval = sd_check_switch_mode(chip, SD_SWITCH_MODE, |
| 1131 | func_group, func_to_switch, bus_width); |
| 1132 | if (retval == STATUS_SUCCESS) { |
| 1133 | switch_good = 1; |
| 1134 | break; |
| 1135 | } |
| 1136 | |
| 1137 | RTSX_READ_REG(chip, SD_STAT1, &stat); |
| 1138 | if (stat & SD_CRC16_ERR) { |
| 1139 | RTSX_DEBUGP("SD CRC16 error when switching mode\n"); |
| 1140 | TRACE_RET(chip, STATUS_FAIL); |
| 1141 | } |
| 1142 | } |
| 1143 | |
| 1144 | func_to_switch = downgrade_switch_mode(func_group, |
| 1145 | func_to_switch); |
| 1146 | |
| 1147 | wait_timeout(20); |
| 1148 | } |
| 1149 | |
| 1150 | if (!switch_good) |
| 1151 | TRACE_RET(chip, STATUS_FAIL); |
| 1152 | |
| 1153 | return STATUS_SUCCESS; |
| 1154 | } |
| 1155 | |
| 1156 | static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width) |
| 1157 | { |
| 1158 | struct sd_info *sd_card = &(chip->sd_card); |
| 1159 | int retval; |
| 1160 | int i; |
| 1161 | u8 func_to_switch = 0; |
| 1162 | |
| 1163 | /* Get supported functions */ |
| 1164 | retval = sd_check_switch_mode(chip, SD_CHECK_MODE, |
| 1165 | NO_ARGUMENT, NO_ARGUMENT, bus_width); |
| 1166 | if (retval != STATUS_SUCCESS) |
| 1167 | TRACE_RET(chip, STATUS_FAIL); |
| 1168 | |
| 1169 | sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail); |
| 1170 | |
| 1171 | /* Function Group 1: Access Mode */ |
| 1172 | for (i = 0; i < 4; i++) { |
| 1173 | switch ((u8)(chip->sd_speed_prior >> (i*8))) { |
| 1174 | case SDR104_SUPPORT: |
| 1175 | if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK) |
| 1176 | && chip->sdr104_en) { |
| 1177 | func_to_switch = SDR104_SUPPORT; |
| 1178 | } |
| 1179 | break; |
| 1180 | |
| 1181 | case DDR50_SUPPORT: |
| 1182 | if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK) |
| 1183 | && chip->ddr50_en) { |
| 1184 | func_to_switch = DDR50_SUPPORT; |
| 1185 | } |
| 1186 | break; |
| 1187 | |
| 1188 | case SDR50_SUPPORT: |
| 1189 | if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK) |
| 1190 | && chip->sdr50_en) { |
| 1191 | func_to_switch = SDR50_SUPPORT; |
| 1192 | } |
| 1193 | break; |
| 1194 | |
| 1195 | case HS_SUPPORT: |
| 1196 | if (sd_card->func_group1_mask & HS_SUPPORT_MASK) |
| 1197 | func_to_switch = HS_SUPPORT; |
| 1198 | |
| 1199 | break; |
| 1200 | |
| 1201 | default: |
| 1202 | continue; |
| 1203 | } |
| 1204 | |
| 1205 | |
| 1206 | if (func_to_switch) |
| 1207 | break; |
| 1208 | |
| 1209 | } |
| 1210 | RTSX_DEBUGP("SD_FUNC_GROUP_1: func_to_switch = 0x%02x", func_to_switch); |
| 1211 | |
| 1212 | #ifdef SUPPORT_SD_LOCK |
| 1213 | if ((sd_card->sd_lock_status & SD_SDR_RST) |
| 1214 | && (DDR50_SUPPORT == func_to_switch) |
| 1215 | && (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) { |
| 1216 | func_to_switch = SDR50_SUPPORT; |
| 1217 | RTSX_DEBUGP("Using SDR50 instead of DDR50 for SD Lock\n"); |
| 1218 | } |
| 1219 | #endif |
| 1220 | |
| 1221 | if (func_to_switch) { |
| 1222 | retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch, |
| 1223 | bus_width); |
| 1224 | if (retval != STATUS_SUCCESS) { |
| 1225 | if (func_to_switch == SDR104_SUPPORT) { |
| 1226 | sd_card->sd_switch_fail = SDR104_SUPPORT_MASK; |
| 1227 | } else if (func_to_switch == DDR50_SUPPORT) { |
| 1228 | sd_card->sd_switch_fail = SDR104_SUPPORT_MASK | |
| 1229 | DDR50_SUPPORT_MASK; |
| 1230 | } else if (func_to_switch == SDR50_SUPPORT) { |
| 1231 | sd_card->sd_switch_fail = SDR104_SUPPORT_MASK | |
| 1232 | DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK; |
| 1233 | } |
| 1234 | TRACE_RET(chip, STATUS_FAIL); |
| 1235 | } |
| 1236 | |
| 1237 | if (func_to_switch == SDR104_SUPPORT) |
| 1238 | SET_SD_SDR104(sd_card); |
| 1239 | else if (func_to_switch == DDR50_SUPPORT) |
| 1240 | SET_SD_DDR50(sd_card); |
| 1241 | else if (func_to_switch == SDR50_SUPPORT) |
| 1242 | SET_SD_SDR50(sd_card); |
| 1243 | else |
| 1244 | SET_SD_HS(sd_card); |
| 1245 | } |
| 1246 | |
| 1247 | if (CHK_SD_DDR50(sd_card)) { |
| 1248 | RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0x04); |
| 1249 | retval = sd_set_sample_push_timing(chip); |
| 1250 | if (retval != STATUS_SUCCESS) |
| 1251 | TRACE_RET(chip, STATUS_FAIL); |
| 1252 | } |
| 1253 | |
| 1254 | if (!func_to_switch || (func_to_switch == HS_SUPPORT)) { |
| 1255 | /* Do not try to switch current limit if the card doesn't |
| 1256 | * support UHS mode or we don't want it to support UHS mode |
| 1257 | */ |
| 1258 | return STATUS_SUCCESS; |
| 1259 | } |
| 1260 | |
| 1261 | /* Function Group 4: Current Limit */ |
| 1262 | func_to_switch = 0xFF; |
| 1263 | |
| 1264 | for (i = 0; i < 4; i++) { |
| 1265 | switch ((u8)(chip->sd_current_prior >> (i*8))) { |
| 1266 | case CURRENT_LIMIT_800: |
| 1267 | if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK) |
| 1268 | func_to_switch = CURRENT_LIMIT_800; |
| 1269 | |
| 1270 | break; |
| 1271 | |
| 1272 | case CURRENT_LIMIT_600: |
| 1273 | if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK) |
| 1274 | func_to_switch = CURRENT_LIMIT_600; |
| 1275 | |
| 1276 | break; |
| 1277 | |
| 1278 | case CURRENT_LIMIT_400: |
| 1279 | if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK) |
| 1280 | func_to_switch = CURRENT_LIMIT_400; |
| 1281 | |
| 1282 | break; |
| 1283 | |
| 1284 | case CURRENT_LIMIT_200: |
| 1285 | if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK) |
| 1286 | func_to_switch = CURRENT_LIMIT_200; |
| 1287 | |
| 1288 | break; |
| 1289 | |
| 1290 | default: |
| 1291 | continue; |
| 1292 | } |
| 1293 | |
| 1294 | if (func_to_switch != 0xFF) |
| 1295 | break; |
| 1296 | } |
| 1297 | |
| 1298 | RTSX_DEBUGP("SD_FUNC_GROUP_4: func_to_switch = 0x%02x", func_to_switch); |
| 1299 | |
| 1300 | if (func_to_switch <= CURRENT_LIMIT_800) { |
| 1301 | retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch, |
| 1302 | bus_width); |
| 1303 | if (retval != STATUS_SUCCESS) { |
| 1304 | if (sd_check_err_code(chip, SD_NO_CARD)) |
| 1305 | TRACE_RET(chip, STATUS_FAIL); |
| 1306 | } |
| 1307 | RTSX_DEBUGP("Switch current limit finished! (%d)\n", retval); |
| 1308 | } |
| 1309 | |
| 1310 | if (CHK_SD_DDR50(sd_card)) |
| 1311 | RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0); |
| 1312 | |
| 1313 | return STATUS_SUCCESS; |
| 1314 | } |
| 1315 | |
| 1316 | static int sd_wait_data_idle(struct rtsx_chip *chip) |
| 1317 | { |
| 1318 | int retval = STATUS_TIMEDOUT; |
| 1319 | int i; |
| 1320 | u8 val = 0; |
| 1321 | |
| 1322 | for (i = 0; i < 100; i++) { |
| 1323 | RTSX_READ_REG(chip, SD_DATA_STATE, &val); |
| 1324 | if (val & SD_DATA_IDLE) { |
| 1325 | retval = STATUS_SUCCESS; |
| 1326 | break; |
| 1327 | } |
| 1328 | udelay(100); |
| 1329 | } |
| 1330 | RTSX_DEBUGP("SD_DATA_STATE: 0x%02x\n", val); |
| 1331 | |
| 1332 | return retval; |
| 1333 | } |
| 1334 | |
| 1335 | static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point) |
| 1336 | { |
| 1337 | int retval; |
| 1338 | u8 cmd[5]; |
| 1339 | |
| 1340 | retval = sd_change_phase(chip, sample_point, TUNE_RX); |
| 1341 | if (retval != STATUS_SUCCESS) |
| 1342 | TRACE_RET(chip, STATUS_FAIL); |
| 1343 | |
| 1344 | cmd[0] = 0x40 | SEND_TUNING_PATTERN; |
| 1345 | cmd[1] = 0; |
| 1346 | cmd[2] = 0; |
| 1347 | cmd[3] = 0; |
| 1348 | cmd[4] = 0; |
| 1349 | |
| 1350 | retval = sd_read_data(chip, SD_TM_AUTO_TUNING, |
| 1351 | cmd, 5, 0x40, 1, SD_BUS_WIDTH_4, NULL, 0, 100); |
| 1352 | if (retval != STATUS_SUCCESS) { |
| 1353 | (void)sd_wait_data_idle(chip); |
| 1354 | |
| 1355 | rtsx_clear_sd_error(chip); |
| 1356 | TRACE_RET(chip, STATUS_FAIL); |
| 1357 | } |
| 1358 | |
| 1359 | return STATUS_SUCCESS; |
| 1360 | } |
| 1361 | |
| 1362 | static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point) |
| 1363 | { |
| 1364 | struct sd_info *sd_card = &(chip->sd_card); |
| 1365 | int retval; |
| 1366 | u8 cmd[5]; |
| 1367 | |
| 1368 | retval = sd_change_phase(chip, sample_point, TUNE_RX); |
| 1369 | if (retval != STATUS_SUCCESS) |
| 1370 | TRACE_RET(chip, STATUS_FAIL); |
| 1371 | |
| 1372 | RTSX_DEBUGP("sd ddr tuning rx\n"); |
| 1373 | |
| 1374 | retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, |
| 1375 | SD_RSP_TYPE_R1, NULL, 0); |
| 1376 | if (retval != STATUS_SUCCESS) |
| 1377 | TRACE_RET(chip, STATUS_FAIL); |
| 1378 | |
| 1379 | cmd[0] = 0x40 | SD_STATUS; |
| 1380 | cmd[1] = 0; |
| 1381 | cmd[2] = 0; |
| 1382 | cmd[3] = 0; |
| 1383 | cmd[4] = 0; |
| 1384 | |
| 1385 | retval = sd_read_data(chip, SD_TM_NORMAL_READ, |
| 1386 | cmd, 5, 64, 1, SD_BUS_WIDTH_4, NULL, 0, 100); |
| 1387 | if (retval != STATUS_SUCCESS) { |
| 1388 | (void)sd_wait_data_idle(chip); |
| 1389 | |
| 1390 | rtsx_clear_sd_error(chip); |
| 1391 | TRACE_RET(chip, STATUS_FAIL); |
| 1392 | } |
| 1393 | |
| 1394 | return STATUS_SUCCESS; |
| 1395 | } |
| 1396 | |
| 1397 | static int mmc_ddr_tunning_rx_cmd(struct rtsx_chip *chip, u8 sample_point) |
| 1398 | { |
| 1399 | struct sd_info *sd_card = &(chip->sd_card); |
| 1400 | int retval; |
| 1401 | u8 cmd[5], bus_width; |
| 1402 | |
| 1403 | if (CHK_MMC_8BIT(sd_card)) |
| 1404 | bus_width = SD_BUS_WIDTH_8; |
| 1405 | else if (CHK_MMC_4BIT(sd_card)) |
| 1406 | bus_width = SD_BUS_WIDTH_4; |
| 1407 | else |
| 1408 | bus_width = SD_BUS_WIDTH_1; |
| 1409 | |
| 1410 | retval = sd_change_phase(chip, sample_point, TUNE_RX); |
| 1411 | if (retval != STATUS_SUCCESS) |
| 1412 | TRACE_RET(chip, STATUS_FAIL); |
| 1413 | |
| 1414 | RTSX_DEBUGP("mmc ddr tuning rx\n"); |
| 1415 | |
| 1416 | cmd[0] = 0x40 | SEND_EXT_CSD; |
| 1417 | cmd[1] = 0; |
| 1418 | cmd[2] = 0; |
| 1419 | cmd[3] = 0; |
| 1420 | cmd[4] = 0; |
| 1421 | |
| 1422 | retval = sd_read_data(chip, SD_TM_NORMAL_READ, |
| 1423 | cmd, 5, 0x200, 1, bus_width, NULL, 0, 100); |
| 1424 | if (retval != STATUS_SUCCESS) { |
| 1425 | (void)sd_wait_data_idle(chip); |
| 1426 | |
| 1427 | rtsx_clear_sd_error(chip); |
| 1428 | TRACE_RET(chip, STATUS_FAIL); |
| 1429 | } |
| 1430 | |
| 1431 | return STATUS_SUCCESS; |
| 1432 | } |
| 1433 | |
| 1434 | static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point) |
| 1435 | { |
| 1436 | struct sd_info *sd_card = &(chip->sd_card); |
| 1437 | int retval; |
| 1438 | |
| 1439 | retval = sd_change_phase(chip, sample_point, TUNE_TX); |
| 1440 | if (retval != STATUS_SUCCESS) |
| 1441 | TRACE_RET(chip, STATUS_FAIL); |
| 1442 | |
| 1443 | RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, |
| 1444 | SD_RSP_80CLK_TIMEOUT_EN); |
| 1445 | |
| 1446 | retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, |
| 1447 | SD_RSP_TYPE_R1, NULL, 0); |
| 1448 | if (retval != STATUS_SUCCESS) { |
| 1449 | if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) { |
| 1450 | rtsx_write_register(chip, SD_CFG3, |
| 1451 | SD_RSP_80CLK_TIMEOUT_EN, 0); |
| 1452 | TRACE_RET(chip, STATUS_FAIL); |
| 1453 | } |
| 1454 | } |
| 1455 | |
| 1456 | RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); |
| 1457 | |
| 1458 | return STATUS_SUCCESS; |
| 1459 | } |
| 1460 | |
| 1461 | static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point) |
| 1462 | { |
| 1463 | struct sd_info *sd_card = &(chip->sd_card); |
| 1464 | int retval; |
| 1465 | u8 cmd[5], bus_width; |
| 1466 | |
| 1467 | retval = sd_change_phase(chip, sample_point, TUNE_TX); |
| 1468 | if (retval != STATUS_SUCCESS) |
| 1469 | TRACE_RET(chip, STATUS_FAIL); |
| 1470 | |
| 1471 | if (CHK_SD(sd_card)) { |
| 1472 | bus_width = SD_BUS_WIDTH_4; |
| 1473 | } else { |
| 1474 | if (CHK_MMC_8BIT(sd_card)) |
| 1475 | bus_width = SD_BUS_WIDTH_8; |
| 1476 | else if (CHK_MMC_4BIT(sd_card)) |
| 1477 | bus_width = SD_BUS_WIDTH_4; |
| 1478 | else |
| 1479 | bus_width = SD_BUS_WIDTH_1; |
| 1480 | } |
| 1481 | |
| 1482 | retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); |
| 1483 | if (retval != STATUS_SUCCESS) |
| 1484 | TRACE_RET(chip, STATUS_FAIL); |
| 1485 | |
| 1486 | RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, |
| 1487 | SD_RSP_80CLK_TIMEOUT_EN); |
| 1488 | |
| 1489 | cmd[0] = 0x40 | PROGRAM_CSD; |
| 1490 | cmd[1] = 0; |
| 1491 | cmd[2] = 0; |
| 1492 | cmd[3] = 0; |
| 1493 | cmd[4] = 0; |
| 1494 | |
| 1495 | retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2, |
| 1496 | cmd, 5, 16, 1, bus_width, sd_card->raw_csd, 16, 100); |
| 1497 | if (retval != STATUS_SUCCESS) { |
| 1498 | rtsx_clear_sd_error(chip); |
| 1499 | rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); |
| 1500 | TRACE_RET(chip, STATUS_FAIL); |
| 1501 | } |
| 1502 | |
| 1503 | RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); |
| 1504 | |
| 1505 | sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, |
| 1506 | NULL, 0); |
| 1507 | |
| 1508 | return STATUS_SUCCESS; |
| 1509 | } |
| 1510 | |
| 1511 | static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map, |
| 1512 | u8 tune_dir) |
| 1513 | { |
| 1514 | struct sd_info *sd_card = &(chip->sd_card); |
| 1515 | struct timing_phase_path path[MAX_PHASE + 1]; |
| 1516 | int i, j, cont_path_cnt; |
| 1517 | int new_block, max_len, final_path_idx; |
| 1518 | u8 final_phase = 0xFF; |
| 1519 | |
| 1520 | if (phase_map == 0xFFFFFFFF) { |
| 1521 | if (tune_dir == TUNE_RX) |
| 1522 | final_phase = (u8)chip->sd_default_rx_phase; |
| 1523 | else |
| 1524 | final_phase = (u8)chip->sd_default_tx_phase; |
| 1525 | |
| 1526 | goto Search_Finish; |
| 1527 | } |
| 1528 | |
| 1529 | cont_path_cnt = 0; |
| 1530 | new_block = 1; |
| 1531 | j = 0; |
| 1532 | for (i = 0; i < MAX_PHASE + 1; i++) { |
| 1533 | if (phase_map & (1 << i)) { |
| 1534 | if (new_block) { |
| 1535 | new_block = 0; |
| 1536 | j = cont_path_cnt++; |
| 1537 | path[j].start = i; |
| 1538 | path[j].end = i; |
| 1539 | } else { |
| 1540 | path[j].end = i; |
| 1541 | } |
| 1542 | } else { |
| 1543 | new_block = 1; |
| 1544 | if (cont_path_cnt) { |
| 1545 | int idx = cont_path_cnt - 1; |
| 1546 | path[idx].len = path[idx].end - |
| 1547 | path[idx].start + 1; |
| 1548 | path[idx].mid = path[idx].start + |
| 1549 | path[idx].len / 2; |
| 1550 | } |
| 1551 | } |
| 1552 | } |
| 1553 | |
| 1554 | if (cont_path_cnt == 0) { |
| 1555 | RTSX_DEBUGP("No continuous phase path\n"); |
| 1556 | goto Search_Finish; |
| 1557 | } else { |
| 1558 | int idx = cont_path_cnt - 1; |
| 1559 | path[idx].len = path[idx].end - path[idx].start + 1; |
| 1560 | path[idx].mid = path[idx].start + path[idx].len / 2; |
| 1561 | } |
| 1562 | |
| 1563 | if ((path[0].start == 0) && |
| 1564 | (path[cont_path_cnt - 1].end == MAX_PHASE)) { |
| 1565 | path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1; |
| 1566 | path[0].len += path[cont_path_cnt - 1].len; |
| 1567 | path[0].mid = path[0].start + path[0].len / 2; |
| 1568 | if (path[0].mid < 0) |
| 1569 | path[0].mid += MAX_PHASE + 1; |
| 1570 | |
| 1571 | cont_path_cnt--; |
| 1572 | } |
| 1573 | |
| 1574 | max_len = 0; |
| 1575 | final_phase = 0; |
| 1576 | final_path_idx = 0; |
| 1577 | for (i = 0; i < cont_path_cnt; i++) { |
| 1578 | if (path[i].len > max_len) { |
| 1579 | max_len = path[i].len; |
| 1580 | final_phase = (u8)path[i].mid; |
| 1581 | final_path_idx = i; |
| 1582 | } |
| 1583 | |
| 1584 | RTSX_DEBUGP("path[%d].start = %d\n", i, path[i].start); |
| 1585 | RTSX_DEBUGP("path[%d].end = %d\n", i, path[i].end); |
| 1586 | RTSX_DEBUGP("path[%d].len = %d\n", i, path[i].len); |
| 1587 | RTSX_DEBUGP("path[%d].mid = %d\n", i, path[i].mid); |
| 1588 | RTSX_DEBUGP("\n"); |
| 1589 | } |
| 1590 | |
| 1591 | if (tune_dir == TUNE_TX) { |
| 1592 | if (CHK_SD_SDR104(sd_card)) { |
| 1593 | if (max_len > 15) { |
| 1594 | int temp_mid = (max_len - 16) / 2; |
| 1595 | int temp_final_phase = |
| 1596 | path[final_path_idx].end - |
| 1597 | (max_len - (6 + temp_mid)); |
| 1598 | |
| 1599 | if (temp_final_phase < 0) |
| 1600 | final_phase = (u8)(temp_final_phase + |
| 1601 | MAX_PHASE + 1); |
| 1602 | else |
| 1603 | final_phase = (u8)temp_final_phase; |
| 1604 | } |
| 1605 | } else if (CHK_SD_SDR50(sd_card)) { |
| 1606 | if (max_len > 12) { |
| 1607 | int temp_mid = (max_len - 13) / 2; |
| 1608 | int temp_final_phase = |
| 1609 | path[final_path_idx].end - |
| 1610 | (max_len - (3 + temp_mid)); |
| 1611 | |
| 1612 | if (temp_final_phase < 0) |
| 1613 | final_phase = (u8)(temp_final_phase + |
| 1614 | MAX_PHASE + 1); |
| 1615 | else |
| 1616 | final_phase = (u8)temp_final_phase; |
| 1617 | } |
| 1618 | } |
| 1619 | } |
| 1620 | |
| 1621 | Search_Finish: |
| 1622 | RTSX_DEBUGP("Final chosen phase: %d\n", final_phase); |
| 1623 | return final_phase; |
| 1624 | } |
| 1625 | |
| 1626 | static int sd_tuning_rx(struct rtsx_chip *chip) |
| 1627 | { |
| 1628 | struct sd_info *sd_card = &(chip->sd_card); |
| 1629 | int retval; |
| 1630 | int i, j; |
| 1631 | u32 raw_phase_map[3], phase_map; |
| 1632 | u8 final_phase; |
| 1633 | int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point); |
| 1634 | |
| 1635 | if (CHK_SD(sd_card)) { |
| 1636 | if (CHK_SD_DDR50(sd_card)) |
| 1637 | tuning_cmd = sd_ddr_tuning_rx_cmd; |
| 1638 | else |
| 1639 | tuning_cmd = sd_sdr_tuning_rx_cmd; |
| 1640 | |
| 1641 | } else { |
| 1642 | if (CHK_MMC_DDR52(sd_card)) |
| 1643 | tuning_cmd = mmc_ddr_tunning_rx_cmd; |
| 1644 | else |
| 1645 | TRACE_RET(chip, STATUS_FAIL); |
| 1646 | } |
| 1647 | |
| 1648 | for (i = 0; i < 3; i++) { |
| 1649 | raw_phase_map[i] = 0; |
| 1650 | for (j = MAX_PHASE; j >= 0; j--) { |
| 1651 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { |
| 1652 | sd_set_err_code(chip, SD_NO_CARD); |
| 1653 | TRACE_RET(chip, STATUS_FAIL); |
| 1654 | } |
| 1655 | |
| 1656 | retval = tuning_cmd(chip, (u8)j); |
| 1657 | if (retval == STATUS_SUCCESS) |
| 1658 | raw_phase_map[i] |= 1 << j; |
| 1659 | } |
| 1660 | } |
| 1661 | |
| 1662 | phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2]; |
| 1663 | for (i = 0; i < 3; i++) |
| 1664 | RTSX_DEBUGP("RX raw_phase_map[%d] = 0x%08x\n", i, |
| 1665 | raw_phase_map[i]); |
| 1666 | |
| 1667 | RTSX_DEBUGP("RX phase_map = 0x%08x\n", phase_map); |
| 1668 | |
| 1669 | final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX); |
| 1670 | if (final_phase == 0xFF) |
| 1671 | TRACE_RET(chip, STATUS_FAIL); |
| 1672 | |
| 1673 | retval = sd_change_phase(chip, final_phase, TUNE_RX); |
| 1674 | if (retval != STATUS_SUCCESS) |
| 1675 | TRACE_RET(chip, STATUS_FAIL); |
| 1676 | |
| 1677 | return STATUS_SUCCESS; |
| 1678 | } |
| 1679 | |
| 1680 | static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip) |
| 1681 | { |
| 1682 | struct sd_info *sd_card = &(chip->sd_card); |
| 1683 | int retval; |
| 1684 | int i; |
| 1685 | u32 phase_map; |
| 1686 | u8 final_phase; |
| 1687 | |
| 1688 | RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, |
| 1689 | SD_RSP_80CLK_TIMEOUT_EN); |
| 1690 | |
| 1691 | phase_map = 0; |
| 1692 | for (i = MAX_PHASE; i >= 0; i--) { |
| 1693 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { |
| 1694 | sd_set_err_code(chip, SD_NO_CARD); |
| 1695 | rtsx_write_register(chip, SD_CFG3, |
| 1696 | SD_RSP_80CLK_TIMEOUT_EN, 0); |
| 1697 | TRACE_RET(chip, STATUS_FAIL); |
| 1698 | } |
| 1699 | |
| 1700 | retval = sd_change_phase(chip, (u8)i, TUNE_TX); |
| 1701 | if (retval != STATUS_SUCCESS) |
| 1702 | continue; |
| 1703 | |
| 1704 | retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, |
| 1705 | sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, |
| 1706 | 0); |
| 1707 | if ((retval == STATUS_SUCCESS) || |
| 1708 | !sd_check_err_code(chip, SD_RSP_TIMEOUT)) |
| 1709 | phase_map |= 1 << i; |
| 1710 | } |
| 1711 | |
| 1712 | RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); |
| 1713 | |
| 1714 | RTSX_DEBUGP("DDR TX pre tune phase_map = 0x%08x\n", phase_map); |
| 1715 | |
| 1716 | final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX); |
| 1717 | if (final_phase == 0xFF) |
| 1718 | TRACE_RET(chip, STATUS_FAIL); |
| 1719 | |
| 1720 | retval = sd_change_phase(chip, final_phase, TUNE_TX); |
| 1721 | if (retval != STATUS_SUCCESS) |
| 1722 | TRACE_RET(chip, STATUS_FAIL); |
| 1723 | |
| 1724 | RTSX_DEBUGP("DDR TX pre tune phase: %d\n", (int)final_phase); |
| 1725 | |
| 1726 | return STATUS_SUCCESS; |
| 1727 | } |
| 1728 | |
| 1729 | static int sd_tuning_tx(struct rtsx_chip *chip) |
| 1730 | { |
| 1731 | struct sd_info *sd_card = &(chip->sd_card); |
| 1732 | int retval; |
| 1733 | int i, j; |
| 1734 | u32 raw_phase_map[3], phase_map; |
| 1735 | u8 final_phase; |
| 1736 | int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point); |
| 1737 | |
| 1738 | if (CHK_SD(sd_card)) { |
| 1739 | if (CHK_SD_DDR50(sd_card)) |
| 1740 | tuning_cmd = sd_ddr_tuning_tx_cmd; |
| 1741 | else |
| 1742 | tuning_cmd = sd_sdr_tuning_tx_cmd; |
| 1743 | |
| 1744 | } else { |
| 1745 | if (CHK_MMC_DDR52(sd_card)) |
| 1746 | tuning_cmd = sd_ddr_tuning_tx_cmd; |
| 1747 | else |
| 1748 | TRACE_RET(chip, STATUS_FAIL); |
| 1749 | } |
| 1750 | |
| 1751 | for (i = 0; i < 3; i++) { |
| 1752 | raw_phase_map[i] = 0; |
| 1753 | for (j = MAX_PHASE; j >= 0; j--) { |
| 1754 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { |
| 1755 | sd_set_err_code(chip, SD_NO_CARD); |
| 1756 | rtsx_write_register(chip, SD_CFG3, |
| 1757 | SD_RSP_80CLK_TIMEOUT_EN, 0); |
| 1758 | TRACE_RET(chip, STATUS_FAIL); |
| 1759 | } |
| 1760 | |
| 1761 | retval = tuning_cmd(chip, (u8)j); |
| 1762 | if (retval == STATUS_SUCCESS) |
| 1763 | raw_phase_map[i] |= 1 << j; |
| 1764 | } |
| 1765 | } |
| 1766 | |
| 1767 | phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2]; |
| 1768 | for (i = 0; i < 3; i++) |
| 1769 | RTSX_DEBUGP("TX raw_phase_map[%d] = 0x%08x\n", |
| 1770 | i, raw_phase_map[i]); |
| 1771 | |
| 1772 | RTSX_DEBUGP("TX phase_map = 0x%08x\n", phase_map); |
| 1773 | |
| 1774 | final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX); |
| 1775 | if (final_phase == 0xFF) |
| 1776 | TRACE_RET(chip, STATUS_FAIL); |
| 1777 | |
| 1778 | retval = sd_change_phase(chip, final_phase, TUNE_TX); |
| 1779 | if (retval != STATUS_SUCCESS) |
| 1780 | TRACE_RET(chip, STATUS_FAIL); |
| 1781 | |
| 1782 | return STATUS_SUCCESS; |
| 1783 | } |
| 1784 | |
| 1785 | static int sd_sdr_tuning(struct rtsx_chip *chip) |
| 1786 | { |
| 1787 | int retval; |
| 1788 | |
| 1789 | retval = sd_tuning_tx(chip); |
| 1790 | if (retval != STATUS_SUCCESS) |
| 1791 | TRACE_RET(chip, STATUS_FAIL); |
| 1792 | |
| 1793 | retval = sd_tuning_rx(chip); |
| 1794 | if (retval != STATUS_SUCCESS) |
| 1795 | TRACE_RET(chip, STATUS_FAIL); |
| 1796 | |
| 1797 | return STATUS_SUCCESS; |
| 1798 | } |
| 1799 | |
| 1800 | static int sd_ddr_tuning(struct rtsx_chip *chip) |
| 1801 | { |
| 1802 | int retval; |
| 1803 | |
| 1804 | if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) { |
| 1805 | retval = sd_ddr_pre_tuning_tx(chip); |
| 1806 | if (retval != STATUS_SUCCESS) |
| 1807 | TRACE_RET(chip, STATUS_FAIL); |
| 1808 | } else { |
| 1809 | retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase, |
| 1810 | TUNE_TX); |
| 1811 | if (retval != STATUS_SUCCESS) |
| 1812 | TRACE_RET(chip, STATUS_FAIL); |
| 1813 | } |
| 1814 | |
| 1815 | retval = sd_tuning_rx(chip); |
| 1816 | if (retval != STATUS_SUCCESS) |
| 1817 | TRACE_RET(chip, STATUS_FAIL); |
| 1818 | |
| 1819 | if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) { |
| 1820 | retval = sd_tuning_tx(chip); |
| 1821 | if (retval != STATUS_SUCCESS) |
| 1822 | TRACE_RET(chip, STATUS_FAIL); |
| 1823 | } |
| 1824 | |
| 1825 | return STATUS_SUCCESS; |
| 1826 | } |
| 1827 | |
| 1828 | static int mmc_ddr_tuning(struct rtsx_chip *chip) |
| 1829 | { |
| 1830 | int retval; |
| 1831 | |
| 1832 | if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) { |
| 1833 | retval = sd_ddr_pre_tuning_tx(chip); |
| 1834 | if (retval != STATUS_SUCCESS) |
| 1835 | TRACE_RET(chip, STATUS_FAIL); |
| 1836 | } else { |
| 1837 | retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase, |
| 1838 | TUNE_TX); |
| 1839 | if (retval != STATUS_SUCCESS) |
| 1840 | TRACE_RET(chip, STATUS_FAIL); |
| 1841 | } |
| 1842 | |
| 1843 | retval = sd_tuning_rx(chip); |
| 1844 | if (retval != STATUS_SUCCESS) |
| 1845 | TRACE_RET(chip, STATUS_FAIL); |
| 1846 | |
| 1847 | if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) { |
| 1848 | retval = sd_tuning_tx(chip); |
| 1849 | if (retval != STATUS_SUCCESS) |
| 1850 | TRACE_RET(chip, STATUS_FAIL); |
| 1851 | } |
| 1852 | |
| 1853 | return STATUS_SUCCESS; |
| 1854 | } |
| 1855 | |
| 1856 | int sd_switch_clock(struct rtsx_chip *chip) |
| 1857 | { |
| 1858 | struct sd_info *sd_card = &(chip->sd_card); |
| 1859 | int retval; |
| 1860 | int re_tuning = 0; |
| 1861 | |
| 1862 | retval = select_card(chip, SD_CARD); |
| 1863 | if (retval != STATUS_SUCCESS) |
| 1864 | TRACE_RET(chip, STATUS_FAIL); |
| 1865 | |
| 1866 | retval = switch_clock(chip, sd_card->sd_clock); |
| 1867 | if (retval != STATUS_SUCCESS) |
| 1868 | TRACE_RET(chip, STATUS_FAIL); |
| 1869 | |
| 1870 | if (re_tuning) { |
| 1871 | if (CHK_SD(sd_card)) { |
| 1872 | if (CHK_SD_DDR50(sd_card)) |
| 1873 | retval = sd_ddr_tuning(chip); |
| 1874 | else |
| 1875 | retval = sd_sdr_tuning(chip); |
| 1876 | } else { |
| 1877 | if (CHK_MMC_DDR52(sd_card)) |
| 1878 | retval = mmc_ddr_tuning(chip); |
| 1879 | } |
| 1880 | |
| 1881 | if (retval != STATUS_SUCCESS) |
| 1882 | TRACE_RET(chip, STATUS_FAIL); |
| 1883 | } |
| 1884 | |
| 1885 | return STATUS_SUCCESS; |
| 1886 | } |
| 1887 | |
| 1888 | static int sd_prepare_reset(struct rtsx_chip *chip) |
| 1889 | { |
| 1890 | struct sd_info *sd_card = &(chip->sd_card); |
| 1891 | int retval; |
| 1892 | |
| 1893 | if (chip->asic_code) |
| 1894 | sd_card->sd_clock = 29; |
| 1895 | else |
| 1896 | sd_card->sd_clock = CLK_30; |
| 1897 | |
| 1898 | sd_card->sd_type = 0; |
| 1899 | sd_card->seq_mode = 0; |
| 1900 | sd_card->sd_data_buf_ready = 0; |
| 1901 | sd_card->capacity = 0; |
| 1902 | |
| 1903 | #ifdef SUPPORT_SD_LOCK |
| 1904 | sd_card->sd_lock_status = 0; |
| 1905 | sd_card->sd_erase_status = 0; |
| 1906 | #endif |
| 1907 | |
| 1908 | chip->capacity[chip->card2lun[SD_CARD]] = 0; |
| 1909 | chip->sd_io = 0; |
| 1910 | |
| 1911 | retval = sd_set_init_para(chip); |
| 1912 | if (retval != STATUS_SUCCESS) |
| 1913 | TRACE_RET(chip, retval); |
| 1914 | |
| 1915 | RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF, 0x40); |
| 1916 | |
| 1917 | RTSX_WRITE_REG(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, |
| 1918 | SD_STOP | SD_CLR_ERR); |
| 1919 | |
| 1920 | retval = select_card(chip, SD_CARD); |
| 1921 | if (retval != STATUS_SUCCESS) |
| 1922 | TRACE_RET(chip, STATUS_FAIL); |
| 1923 | |
| 1924 | return STATUS_SUCCESS; |
| 1925 | } |
| 1926 | |
| 1927 | static int sd_pull_ctl_disable(struct rtsx_chip *chip) |
| 1928 | { |
| 1929 | if (CHECK_PID(chip, 0x5208)) { |
| 1930 | RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, |
| 1931 | XD_D3_PD | SD_D7_PD | SD_CLK_PD | SD_D5_PD); |
| 1932 | RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, |
| 1933 | SD_D6_PD | SD_D0_PD | SD_D1_PD | XD_D5_PD); |
| 1934 | RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, |
| 1935 | SD_D4_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); |
| 1936 | RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, |
| 1937 | XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); |
| 1938 | RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, |
| 1939 | MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); |
| 1940 | RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD); |
| 1941 | } else if (CHECK_PID(chip, 0x5288)) { |
| 1942 | if (CHECK_BARO_PKG(chip, QFN)) { |
| 1943 | RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55); |
| 1944 | RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55); |
| 1945 | RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B); |
| 1946 | RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69); |
| 1947 | } |
| 1948 | } |
| 1949 | |
| 1950 | return STATUS_SUCCESS; |
| 1951 | } |
| 1952 | |
| 1953 | int sd_pull_ctl_enable(struct rtsx_chip *chip) |
| 1954 | { |
| 1955 | int retval; |
| 1956 | |
| 1957 | rtsx_init_cmd(chip); |
| 1958 | |
| 1959 | if (CHECK_PID(chip, 0x5208)) { |
| 1960 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, |
| 1961 | XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU); |
| 1962 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, |
| 1963 | SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD); |
| 1964 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, |
| 1965 | SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU); |
| 1966 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, |
| 1967 | XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD); |
| 1968 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, |
| 1969 | MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU); |
| 1970 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, |
| 1971 | MS_D5_PD | MS_D4_PD); |
| 1972 | } else if (CHECK_PID(chip, 0x5288)) { |
| 1973 | if (CHECK_BARO_PKG(chip, QFN)) { |
| 1974 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, |
| 1975 | 0xA8); |
| 1976 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, |
| 1977 | 0x5A); |
| 1978 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, |
| 1979 | 0x95); |
| 1980 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, |
| 1981 | 0xAA); |
| 1982 | } |
| 1983 | } |
| 1984 | |
| 1985 | retval = rtsx_send_cmd(chip, SD_CARD, 100); |
| 1986 | if (retval < 0) |
| 1987 | TRACE_RET(chip, STATUS_FAIL); |
| 1988 | |
| 1989 | return STATUS_SUCCESS; |
| 1990 | } |
| 1991 | |
| 1992 | static int sd_init_power(struct rtsx_chip *chip) |
| 1993 | { |
| 1994 | int retval; |
| 1995 | |
| 1996 | retval = sd_power_off_card3v3(chip); |
| 1997 | if (retval != STATUS_SUCCESS) |
| 1998 | TRACE_RET(chip, STATUS_FAIL); |
| 1999 | |
| 2000 | if (!chip->ft2_fast_mode) |
| 2001 | wait_timeout(250); |
| 2002 | |
| 2003 | retval = enable_card_clock(chip, SD_CARD); |
| 2004 | if (retval != STATUS_SUCCESS) |
| 2005 | TRACE_RET(chip, STATUS_FAIL); |
| 2006 | |
| 2007 | if (chip->asic_code) { |
| 2008 | retval = sd_pull_ctl_enable(chip); |
| 2009 | if (retval != STATUS_SUCCESS) |
| 2010 | TRACE_RET(chip, STATUS_FAIL); |
| 2011 | } else { |
| 2012 | RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_SD_PULL_CTL_BIT | 0x20, |
| 2013 | 0); |
| 2014 | } |
| 2015 | |
| 2016 | if (!chip->ft2_fast_mode) { |
| 2017 | retval = card_power_on(chip, SD_CARD); |
| 2018 | if (retval != STATUS_SUCCESS) |
| 2019 | TRACE_RET(chip, STATUS_FAIL); |
| 2020 | |
| 2021 | wait_timeout(260); |
| 2022 | |
| 2023 | #ifdef SUPPORT_OCP |
| 2024 | if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { |
| 2025 | RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", |
| 2026 | chip->ocp_stat); |
| 2027 | TRACE_RET(chip, STATUS_FAIL); |
| 2028 | } |
| 2029 | #endif |
| 2030 | } |
| 2031 | |
| 2032 | RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); |
| 2033 | |
| 2034 | return STATUS_SUCCESS; |
| 2035 | } |
| 2036 | |
| 2037 | static int sd_dummy_clock(struct rtsx_chip *chip) |
| 2038 | { |
| 2039 | RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0x01); |
| 2040 | wait_timeout(5); |
| 2041 | RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0); |
| 2042 | |
| 2043 | return STATUS_SUCCESS; |
| 2044 | } |
| 2045 | |
| 2046 | static int sd_read_lba0(struct rtsx_chip *chip) |
| 2047 | { |
| 2048 | struct sd_info *sd_card = &(chip->sd_card); |
| 2049 | int retval; |
| 2050 | u8 cmd[5], bus_width; |
| 2051 | |
| 2052 | cmd[0] = 0x40 | READ_SINGLE_BLOCK; |
| 2053 | cmd[1] = 0; |
| 2054 | cmd[2] = 0; |
| 2055 | cmd[3] = 0; |
| 2056 | cmd[4] = 0; |
| 2057 | |
| 2058 | if (CHK_SD(sd_card)) { |
| 2059 | bus_width = SD_BUS_WIDTH_4; |
| 2060 | } else { |
| 2061 | if (CHK_MMC_8BIT(sd_card)) |
| 2062 | bus_width = SD_BUS_WIDTH_8; |
| 2063 | else if (CHK_MMC_4BIT(sd_card)) |
| 2064 | bus_width = SD_BUS_WIDTH_4; |
| 2065 | else |
| 2066 | bus_width = SD_BUS_WIDTH_1; |
| 2067 | } |
| 2068 | |
| 2069 | retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, |
| 2070 | 5, 512, 1, bus_width, NULL, 0, 100); |
| 2071 | if (retval != STATUS_SUCCESS) { |
| 2072 | rtsx_clear_sd_error(chip); |
| 2073 | TRACE_RET(chip, STATUS_FAIL); |
| 2074 | } |
| 2075 | |
| 2076 | return STATUS_SUCCESS; |
| 2077 | } |
| 2078 | |
| 2079 | static int sd_check_wp_state(struct rtsx_chip *chip) |
| 2080 | { |
| 2081 | struct sd_info *sd_card = &(chip->sd_card); |
| 2082 | int retval; |
| 2083 | u32 val; |
| 2084 | u16 sd_card_type; |
| 2085 | u8 cmd[5], buf[64]; |
| 2086 | |
| 2087 | retval = sd_send_cmd_get_rsp(chip, APP_CMD, |
| 2088 | sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); |
| 2089 | if (retval != STATUS_SUCCESS) |
| 2090 | TRACE_RET(chip, STATUS_FAIL); |
| 2091 | |
| 2092 | cmd[0] = 0x40 | SD_STATUS; |
| 2093 | cmd[1] = 0; |
| 2094 | cmd[2] = 0; |
| 2095 | cmd[3] = 0; |
| 2096 | cmd[4] = 0; |
| 2097 | |
| 2098 | retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, |
| 2099 | SD_BUS_WIDTH_4, buf, 64, 250); |
| 2100 | if (retval != STATUS_SUCCESS) { |
| 2101 | rtsx_clear_sd_error(chip); |
| 2102 | |
| 2103 | sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, |
| 2104 | SD_RSP_TYPE_R1, NULL, 0); |
| 2105 | TRACE_RET(chip, STATUS_FAIL); |
| 2106 | } |
| 2107 | |
| 2108 | RTSX_DEBUGP("ACMD13:\n"); |
| 2109 | RTSX_DUMP(buf, 64); |
| 2110 | |
| 2111 | sd_card_type = ((u16)buf[2] << 8) | buf[3]; |
| 2112 | RTSX_DEBUGP("sd_card_type = 0x%04x\n", sd_card_type); |
| 2113 | if ((sd_card_type == 0x0001) || (sd_card_type == 0x0002)) { |
| 2114 | /* ROM card or OTP */ |
| 2115 | chip->card_wp |= SD_CARD; |
| 2116 | } |
| 2117 | |
| 2118 | /* Check SD Machanical Write-Protect Switch */ |
| 2119 | val = rtsx_readl(chip, RTSX_BIPR); |
| 2120 | if (val & SD_WRITE_PROTECT) |
| 2121 | chip->card_wp |= SD_CARD; |
| 2122 | |
| 2123 | return STATUS_SUCCESS; |
| 2124 | } |
| 2125 | |
| 2126 | static int reset_sd(struct rtsx_chip *chip) |
| 2127 | { |
| 2128 | struct sd_info *sd_card = &(chip->sd_card); |
| 2129 | int retval, i = 0, j = 0, k = 0, hi_cap_flow = 0; |
| 2130 | int sd_dont_switch = 0; |
| 2131 | int support_1v8 = 0; |
| 2132 | int try_sdio = 1; |
| 2133 | u8 rsp[16]; |
| 2134 | u8 switch_bus_width; |
| 2135 | u32 voltage = 0; |
| 2136 | int sd20_mode = 0; |
| 2137 | |
| 2138 | SET_SD(sd_card); |
| 2139 | |
| 2140 | Switch_Fail: |
| 2141 | |
| 2142 | i = 0; |
| 2143 | j = 0; |
| 2144 | k = 0; |
| 2145 | hi_cap_flow = 0; |
| 2146 | |
| 2147 | #ifdef SUPPORT_SD_LOCK |
| 2148 | if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) |
| 2149 | goto SD_UNLOCK_ENTRY; |
| 2150 | #endif |
| 2151 | |
| 2152 | retval = sd_prepare_reset(chip); |
| 2153 | if (retval != STATUS_SUCCESS) |
| 2154 | TRACE_RET(chip, STATUS_FAIL); |
| 2155 | |
| 2156 | retval = sd_dummy_clock(chip); |
| 2157 | if (retval != STATUS_SUCCESS) |
| 2158 | TRACE_RET(chip, STATUS_FAIL); |
| 2159 | |
| 2160 | if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) { |
| 2161 | int rty_cnt = 0; |
| 2162 | |
| 2163 | for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) { |
| 2164 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { |
| 2165 | sd_set_err_code(chip, SD_NO_CARD); |
| 2166 | TRACE_RET(chip, STATUS_FAIL); |
| 2167 | } |
| 2168 | |
| 2169 | retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0, |
| 2170 | SD_RSP_TYPE_R4, rsp, 5); |
| 2171 | if (retval == STATUS_SUCCESS) { |
| 2172 | int func_num = (rsp[1] >> 4) & 0x07; |
| 2173 | if (func_num) { |
| 2174 | RTSX_DEBUGP("SD_IO card (Function number: %d)!\n", func_num); |
| 2175 | chip->sd_io = 1; |
| 2176 | TRACE_RET(chip, STATUS_FAIL); |
| 2177 | } |
| 2178 | |
| 2179 | break; |
| 2180 | } |
| 2181 | |
| 2182 | sd_init_power(chip); |
| 2183 | |
| 2184 | sd_dummy_clock(chip); |
| 2185 | } |
| 2186 | |
| 2187 | RTSX_DEBUGP("Normal card!\n"); |
| 2188 | } |
| 2189 | |
| 2190 | /* Start Initialization Process of SD Card */ |
| 2191 | RTY_SD_RST: |
| 2192 | retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, |
| 2193 | NULL, 0); |
| 2194 | if (retval != STATUS_SUCCESS) |
| 2195 | TRACE_RET(chip, STATUS_FAIL); |
| 2196 | |
| 2197 | wait_timeout(20); |
| 2198 | |
| 2199 | retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA, |
| 2200 | SD_RSP_TYPE_R7, rsp, 5); |
| 2201 | if (retval == STATUS_SUCCESS) { |
| 2202 | if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) { |
| 2203 | hi_cap_flow = 1; |
| 2204 | voltage = SUPPORT_VOLTAGE | 0x40000000; |
| 2205 | } |
| 2206 | } |
| 2207 | |
| 2208 | if (!hi_cap_flow) { |
| 2209 | voltage = SUPPORT_VOLTAGE; |
| 2210 | |
| 2211 | retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, |
| 2212 | SD_RSP_TYPE_R0, NULL, 0); |
| 2213 | if (retval != STATUS_SUCCESS) |
| 2214 | TRACE_RET(chip, STATUS_FAIL); |
| 2215 | |
| 2216 | wait_timeout(20); |
| 2217 | } |
| 2218 | |
| 2219 | do { |
| 2220 | retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1, |
| 2221 | NULL, 0); |
| 2222 | if (retval != STATUS_SUCCESS) { |
| 2223 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { |
| 2224 | sd_set_err_code(chip, SD_NO_CARD); |
| 2225 | TRACE_RET(chip, STATUS_FAIL); |
| 2226 | } |
| 2227 | |
| 2228 | j++; |
| 2229 | if (j < 3) |
| 2230 | goto RTY_SD_RST; |
| 2231 | else |
| 2232 | TRACE_RET(chip, STATUS_FAIL); |
| 2233 | } |
| 2234 | |
| 2235 | retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage, |
| 2236 | SD_RSP_TYPE_R3, rsp, 5); |
| 2237 | if (retval != STATUS_SUCCESS) { |
| 2238 | k++; |
| 2239 | if (k < 3) |
| 2240 | goto RTY_SD_RST; |
| 2241 | else |
| 2242 | TRACE_RET(chip, STATUS_FAIL); |
| 2243 | } |
| 2244 | |
| 2245 | i++; |
| 2246 | wait_timeout(20); |
| 2247 | } while (!(rsp[1] & 0x80) && (i < 255)); |
| 2248 | |
| 2249 | if (i == 255) |
| 2250 | TRACE_RET(chip, STATUS_FAIL); |
| 2251 | |
| 2252 | if (hi_cap_flow) { |
| 2253 | if (rsp[1] & 0x40) |
| 2254 | SET_SD_HCXC(sd_card); |
| 2255 | else |
| 2256 | CLR_SD_HCXC(sd_card); |
| 2257 | |
| 2258 | support_1v8 = 0; |
| 2259 | } else { |
| 2260 | CLR_SD_HCXC(sd_card); |
| 2261 | support_1v8 = 0; |
| 2262 | } |
| 2263 | RTSX_DEBUGP("support_1v8 = %d\n", support_1v8); |
| 2264 | |
| 2265 | if (support_1v8) { |
| 2266 | retval = sd_voltage_switch(chip); |
| 2267 | if (retval != STATUS_SUCCESS) |
| 2268 | TRACE_RET(chip, STATUS_FAIL); |
| 2269 | } |
| 2270 | |
| 2271 | retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, |
| 2272 | NULL, 0); |
| 2273 | if (retval != STATUS_SUCCESS) |
| 2274 | TRACE_RET(chip, STATUS_FAIL); |
| 2275 | |
| 2276 | for (i = 0; i < 3; i++) { |
| 2277 | retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0, |
| 2278 | SD_RSP_TYPE_R6, rsp, 5); |
| 2279 | if (retval != STATUS_SUCCESS) |
| 2280 | TRACE_RET(chip, STATUS_FAIL); |
| 2281 | |
| 2282 | sd_card->sd_addr = (u32)rsp[1] << 24; |
| 2283 | sd_card->sd_addr += (u32)rsp[2] << 16; |
| 2284 | |
| 2285 | if (sd_card->sd_addr) |
| 2286 | break; |
| 2287 | } |
| 2288 | |
| 2289 | retval = sd_check_csd(chip, 1); |
| 2290 | if (retval != STATUS_SUCCESS) |
| 2291 | TRACE_RET(chip, STATUS_FAIL); |
| 2292 | |
| 2293 | retval = sd_select_card(chip, 1); |
| 2294 | if (retval != STATUS_SUCCESS) |
| 2295 | TRACE_RET(chip, STATUS_FAIL); |
| 2296 | |
| 2297 | #ifdef SUPPORT_SD_LOCK |
| 2298 | SD_UNLOCK_ENTRY: |
| 2299 | retval = sd_update_lock_status(chip); |
| 2300 | if (retval != STATUS_SUCCESS) |
| 2301 | TRACE_RET(chip, STATUS_FAIL); |
| 2302 | |
| 2303 | if (sd_card->sd_lock_status & SD_LOCKED) { |
| 2304 | sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST); |
| 2305 | return STATUS_SUCCESS; |
| 2306 | } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) { |
| 2307 | sd_card->sd_lock_status &= ~SD_PWD_EXIST; |
| 2308 | } |
| 2309 | #endif |
| 2310 | |
| 2311 | retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, |
| 2312 | SD_RSP_TYPE_R1, NULL, 0); |
| 2313 | if (retval != STATUS_SUCCESS) |
| 2314 | TRACE_RET(chip, STATUS_FAIL); |
| 2315 | |
| 2316 | retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0, |
| 2317 | SD_RSP_TYPE_R1, NULL, 0); |
| 2318 | if (retval != STATUS_SUCCESS) |
| 2319 | TRACE_RET(chip, STATUS_FAIL); |
| 2320 | |
| 2321 | if (support_1v8) { |
| 2322 | retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, |
| 2323 | SD_RSP_TYPE_R1, NULL, 0); |
| 2324 | if (retval != STATUS_SUCCESS) |
| 2325 | TRACE_RET(chip, STATUS_FAIL); |
| 2326 | |
| 2327 | retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, |
| 2328 | SD_RSP_TYPE_R1, NULL, 0); |
| 2329 | if (retval != STATUS_SUCCESS) |
| 2330 | TRACE_RET(chip, STATUS_FAIL); |
| 2331 | |
| 2332 | switch_bus_width = SD_BUS_WIDTH_4; |
| 2333 | } else { |
| 2334 | switch_bus_width = SD_BUS_WIDTH_1; |
| 2335 | } |
| 2336 | |
| 2337 | retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, |
| 2338 | NULL, 0); |
| 2339 | if (retval != STATUS_SUCCESS) |
| 2340 | TRACE_RET(chip, STATUS_FAIL); |
| 2341 | |
| 2342 | retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); |
| 2343 | if (retval != STATUS_SUCCESS) |
| 2344 | TRACE_RET(chip, STATUS_FAIL); |
| 2345 | |
| 2346 | if (!(sd_card->raw_csd[4] & 0x40)) |
| 2347 | sd_dont_switch = 1; |
| 2348 | |
| 2349 | if (!sd_dont_switch) { |
| 2350 | if (sd20_mode) { |
| 2351 | /* Set sd_switch_fail here, because we needn't |
| 2352 | * switch to UHS mode |
| 2353 | */ |
| 2354 | sd_card->sd_switch_fail = SDR104_SUPPORT_MASK | |
| 2355 | DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK; |
| 2356 | } |
| 2357 | |
| 2358 | /* Check the card whether follow SD1.1 spec or higher */ |
| 2359 | retval = sd_check_spec(chip, switch_bus_width); |
| 2360 | if (retval == STATUS_SUCCESS) { |
| 2361 | retval = sd_switch_function(chip, switch_bus_width); |
| 2362 | if (retval != STATUS_SUCCESS) { |
| 2363 | sd_init_power(chip); |
| 2364 | sd_dont_switch = 1; |
| 2365 | try_sdio = 0; |
| 2366 | |
| 2367 | goto Switch_Fail; |
| 2368 | } |
| 2369 | } else { |
| 2370 | if (support_1v8) { |
| 2371 | sd_init_power(chip); |
| 2372 | sd_dont_switch = 1; |
| 2373 | try_sdio = 0; |
| 2374 | |
| 2375 | goto Switch_Fail; |
| 2376 | } |
| 2377 | } |
| 2378 | } |
| 2379 | |
| 2380 | if (!support_1v8) { |
| 2381 | retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, |
| 2382 | SD_RSP_TYPE_R1, NULL, 0); |
| 2383 | if (retval != STATUS_SUCCESS) |
| 2384 | TRACE_RET(chip, STATUS_FAIL); |
| 2385 | |
| 2386 | retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, |
| 2387 | SD_RSP_TYPE_R1, NULL, 0); |
| 2388 | if (retval != STATUS_SUCCESS) |
| 2389 | TRACE_RET(chip, STATUS_FAIL); |
| 2390 | } |
| 2391 | |
| 2392 | #ifdef SUPPORT_SD_LOCK |
| 2393 | sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE; |
| 2394 | #endif |
| 2395 | |
| 2396 | if (!sd20_mode && CHK_SD30_SPEED(sd_card)) { |
| 2397 | int read_lba0 = 1; |
| 2398 | |
| 2399 | RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, |
| 2400 | chip->sd30_drive_sel_1v8); |
| 2401 | |
| 2402 | retval = sd_set_init_para(chip); |
| 2403 | if (retval != STATUS_SUCCESS) |
| 2404 | TRACE_RET(chip, STATUS_FAIL); |
| 2405 | |
| 2406 | if (CHK_SD_DDR50(sd_card)) |
| 2407 | retval = sd_ddr_tuning(chip); |
| 2408 | else |
| 2409 | retval = sd_sdr_tuning(chip); |
| 2410 | |
| 2411 | if (retval != STATUS_SUCCESS) { |
| 2412 | if (sd20_mode) { |
| 2413 | TRACE_RET(chip, STATUS_FAIL); |
| 2414 | } else { |
| 2415 | retval = sd_init_power(chip); |
| 2416 | if (retval != STATUS_SUCCESS) |
| 2417 | TRACE_RET(chip, STATUS_FAIL); |
| 2418 | |
| 2419 | try_sdio = 0; |
| 2420 | sd20_mode = 1; |
| 2421 | goto Switch_Fail; |
| 2422 | } |
| 2423 | } |
| 2424 | |
| 2425 | sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, |
| 2426 | SD_RSP_TYPE_R1, NULL, 0); |
| 2427 | |
| 2428 | if (CHK_SD_DDR50(sd_card)) { |
| 2429 | retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); |
| 2430 | if (retval != STATUS_SUCCESS) |
| 2431 | read_lba0 = 0; |
| 2432 | } |
| 2433 | |
| 2434 | if (read_lba0) { |
| 2435 | retval = sd_read_lba0(chip); |
| 2436 | if (retval != STATUS_SUCCESS) { |
| 2437 | if (sd20_mode) { |
| 2438 | TRACE_RET(chip, STATUS_FAIL); |
| 2439 | } else { |
| 2440 | retval = sd_init_power(chip); |
| 2441 | if (retval != STATUS_SUCCESS) |
| 2442 | TRACE_RET(chip, STATUS_FAIL); |
| 2443 | |
| 2444 | try_sdio = 0; |
| 2445 | sd20_mode = 1; |
| 2446 | goto Switch_Fail; |
| 2447 | } |
| 2448 | } |
| 2449 | } |
| 2450 | } |
| 2451 | |
| 2452 | retval = sd_check_wp_state(chip); |
| 2453 | if (retval != STATUS_SUCCESS) |
| 2454 | TRACE_RET(chip, STATUS_FAIL); |
| 2455 | |
| 2456 | chip->card_bus_width[chip->card2lun[SD_CARD]] = 4; |
| 2457 | |
| 2458 | #ifdef SUPPORT_SD_LOCK |
| 2459 | if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) { |
| 2460 | RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02); |
| 2461 | RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00); |
| 2462 | } |
| 2463 | #endif |
| 2464 | |
| 2465 | return STATUS_SUCCESS; |
| 2466 | } |
| 2467 | |
| 2468 | |
| 2469 | static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width) |
| 2470 | { |
| 2471 | struct sd_info *sd_card = &(chip->sd_card); |
| 2472 | int retval; |
| 2473 | u8 buf[8] = {0}, bus_width, *ptr; |
| 2474 | u16 byte_cnt; |
| 2475 | int len; |
| 2476 | |
| 2477 | retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL, |
| 2478 | 0); |
| 2479 | if (retval != STATUS_SUCCESS) |
| 2480 | TRACE_RET(chip, SWITCH_FAIL); |
| 2481 | |
| 2482 | if (width == MMC_8BIT_BUS) { |
| 2483 | buf[0] = 0x55; |
| 2484 | buf[1] = 0xAA; |
| 2485 | len = 8; |
| 2486 | byte_cnt = 8; |
| 2487 | bus_width = SD_BUS_WIDTH_8; |
| 2488 | } else { |
| 2489 | buf[0] = 0x5A; |
| 2490 | len = 4; |
| 2491 | byte_cnt = 4; |
| 2492 | bus_width = SD_BUS_WIDTH_4; |
| 2493 | } |
| 2494 | |
| 2495 | retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0x02); |
| 2496 | if (retval != STATUS_SUCCESS) |
| 2497 | TRACE_RET(chip, SWITCH_ERR); |
| 2498 | |
| 2499 | retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3, |
| 2500 | NULL, 0, byte_cnt, 1, bus_width, buf, len, 100); |
| 2501 | if (retval != STATUS_SUCCESS) { |
| 2502 | rtsx_clear_sd_error(chip); |
| 2503 | rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0); |
| 2504 | TRACE_RET(chip, SWITCH_ERR); |
| 2505 | } |
| 2506 | |
| 2507 | retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0); |
| 2508 | if (retval != STATUS_SUCCESS) |
| 2509 | TRACE_RET(chip, SWITCH_ERR); |
| 2510 | |
| 2511 | RTSX_DEBUGP("SD/MMC CMD %d\n", BUSTEST_R); |
| 2512 | |
| 2513 | rtsx_init_cmd(chip); |
| 2514 | |
| 2515 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R); |
| 2516 | |
| 2517 | if (width == MMC_8BIT_BUS) |
| 2518 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, |
| 2519 | 0xFF, 0x08); |
| 2520 | else |
| 2521 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, |
| 2522 | 0xFF, 0x04); |
| 2523 | |
| 2524 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1); |
| 2525 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0); |
| 2526 | |
| 2527 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, |
| 2528 | SD_CALCULATE_CRC7 | SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END| |
| 2529 | SD_CHECK_CRC7 | SD_RSP_LEN_6); |
| 2530 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, |
| 2531 | PINGPONG_BUFFER); |
| 2532 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, |
| 2533 | SD_TM_NORMAL_READ | SD_TRANSFER_START); |
| 2534 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, |
| 2535 | SD_TRANSFER_END); |
| 2536 | |
| 2537 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0); |
| 2538 | if (width == MMC_8BIT_BUS) |
| 2539 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0); |
| 2540 | |
| 2541 | retval = rtsx_send_cmd(chip, SD_CARD, 100); |
| 2542 | if (retval < 0) { |
| 2543 | rtsx_clear_sd_error(chip); |
| 2544 | TRACE_RET(chip, SWITCH_ERR); |
| 2545 | } |
| 2546 | |
| 2547 | ptr = rtsx_get_cmd_data(chip) + 1; |
| 2548 | |
| 2549 | if (width == MMC_8BIT_BUS) { |
| 2550 | RTSX_DEBUGP("BUSTEST_R [8bits]: 0x%02x 0x%02x\n", ptr[0], |
| 2551 | ptr[1]); |
| 2552 | if ((ptr[0] == 0xAA) && (ptr[1] == 0x55)) { |
| 2553 | u8 rsp[5]; |
| 2554 | u32 arg; |
| 2555 | |
| 2556 | if (CHK_MMC_DDR52(sd_card)) |
| 2557 | arg = 0x03B70600; |
| 2558 | else |
| 2559 | arg = 0x03B70200; |
| 2560 | |
| 2561 | retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, |
| 2562 | SD_RSP_TYPE_R1b, rsp, 5); |
| 2563 | if ((retval == STATUS_SUCCESS) && |
| 2564 | !(rsp[4] & MMC_SWITCH_ERR)) |
| 2565 | return SWITCH_SUCCESS; |
| 2566 | } |
| 2567 | } else { |
| 2568 | RTSX_DEBUGP("BUSTEST_R [4bits]: 0x%02x\n", ptr[0]); |
| 2569 | if (ptr[0] == 0xA5) { |
| 2570 | u8 rsp[5]; |
| 2571 | u32 arg; |
| 2572 | |
| 2573 | if (CHK_MMC_DDR52(sd_card)) |
| 2574 | arg = 0x03B70500; |
| 2575 | else |
| 2576 | arg = 0x03B70100; |
| 2577 | |
| 2578 | retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, |
| 2579 | SD_RSP_TYPE_R1b, rsp, 5); |
| 2580 | if ((retval == STATUS_SUCCESS) && |
| 2581 | !(rsp[4] & MMC_SWITCH_ERR)) |
| 2582 | return SWITCH_SUCCESS; |
| 2583 | } |
| 2584 | } |
| 2585 | |
| 2586 | TRACE_RET(chip, SWITCH_FAIL); |
| 2587 | } |
| 2588 | |
| 2589 | |
| 2590 | static int mmc_switch_timing_bus(struct rtsx_chip *chip, int switch_ddr) |
| 2591 | { |
| 2592 | struct sd_info *sd_card = &(chip->sd_card); |
| 2593 | int retval; |
| 2594 | u8 *ptr, card_type, card_type_mask = 0; |
| 2595 | |
| 2596 | CLR_MMC_HS(sd_card); |
| 2597 | |
| 2598 | RTSX_DEBUGP("SD/MMC CMD %d\n", SEND_EXT_CSD); |
| 2599 | |
| 2600 | rtsx_init_cmd(chip); |
| 2601 | |
| 2602 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, |
| 2603 | 0x40 | SEND_EXT_CSD); |
| 2604 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0); |
| 2605 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0); |
| 2606 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0); |
| 2607 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0); |
| 2608 | |
| 2609 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0); |
| 2610 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2); |
| 2611 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1); |
| 2612 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0); |
| 2613 | |
| 2614 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, |
| 2615 | SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END| |
| 2616 | SD_CHECK_CRC7 | SD_RSP_LEN_6); |
| 2617 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, |
| 2618 | PINGPONG_BUFFER); |
| 2619 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, |
| 2620 | SD_TM_NORMAL_READ | SD_TRANSFER_START); |
| 2621 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, |
| 2622 | SD_TRANSFER_END); |
| 2623 | |
| 2624 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0); |
| 2625 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0); |
| 2626 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0); |
| 2627 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0); |
| 2628 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0); |
| 2629 | |
| 2630 | retval = rtsx_send_cmd(chip, SD_CARD, 1000); |
| 2631 | if (retval < 0) { |
| 2632 | if (retval == -ETIMEDOUT) { |
| 2633 | rtsx_clear_sd_error(chip); |
| 2634 | sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, |
| 2635 | SD_RSP_TYPE_R1, NULL, 0); |
| 2636 | } |
| 2637 | TRACE_RET(chip, STATUS_FAIL); |
| 2638 | } |
| 2639 | |
| 2640 | ptr = rtsx_get_cmd_data(chip); |
| 2641 | if (ptr[0] & SD_TRANSFER_ERR) { |
| 2642 | sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, |
| 2643 | SD_RSP_TYPE_R1, NULL, 0); |
| 2644 | TRACE_RET(chip, STATUS_FAIL); |
| 2645 | } |
| 2646 | |
| 2647 | if (CHK_MMC_SECTOR_MODE(sd_card)) { |
| 2648 | sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) | |
| 2649 | ((u32)ptr[3] << 8) | ((u32)ptr[2]); |
| 2650 | } |
| 2651 | |
| 2652 | card_type_mask = 0x03; |
| 2653 | card_type = ptr[1] & card_type_mask; |
| 2654 | if (card_type) { |
| 2655 | u8 rsp[5]; |
| 2656 | |
| 2657 | if (card_type & 0x04) { |
| 2658 | if (switch_ddr) |
| 2659 | SET_MMC_DDR52(sd_card); |
| 2660 | else |
| 2661 | SET_MMC_52M(sd_card); |
| 2662 | } else if (card_type & 0x02) { |
| 2663 | SET_MMC_52M(sd_card); |
| 2664 | } else { |
| 2665 | SET_MMC_26M(sd_card); |
| 2666 | } |
| 2667 | |
| 2668 | retval = sd_send_cmd_get_rsp(chip, SWITCH, |
| 2669 | 0x03B90100, SD_RSP_TYPE_R1b, rsp, 5); |
| 2670 | if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR)) |
| 2671 | CLR_MMC_HS(sd_card); |
| 2672 | } |
| 2673 | |
| 2674 | sd_choose_proper_clock(chip); |
| 2675 | retval = switch_clock(chip, sd_card->sd_clock); |
| 2676 | if (retval != STATUS_SUCCESS) |
| 2677 | TRACE_RET(chip, STATUS_FAIL); |
| 2678 | |
| 2679 | /* Test Bus Procedure */ |
| 2680 | retval = mmc_test_switch_bus(chip, MMC_8BIT_BUS); |
| 2681 | if (retval == SWITCH_SUCCESS) { |
| 2682 | SET_MMC_8BIT(sd_card); |
| 2683 | chip->card_bus_width[chip->card2lun[SD_CARD]] = 8; |
| 2684 | #ifdef SUPPORT_SD_LOCK |
| 2685 | sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE; |
| 2686 | #endif |
| 2687 | } else if (retval == SWITCH_FAIL) { |
| 2688 | retval = mmc_test_switch_bus(chip, MMC_4BIT_BUS); |
| 2689 | if (retval == SWITCH_SUCCESS) { |
| 2690 | SET_MMC_4BIT(sd_card); |
| 2691 | chip->card_bus_width[chip->card2lun[SD_CARD]] = 4; |
| 2692 | #ifdef SUPPORT_SD_LOCK |
| 2693 | sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE; |
| 2694 | #endif |
| 2695 | } else if (retval == SWITCH_FAIL) { |
| 2696 | CLR_MMC_8BIT(sd_card); |
| 2697 | CLR_MMC_4BIT(sd_card); |
| 2698 | } else { |
| 2699 | TRACE_RET(chip, STATUS_FAIL); |
| 2700 | } |
| 2701 | } else { |
| 2702 | TRACE_RET(chip, STATUS_FAIL); |
| 2703 | } |
| 2704 | |
| 2705 | return STATUS_SUCCESS; |
| 2706 | } |
| 2707 | |
| 2708 | |
| 2709 | static int reset_mmc(struct rtsx_chip *chip) |
| 2710 | { |
| 2711 | struct sd_info *sd_card = &(chip->sd_card); |
| 2712 | int retval, i = 0, j = 0, k = 0; |
| 2713 | int switch_ddr = 1; |
| 2714 | u8 rsp[16]; |
| 2715 | u8 spec_ver = 0; |
| 2716 | u32 temp; |
| 2717 | |
| 2718 | #ifdef SUPPORT_SD_LOCK |
| 2719 | if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) |
| 2720 | goto MMC_UNLOCK_ENTRY; |
| 2721 | #endif |
| 2722 | |
| 2723 | Switch_Fail: |
| 2724 | retval = sd_prepare_reset(chip); |
| 2725 | if (retval != STATUS_SUCCESS) |
| 2726 | TRACE_RET(chip, retval); |
| 2727 | |
| 2728 | SET_MMC(sd_card); |
| 2729 | |
| 2730 | RTY_MMC_RST: |
| 2731 | retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, |
| 2732 | NULL, 0); |
| 2733 | if (retval != STATUS_SUCCESS) |
| 2734 | TRACE_RET(chip, STATUS_FAIL); |
| 2735 | |
| 2736 | do { |
| 2737 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { |
| 2738 | sd_set_err_code(chip, SD_NO_CARD); |
| 2739 | TRACE_RET(chip, STATUS_FAIL); |
| 2740 | } |
| 2741 | |
| 2742 | retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND, |
| 2743 | (SUPPORT_VOLTAGE | 0x40000000), |
| 2744 | SD_RSP_TYPE_R3, rsp, 5); |
| 2745 | if (retval != STATUS_SUCCESS) { |
| 2746 | if (sd_check_err_code(chip, SD_BUSY) || |
| 2747 | sd_check_err_code(chip, SD_TO_ERR)) { |
| 2748 | k++; |
| 2749 | if (k < 20) { |
| 2750 | sd_clr_err_code(chip); |
| 2751 | goto RTY_MMC_RST; |
| 2752 | } else { |
| 2753 | TRACE_RET(chip, STATUS_FAIL); |
| 2754 | } |
| 2755 | } else { |
| 2756 | j++; |
| 2757 | if (j < 100) { |
| 2758 | sd_clr_err_code(chip); |
| 2759 | goto RTY_MMC_RST; |
| 2760 | } else { |
| 2761 | TRACE_RET(chip, STATUS_FAIL); |
| 2762 | } |
| 2763 | } |
| 2764 | } |
| 2765 | |
| 2766 | wait_timeout(20); |
| 2767 | i++; |
| 2768 | } while (!(rsp[1] & 0x80) && (i < 255)); |
| 2769 | |
| 2770 | if (i == 255) |
| 2771 | TRACE_RET(chip, STATUS_FAIL); |
| 2772 | |
| 2773 | if ((rsp[1] & 0x60) == 0x40) |
| 2774 | SET_MMC_SECTOR_MODE(sd_card); |
| 2775 | else |
| 2776 | CLR_MMC_SECTOR_MODE(sd_card); |
| 2777 | |
| 2778 | retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, |
| 2779 | NULL, 0); |
| 2780 | if (retval != STATUS_SUCCESS) |
| 2781 | TRACE_RET(chip, STATUS_FAIL); |
| 2782 | |
| 2783 | sd_card->sd_addr = 0x00100000; |
| 2784 | retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr, |
| 2785 | SD_RSP_TYPE_R6, rsp, 5); |
| 2786 | if (retval != STATUS_SUCCESS) |
| 2787 | TRACE_RET(chip, STATUS_FAIL); |
| 2788 | |
| 2789 | retval = sd_check_csd(chip, 1); |
| 2790 | if (retval != STATUS_SUCCESS) |
| 2791 | TRACE_RET(chip, STATUS_FAIL); |
| 2792 | |
| 2793 | spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2; |
| 2794 | |
| 2795 | retval = sd_select_card(chip, 1); |
| 2796 | if (retval != STATUS_SUCCESS) |
| 2797 | TRACE_RET(chip, STATUS_FAIL); |
| 2798 | |
| 2799 | retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, |
| 2800 | NULL, 0); |
| 2801 | if (retval != STATUS_SUCCESS) |
| 2802 | TRACE_RET(chip, STATUS_FAIL); |
| 2803 | |
| 2804 | #ifdef SUPPORT_SD_LOCK |
| 2805 | MMC_UNLOCK_ENTRY: |
| 2806 | retval = sd_update_lock_status(chip); |
| 2807 | if (retval != STATUS_SUCCESS) |
| 2808 | TRACE_RET(chip, STATUS_FAIL); |
| 2809 | #endif |
| 2810 | |
| 2811 | retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); |
| 2812 | if (retval != STATUS_SUCCESS) |
| 2813 | TRACE_RET(chip, STATUS_FAIL); |
| 2814 | |
| 2815 | chip->card_bus_width[chip->card2lun[SD_CARD]] = 1; |
| 2816 | |
| 2817 | if (!sd_card->mmc_dont_switch_bus) { |
| 2818 | if (spec_ver == 4) { |
| 2819 | /* MMC 4.x Cards */ |
| 2820 | retval = mmc_switch_timing_bus(chip, switch_ddr); |
| 2821 | if (retval != STATUS_SUCCESS) { |
| 2822 | retval = sd_init_power(chip); |
| 2823 | if (retval != STATUS_SUCCESS) |
| 2824 | TRACE_RET(chip, STATUS_FAIL); |
| 2825 | sd_card->mmc_dont_switch_bus = 1; |
| 2826 | TRACE_GOTO(chip, Switch_Fail); |
| 2827 | } |
| 2828 | } |
| 2829 | |
| 2830 | if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0)) |
| 2831 | TRACE_RET(chip, STATUS_FAIL); |
| 2832 | |
| 2833 | if (switch_ddr && CHK_MMC_DDR52(sd_card)) { |
| 2834 | retval = sd_set_init_para(chip); |
| 2835 | if (retval != STATUS_SUCCESS) |
| 2836 | TRACE_RET(chip, STATUS_FAIL); |
| 2837 | |
| 2838 | retval = mmc_ddr_tuning(chip); |
| 2839 | if (retval != STATUS_SUCCESS) { |
| 2840 | retval = sd_init_power(chip); |
| 2841 | if (retval != STATUS_SUCCESS) |
| 2842 | TRACE_RET(chip, STATUS_FAIL); |
| 2843 | |
| 2844 | switch_ddr = 0; |
| 2845 | TRACE_GOTO(chip, Switch_Fail); |
| 2846 | } |
| 2847 | |
| 2848 | retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); |
| 2849 | if (retval == STATUS_SUCCESS) { |
| 2850 | retval = sd_read_lba0(chip); |
| 2851 | if (retval != STATUS_SUCCESS) { |
| 2852 | retval = sd_init_power(chip); |
| 2853 | if (retval != STATUS_SUCCESS) |
| 2854 | TRACE_RET(chip, STATUS_FAIL); |
| 2855 | |
| 2856 | switch_ddr = 0; |
| 2857 | TRACE_GOTO(chip, Switch_Fail); |
| 2858 | } |
| 2859 | } |
| 2860 | } |
| 2861 | } |
| 2862 | |
| 2863 | #ifdef SUPPORT_SD_LOCK |
| 2864 | if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) { |
| 2865 | RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02); |
| 2866 | RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00); |
| 2867 | } |
| 2868 | #endif |
| 2869 | |
| 2870 | temp = rtsx_readl(chip, RTSX_BIPR); |
| 2871 | if (temp & SD_WRITE_PROTECT) |
| 2872 | chip->card_wp |= SD_CARD; |
| 2873 | |
| 2874 | return STATUS_SUCCESS; |
| 2875 | } |
| 2876 | |
| 2877 | int reset_sd_card(struct rtsx_chip *chip) |
| 2878 | { |
| 2879 | struct sd_info *sd_card = &(chip->sd_card); |
| 2880 | int retval; |
| 2881 | |
| 2882 | sd_init_reg_addr(chip); |
| 2883 | |
| 2884 | memset(sd_card, 0, sizeof(struct sd_info)); |
| 2885 | chip->capacity[chip->card2lun[SD_CARD]] = 0; |
| 2886 | |
| 2887 | retval = enable_card_clock(chip, SD_CARD); |
| 2888 | if (retval != STATUS_SUCCESS) |
| 2889 | TRACE_RET(chip, STATUS_FAIL); |
| 2890 | |
| 2891 | if (chip->ignore_sd && CHK_SDIO_EXIST(chip) && |
| 2892 | !CHK_SDIO_IGNORED(chip)) { |
| 2893 | if (chip->asic_code) { |
| 2894 | retval = sd_pull_ctl_enable(chip); |
| 2895 | if (retval != STATUS_SUCCESS) |
| 2896 | TRACE_RET(chip, STATUS_FAIL); |
| 2897 | } else { |
| 2898 | retval = rtsx_write_register(chip, FPGA_PULL_CTL, |
| 2899 | FPGA_SD_PULL_CTL_BIT | 0x20, 0); |
| 2900 | if (retval != STATUS_SUCCESS) |
| 2901 | TRACE_RET(chip, STATUS_FAIL); |
| 2902 | } |
| 2903 | retval = card_share_mode(chip, SD_CARD); |
| 2904 | if (retval != STATUS_SUCCESS) |
| 2905 | TRACE_RET(chip, STATUS_FAIL); |
| 2906 | |
| 2907 | chip->sd_io = 1; |
| 2908 | TRACE_RET(chip, STATUS_FAIL); |
| 2909 | } |
| 2910 | |
| 2911 | retval = sd_init_power(chip); |
| 2912 | if (retval != STATUS_SUCCESS) |
| 2913 | TRACE_RET(chip, STATUS_FAIL); |
| 2914 | |
| 2915 | if (chip->sd_ctl & RESET_MMC_FIRST) { |
| 2916 | retval = reset_mmc(chip); |
| 2917 | if (retval != STATUS_SUCCESS) { |
| 2918 | if (sd_check_err_code(chip, SD_NO_CARD)) |
| 2919 | TRACE_RET(chip, STATUS_FAIL); |
| 2920 | |
| 2921 | retval = reset_sd(chip); |
| 2922 | if (retval != STATUS_SUCCESS) |
| 2923 | TRACE_RET(chip, STATUS_FAIL); |
| 2924 | } |
| 2925 | } else { |
| 2926 | retval = reset_sd(chip); |
| 2927 | if (retval != STATUS_SUCCESS) { |
| 2928 | if (sd_check_err_code(chip, SD_NO_CARD)) |
| 2929 | TRACE_RET(chip, STATUS_FAIL); |
| 2930 | |
| 2931 | if (chip->sd_io) { |
| 2932 | TRACE_RET(chip, STATUS_FAIL); |
| 2933 | } else { |
| 2934 | retval = reset_mmc(chip); |
| 2935 | if (retval != STATUS_SUCCESS) |
| 2936 | TRACE_RET(chip, STATUS_FAIL); |
| 2937 | } |
| 2938 | } |
| 2939 | } |
| 2940 | |
| 2941 | retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); |
| 2942 | if (retval != STATUS_SUCCESS) |
| 2943 | TRACE_RET(chip, STATUS_FAIL); |
| 2944 | |
| 2945 | RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0); |
| 2946 | RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2); |
| 2947 | |
| 2948 | chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity; |
| 2949 | |
| 2950 | retval = sd_set_init_para(chip); |
| 2951 | if (retval != STATUS_SUCCESS) |
| 2952 | TRACE_RET(chip, STATUS_FAIL); |
| 2953 | |
| 2954 | RTSX_DEBUGP("sd_card->sd_type = 0x%x\n", sd_card->sd_type); |
| 2955 | |
| 2956 | return STATUS_SUCCESS; |
| 2957 | } |
| 2958 | |
| 2959 | static int reset_mmc_only(struct rtsx_chip *chip) |
| 2960 | { |
| 2961 | struct sd_info *sd_card = &(chip->sd_card); |
| 2962 | int retval; |
| 2963 | |
| 2964 | sd_card->sd_type = 0; |
| 2965 | sd_card->seq_mode = 0; |
| 2966 | sd_card->sd_data_buf_ready = 0; |
| 2967 | sd_card->capacity = 0; |
| 2968 | sd_card->sd_switch_fail = 0; |
| 2969 | |
| 2970 | #ifdef SUPPORT_SD_LOCK |
| 2971 | sd_card->sd_lock_status = 0; |
| 2972 | sd_card->sd_erase_status = 0; |
| 2973 | #endif |
| 2974 | |
| 2975 | chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0; |
| 2976 | |
| 2977 | retval = enable_card_clock(chip, SD_CARD); |
| 2978 | if (retval != STATUS_SUCCESS) |
| 2979 | TRACE_RET(chip, STATUS_FAIL); |
| 2980 | |
| 2981 | retval = sd_init_power(chip); |
| 2982 | if (retval != STATUS_SUCCESS) |
| 2983 | TRACE_RET(chip, STATUS_FAIL); |
| 2984 | |
| 2985 | retval = reset_mmc(chip); |
| 2986 | if (retval != STATUS_SUCCESS) |
| 2987 | TRACE_RET(chip, STATUS_FAIL); |
| 2988 | |
| 2989 | retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); |
| 2990 | if (retval != STATUS_SUCCESS) |
| 2991 | TRACE_RET(chip, STATUS_FAIL); |
| 2992 | |
| 2993 | RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0); |
| 2994 | RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2); |
| 2995 | |
| 2996 | chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity; |
| 2997 | |
| 2998 | retval = sd_set_init_para(chip); |
| 2999 | if (retval != STATUS_SUCCESS) |
| 3000 | TRACE_RET(chip, STATUS_FAIL); |
| 3001 | |
| 3002 | RTSX_DEBUGP("In reset_mmc_only, sd_card->sd_type = 0x%x\n", |
| 3003 | sd_card->sd_type); |
| 3004 | |
| 3005 | return STATUS_SUCCESS; |
| 3006 | } |
| 3007 | |
| 3008 | #define WAIT_DATA_READY_RTY_CNT 255 |
| 3009 | |
| 3010 | static int wait_data_buf_ready(struct rtsx_chip *chip) |
| 3011 | { |
| 3012 | struct sd_info *sd_card = &(chip->sd_card); |
| 3013 | int i, retval; |
| 3014 | |
| 3015 | for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) { |
| 3016 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { |
| 3017 | sd_set_err_code(chip, SD_NO_CARD); |
| 3018 | TRACE_RET(chip, STATUS_FAIL); |
| 3019 | } |
| 3020 | |
| 3021 | sd_card->sd_data_buf_ready = 0; |
| 3022 | |
| 3023 | retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, |
| 3024 | sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); |
| 3025 | if (retval != STATUS_SUCCESS) |
| 3026 | TRACE_RET(chip, STATUS_FAIL); |
| 3027 | |
| 3028 | if (sd_card->sd_data_buf_ready) { |
| 3029 | return sd_send_cmd_get_rsp(chip, SEND_STATUS, |
| 3030 | sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); |
| 3031 | } |
| 3032 | } |
| 3033 | |
| 3034 | sd_set_err_code(chip, SD_TO_ERR); |
| 3035 | |
| 3036 | TRACE_RET(chip, STATUS_FAIL); |
| 3037 | } |
| 3038 | |
| 3039 | void sd_stop_seq_mode(struct rtsx_chip *chip) |
| 3040 | { |
| 3041 | struct sd_info *sd_card = &(chip->sd_card); |
| 3042 | int retval; |
| 3043 | |
| 3044 | if (sd_card->seq_mode) { |
| 3045 | retval = sd_switch_clock(chip); |
| 3046 | if (retval != STATUS_SUCCESS) |
| 3047 | return; |
| 3048 | |
| 3049 | retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, |
| 3050 | SD_RSP_TYPE_R1b, NULL, 0); |
| 3051 | if (retval != STATUS_SUCCESS) |
| 3052 | sd_set_err_code(chip, SD_STS_ERR); |
| 3053 | |
| 3054 | retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); |
| 3055 | if (retval != STATUS_SUCCESS) |
| 3056 | sd_set_err_code(chip, SD_STS_ERR); |
| 3057 | |
| 3058 | sd_card->seq_mode = 0; |
| 3059 | |
| 3060 | rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); |
| 3061 | } |
| 3062 | } |
| 3063 | |
| 3064 | static inline int sd_auto_tune_clock(struct rtsx_chip *chip) |
| 3065 | { |
| 3066 | struct sd_info *sd_card = &(chip->sd_card); |
| 3067 | int retval; |
| 3068 | |
| 3069 | if (chip->asic_code) { |
| 3070 | if (sd_card->sd_clock > 30) |
| 3071 | sd_card->sd_clock -= 20; |
| 3072 | } else { |
| 3073 | switch (sd_card->sd_clock) { |
| 3074 | case CLK_200: |
| 3075 | sd_card->sd_clock = CLK_150; |
| 3076 | break; |
| 3077 | |
| 3078 | case CLK_150: |
| 3079 | sd_card->sd_clock = CLK_120; |
| 3080 | break; |
| 3081 | |
| 3082 | case CLK_120: |
| 3083 | sd_card->sd_clock = CLK_100; |
| 3084 | break; |
| 3085 | |
| 3086 | case CLK_100: |
| 3087 | sd_card->sd_clock = CLK_80; |
| 3088 | break; |
| 3089 | |
| 3090 | case CLK_80: |
| 3091 | sd_card->sd_clock = CLK_60; |
| 3092 | break; |
| 3093 | |
| 3094 | case CLK_60: |
| 3095 | sd_card->sd_clock = CLK_50; |
| 3096 | break; |
| 3097 | |
| 3098 | default: |
| 3099 | break; |
| 3100 | } |
| 3101 | } |
| 3102 | |
| 3103 | retval = sd_switch_clock(chip); |
| 3104 | if (retval != STATUS_SUCCESS) |
| 3105 | TRACE_RET(chip, STATUS_FAIL); |
| 3106 | |
| 3107 | return STATUS_SUCCESS; |
| 3108 | } |
| 3109 | |
| 3110 | int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, |
| 3111 | u16 sector_cnt) |
| 3112 | { |
| 3113 | struct sd_info *sd_card = &(chip->sd_card); |
| 3114 | u32 data_addr; |
| 3115 | u8 cfg2; |
| 3116 | int retval; |
| 3117 | |
| 3118 | if (srb->sc_data_direction == DMA_FROM_DEVICE) { |
| 3119 | RTSX_DEBUGP("sd_rw: Read %d %s from 0x%x\n", sector_cnt, |
| 3120 | (sector_cnt > 1) ? "sectors" : "sector", start_sector); |
| 3121 | } else { |
| 3122 | RTSX_DEBUGP("sd_rw: Write %d %s to 0x%x\n", sector_cnt, |
| 3123 | (sector_cnt > 1) ? "sectors" : "sector", start_sector); |
| 3124 | } |
| 3125 | |
| 3126 | sd_card->cleanup_counter = 0; |
| 3127 | |
| 3128 | if (!(chip->card_ready & SD_CARD)) { |
| 3129 | sd_card->seq_mode = 0; |
| 3130 | |
| 3131 | retval = reset_sd_card(chip); |
| 3132 | if (retval == STATUS_SUCCESS) { |
| 3133 | chip->card_ready |= SD_CARD; |
| 3134 | chip->card_fail &= ~SD_CARD; |
| 3135 | } else { |
| 3136 | chip->card_ready &= ~SD_CARD; |
| 3137 | chip->card_fail |= SD_CARD; |
| 3138 | chip->capacity[chip->card2lun[SD_CARD]] = 0; |
| 3139 | chip->rw_need_retry = 1; |
| 3140 | TRACE_RET(chip, STATUS_FAIL); |
| 3141 | } |
| 3142 | } |
| 3143 | |
| 3144 | if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card)) |
| 3145 | data_addr = start_sector << 9; |
| 3146 | else |
| 3147 | data_addr = start_sector; |
| 3148 | |
| 3149 | sd_clr_err_code(chip); |
| 3150 | |
| 3151 | retval = sd_switch_clock(chip); |
| 3152 | if (retval != STATUS_SUCCESS) { |
| 3153 | sd_set_err_code(chip, SD_IO_ERR); |
| 3154 | TRACE_GOTO(chip, RW_FAIL); |
| 3155 | } |
| 3156 | |
| 3157 | if (sd_card->seq_mode && |
| 3158 | ((sd_card->pre_dir != srb->sc_data_direction) || |
| 3159 | ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) != |
| 3160 | start_sector))) { |
| 3161 | if ((sd_card->pre_sec_cnt < 0x80) |
| 3162 | && (sd_card->pre_dir == DMA_FROM_DEVICE) |
| 3163 | && !CHK_SD30_SPEED(sd_card) |
| 3164 | && !CHK_SD_HS(sd_card) |
| 3165 | && !CHK_MMC_HS(sd_card)) { |
| 3166 | sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, |
| 3167 | SD_RSP_TYPE_R1, NULL, 0); |
| 3168 | } |
| 3169 | |
| 3170 | retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, |
| 3171 | 0, SD_RSP_TYPE_R1b, NULL, 0); |
| 3172 | if (retval != STATUS_SUCCESS) { |
| 3173 | chip->rw_need_retry = 1; |
| 3174 | sd_set_err_code(chip, SD_STS_ERR); |
| 3175 | TRACE_GOTO(chip, RW_FAIL); |
| 3176 | } |
| 3177 | |
| 3178 | sd_card->seq_mode = 0; |
| 3179 | |
| 3180 | retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); |
| 3181 | if (retval != STATUS_SUCCESS) { |
| 3182 | sd_set_err_code(chip, SD_IO_ERR); |
| 3183 | TRACE_GOTO(chip, RW_FAIL); |
| 3184 | } |
| 3185 | |
| 3186 | if ((sd_card->pre_sec_cnt < 0x80) |
| 3187 | && !CHK_SD30_SPEED(sd_card) |
| 3188 | && !CHK_SD_HS(sd_card) |
| 3189 | && !CHK_MMC_HS(sd_card)) { |
| 3190 | sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, |
| 3191 | SD_RSP_TYPE_R1, NULL, 0); |
| 3192 | } |
| 3193 | } |
| 3194 | |
| 3195 | rtsx_init_cmd(chip); |
| 3196 | |
| 3197 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00); |
| 3198 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02); |
| 3199 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, |
| 3200 | (u8)sector_cnt); |
| 3201 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, |
| 3202 | (u8)(sector_cnt >> 8)); |
| 3203 | |
| 3204 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); |
| 3205 | |
| 3206 | if (CHK_MMC_8BIT(sd_card)) |
| 3207 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, |
| 3208 | 0x03, SD_BUS_WIDTH_8); |
| 3209 | else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card)) |
| 3210 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, |
| 3211 | 0x03, SD_BUS_WIDTH_4); |
| 3212 | else |
| 3213 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, |
| 3214 | 0x03, SD_BUS_WIDTH_1); |
| 3215 | |
| 3216 | if (sd_card->seq_mode) { |
| 3217 | cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16| |
| 3218 | SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | |
| 3219 | SD_RSP_LEN_0; |
| 3220 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2); |
| 3221 | |
| 3222 | trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, |
| 3223 | DMA_512); |
| 3224 | |
| 3225 | if (srb->sc_data_direction == DMA_FROM_DEVICE) { |
| 3226 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, |
| 3227 | SD_TM_AUTO_READ_3 | SD_TRANSFER_START); |
| 3228 | } else { |
| 3229 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, |
| 3230 | SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); |
| 3231 | } |
| 3232 | |
| 3233 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, |
| 3234 | SD_TRANSFER_END, SD_TRANSFER_END); |
| 3235 | |
| 3236 | rtsx_send_cmd_no_wait(chip); |
| 3237 | } else { |
| 3238 | if (srb->sc_data_direction == DMA_FROM_DEVICE) { |
| 3239 | RTSX_DEBUGP("SD/MMC CMD %d\n", READ_MULTIPLE_BLOCK); |
| 3240 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, |
| 3241 | 0x40 | READ_MULTIPLE_BLOCK); |
| 3242 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, |
| 3243 | (u8)(data_addr >> 24)); |
| 3244 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, |
| 3245 | (u8)(data_addr >> 16)); |
| 3246 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, |
| 3247 | (u8)(data_addr >> 8)); |
| 3248 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, |
| 3249 | (u8)data_addr); |
| 3250 | |
| 3251 | cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | |
| 3252 | SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | |
| 3253 | SD_RSP_LEN_6; |
| 3254 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, |
| 3255 | cfg2); |
| 3256 | |
| 3257 | trans_dma_enable(srb->sc_data_direction, chip, |
| 3258 | sector_cnt * 512, DMA_512); |
| 3259 | |
| 3260 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, |
| 3261 | SD_TM_AUTO_READ_2 | SD_TRANSFER_START); |
| 3262 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, |
| 3263 | SD_TRANSFER_END, SD_TRANSFER_END); |
| 3264 | |
| 3265 | rtsx_send_cmd_no_wait(chip); |
| 3266 | } else { |
| 3267 | retval = rtsx_send_cmd(chip, SD_CARD, 50); |
| 3268 | if (retval < 0) { |
| 3269 | rtsx_clear_sd_error(chip); |
| 3270 | |
| 3271 | chip->rw_need_retry = 1; |
| 3272 | sd_set_err_code(chip, SD_TO_ERR); |
| 3273 | TRACE_GOTO(chip, RW_FAIL); |
| 3274 | } |
| 3275 | |
| 3276 | retval = wait_data_buf_ready(chip); |
| 3277 | if (retval != STATUS_SUCCESS) { |
| 3278 | chip->rw_need_retry = 1; |
| 3279 | sd_set_err_code(chip, SD_TO_ERR); |
| 3280 | TRACE_GOTO(chip, RW_FAIL); |
| 3281 | } |
| 3282 | |
| 3283 | retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK, |
| 3284 | data_addr, SD_RSP_TYPE_R1, NULL, 0); |
| 3285 | if (retval != STATUS_SUCCESS) { |
| 3286 | chip->rw_need_retry = 1; |
| 3287 | TRACE_GOTO(chip, RW_FAIL); |
| 3288 | } |
| 3289 | |
| 3290 | rtsx_init_cmd(chip); |
| 3291 | |
| 3292 | cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | |
| 3293 | SD_NO_WAIT_BUSY_END | |
| 3294 | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; |
| 3295 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, |
| 3296 | cfg2); |
| 3297 | |
| 3298 | trans_dma_enable(srb->sc_data_direction, chip, |
| 3299 | sector_cnt * 512, DMA_512); |
| 3300 | |
| 3301 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, |
| 3302 | SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); |
| 3303 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, |
| 3304 | SD_TRANSFER_END, SD_TRANSFER_END); |
| 3305 | |
| 3306 | rtsx_send_cmd_no_wait(chip); |
| 3307 | } |
| 3308 | |
| 3309 | sd_card->seq_mode = 1; |
| 3310 | } |
| 3311 | |
| 3312 | retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), |
| 3313 | scsi_bufflen(srb), scsi_sg_count(srb), |
| 3314 | srb->sc_data_direction, chip->sd_timeout); |
| 3315 | if (retval < 0) { |
| 3316 | u8 stat = 0; |
| 3317 | int err; |
| 3318 | |
| 3319 | sd_card->seq_mode = 0; |
| 3320 | |
| 3321 | if (retval == -ETIMEDOUT) |
| 3322 | err = STATUS_TIMEDOUT; |
| 3323 | else |
| 3324 | err = STATUS_FAIL; |
| 3325 | |
| 3326 | rtsx_read_register(chip, REG_SD_STAT1, &stat); |
| 3327 | rtsx_clear_sd_error(chip); |
| 3328 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { |
| 3329 | chip->rw_need_retry = 0; |
| 3330 | RTSX_DEBUGP("No card exist, exit sd_rw\n"); |
| 3331 | TRACE_RET(chip, STATUS_FAIL); |
| 3332 | } |
| 3333 | |
| 3334 | chip->rw_need_retry = 1; |
| 3335 | |
| 3336 | retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, |
| 3337 | SD_RSP_TYPE_R1b, NULL, 0); |
| 3338 | if (retval != STATUS_SUCCESS) { |
| 3339 | sd_set_err_code(chip, SD_STS_ERR); |
| 3340 | TRACE_GOTO(chip, RW_FAIL); |
| 3341 | } |
| 3342 | |
| 3343 | if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) { |
| 3344 | RTSX_DEBUGP("SD CRC error, tune clock!\n"); |
| 3345 | sd_set_err_code(chip, SD_CRC_ERR); |
| 3346 | TRACE_GOTO(chip, RW_FAIL); |
| 3347 | } |
| 3348 | |
| 3349 | if (err == STATUS_TIMEDOUT) { |
| 3350 | sd_set_err_code(chip, SD_TO_ERR); |
| 3351 | TRACE_GOTO(chip, RW_FAIL); |
| 3352 | } |
| 3353 | |
| 3354 | TRACE_RET(chip, err); |
| 3355 | } |
| 3356 | |
| 3357 | sd_card->pre_sec_addr = start_sector; |
| 3358 | sd_card->pre_sec_cnt = sector_cnt; |
| 3359 | sd_card->pre_dir = srb->sc_data_direction; |
| 3360 | |
| 3361 | return STATUS_SUCCESS; |
| 3362 | |
| 3363 | RW_FAIL: |
| 3364 | sd_card->seq_mode = 0; |
| 3365 | |
| 3366 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { |
| 3367 | chip->rw_need_retry = 0; |
| 3368 | RTSX_DEBUGP("No card exist, exit sd_rw\n"); |
| 3369 | TRACE_RET(chip, STATUS_FAIL); |
| 3370 | } |
| 3371 | |
| 3372 | if (sd_check_err_code(chip, SD_CRC_ERR)) { |
| 3373 | if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) { |
| 3374 | sd_card->mmc_dont_switch_bus = 1; |
| 3375 | reset_mmc_only(chip); |
| 3376 | sd_card->mmc_dont_switch_bus = 0; |
| 3377 | } else { |
| 3378 | sd_card->need_retune = 1; |
| 3379 | sd_auto_tune_clock(chip); |
| 3380 | } |
| 3381 | } else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) { |
| 3382 | retval = reset_sd_card(chip); |
| 3383 | if (retval != STATUS_SUCCESS) { |
| 3384 | chip->card_ready &= ~SD_CARD; |
| 3385 | chip->card_fail |= SD_CARD; |
| 3386 | chip->capacity[chip->card2lun[SD_CARD]] = 0; |
| 3387 | } |
| 3388 | } |
| 3389 | |
| 3390 | TRACE_RET(chip, STATUS_FAIL); |
| 3391 | } |
| 3392 | |
| 3393 | #ifdef SUPPORT_CPRM |
| 3394 | int soft_reset_sd_card(struct rtsx_chip *chip) |
| 3395 | { |
| 3396 | return reset_sd(chip); |
| 3397 | } |
| 3398 | |
| 3399 | int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, |
| 3400 | u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, int special_check) |
| 3401 | { |
| 3402 | int retval; |
| 3403 | int timeout = 100; |
| 3404 | u16 reg_addr; |
| 3405 | u8 *ptr; |
| 3406 | int stat_idx = 0; |
| 3407 | int rty_cnt = 0; |
| 3408 | |
| 3409 | RTSX_DEBUGP("EXT SD/MMC CMD %d\n", cmd_idx); |
| 3410 | |
| 3411 | if (rsp_type == SD_RSP_TYPE_R1b) |
| 3412 | timeout = 3000; |
| 3413 | |
| 3414 | RTY_SEND_CMD: |
| 3415 | |
| 3416 | rtsx_init_cmd(chip); |
| 3417 | |
| 3418 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx); |
| 3419 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24)); |
| 3420 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16)); |
| 3421 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8)); |
| 3422 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg); |
| 3423 | |
| 3424 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type); |
| 3425 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, |
| 3426 | 0x01, PINGPONG_BUFFER); |
| 3427 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, |
| 3428 | 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); |
| 3429 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, |
| 3430 | SD_TRANSFER_END); |
| 3431 | |
| 3432 | if (rsp_type == SD_RSP_TYPE_R2) { |
| 3433 | for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; |
| 3434 | reg_addr++) |
| 3435 | rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); |
| 3436 | |
| 3437 | stat_idx = 17; |
| 3438 | } else if (rsp_type != SD_RSP_TYPE_R0) { |
| 3439 | for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; |
| 3440 | reg_addr++) |
| 3441 | rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); |
| 3442 | |
| 3443 | stat_idx = 6; |
| 3444 | } |
| 3445 | rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0); |
| 3446 | |
| 3447 | rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0); |
| 3448 | |
| 3449 | retval = rtsx_send_cmd(chip, SD_CARD, timeout); |
| 3450 | if (retval < 0) { |
| 3451 | if (retval == -ETIMEDOUT) { |
| 3452 | rtsx_clear_sd_error(chip); |
| 3453 | |
| 3454 | if (rsp_type & SD_WAIT_BUSY_END) { |
| 3455 | retval = sd_check_data0_status(chip); |
| 3456 | if (retval != STATUS_SUCCESS) |
| 3457 | TRACE_RET(chip, retval); |
| 3458 | } else { |
| 3459 | sd_set_err_code(chip, SD_TO_ERR); |
| 3460 | } |
| 3461 | } |
| 3462 | TRACE_RET(chip, STATUS_FAIL); |
| 3463 | } |
| 3464 | |
| 3465 | if (rsp_type == SD_RSP_TYPE_R0) |
| 3466 | return STATUS_SUCCESS; |
| 3467 | |
| 3468 | ptr = rtsx_get_cmd_data(chip) + 1; |
| 3469 | |
| 3470 | if ((ptr[0] & 0xC0) != 0) { |
| 3471 | sd_set_err_code(chip, SD_STS_ERR); |
| 3472 | TRACE_RET(chip, STATUS_FAIL); |
| 3473 | } |
| 3474 | |
| 3475 | if (!(rsp_type & SD_NO_CHECK_CRC7)) { |
| 3476 | if (ptr[stat_idx] & SD_CRC7_ERR) { |
| 3477 | if (cmd_idx == WRITE_MULTIPLE_BLOCK) { |
| 3478 | sd_set_err_code(chip, SD_CRC_ERR); |
| 3479 | TRACE_RET(chip, STATUS_FAIL); |
| 3480 | } |
| 3481 | if (rty_cnt < SD_MAX_RETRY_COUNT) { |
| 3482 | wait_timeout(20); |
| 3483 | rty_cnt++; |
| 3484 | goto RTY_SEND_CMD; |
| 3485 | } else { |
| 3486 | sd_set_err_code(chip, SD_CRC_ERR); |
| 3487 | TRACE_RET(chip, STATUS_FAIL); |
| 3488 | } |
| 3489 | } |
| 3490 | } |
| 3491 | |
| 3492 | if ((cmd_idx == SELECT_CARD) || (cmd_idx == APP_CMD) || |
| 3493 | (cmd_idx == SEND_STATUS) || (cmd_idx == STOP_TRANSMISSION)) { |
| 3494 | if ((cmd_idx != STOP_TRANSMISSION) && (special_check == 0)) { |
| 3495 | if (ptr[1] & 0x80) |
| 3496 | TRACE_RET(chip, STATUS_FAIL); |
| 3497 | } |
| 3498 | #ifdef SUPPORT_SD_LOCK |
| 3499 | if (ptr[1] & 0x7D) |
| 3500 | #else |
| 3501 | if (ptr[1] & 0x7F) |
| 3502 | #endif |
| 3503 | { |
| 3504 | TRACE_RET(chip, STATUS_FAIL); |
| 3505 | } |
| 3506 | if (ptr[2] & 0xF8) |
| 3507 | TRACE_RET(chip, STATUS_FAIL); |
| 3508 | |
| 3509 | if (cmd_idx == SELECT_CARD) { |
| 3510 | if (rsp_type == SD_RSP_TYPE_R2) { |
| 3511 | if ((ptr[3] & 0x1E) != 0x04) |
| 3512 | TRACE_RET(chip, STATUS_FAIL); |
| 3513 | |
| 3514 | } else if (rsp_type == SD_RSP_TYPE_R0) { |
| 3515 | if ((ptr[3] & 0x1E) != 0x03) |
| 3516 | TRACE_RET(chip, STATUS_FAIL); |
| 3517 | } |
| 3518 | } |
| 3519 | } |
| 3520 | |
| 3521 | if (rsp && rsp_len) |
| 3522 | memcpy(rsp, ptr, rsp_len); |
| 3523 | |
| 3524 | return STATUS_SUCCESS; |
| 3525 | } |
| 3526 | |
| 3527 | int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type) |
| 3528 | { |
| 3529 | int retval, rsp_len; |
| 3530 | u16 reg_addr; |
| 3531 | |
| 3532 | if (rsp_type == SD_RSP_TYPE_R0) |
| 3533 | return STATUS_SUCCESS; |
| 3534 | |
| 3535 | rtsx_init_cmd(chip); |
| 3536 | |
| 3537 | if (rsp_type == SD_RSP_TYPE_R2) { |
| 3538 | for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; |
| 3539 | reg_addr++) |
| 3540 | rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0); |
| 3541 | |
| 3542 | rsp_len = 17; |
| 3543 | } else if (rsp_type != SD_RSP_TYPE_R0) { |
| 3544 | for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; |
| 3545 | reg_addr++) |
| 3546 | rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0); |
| 3547 | |
| 3548 | rsp_len = 6; |
| 3549 | } |
| 3550 | rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0); |
| 3551 | |
| 3552 | retval = rtsx_send_cmd(chip, SD_CARD, 100); |
| 3553 | if (retval != STATUS_SUCCESS) |
| 3554 | TRACE_RET(chip, STATUS_FAIL); |
| 3555 | |
| 3556 | if (rsp) { |
| 3557 | int min_len = (rsp_len < len) ? rsp_len : len; |
| 3558 | |
| 3559 | memcpy(rsp, rtsx_get_cmd_data(chip), min_len); |
| 3560 | |
| 3561 | RTSX_DEBUGP("min_len = %d\n", min_len); |
| 3562 | RTSX_DEBUGP("Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n", |
| 3563 | rsp[0], rsp[1], rsp[2], rsp[3]); |
| 3564 | } |
| 3565 | |
| 3566 | return STATUS_SUCCESS; |
| 3567 | } |
| 3568 | |
| 3569 | int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip) |
| 3570 | { |
| 3571 | struct sd_info *sd_card = &(chip->sd_card); |
| 3572 | unsigned int lun = SCSI_LUN(srb); |
| 3573 | int len; |
| 3574 | u8 buf[18] = { |
| 3575 | 0x00, |
| 3576 | 0x00, |
| 3577 | 0x00, |
| 3578 | 0x0E, |
| 3579 | 0x00, |
| 3580 | 0x00, |
| 3581 | 0x00, |
| 3582 | 0x00, |
| 3583 | 0x53, |
| 3584 | 0x44, |
| 3585 | 0x20, |
| 3586 | 0x43, |
| 3587 | 0x61, |
| 3588 | 0x72, |
| 3589 | 0x64, |
| 3590 | 0x00, |
| 3591 | 0x00, |
| 3592 | 0x00, |
| 3593 | }; |
| 3594 | |
| 3595 | sd_card->pre_cmd_err = 0; |
| 3596 | |
| 3597 | if (!(CHK_BIT(chip->lun_mc, lun))) { |
| 3598 | SET_BIT(chip->lun_mc, lun); |
| 3599 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); |
| 3600 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3601 | } |
| 3602 | |
| 3603 | if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) || |
| 3604 | (0x20 != srb->cmnd[4]) || (0x43 != srb->cmnd[5]) || |
| 3605 | (0x61 != srb->cmnd[6]) || (0x72 != srb->cmnd[7]) || |
| 3606 | (0x64 != srb->cmnd[8])) { |
| 3607 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); |
| 3608 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3609 | } |
| 3610 | |
| 3611 | switch (srb->cmnd[1] & 0x0F) { |
| 3612 | case 0: |
| 3613 | sd_card->sd_pass_thru_en = 0; |
| 3614 | break; |
| 3615 | |
| 3616 | case 1: |
| 3617 | sd_card->sd_pass_thru_en = 1; |
| 3618 | break; |
| 3619 | |
| 3620 | default: |
| 3621 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); |
| 3622 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3623 | } |
| 3624 | |
| 3625 | buf[5] = (1 == CHK_SD(sd_card)) ? 0x01 : 0x02; |
| 3626 | if (chip->card_wp & SD_CARD) |
| 3627 | buf[5] |= 0x80; |
| 3628 | |
| 3629 | buf[6] = (u8)(sd_card->sd_addr >> 16); |
| 3630 | buf[7] = (u8)(sd_card->sd_addr >> 24); |
| 3631 | |
| 3632 | buf[15] = chip->max_lun; |
| 3633 | |
| 3634 | len = min_t(int, 18, scsi_bufflen(srb)); |
| 3635 | rtsx_stor_set_xfer_buf(buf, len, srb); |
| 3636 | |
| 3637 | return TRANSPORT_GOOD; |
| 3638 | } |
| 3639 | |
| 3640 | static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type, |
| 3641 | int *rsp_len) |
| 3642 | { |
| 3643 | if (!rsp_type || !rsp_len) |
| 3644 | return STATUS_FAIL; |
| 3645 | |
| 3646 | switch (srb->cmnd[10]) { |
| 3647 | case 0x03: |
| 3648 | *rsp_type = SD_RSP_TYPE_R0; |
| 3649 | *rsp_len = 0; |
| 3650 | break; |
| 3651 | |
| 3652 | case 0x04: |
| 3653 | *rsp_type = SD_RSP_TYPE_R1; |
| 3654 | *rsp_len = 6; |
| 3655 | break; |
| 3656 | |
| 3657 | case 0x05: |
| 3658 | *rsp_type = SD_RSP_TYPE_R1b; |
| 3659 | *rsp_len = 6; |
| 3660 | break; |
| 3661 | |
| 3662 | case 0x06: |
| 3663 | *rsp_type = SD_RSP_TYPE_R2; |
| 3664 | *rsp_len = 17; |
| 3665 | break; |
| 3666 | |
| 3667 | case 0x07: |
| 3668 | *rsp_type = SD_RSP_TYPE_R3; |
| 3669 | *rsp_len = 6; |
| 3670 | break; |
| 3671 | |
| 3672 | default: |
| 3673 | return STATUS_FAIL; |
| 3674 | } |
| 3675 | |
| 3676 | return STATUS_SUCCESS; |
| 3677 | } |
| 3678 | |
| 3679 | int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip) |
| 3680 | { |
| 3681 | struct sd_info *sd_card = &(chip->sd_card); |
| 3682 | unsigned int lun = SCSI_LUN(srb); |
| 3683 | int retval, rsp_len; |
| 3684 | u8 cmd_idx, rsp_type; |
| 3685 | u8 standby = 0, acmd = 0; |
| 3686 | u32 arg; |
| 3687 | |
| 3688 | if (!sd_card->sd_pass_thru_en) { |
| 3689 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); |
| 3690 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3691 | } |
| 3692 | |
| 3693 | retval = sd_switch_clock(chip); |
| 3694 | if (retval != STATUS_SUCCESS) |
| 3695 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3696 | |
| 3697 | if (sd_card->pre_cmd_err) { |
| 3698 | sd_card->pre_cmd_err = 0; |
| 3699 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); |
| 3700 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3701 | } |
| 3702 | |
| 3703 | cmd_idx = srb->cmnd[2] & 0x3F; |
| 3704 | if (srb->cmnd[1] & 0x02) |
| 3705 | standby = 1; |
| 3706 | |
| 3707 | if (srb->cmnd[1] & 0x01) |
| 3708 | acmd = 1; |
| 3709 | |
| 3710 | arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) | |
| 3711 | ((u32)srb->cmnd[5] << 8) | srb->cmnd[6]; |
| 3712 | |
| 3713 | retval = get_rsp_type(srb, &rsp_type, &rsp_len); |
| 3714 | if (retval != STATUS_SUCCESS) { |
| 3715 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); |
| 3716 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3717 | } |
| 3718 | sd_card->last_rsp_type = rsp_type; |
| 3719 | |
| 3720 | retval = sd_switch_clock(chip); |
| 3721 | if (retval != STATUS_SUCCESS) |
| 3722 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3723 | |
| 3724 | #ifdef SUPPORT_SD_LOCK |
| 3725 | if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) { |
| 3726 | if (CHK_MMC_8BIT(sd_card)) { |
| 3727 | retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, |
| 3728 | SD_BUS_WIDTH_8); |
| 3729 | if (retval != STATUS_SUCCESS) |
| 3730 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3731 | |
| 3732 | } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) { |
| 3733 | retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, |
| 3734 | SD_BUS_WIDTH_4); |
| 3735 | if (retval != STATUS_SUCCESS) |
| 3736 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3737 | } |
| 3738 | } |
| 3739 | #else |
| 3740 | retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4); |
| 3741 | if (retval != STATUS_SUCCESS) |
| 3742 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3743 | #endif |
| 3744 | |
| 3745 | if (standby) { |
| 3746 | retval = sd_select_card(chip, 0); |
| 3747 | if (retval != STATUS_SUCCESS) |
| 3748 | TRACE_GOTO(chip, SD_Execute_Cmd_Failed); |
| 3749 | } |
| 3750 | |
| 3751 | if (acmd) { |
| 3752 | retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, |
| 3753 | sd_card->sd_addr, |
| 3754 | SD_RSP_TYPE_R1, NULL, 0, 0); |
| 3755 | if (retval != STATUS_SUCCESS) |
| 3756 | TRACE_GOTO(chip, SD_Execute_Cmd_Failed); |
| 3757 | } |
| 3758 | |
| 3759 | retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type, |
| 3760 | sd_card->rsp, rsp_len, 0); |
| 3761 | if (retval != STATUS_SUCCESS) |
| 3762 | TRACE_GOTO(chip, SD_Execute_Cmd_Failed); |
| 3763 | |
| 3764 | if (standby) { |
| 3765 | retval = sd_select_card(chip, 1); |
| 3766 | if (retval != STATUS_SUCCESS) |
| 3767 | TRACE_GOTO(chip, SD_Execute_Cmd_Failed); |
| 3768 | } |
| 3769 | |
| 3770 | #ifdef SUPPORT_SD_LOCK |
| 3771 | retval = sd_update_lock_status(chip); |
| 3772 | if (retval != STATUS_SUCCESS) |
| 3773 | TRACE_GOTO(chip, SD_Execute_Cmd_Failed); |
| 3774 | #endif |
| 3775 | |
| 3776 | scsi_set_resid(srb, 0); |
| 3777 | return TRANSPORT_GOOD; |
| 3778 | |
| 3779 | SD_Execute_Cmd_Failed: |
| 3780 | sd_card->pre_cmd_err = 1; |
| 3781 | set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); |
| 3782 | release_sd_card(chip); |
| 3783 | do_reset_sd_card(chip); |
| 3784 | if (!(chip->card_ready & SD_CARD)) |
| 3785 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); |
| 3786 | |
| 3787 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3788 | } |
| 3789 | |
| 3790 | int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip) |
| 3791 | { |
| 3792 | struct sd_info *sd_card = &(chip->sd_card); |
| 3793 | unsigned int lun = SCSI_LUN(srb); |
| 3794 | int retval, rsp_len, i; |
| 3795 | int cmd13_checkbit = 0, read_err = 0; |
| 3796 | u8 cmd_idx, rsp_type, bus_width; |
| 3797 | u8 send_cmd12 = 0, standby = 0, acmd = 0; |
| 3798 | u32 data_len; |
| 3799 | |
| 3800 | if (!sd_card->sd_pass_thru_en) { |
| 3801 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); |
| 3802 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3803 | } |
| 3804 | |
| 3805 | if (sd_card->pre_cmd_err) { |
| 3806 | sd_card->pre_cmd_err = 0; |
| 3807 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); |
| 3808 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3809 | } |
| 3810 | |
| 3811 | retval = sd_switch_clock(chip); |
| 3812 | if (retval != STATUS_SUCCESS) |
| 3813 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3814 | |
| 3815 | cmd_idx = srb->cmnd[2] & 0x3F; |
| 3816 | if (srb->cmnd[1] & 0x04) |
| 3817 | send_cmd12 = 1; |
| 3818 | |
| 3819 | if (srb->cmnd[1] & 0x02) |
| 3820 | standby = 1; |
| 3821 | |
| 3822 | if (srb->cmnd[1] & 0x01) |
| 3823 | acmd = 1; |
| 3824 | |
| 3825 | data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] |
| 3826 | << 8) | srb->cmnd[9]; |
| 3827 | |
| 3828 | retval = get_rsp_type(srb, &rsp_type, &rsp_len); |
| 3829 | if (retval != STATUS_SUCCESS) { |
| 3830 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); |
| 3831 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3832 | } |
| 3833 | sd_card->last_rsp_type = rsp_type; |
| 3834 | |
| 3835 | retval = sd_switch_clock(chip); |
| 3836 | if (retval != STATUS_SUCCESS) |
| 3837 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 3838 | |
| 3839 | #ifdef SUPPORT_SD_LOCK |
| 3840 | if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) { |
| 3841 | if (CHK_MMC_8BIT(sd_card)) |
| 3842 | bus_width = SD_BUS_WIDTH_8; |
| 3843 | else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) |
| 3844 | bus_width = SD_BUS_WIDTH_4; |
| 3845 | else |
| 3846 | bus_width = SD_BUS_WIDTH_1; |
| 3847 | } else { |
| 3848 | bus_width = SD_BUS_WIDTH_4; |
| 3849 | } |
| 3850 | RTSX_DEBUGP("bus_width = %d\n", bus_width); |
| 3851 | #else |
| 3852 | bus_width = SD_BUS_WIDTH_4; |
| 3853 | #endif |
| 3854 | |
| 3855 | if (data_len < 512) { |
| 3856 | retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len, |
| 3857 | SD_RSP_TYPE_R1, NULL, 0, 0); |
| 3858 | if (retval != STATUS_SUCCESS) |
| 3859 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); |
| 3860 | } |
| 3861 | |
| 3862 | if (standby) { |
| 3863 | retval = sd_select_card(chip, 0); |
| 3864 | if (retval != STATUS_SUCCESS) |
| 3865 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); |
| 3866 | } |
| 3867 | |
| 3868 | if (acmd) { |
| 3869 | retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, |
| 3870 | sd_card->sd_addr, |
| 3871 | SD_RSP_TYPE_R1, NULL, 0, 0); |
| 3872 | if (retval != STATUS_SUCCESS) |
| 3873 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); |
| 3874 | } |
| 3875 | |
| 3876 | if (data_len <= 512) { |
| 3877 | int min_len; |
| 3878 | u8 *buf; |
| 3879 | u16 byte_cnt, blk_cnt; |
| 3880 | u8 cmd[5]; |
| 3881 | |
| 3882 | byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9]; |
| 3883 | blk_cnt = 1; |
| 3884 | |
| 3885 | cmd[0] = 0x40 | cmd_idx; |
| 3886 | cmd[1] = srb->cmnd[3]; |
| 3887 | cmd[2] = srb->cmnd[4]; |
| 3888 | cmd[3] = srb->cmnd[5]; |
| 3889 | cmd[4] = srb->cmnd[6]; |
| 3890 | |
| 3891 | buf = kmalloc(data_len, GFP_KERNEL); |
| 3892 | if (buf == NULL) |
| 3893 | TRACE_RET(chip, TRANSPORT_ERROR); |
| 3894 | |
| 3895 | retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt, |
| 3896 | blk_cnt, bus_width, buf, data_len, 2000); |
| 3897 | if (retval != STATUS_SUCCESS) { |
| 3898 | read_err = 1; |
| 3899 | kfree(buf); |
| 3900 | rtsx_clear_sd_error(chip); |
| 3901 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); |
| 3902 | } |
| 3903 | |
| 3904 | min_len = min(data_len, scsi_bufflen(srb)); |
| 3905 | rtsx_stor_set_xfer_buf(buf, min_len, srb); |
| 3906 | |
| 3907 | kfree(buf); |
| 3908 | } else if (!(data_len & 0x1FF)) { |
| 3909 | rtsx_init_cmd(chip); |
| 3910 | |
| 3911 | trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512); |
| 3912 | |
| 3913 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, |
| 3914 | 0x02); |
| 3915 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, |
| 3916 | 0x00); |
| 3917 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, |
| 3918 | 0xFF, (srb->cmnd[7] & 0xFE) >> 1); |
| 3919 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, |
| 3920 | 0xFF, (u8)((data_len & 0x0001FE00) >> 9)); |
| 3921 | |
| 3922 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, |
| 3923 | 0x40 | cmd_idx); |
| 3924 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, |
| 3925 | srb->cmnd[3]); |
| 3926 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, |
| 3927 | srb->cmnd[4]); |
| 3928 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, |
| 3929 | srb->cmnd[5]); |
| 3930 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, |
| 3931 | srb->cmnd[6]); |
| 3932 | |
| 3933 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width); |
| 3934 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type); |
| 3935 | |
| 3936 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, |
| 3937 | 0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START); |
| 3938 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, |
| 3939 | SD_TRANSFER_END, SD_TRANSFER_END); |
| 3940 | |
| 3941 | rtsx_send_cmd_no_wait(chip); |
| 3942 | |
| 3943 | retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), |
| 3944 | scsi_bufflen(srb), scsi_sg_count(srb), |
| 3945 | DMA_FROM_DEVICE, 10000); |
| 3946 | if (retval < 0) { |
| 3947 | read_err = 1; |
| 3948 | rtsx_clear_sd_error(chip); |
| 3949 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); |
| 3950 | } |
| 3951 | |
| 3952 | } else { |
| 3953 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); |
| 3954 | } |
| 3955 | |
| 3956 | retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type); |
| 3957 | if (retval != STATUS_SUCCESS) |
| 3958 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); |
| 3959 | |
| 3960 | if (standby) { |
| 3961 | retval = sd_select_card(chip, 1); |
| 3962 | if (retval != STATUS_SUCCESS) |
| 3963 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); |
| 3964 | } |
| 3965 | |
| 3966 | if (send_cmd12) { |
| 3967 | retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, |
| 3968 | 0, SD_RSP_TYPE_R1b, NULL, 0, 0); |
| 3969 | if (retval != STATUS_SUCCESS) |
| 3970 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); |
| 3971 | } |
| 3972 | |
| 3973 | if (data_len < 512) { |
| 3974 | retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, |
| 3975 | SD_RSP_TYPE_R1, NULL, 0, 0); |
| 3976 | if (retval != STATUS_SUCCESS) |
| 3977 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); |
| 3978 | |
| 3979 | retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02); |
| 3980 | if (retval != STATUS_SUCCESS) |
| 3981 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); |
| 3982 | |
| 3983 | retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00); |
| 3984 | if (retval != STATUS_SUCCESS) |
| 3985 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); |
| 3986 | } |
| 3987 | |
| 3988 | if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) |
| 3989 | cmd13_checkbit = 1; |
| 3990 | |
| 3991 | for (i = 0; i < 3; i++) { |
| 3992 | retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, |
| 3993 | sd_card->sd_addr, |
| 3994 | SD_RSP_TYPE_R1, NULL, 0, |
| 3995 | cmd13_checkbit); |
| 3996 | if (retval == STATUS_SUCCESS) |
| 3997 | break; |
| 3998 | } |
| 3999 | if (retval != STATUS_SUCCESS) |
| 4000 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); |
| 4001 | |
| 4002 | scsi_set_resid(srb, 0); |
| 4003 | return TRANSPORT_GOOD; |
| 4004 | |
| 4005 | SD_Execute_Read_Cmd_Failed: |
| 4006 | sd_card->pre_cmd_err = 1; |
| 4007 | set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); |
| 4008 | if (read_err) |
| 4009 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); |
| 4010 | |
| 4011 | release_sd_card(chip); |
| 4012 | do_reset_sd_card(chip); |
| 4013 | if (!(chip->card_ready & SD_CARD)) |
| 4014 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); |
| 4015 | |
| 4016 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4017 | } |
| 4018 | |
| 4019 | int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip) |
| 4020 | { |
| 4021 | struct sd_info *sd_card = &(chip->sd_card); |
| 4022 | unsigned int lun = SCSI_LUN(srb); |
| 4023 | int retval, rsp_len, i; |
| 4024 | int cmd13_checkbit = 0, write_err = 0; |
| 4025 | u8 cmd_idx, rsp_type; |
| 4026 | u8 send_cmd12 = 0, standby = 0, acmd = 0; |
| 4027 | u32 data_len, arg; |
| 4028 | #ifdef SUPPORT_SD_LOCK |
| 4029 | int lock_cmd_fail = 0; |
| 4030 | u8 sd_lock_state = 0; |
| 4031 | u8 lock_cmd_type = 0; |
| 4032 | #endif |
| 4033 | |
| 4034 | if (!sd_card->sd_pass_thru_en) { |
| 4035 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); |
| 4036 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4037 | } |
| 4038 | |
| 4039 | if (sd_card->pre_cmd_err) { |
| 4040 | sd_card->pre_cmd_err = 0; |
| 4041 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); |
| 4042 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4043 | } |
| 4044 | |
| 4045 | retval = sd_switch_clock(chip); |
| 4046 | if (retval != STATUS_SUCCESS) |
| 4047 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4048 | |
| 4049 | cmd_idx = srb->cmnd[2] & 0x3F; |
| 4050 | if (srb->cmnd[1] & 0x04) |
| 4051 | send_cmd12 = 1; |
| 4052 | |
| 4053 | if (srb->cmnd[1] & 0x02) |
| 4054 | standby = 1; |
| 4055 | |
| 4056 | if (srb->cmnd[1] & 0x01) |
| 4057 | acmd = 1; |
| 4058 | |
| 4059 | data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] |
| 4060 | << 8) | srb->cmnd[9]; |
| 4061 | arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) | |
| 4062 | ((u32)srb->cmnd[5] << 8) | srb->cmnd[6]; |
| 4063 | |
| 4064 | #ifdef SUPPORT_SD_LOCK |
| 4065 | if (cmd_idx == LOCK_UNLOCK) { |
| 4066 | sd_lock_state = sd_card->sd_lock_status; |
| 4067 | sd_lock_state &= SD_LOCKED; |
| 4068 | } |
| 4069 | #endif |
| 4070 | |
| 4071 | retval = get_rsp_type(srb, &rsp_type, &rsp_len); |
| 4072 | if (retval != STATUS_SUCCESS) { |
| 4073 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); |
| 4074 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4075 | } |
| 4076 | sd_card->last_rsp_type = rsp_type; |
| 4077 | |
| 4078 | retval = sd_switch_clock(chip); |
| 4079 | if (retval != STATUS_SUCCESS) |
| 4080 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4081 | |
| 4082 | #ifdef SUPPORT_SD_LOCK |
| 4083 | if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) { |
| 4084 | if (CHK_MMC_8BIT(sd_card)) { |
| 4085 | retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, |
| 4086 | SD_BUS_WIDTH_8); |
| 4087 | if (retval != STATUS_SUCCESS) |
| 4088 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4089 | |
| 4090 | } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) { |
| 4091 | retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, |
| 4092 | SD_BUS_WIDTH_4); |
| 4093 | if (retval != STATUS_SUCCESS) |
| 4094 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4095 | } |
| 4096 | } |
| 4097 | #else |
| 4098 | retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4); |
| 4099 | if (retval != STATUS_SUCCESS) |
| 4100 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4101 | #endif |
| 4102 | |
| 4103 | if (data_len < 512) { |
| 4104 | retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len, |
| 4105 | SD_RSP_TYPE_R1, NULL, 0, 0); |
| 4106 | if (retval != STATUS_SUCCESS) |
| 4107 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4108 | } |
| 4109 | |
| 4110 | if (standby) { |
| 4111 | retval = sd_select_card(chip, 0); |
| 4112 | if (retval != STATUS_SUCCESS) |
| 4113 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4114 | } |
| 4115 | |
| 4116 | if (acmd) { |
| 4117 | retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, |
| 4118 | sd_card->sd_addr, |
| 4119 | SD_RSP_TYPE_R1, NULL, 0, 0); |
| 4120 | if (retval != STATUS_SUCCESS) |
| 4121 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4122 | } |
| 4123 | |
| 4124 | retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type, |
| 4125 | sd_card->rsp, rsp_len, 0); |
| 4126 | if (retval != STATUS_SUCCESS) |
| 4127 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4128 | |
| 4129 | if (data_len <= 512) { |
| 4130 | u16 i; |
| 4131 | u8 *buf; |
| 4132 | |
| 4133 | buf = kmalloc(data_len, GFP_KERNEL); |
| 4134 | if (buf == NULL) |
| 4135 | TRACE_RET(chip, TRANSPORT_ERROR); |
| 4136 | |
| 4137 | rtsx_stor_get_xfer_buf(buf, data_len, srb); |
| 4138 | |
| 4139 | #ifdef SUPPORT_SD_LOCK |
| 4140 | if (cmd_idx == LOCK_UNLOCK) |
| 4141 | lock_cmd_type = buf[0] & 0x0F; |
| 4142 | #endif |
| 4143 | |
| 4144 | if (data_len > 256) { |
| 4145 | rtsx_init_cmd(chip); |
| 4146 | for (i = 0; i < 256; i++) { |
| 4147 | rtsx_add_cmd(chip, WRITE_REG_CMD, |
| 4148 | PPBUF_BASE2 + i, 0xFF, buf[i]); |
| 4149 | } |
| 4150 | retval = rtsx_send_cmd(chip, 0, 250); |
| 4151 | if (retval != STATUS_SUCCESS) { |
| 4152 | kfree(buf); |
| 4153 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4154 | } |
| 4155 | |
| 4156 | rtsx_init_cmd(chip); |
| 4157 | for (i = 256; i < data_len; i++) { |
| 4158 | rtsx_add_cmd(chip, WRITE_REG_CMD, |
| 4159 | PPBUF_BASE2 + i, 0xFF, buf[i]); |
| 4160 | } |
| 4161 | retval = rtsx_send_cmd(chip, 0, 250); |
| 4162 | if (retval != STATUS_SUCCESS) { |
| 4163 | kfree(buf); |
| 4164 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4165 | } |
| 4166 | } else { |
| 4167 | rtsx_init_cmd(chip); |
| 4168 | for (i = 0; i < data_len; i++) { |
| 4169 | rtsx_add_cmd(chip, WRITE_REG_CMD, |
| 4170 | PPBUF_BASE2 + i, 0xFF, buf[i]); |
| 4171 | } |
| 4172 | retval = rtsx_send_cmd(chip, 0, 250); |
| 4173 | if (retval != STATUS_SUCCESS) { |
| 4174 | kfree(buf); |
| 4175 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4176 | } |
| 4177 | } |
| 4178 | |
| 4179 | kfree(buf); |
| 4180 | |
| 4181 | rtsx_init_cmd(chip); |
| 4182 | |
| 4183 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, |
| 4184 | srb->cmnd[8] & 0x03); |
| 4185 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, |
| 4186 | srb->cmnd[9]); |
| 4187 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, |
| 4188 | 0x00); |
| 4189 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, |
| 4190 | 0x01); |
| 4191 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, |
| 4192 | PINGPONG_BUFFER); |
| 4193 | |
| 4194 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, |
| 4195 | SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); |
| 4196 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, |
| 4197 | SD_TRANSFER_END, SD_TRANSFER_END); |
| 4198 | |
| 4199 | retval = rtsx_send_cmd(chip, SD_CARD, 250); |
| 4200 | } else if (!(data_len & 0x1FF)) { |
| 4201 | rtsx_init_cmd(chip); |
| 4202 | |
| 4203 | trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512); |
| 4204 | |
| 4205 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, |
| 4206 | 0x02); |
| 4207 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, |
| 4208 | 0x00); |
| 4209 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, |
| 4210 | 0xFF, (srb->cmnd[7] & 0xFE) >> 1); |
| 4211 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, |
| 4212 | 0xFF, (u8)((data_len & 0x0001FE00) >> 9)); |
| 4213 | |
| 4214 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, |
| 4215 | SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); |
| 4216 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, |
| 4217 | SD_TRANSFER_END, SD_TRANSFER_END); |
| 4218 | |
| 4219 | rtsx_send_cmd_no_wait(chip); |
| 4220 | |
| 4221 | retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), |
| 4222 | scsi_bufflen(srb), scsi_sg_count(srb), |
| 4223 | DMA_TO_DEVICE, 10000); |
| 4224 | |
| 4225 | } else { |
| 4226 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4227 | } |
| 4228 | |
| 4229 | if (retval < 0) { |
| 4230 | write_err = 1; |
| 4231 | rtsx_clear_sd_error(chip); |
| 4232 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4233 | } |
| 4234 | |
| 4235 | #ifdef SUPPORT_SD_LOCK |
| 4236 | if (cmd_idx == LOCK_UNLOCK) { |
| 4237 | if (lock_cmd_type == SD_ERASE) { |
| 4238 | sd_card->sd_erase_status = SD_UNDER_ERASING; |
| 4239 | scsi_set_resid(srb, 0); |
| 4240 | return TRANSPORT_GOOD; |
| 4241 | } |
| 4242 | |
| 4243 | rtsx_init_cmd(chip); |
| 4244 | rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02); |
| 4245 | |
| 4246 | rtsx_send_cmd(chip, SD_CARD, 250); |
| 4247 | |
| 4248 | retval = sd_update_lock_status(chip); |
| 4249 | if (retval != STATUS_SUCCESS) { |
| 4250 | RTSX_DEBUGP("Lock command fail!\n"); |
| 4251 | lock_cmd_fail = 1; |
| 4252 | } |
| 4253 | } |
| 4254 | #endif /* SUPPORT_SD_LOCK */ |
| 4255 | |
| 4256 | if (standby) { |
| 4257 | retval = sd_select_card(chip, 1); |
| 4258 | if (retval != STATUS_SUCCESS) |
| 4259 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4260 | } |
| 4261 | |
| 4262 | if (send_cmd12) { |
| 4263 | retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, |
| 4264 | 0, SD_RSP_TYPE_R1b, NULL, 0, 0); |
| 4265 | if (retval != STATUS_SUCCESS) |
| 4266 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4267 | } |
| 4268 | |
| 4269 | if (data_len < 512) { |
| 4270 | retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, |
| 4271 | SD_RSP_TYPE_R1, NULL, 0, 0); |
| 4272 | if (retval != STATUS_SUCCESS) |
| 4273 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4274 | |
| 4275 | retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02); |
| 4276 | if (retval != STATUS_SUCCESS) |
| 4277 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4278 | |
| 4279 | rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00); |
| 4280 | if (retval != STATUS_SUCCESS) |
| 4281 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4282 | } |
| 4283 | |
| 4284 | if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) |
| 4285 | cmd13_checkbit = 1; |
| 4286 | |
| 4287 | for (i = 0; i < 3; i++) { |
| 4288 | retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, |
| 4289 | sd_card->sd_addr, |
| 4290 | SD_RSP_TYPE_R1, NULL, 0, |
| 4291 | cmd13_checkbit); |
| 4292 | if (retval == STATUS_SUCCESS) |
| 4293 | break; |
| 4294 | } |
| 4295 | if (retval != STATUS_SUCCESS) |
| 4296 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4297 | |
| 4298 | #ifdef SUPPORT_SD_LOCK |
| 4299 | if (cmd_idx == LOCK_UNLOCK) { |
| 4300 | if (!lock_cmd_fail) { |
| 4301 | RTSX_DEBUGP("lock_cmd_type = 0x%x\n", lock_cmd_type); |
| 4302 | if (lock_cmd_type & SD_CLR_PWD) |
| 4303 | sd_card->sd_lock_status &= ~SD_PWD_EXIST; |
| 4304 | |
| 4305 | if (lock_cmd_type & SD_SET_PWD) |
| 4306 | sd_card->sd_lock_status |= SD_PWD_EXIST; |
| 4307 | } |
| 4308 | |
| 4309 | RTSX_DEBUGP("sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n", |
| 4310 | sd_lock_state, sd_card->sd_lock_status); |
| 4311 | if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) { |
| 4312 | sd_card->sd_lock_notify = 1; |
| 4313 | if (sd_lock_state) { |
| 4314 | if (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) { |
| 4315 | sd_card->sd_lock_status |= ( |
| 4316 | SD_UNLOCK_POW_ON | SD_SDR_RST); |
| 4317 | if (CHK_SD(sd_card)) { |
| 4318 | retval = reset_sd(chip); |
| 4319 | if (retval != STATUS_SUCCESS) { |
| 4320 | sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST); |
| 4321 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); |
| 4322 | } |
| 4323 | } |
| 4324 | |
| 4325 | sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST); |
| 4326 | } |
| 4327 | } |
| 4328 | } |
| 4329 | } |
| 4330 | |
| 4331 | if (lock_cmd_fail) { |
| 4332 | scsi_set_resid(srb, 0); |
| 4333 | set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); |
| 4334 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4335 | } |
| 4336 | #endif /* SUPPORT_SD_LOCK */ |
| 4337 | |
| 4338 | scsi_set_resid(srb, 0); |
| 4339 | return TRANSPORT_GOOD; |
| 4340 | |
| 4341 | SD_Execute_Write_Cmd_Failed: |
| 4342 | sd_card->pre_cmd_err = 1; |
| 4343 | set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); |
| 4344 | if (write_err) |
| 4345 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR); |
| 4346 | |
| 4347 | release_sd_card(chip); |
| 4348 | do_reset_sd_card(chip); |
| 4349 | if (!(chip->card_ready & SD_CARD)) |
| 4350 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); |
| 4351 | |
| 4352 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4353 | } |
| 4354 | |
| 4355 | int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip) |
| 4356 | { |
| 4357 | struct sd_info *sd_card = &(chip->sd_card); |
| 4358 | unsigned int lun = SCSI_LUN(srb); |
| 4359 | int count; |
| 4360 | u16 data_len; |
| 4361 | |
| 4362 | if (!sd_card->sd_pass_thru_en) { |
| 4363 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); |
| 4364 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4365 | } |
| 4366 | |
| 4367 | if (sd_card->pre_cmd_err) { |
| 4368 | sd_card->pre_cmd_err = 0; |
| 4369 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); |
| 4370 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4371 | } |
| 4372 | |
| 4373 | data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8]; |
| 4374 | |
| 4375 | if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) { |
| 4376 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); |
| 4377 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4378 | } else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) { |
| 4379 | count = (data_len < 17) ? data_len : 17; |
| 4380 | } else { |
| 4381 | count = (data_len < 6) ? data_len : 6; |
| 4382 | } |
| 4383 | rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb); |
| 4384 | |
| 4385 | RTSX_DEBUGP("Response length: %d\n", data_len); |
| 4386 | RTSX_DEBUGP("Response: 0x%x 0x%x 0x%x 0x%x\n", sd_card->rsp[0], |
| 4387 | sd_card->rsp[1], sd_card->rsp[2], sd_card->rsp[3]); |
| 4388 | |
| 4389 | scsi_set_resid(srb, 0); |
| 4390 | return TRANSPORT_GOOD; |
| 4391 | } |
| 4392 | |
| 4393 | int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip) |
| 4394 | { |
| 4395 | struct sd_info *sd_card = &(chip->sd_card); |
| 4396 | unsigned int lun = SCSI_LUN(srb); |
| 4397 | int retval; |
| 4398 | |
| 4399 | if (!sd_card->sd_pass_thru_en) { |
| 4400 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); |
| 4401 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4402 | } |
| 4403 | |
| 4404 | if (sd_card->pre_cmd_err) { |
| 4405 | sd_card->pre_cmd_err = 0; |
| 4406 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); |
| 4407 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4408 | } |
| 4409 | |
| 4410 | if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) || |
| 4411 | (0x20 != srb->cmnd[4]) || (0x43 != srb->cmnd[5]) || |
| 4412 | (0x61 != srb->cmnd[6]) || (0x72 != srb->cmnd[7]) || |
| 4413 | (0x64 != srb->cmnd[8])) { |
| 4414 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); |
| 4415 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4416 | } |
| 4417 | |
| 4418 | switch (srb->cmnd[1] & 0x0F) { |
| 4419 | case 0: |
| 4420 | #ifdef SUPPORT_SD_LOCK |
| 4421 | if (0x64 == srb->cmnd[9]) |
| 4422 | sd_card->sd_lock_status |= SD_SDR_RST; |
| 4423 | #endif |
| 4424 | retval = reset_sd_card(chip); |
| 4425 | if (retval != STATUS_SUCCESS) { |
| 4426 | #ifdef SUPPORT_SD_LOCK |
| 4427 | sd_card->sd_lock_status &= ~SD_SDR_RST; |
| 4428 | #endif |
| 4429 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); |
| 4430 | sd_card->pre_cmd_err = 1; |
| 4431 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4432 | } |
| 4433 | #ifdef SUPPORT_SD_LOCK |
| 4434 | sd_card->sd_lock_status &= ~SD_SDR_RST; |
| 4435 | #endif |
| 4436 | break; |
| 4437 | |
| 4438 | case 1: |
| 4439 | retval = soft_reset_sd_card(chip); |
| 4440 | if (retval != STATUS_SUCCESS) { |
| 4441 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); |
| 4442 | sd_card->pre_cmd_err = 1; |
| 4443 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4444 | } |
| 4445 | break; |
| 4446 | |
| 4447 | default: |
| 4448 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); |
| 4449 | TRACE_RET(chip, TRANSPORT_FAILED); |
| 4450 | } |
| 4451 | |
| 4452 | scsi_set_resid(srb, 0); |
| 4453 | return TRANSPORT_GOOD; |
| 4454 | } |
| 4455 | #endif |
| 4456 | |
| 4457 | void sd_cleanup_work(struct rtsx_chip *chip) |
| 4458 | { |
| 4459 | struct sd_info *sd_card = &(chip->sd_card); |
| 4460 | |
| 4461 | if (sd_card->seq_mode) { |
| 4462 | RTSX_DEBUGP("SD: stop transmission\n"); |
| 4463 | sd_stop_seq_mode(chip); |
| 4464 | sd_card->cleanup_counter = 0; |
| 4465 | } |
| 4466 | } |
| 4467 | |
| 4468 | int sd_power_off_card3v3(struct rtsx_chip *chip) |
| 4469 | { |
| 4470 | int retval; |
| 4471 | |
| 4472 | retval = disable_card_clock(chip, SD_CARD); |
| 4473 | if (retval != STATUS_SUCCESS) |
| 4474 | TRACE_RET(chip, STATUS_FAIL); |
| 4475 | |
| 4476 | RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, 0); |
| 4477 | |
| 4478 | if (!chip->ft2_fast_mode) { |
| 4479 | retval = card_power_off(chip, SD_CARD); |
| 4480 | if (retval != STATUS_SUCCESS) |
| 4481 | TRACE_RET(chip, STATUS_FAIL); |
| 4482 | |
| 4483 | wait_timeout(50); |
| 4484 | } |
| 4485 | |
| 4486 | if (chip->asic_code) { |
| 4487 | retval = sd_pull_ctl_disable(chip); |
| 4488 | if (retval != STATUS_SUCCESS) |
| 4489 | TRACE_RET(chip, STATUS_FAIL); |
| 4490 | } else { |
| 4491 | RTSX_WRITE_REG(chip, FPGA_PULL_CTL, |
| 4492 | FPGA_SD_PULL_CTL_BIT | 0x20, FPGA_SD_PULL_CTL_BIT); |
| 4493 | } |
| 4494 | |
| 4495 | return STATUS_SUCCESS; |
| 4496 | } |
| 4497 | |
| 4498 | int release_sd_card(struct rtsx_chip *chip) |
| 4499 | { |
| 4500 | struct sd_info *sd_card = &(chip->sd_card); |
| 4501 | int retval; |
| 4502 | |
| 4503 | RTSX_DEBUGP("release_sd_card\n"); |
| 4504 | |
| 4505 | chip->card_ready &= ~SD_CARD; |
| 4506 | chip->card_fail &= ~SD_CARD; |
| 4507 | chip->card_wp &= ~SD_CARD; |
| 4508 | |
| 4509 | chip->sd_io = 0; |
| 4510 | chip->sd_int = 0; |
| 4511 | |
| 4512 | #ifdef SUPPORT_SD_LOCK |
| 4513 | sd_card->sd_lock_status = 0; |
| 4514 | sd_card->sd_erase_status = 0; |
| 4515 | #endif |
| 4516 | |
| 4517 | memset(sd_card->raw_csd, 0, 16); |
| 4518 | memset(sd_card->raw_scr, 0, 8); |
| 4519 | |
| 4520 | retval = sd_power_off_card3v3(chip); |
| 4521 | if (retval != STATUS_SUCCESS) |
| 4522 | TRACE_RET(chip, STATUS_FAIL); |
| 4523 | |
| 4524 | return STATUS_SUCCESS; |
| 4525 | } |