Micky Ching | fa590c2 | 2013-11-12 17:16:08 +0800 | [diff] [blame] | 1 | /* Driver for Realtek PCI-Express card reader |
| 2 | * |
| 3 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation; either version 2, or (at your option) any |
| 8 | * later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, but |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 13 | * General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along |
| 16 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 17 | * |
| 18 | * Author: |
| 19 | * Wei WANG (wei_wang@realsil.com.cn) |
| 20 | * Micky Ching (micky_ching@realsil.com.cn) |
| 21 | */ |
| 22 | |
| 23 | #include <linux/blkdev.h> |
| 24 | #include <linux/kthread.h> |
| 25 | #include <linux/sched.h> |
| 26 | #include <linux/vmalloc.h> |
| 27 | |
| 28 | #include "rtsx.h" |
| 29 | #include "rtsx_transport.h" |
| 30 | #include "rtsx_scsi.h" |
| 31 | #include "rtsx_card.h" |
| 32 | #include "xd.h" |
| 33 | |
| 34 | static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no); |
| 35 | static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff, |
| 36 | u8 start_page, u8 end_page); |
| 37 | |
| 38 | static inline void xd_set_err_code(struct rtsx_chip *chip, u8 err_code) |
| 39 | { |
| 40 | struct xd_info *xd_card = &(chip->xd_card); |
| 41 | |
| 42 | xd_card->err_code = err_code; |
| 43 | } |
| 44 | |
| 45 | static inline int xd_check_err_code(struct rtsx_chip *chip, u8 err_code) |
| 46 | { |
| 47 | struct xd_info *xd_card = &(chip->xd_card); |
| 48 | |
| 49 | return (xd_card->err_code == err_code); |
| 50 | } |
| 51 | |
| 52 | static int xd_set_init_para(struct rtsx_chip *chip) |
| 53 | { |
| 54 | struct xd_info *xd_card = &(chip->xd_card); |
| 55 | int retval; |
| 56 | |
| 57 | if (chip->asic_code) |
| 58 | xd_card->xd_clock = 47; |
| 59 | else |
| 60 | xd_card->xd_clock = CLK_50; |
| 61 | |
| 62 | retval = switch_clock(chip, xd_card->xd_clock); |
| 63 | if (retval != STATUS_SUCCESS) |
| 64 | TRACE_RET(chip, STATUS_FAIL); |
| 65 | |
| 66 | return STATUS_SUCCESS; |
| 67 | } |
| 68 | |
| 69 | static int xd_switch_clock(struct rtsx_chip *chip) |
| 70 | { |
| 71 | struct xd_info *xd_card = &(chip->xd_card); |
| 72 | int retval; |
| 73 | |
| 74 | retval = select_card(chip, XD_CARD); |
| 75 | if (retval != STATUS_SUCCESS) |
| 76 | TRACE_RET(chip, STATUS_FAIL); |
| 77 | |
| 78 | retval = switch_clock(chip, xd_card->xd_clock); |
| 79 | if (retval != STATUS_SUCCESS) |
| 80 | TRACE_RET(chip, STATUS_FAIL); |
| 81 | |
| 82 | return STATUS_SUCCESS; |
| 83 | } |
| 84 | |
| 85 | static int xd_read_id(struct rtsx_chip *chip, u8 id_cmd, u8 *id_buf, u8 buf_len) |
| 86 | { |
| 87 | int retval, i; |
| 88 | u8 *ptr; |
| 89 | |
| 90 | rtsx_init_cmd(chip); |
| 91 | |
| 92 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd); |
| 93 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, |
| 94 | XD_TRANSFER_START | XD_READ_ID); |
| 95 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, |
| 96 | XD_TRANSFER_END); |
| 97 | |
| 98 | for (i = 0; i < 4; i++) |
| 99 | rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0); |
| 100 | |
| 101 | retval = rtsx_send_cmd(chip, XD_CARD, 20); |
| 102 | if (retval < 0) |
| 103 | TRACE_RET(chip, STATUS_FAIL); |
| 104 | |
| 105 | ptr = rtsx_get_cmd_data(chip) + 1; |
| 106 | if (id_buf && buf_len) { |
| 107 | if (buf_len > 4) |
| 108 | buf_len = 4; |
| 109 | memcpy(id_buf, ptr, buf_len); |
| 110 | } |
| 111 | |
| 112 | return STATUS_SUCCESS; |
| 113 | } |
| 114 | |
| 115 | static void xd_assign_phy_addr(struct rtsx_chip *chip, u32 addr, u8 mode) |
| 116 | { |
| 117 | struct xd_info *xd_card = &(chip->xd_card); |
| 118 | |
| 119 | switch (mode) { |
| 120 | case XD_RW_ADDR: |
| 121 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0); |
| 122 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr); |
| 123 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, |
| 124 | 0xFF, (u8)(addr >> 8)); |
| 125 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, |
| 126 | 0xFF, (u8)(addr >> 16)); |
| 127 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF, |
| 128 | xd_card->addr_cycle | XD_CALC_ECC | XD_BA_NO_TRANSFORM); |
| 129 | break; |
| 130 | |
| 131 | case XD_ERASE_ADDR: |
| 132 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr); |
| 133 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, |
| 134 | 0xFF, (u8)(addr >> 8)); |
| 135 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, |
| 136 | 0xFF, (u8)(addr >> 16)); |
| 137 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF, |
| 138 | (xd_card->addr_cycle - 1) | XD_CALC_ECC | |
| 139 | XD_BA_NO_TRANSFORM); |
| 140 | break; |
| 141 | |
| 142 | default: |
| 143 | break; |
| 144 | } |
| 145 | } |
| 146 | |
| 147 | static int xd_read_redundant(struct rtsx_chip *chip, u32 page_addr, |
| 148 | u8 *buf, int buf_len) |
| 149 | { |
| 150 | int retval, i; |
| 151 | |
| 152 | rtsx_init_cmd(chip); |
| 153 | |
| 154 | xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); |
| 155 | |
| 156 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, |
| 157 | 0xFF, XD_TRANSFER_START | XD_READ_REDUNDANT); |
| 158 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
| 159 | XD_TRANSFER_END, XD_TRANSFER_END); |
| 160 | |
| 161 | for (i = 0; i < 6; i++) |
| 162 | rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i), |
| 163 | 0, 0); |
| 164 | for (i = 0; i < 4; i++) |
| 165 | rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i), |
| 166 | 0, 0); |
| 167 | rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0); |
| 168 | |
| 169 | retval = rtsx_send_cmd(chip, XD_CARD, 500); |
| 170 | if (retval < 0) |
| 171 | TRACE_RET(chip, STATUS_FAIL); |
| 172 | |
| 173 | if (buf && buf_len) { |
| 174 | u8 *ptr = rtsx_get_cmd_data(chip) + 1; |
| 175 | |
| 176 | if (buf_len > 11) |
| 177 | buf_len = 11; |
| 178 | memcpy(buf, ptr, buf_len); |
| 179 | } |
| 180 | |
| 181 | return STATUS_SUCCESS; |
| 182 | } |
| 183 | |
| 184 | static int xd_read_data_from_ppb(struct rtsx_chip *chip, int offset, |
| 185 | u8 *buf, int buf_len) |
| 186 | { |
| 187 | int retval, i; |
| 188 | |
| 189 | if (!buf || (buf_len < 0)) |
| 190 | TRACE_RET(chip, STATUS_FAIL); |
| 191 | |
| 192 | rtsx_init_cmd(chip); |
| 193 | |
| 194 | for (i = 0; i < buf_len; i++) |
| 195 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, |
| 196 | 0, 0); |
| 197 | |
| 198 | retval = rtsx_send_cmd(chip, 0, 250); |
| 199 | if (retval < 0) { |
| 200 | rtsx_clear_xd_error(chip); |
| 201 | TRACE_RET(chip, STATUS_FAIL); |
| 202 | } |
| 203 | |
| 204 | memcpy(buf, rtsx_get_cmd_data(chip), buf_len); |
| 205 | |
| 206 | return STATUS_SUCCESS; |
| 207 | } |
| 208 | |
| 209 | static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf, |
| 210 | int buf_len) |
| 211 | { |
| 212 | int retval; |
| 213 | u8 reg; |
| 214 | |
| 215 | if (!buf || (buf_len < 10)) |
| 216 | TRACE_RET(chip, STATUS_FAIL); |
| 217 | |
| 218 | rtsx_init_cmd(chip); |
| 219 | |
| 220 | xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); |
| 221 | |
| 222 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, |
| 223 | 0x01, PINGPONG_BUFFER); |
| 224 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1); |
| 225 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, |
| 226 | XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS); |
| 227 | |
| 228 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, |
| 229 | XD_TRANSFER_START | XD_READ_PAGES); |
| 230 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, |
| 231 | XD_TRANSFER_END); |
| 232 | |
| 233 | retval = rtsx_send_cmd(chip, XD_CARD, 250); |
| 234 | if (retval == -ETIMEDOUT) { |
| 235 | rtsx_clear_xd_error(chip); |
| 236 | TRACE_RET(chip, STATUS_FAIL); |
| 237 | } |
| 238 | |
| 239 | RTSX_READ_REG(chip, XD_PAGE_STATUS, ®); |
| 240 | if (reg != XD_GPG) { |
| 241 | rtsx_clear_xd_error(chip); |
| 242 | TRACE_RET(chip, STATUS_FAIL); |
| 243 | } |
| 244 | |
| 245 | RTSX_READ_REG(chip, XD_CTL, ®); |
| 246 | if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) { |
| 247 | retval = xd_read_data_from_ppb(chip, 0, buf, buf_len); |
| 248 | if (retval != STATUS_SUCCESS) |
| 249 | TRACE_RET(chip, STATUS_FAIL); |
| 250 | if (reg & XD_ECC1_ERROR) { |
| 251 | u8 ecc_bit, ecc_byte; |
| 252 | |
| 253 | RTSX_READ_REG(chip, XD_ECC_BIT1, &ecc_bit); |
| 254 | RTSX_READ_REG(chip, XD_ECC_BYTE1, &ecc_byte); |
| 255 | |
| 256 | RTSX_DEBUGP("ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n", |
| 257 | ecc_bit, ecc_byte); |
| 258 | if (ecc_byte < buf_len) { |
| 259 | RTSX_DEBUGP("Before correct: 0x%x\n", |
| 260 | buf[ecc_byte]); |
| 261 | buf[ecc_byte] ^= (1 << ecc_bit); |
| 262 | RTSX_DEBUGP("After correct: 0x%x\n", |
| 263 | buf[ecc_byte]); |
| 264 | } |
| 265 | } |
| 266 | } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) { |
| 267 | rtsx_clear_xd_error(chip); |
| 268 | |
| 269 | retval = xd_read_data_from_ppb(chip, 256, buf, buf_len); |
| 270 | if (retval != STATUS_SUCCESS) |
| 271 | TRACE_RET(chip, STATUS_FAIL); |
| 272 | if (reg & XD_ECC2_ERROR) { |
| 273 | u8 ecc_bit, ecc_byte; |
| 274 | |
| 275 | RTSX_READ_REG(chip, XD_ECC_BIT2, &ecc_bit); |
| 276 | RTSX_READ_REG(chip, XD_ECC_BYTE2, &ecc_byte); |
| 277 | |
| 278 | RTSX_DEBUGP("ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n", |
| 279 | ecc_bit, ecc_byte); |
| 280 | if (ecc_byte < buf_len) { |
| 281 | RTSX_DEBUGP("Before correct: 0x%x\n", |
| 282 | buf[ecc_byte]); |
| 283 | buf[ecc_byte] ^= (1 << ecc_bit); |
| 284 | RTSX_DEBUGP("After correct: 0x%x\n", |
| 285 | buf[ecc_byte]); |
| 286 | } |
| 287 | } |
| 288 | } else { |
| 289 | rtsx_clear_xd_error(chip); |
| 290 | TRACE_RET(chip, STATUS_FAIL); |
| 291 | } |
| 292 | |
| 293 | return STATUS_SUCCESS; |
| 294 | } |
| 295 | |
| 296 | static void xd_fill_pull_ctl_disable(struct rtsx_chip *chip) |
| 297 | { |
| 298 | if (CHECK_PID(chip, 0x5208)) { |
| 299 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, |
| 300 | XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD); |
| 301 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, |
| 302 | XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD); |
| 303 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, |
| 304 | XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); |
| 305 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, |
| 306 | XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD); |
| 307 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, |
| 308 | MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); |
| 309 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, |
| 310 | MS_D5_PD | MS_D4_PD); |
| 311 | } else if (CHECK_PID(chip, 0x5288)) { |
| 312 | if (CHECK_BARO_PKG(chip, QFN)) { |
| 313 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, |
| 314 | 0xFF, 0x55); |
| 315 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, |
| 316 | 0xFF, 0x55); |
| 317 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, |
| 318 | 0xFF, 0x4B); |
| 319 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, |
| 320 | 0xFF, 0x69); |
| 321 | } |
| 322 | } |
| 323 | } |
| 324 | |
| 325 | static void xd_fill_pull_ctl_stage1_barossa(struct rtsx_chip *chip) |
| 326 | { |
| 327 | if (CHECK_BARO_PKG(chip, QFN)) { |
| 328 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55); |
| 329 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55); |
| 330 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B); |
| 331 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55); |
| 332 | } |
| 333 | } |
| 334 | |
| 335 | static void xd_fill_pull_ctl_enable(struct rtsx_chip *chip) |
| 336 | { |
| 337 | if (CHECK_PID(chip, 0x5208)) { |
| 338 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, |
| 339 | XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD); |
| 340 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, |
| 341 | XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD); |
| 342 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, |
| 343 | XD_WP_PD | XD_CE_PU | XD_CLE_PD | XD_CD_PU); |
| 344 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, |
| 345 | XD_RDY_PU | XD_WE_PU | XD_RE_PU | XD_ALE_PD); |
| 346 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, |
| 347 | MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); |
| 348 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, |
| 349 | MS_D5_PD | MS_D4_PD); |
| 350 | } else if (CHECK_PID(chip, 0x5288)) { |
| 351 | if (CHECK_BARO_PKG(chip, QFN)) { |
| 352 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, |
| 353 | 0xFF, 0x55); |
| 354 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, |
| 355 | 0xFF, 0x55); |
| 356 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, |
| 357 | 0xFF, 0x53); |
| 358 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, |
| 359 | 0xFF, 0xA9); |
| 360 | } |
| 361 | } |
| 362 | } |
| 363 | |
| 364 | static int xd_pull_ctl_disable(struct rtsx_chip *chip) |
| 365 | { |
| 366 | if (CHECK_PID(chip, 0x5208)) { |
| 367 | RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, |
| 368 | XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD); |
| 369 | RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, |
| 370 | XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD); |
| 371 | RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, |
| 372 | XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); |
| 373 | RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, |
| 374 | XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD); |
| 375 | RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, |
| 376 | MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); |
| 377 | RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD); |
| 378 | } else if (CHECK_PID(chip, 0x5288)) { |
| 379 | if (CHECK_BARO_PKG(chip, QFN)) { |
| 380 | RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55); |
| 381 | RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55); |
| 382 | RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B); |
| 383 | RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69); |
| 384 | } |
| 385 | } |
| 386 | |
| 387 | return STATUS_SUCCESS; |
| 388 | } |
| 389 | |
| 390 | static int reset_xd(struct rtsx_chip *chip) |
| 391 | { |
| 392 | struct xd_info *xd_card = &(chip->xd_card); |
| 393 | int retval, i, j; |
| 394 | u8 *ptr, id_buf[4], redunt[11]; |
| 395 | |
| 396 | retval = select_card(chip, XD_CARD); |
| 397 | if (retval != STATUS_SUCCESS) |
| 398 | TRACE_RET(chip, STATUS_FAIL); |
| 399 | |
| 400 | rtsx_init_cmd(chip); |
| 401 | |
| 402 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF, |
| 403 | XD_PGSTS_NOT_FF); |
| 404 | if (chip->asic_code) { |
| 405 | if (!CHECK_PID(chip, 0x5288)) |
| 406 | xd_fill_pull_ctl_disable(chip); |
| 407 | else |
| 408 | xd_fill_pull_ctl_stage1_barossa(chip); |
| 409 | } else { |
| 410 | rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, |
| 411 | (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) | 0x20); |
| 412 | } |
| 413 | |
| 414 | if (!chip->ft2_fast_mode) |
| 415 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT, |
| 416 | XD_NO_AUTO_PWR_OFF, 0); |
| 417 | |
| 418 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0); |
| 419 | |
| 420 | retval = rtsx_send_cmd(chip, XD_CARD, 100); |
| 421 | if (retval < 0) |
| 422 | TRACE_RET(chip, STATUS_FAIL); |
| 423 | |
| 424 | if (!chip->ft2_fast_mode) { |
| 425 | retval = card_power_off(chip, XD_CARD); |
| 426 | if (retval != STATUS_SUCCESS) |
| 427 | TRACE_RET(chip, STATUS_FAIL); |
| 428 | |
| 429 | wait_timeout(250); |
| 430 | |
| 431 | rtsx_init_cmd(chip); |
| 432 | |
| 433 | if (chip->asic_code) { |
| 434 | xd_fill_pull_ctl_enable(chip); |
| 435 | } else { |
| 436 | rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, |
| 437 | (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) | |
| 438 | 0x20); |
| 439 | } |
| 440 | |
| 441 | retval = rtsx_send_cmd(chip, XD_CARD, 100); |
| 442 | if (retval < 0) |
| 443 | TRACE_RET(chip, STATUS_FAIL); |
| 444 | |
| 445 | retval = card_power_on(chip, XD_CARD); |
| 446 | if (retval != STATUS_SUCCESS) |
| 447 | TRACE_RET(chip, STATUS_FAIL); |
| 448 | |
| 449 | #ifdef SUPPORT_OCP |
| 450 | wait_timeout(50); |
| 451 | if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { |
| 452 | RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", |
| 453 | chip->ocp_stat); |
| 454 | TRACE_RET(chip, STATUS_FAIL); |
| 455 | } |
| 456 | #endif |
| 457 | } |
| 458 | |
| 459 | rtsx_init_cmd(chip); |
| 460 | |
| 461 | if (chip->ft2_fast_mode) { |
| 462 | if (chip->asic_code) { |
| 463 | xd_fill_pull_ctl_enable(chip); |
| 464 | } else { |
| 465 | rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, |
| 466 | (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) | |
| 467 | 0x20); |
| 468 | } |
| 469 | } |
| 470 | |
| 471 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, XD_OUTPUT_EN); |
| 472 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN); |
| 473 | |
| 474 | retval = rtsx_send_cmd(chip, XD_CARD, 100); |
| 475 | if (retval < 0) |
| 476 | TRACE_RET(chip, STATUS_FAIL); |
| 477 | |
| 478 | if (!chip->ft2_fast_mode) |
| 479 | wait_timeout(200); |
| 480 | |
| 481 | retval = xd_set_init_para(chip); |
| 482 | if (retval != STATUS_SUCCESS) |
| 483 | TRACE_RET(chip, STATUS_FAIL); |
| 484 | |
| 485 | /* Read ID to check if the timing setting is right */ |
| 486 | for (i = 0; i < 4; i++) { |
| 487 | rtsx_init_cmd(chip); |
| 488 | |
| 489 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF, |
| 490 | XD_TIME_SETUP_STEP * 3 + |
| 491 | XD_TIME_RW_STEP * (2 + i) + XD_TIME_RWN_STEP * i); |
| 492 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF, |
| 493 | XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP * (4 + i) + |
| 494 | XD_TIME_RWN_STEP * (3 + i)); |
| 495 | |
| 496 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, |
| 497 | XD_TRANSFER_START | XD_RESET); |
| 498 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
| 499 | XD_TRANSFER_END, XD_TRANSFER_END); |
| 500 | |
| 501 | rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0); |
| 502 | rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0); |
| 503 | |
| 504 | retval = rtsx_send_cmd(chip, XD_CARD, 100); |
| 505 | if (retval < 0) |
| 506 | TRACE_RET(chip, STATUS_FAIL); |
| 507 | |
| 508 | ptr = rtsx_get_cmd_data(chip) + 1; |
| 509 | |
| 510 | RTSX_DEBUGP("XD_DAT: 0x%x, XD_CTL: 0x%x\n", ptr[0], ptr[1]); |
| 511 | |
| 512 | if (((ptr[0] & READY_FLAG) != READY_STATE) || |
| 513 | !(ptr[1] & XD_RDY)) |
| 514 | continue; |
| 515 | |
| 516 | retval = xd_read_id(chip, READ_ID, id_buf, 4); |
| 517 | if (retval != STATUS_SUCCESS) |
| 518 | TRACE_RET(chip, STATUS_FAIL); |
| 519 | |
| 520 | RTSX_DEBUGP("READ_ID: 0x%x 0x%x 0x%x 0x%x\n", |
| 521 | id_buf[0], id_buf[1], id_buf[2], id_buf[3]); |
| 522 | |
| 523 | xd_card->device_code = id_buf[1]; |
| 524 | |
| 525 | /* Check if the xD card is supported */ |
| 526 | switch (xd_card->device_code) { |
| 527 | case XD_4M_X8_512_1: |
| 528 | case XD_4M_X8_512_2: |
| 529 | xd_card->block_shift = 4; |
| 530 | xd_card->page_off = 0x0F; |
| 531 | xd_card->addr_cycle = 3; |
| 532 | xd_card->zone_cnt = 1; |
| 533 | xd_card->capacity = 8000; |
| 534 | XD_SET_4MB(xd_card); |
| 535 | break; |
| 536 | case XD_8M_X8_512: |
| 537 | xd_card->block_shift = 4; |
| 538 | xd_card->page_off = 0x0F; |
| 539 | xd_card->addr_cycle = 3; |
| 540 | xd_card->zone_cnt = 1; |
| 541 | xd_card->capacity = 16000; |
| 542 | break; |
| 543 | case XD_16M_X8_512: |
| 544 | XD_PAGE_512(xd_card); |
| 545 | xd_card->addr_cycle = 3; |
| 546 | xd_card->zone_cnt = 1; |
| 547 | xd_card->capacity = 32000; |
| 548 | break; |
| 549 | case XD_32M_X8_512: |
| 550 | XD_PAGE_512(xd_card); |
| 551 | xd_card->addr_cycle = 3; |
| 552 | xd_card->zone_cnt = 2; |
| 553 | xd_card->capacity = 64000; |
| 554 | break; |
| 555 | case XD_64M_X8_512: |
| 556 | XD_PAGE_512(xd_card); |
| 557 | xd_card->addr_cycle = 4; |
| 558 | xd_card->zone_cnt = 4; |
| 559 | xd_card->capacity = 128000; |
| 560 | break; |
| 561 | case XD_128M_X8_512: |
| 562 | XD_PAGE_512(xd_card); |
| 563 | xd_card->addr_cycle = 4; |
| 564 | xd_card->zone_cnt = 8; |
| 565 | xd_card->capacity = 256000; |
| 566 | break; |
| 567 | case XD_256M_X8_512: |
| 568 | XD_PAGE_512(xd_card); |
| 569 | xd_card->addr_cycle = 4; |
| 570 | xd_card->zone_cnt = 16; |
| 571 | xd_card->capacity = 512000; |
| 572 | break; |
| 573 | case XD_512M_X8: |
| 574 | XD_PAGE_512(xd_card); |
| 575 | xd_card->addr_cycle = 4; |
| 576 | xd_card->zone_cnt = 32; |
| 577 | xd_card->capacity = 1024000; |
| 578 | break; |
| 579 | case xD_1G_X8_512: |
| 580 | XD_PAGE_512(xd_card); |
| 581 | xd_card->addr_cycle = 4; |
| 582 | xd_card->zone_cnt = 64; |
| 583 | xd_card->capacity = 2048000; |
| 584 | break; |
| 585 | case xD_2G_X8_512: |
| 586 | XD_PAGE_512(xd_card); |
| 587 | xd_card->addr_cycle = 4; |
| 588 | xd_card->zone_cnt = 128; |
| 589 | xd_card->capacity = 4096000; |
| 590 | break; |
| 591 | default: |
| 592 | continue; |
| 593 | } |
| 594 | |
| 595 | /* Confirm timing setting */ |
| 596 | for (j = 0; j < 10; j++) { |
| 597 | retval = xd_read_id(chip, READ_ID, id_buf, 4); |
| 598 | if (retval != STATUS_SUCCESS) |
| 599 | TRACE_RET(chip, STATUS_FAIL); |
| 600 | |
| 601 | if (id_buf[1] != xd_card->device_code) |
| 602 | break; |
| 603 | } |
| 604 | |
| 605 | if (j == 10) |
| 606 | break; |
| 607 | } |
| 608 | |
| 609 | if (i == 4) { |
| 610 | xd_card->block_shift = 0; |
| 611 | xd_card->page_off = 0; |
| 612 | xd_card->addr_cycle = 0; |
| 613 | xd_card->capacity = 0; |
| 614 | |
| 615 | TRACE_RET(chip, STATUS_FAIL); |
| 616 | } |
| 617 | |
| 618 | retval = xd_read_id(chip, READ_xD_ID, id_buf, 4); |
| 619 | if (retval != STATUS_SUCCESS) |
| 620 | TRACE_RET(chip, STATUS_FAIL); |
| 621 | RTSX_DEBUGP("READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n", |
| 622 | id_buf[0], id_buf[1], id_buf[2], id_buf[3]); |
| 623 | if (id_buf[2] != XD_ID_CODE) |
| 624 | TRACE_RET(chip, STATUS_FAIL); |
| 625 | |
| 626 | /* Search CIS block */ |
| 627 | for (i = 0; i < 24; i++) { |
| 628 | u32 page_addr; |
| 629 | |
| 630 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) |
| 631 | TRACE_RET(chip, STATUS_FAIL); |
| 632 | |
| 633 | page_addr = (u32)i << xd_card->block_shift; |
| 634 | |
| 635 | for (j = 0; j < 3; j++) { |
| 636 | retval = xd_read_redundant(chip, page_addr, redunt, 11); |
| 637 | if (retval == STATUS_SUCCESS) |
| 638 | break; |
| 639 | } |
| 640 | if (j == 3) |
| 641 | continue; |
| 642 | |
| 643 | if (redunt[BLOCK_STATUS] != XD_GBLK) |
| 644 | continue; |
| 645 | |
| 646 | j = 0; |
| 647 | if (redunt[PAGE_STATUS] != XD_GPG) { |
| 648 | for (j = 1; j <= 8; j++) { |
| 649 | retval = xd_read_redundant(chip, page_addr + j, |
| 650 | redunt, 11); |
| 651 | if (retval == STATUS_SUCCESS) { |
| 652 | if (redunt[PAGE_STATUS] == XD_GPG) |
| 653 | break; |
| 654 | } |
| 655 | } |
| 656 | |
| 657 | if (j == 9) |
| 658 | break; |
| 659 | } |
| 660 | |
| 661 | /* Check CIS data */ |
| 662 | if ((redunt[BLOCK_STATUS] == XD_GBLK) && |
| 663 | (redunt[PARITY] & XD_BA1_ALL0)) { |
| 664 | u8 buf[10]; |
| 665 | |
| 666 | page_addr += j; |
| 667 | |
| 668 | retval = xd_read_cis(chip, page_addr, buf, 10); |
| 669 | if (retval != STATUS_SUCCESS) |
| 670 | TRACE_RET(chip, STATUS_FAIL); |
| 671 | |
| 672 | if ((buf[0] == 0x01) && (buf[1] == 0x03) && |
| 673 | (buf[2] == 0xD9) |
| 674 | && (buf[3] == 0x01) && (buf[4] == 0xFF) |
| 675 | && (buf[5] == 0x18) && (buf[6] == 0x02) |
| 676 | && (buf[7] == 0xDF) && (buf[8] == 0x01) |
| 677 | && (buf[9] == 0x20)) { |
| 678 | xd_card->cis_block = (u16)i; |
| 679 | } |
| 680 | } |
| 681 | |
| 682 | break; |
| 683 | } |
| 684 | |
| 685 | RTSX_DEBUGP("CIS block: 0x%x\n", xd_card->cis_block); |
| 686 | if (xd_card->cis_block == 0xFFFF) |
| 687 | TRACE_RET(chip, STATUS_FAIL); |
| 688 | |
| 689 | chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity; |
| 690 | |
| 691 | return STATUS_SUCCESS; |
| 692 | } |
| 693 | |
| 694 | static int xd_check_data_blank(u8 *redunt) |
| 695 | { |
| 696 | int i; |
| 697 | |
| 698 | for (i = 0; i < 6; i++) { |
| 699 | if (redunt[PAGE_STATUS + i] != 0xFF) |
| 700 | return 0; |
| 701 | } |
| 702 | |
| 703 | if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1)) |
| 704 | != (XD_ECC1_ALL1 | XD_ECC2_ALL1)) |
| 705 | return 0; |
| 706 | |
| 707 | |
| 708 | for (i = 0; i < 4; i++) { |
| 709 | if (redunt[RESERVED0 + i] != 0xFF) |
| 710 | return 0; |
| 711 | } |
| 712 | |
| 713 | return 1; |
| 714 | } |
| 715 | |
| 716 | static u16 xd_load_log_block_addr(u8 *redunt) |
| 717 | { |
| 718 | u16 addr = 0xFFFF; |
| 719 | |
| 720 | if (redunt[PARITY] & XD_BA1_BA2_EQL) |
| 721 | addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | |
| 722 | redunt[BLOCK_ADDR1_L]; |
| 723 | else if (redunt[PARITY] & XD_BA1_VALID) |
| 724 | addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | |
| 725 | redunt[BLOCK_ADDR1_L]; |
| 726 | else if (redunt[PARITY] & XD_BA2_VALID) |
| 727 | addr = ((u16)redunt[BLOCK_ADDR2_H] << 8) | |
| 728 | redunt[BLOCK_ADDR2_L]; |
| 729 | |
| 730 | return addr; |
| 731 | } |
| 732 | |
| 733 | static int xd_init_l2p_tbl(struct rtsx_chip *chip) |
| 734 | { |
| 735 | struct xd_info *xd_card = &(chip->xd_card); |
| 736 | int size, i; |
| 737 | |
| 738 | RTSX_DEBUGP("xd_init_l2p_tbl: zone_cnt = %d\n", xd_card->zone_cnt); |
| 739 | |
| 740 | if (xd_card->zone_cnt < 1) |
| 741 | TRACE_RET(chip, STATUS_FAIL); |
| 742 | |
| 743 | size = xd_card->zone_cnt * sizeof(struct zone_entry); |
| 744 | RTSX_DEBUGP("Buffer size for l2p table is %d\n", size); |
| 745 | |
| 746 | xd_card->zone = vmalloc(size); |
| 747 | if (!xd_card->zone) |
| 748 | TRACE_RET(chip, STATUS_ERROR); |
| 749 | |
| 750 | for (i = 0; i < xd_card->zone_cnt; i++) { |
| 751 | xd_card->zone[i].build_flag = 0; |
| 752 | xd_card->zone[i].l2p_table = NULL; |
| 753 | xd_card->zone[i].free_table = NULL; |
| 754 | xd_card->zone[i].get_index = 0; |
| 755 | xd_card->zone[i].set_index = 0; |
| 756 | xd_card->zone[i].unused_blk_cnt = 0; |
| 757 | } |
| 758 | |
| 759 | return STATUS_SUCCESS; |
| 760 | } |
| 761 | |
| 762 | static inline void free_zone(struct zone_entry *zone) |
| 763 | { |
| 764 | RTSX_DEBUGP("free_zone\n"); |
| 765 | |
| 766 | if (!zone) |
| 767 | return; |
| 768 | |
| 769 | zone->build_flag = 0; |
| 770 | zone->set_index = 0; |
| 771 | zone->get_index = 0; |
| 772 | zone->unused_blk_cnt = 0; |
| 773 | if (zone->l2p_table) { |
| 774 | vfree(zone->l2p_table); |
| 775 | zone->l2p_table = NULL; |
| 776 | } |
| 777 | if (zone->free_table) { |
| 778 | vfree(zone->free_table); |
| 779 | zone->free_table = NULL; |
| 780 | } |
| 781 | } |
| 782 | |
| 783 | static void xd_set_unused_block(struct rtsx_chip *chip, u32 phy_blk) |
| 784 | { |
| 785 | struct xd_info *xd_card = &(chip->xd_card); |
| 786 | struct zone_entry *zone; |
| 787 | int zone_no; |
| 788 | |
| 789 | zone_no = (int)phy_blk >> 10; |
| 790 | if (zone_no >= xd_card->zone_cnt) { |
| 791 | RTSX_DEBUGP("Set unused block to invalid zone (zone_no = %d, zone_cnt = %d)\n", |
| 792 | zone_no, xd_card->zone_cnt); |
| 793 | return; |
| 794 | } |
| 795 | zone = &(xd_card->zone[zone_no]); |
| 796 | |
| 797 | if (zone->free_table == NULL) { |
| 798 | if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS) |
| 799 | return; |
| 800 | } |
| 801 | |
| 802 | if ((zone->set_index >= XD_FREE_TABLE_CNT) |
| 803 | || (zone->set_index < 0)) { |
| 804 | free_zone(zone); |
| 805 | RTSX_DEBUGP("Set unused block fail, invalid set_index\n"); |
| 806 | return; |
| 807 | } |
| 808 | |
| 809 | RTSX_DEBUGP("Set unused block to index %d\n", zone->set_index); |
| 810 | |
| 811 | zone->free_table[zone->set_index++] = (u16) (phy_blk & 0x3ff); |
| 812 | if (zone->set_index >= XD_FREE_TABLE_CNT) |
| 813 | zone->set_index = 0; |
| 814 | zone->unused_blk_cnt++; |
| 815 | } |
| 816 | |
| 817 | static u32 xd_get_unused_block(struct rtsx_chip *chip, int zone_no) |
| 818 | { |
| 819 | struct xd_info *xd_card = &(chip->xd_card); |
| 820 | struct zone_entry *zone; |
| 821 | u32 phy_blk; |
| 822 | |
| 823 | if (zone_no >= xd_card->zone_cnt) { |
| 824 | RTSX_DEBUGP("Get unused block from invalid zone (zone_no = %d, zone_cnt = %d)\n", |
| 825 | zone_no, xd_card->zone_cnt); |
| 826 | return BLK_NOT_FOUND; |
| 827 | } |
| 828 | zone = &(xd_card->zone[zone_no]); |
| 829 | |
| 830 | if ((zone->unused_blk_cnt == 0) || |
| 831 | (zone->set_index == zone->get_index)) { |
| 832 | free_zone(zone); |
| 833 | RTSX_DEBUGP("Get unused block fail, no unused block available\n"); |
| 834 | return BLK_NOT_FOUND; |
| 835 | } |
| 836 | if ((zone->get_index >= XD_FREE_TABLE_CNT) || (zone->get_index < 0)) { |
| 837 | free_zone(zone); |
| 838 | RTSX_DEBUGP("Get unused block fail, invalid get_index\n"); |
| 839 | return BLK_NOT_FOUND; |
| 840 | } |
| 841 | |
| 842 | RTSX_DEBUGP("Get unused block from index %d\n", zone->get_index); |
| 843 | |
| 844 | phy_blk = zone->free_table[zone->get_index]; |
| 845 | zone->free_table[zone->get_index++] = 0xFFFF; |
| 846 | if (zone->get_index >= XD_FREE_TABLE_CNT) |
| 847 | zone->get_index = 0; |
| 848 | zone->unused_blk_cnt--; |
| 849 | |
| 850 | phy_blk += ((u32)(zone_no) << 10); |
| 851 | return phy_blk; |
| 852 | } |
| 853 | |
| 854 | static void xd_set_l2p_tbl(struct rtsx_chip *chip, |
| 855 | int zone_no, u16 log_off, u16 phy_off) |
| 856 | { |
| 857 | struct xd_info *xd_card = &(chip->xd_card); |
| 858 | struct zone_entry *zone; |
| 859 | |
| 860 | zone = &(xd_card->zone[zone_no]); |
| 861 | zone->l2p_table[log_off] = phy_off; |
| 862 | } |
| 863 | |
| 864 | static u32 xd_get_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off) |
| 865 | { |
| 866 | struct xd_info *xd_card = &(chip->xd_card); |
| 867 | struct zone_entry *zone; |
| 868 | int retval; |
| 869 | |
| 870 | zone = &(xd_card->zone[zone_no]); |
| 871 | if (zone->l2p_table[log_off] == 0xFFFF) { |
| 872 | u32 phy_blk = 0; |
| 873 | int i; |
| 874 | |
| 875 | #ifdef XD_DELAY_WRITE |
| 876 | retval = xd_delay_write(chip); |
| 877 | if (retval != STATUS_SUCCESS) { |
| 878 | RTSX_DEBUGP("In xd_get_l2p_tbl, delay write fail!\n"); |
| 879 | return BLK_NOT_FOUND; |
| 880 | } |
| 881 | #endif |
| 882 | |
| 883 | if (zone->unused_blk_cnt <= 0) { |
| 884 | RTSX_DEBUGP("No unused block!\n"); |
| 885 | return BLK_NOT_FOUND; |
| 886 | } |
| 887 | |
| 888 | for (i = 0; i < zone->unused_blk_cnt; i++) { |
| 889 | phy_blk = xd_get_unused_block(chip, zone_no); |
| 890 | if (phy_blk == BLK_NOT_FOUND) { |
| 891 | RTSX_DEBUGP("No unused block available!\n"); |
| 892 | return BLK_NOT_FOUND; |
| 893 | } |
| 894 | |
| 895 | retval = xd_init_page(chip, phy_blk, log_off, |
| 896 | 0, xd_card->page_off + 1); |
| 897 | if (retval == STATUS_SUCCESS) |
| 898 | break; |
| 899 | } |
| 900 | if (i >= zone->unused_blk_cnt) { |
| 901 | RTSX_DEBUGP("No good unused block available!\n"); |
| 902 | return BLK_NOT_FOUND; |
| 903 | } |
| 904 | |
| 905 | xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(phy_blk & 0x3FF)); |
| 906 | return phy_blk; |
| 907 | } |
| 908 | |
| 909 | return (u32)zone->l2p_table[log_off] + ((u32)(zone_no) << 10); |
| 910 | } |
| 911 | |
| 912 | int reset_xd_card(struct rtsx_chip *chip) |
| 913 | { |
| 914 | struct xd_info *xd_card = &(chip->xd_card); |
| 915 | int retval; |
| 916 | |
| 917 | memset(xd_card, 0, sizeof(struct xd_info)); |
| 918 | |
| 919 | xd_card->block_shift = 0; |
| 920 | xd_card->page_off = 0; |
| 921 | xd_card->addr_cycle = 0; |
| 922 | xd_card->capacity = 0; |
| 923 | xd_card->zone_cnt = 0; |
| 924 | xd_card->cis_block = 0xFFFF; |
| 925 | xd_card->delay_write.delay_write_flag = 0; |
| 926 | |
| 927 | retval = enable_card_clock(chip, XD_CARD); |
| 928 | if (retval != STATUS_SUCCESS) |
| 929 | TRACE_RET(chip, STATUS_FAIL); |
| 930 | |
| 931 | retval = reset_xd(chip); |
| 932 | if (retval != STATUS_SUCCESS) |
| 933 | TRACE_RET(chip, STATUS_FAIL); |
| 934 | |
| 935 | retval = xd_init_l2p_tbl(chip); |
| 936 | if (retval != STATUS_SUCCESS) |
| 937 | TRACE_RET(chip, STATUS_FAIL); |
| 938 | |
| 939 | return STATUS_SUCCESS; |
| 940 | } |
| 941 | |
| 942 | static int xd_mark_bad_block(struct rtsx_chip *chip, u32 phy_blk) |
| 943 | { |
| 944 | struct xd_info *xd_card = &(chip->xd_card); |
| 945 | int retval; |
| 946 | u32 page_addr; |
| 947 | u8 reg = 0; |
| 948 | |
| 949 | RTSX_DEBUGP("mark block 0x%x as bad block\n", phy_blk); |
| 950 | |
| 951 | if (phy_blk == BLK_NOT_FOUND) |
| 952 | TRACE_RET(chip, STATUS_FAIL); |
| 953 | |
| 954 | rtsx_init_cmd(chip); |
| 955 | |
| 956 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG); |
| 957 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_LATER_BBLK); |
| 958 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF); |
| 959 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF); |
| 960 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF); |
| 961 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF); |
| 962 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF); |
| 963 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF); |
| 964 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF); |
| 965 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF); |
| 966 | |
| 967 | page_addr = phy_blk << xd_card->block_shift; |
| 968 | |
| 969 | xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); |
| 970 | |
| 971 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, |
| 972 | xd_card->page_off + 1); |
| 973 | |
| 974 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, |
| 975 | XD_TRANSFER_START | XD_WRITE_REDUNDANT); |
| 976 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
| 977 | XD_TRANSFER_END, XD_TRANSFER_END); |
| 978 | |
| 979 | retval = rtsx_send_cmd(chip, XD_CARD, 500); |
| 980 | if (retval < 0) { |
| 981 | rtsx_clear_xd_error(chip); |
| 982 | rtsx_read_register(chip, XD_DAT, ®); |
| 983 | if (reg & PROGRAM_ERROR) |
| 984 | xd_set_err_code(chip, XD_PRG_ERROR); |
| 985 | else |
| 986 | xd_set_err_code(chip, XD_TO_ERROR); |
| 987 | TRACE_RET(chip, STATUS_FAIL); |
| 988 | } |
| 989 | |
| 990 | return STATUS_SUCCESS; |
| 991 | } |
| 992 | |
| 993 | static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, |
| 994 | u16 logoff, u8 start_page, u8 end_page) |
| 995 | { |
| 996 | struct xd_info *xd_card = &(chip->xd_card); |
| 997 | int retval; |
| 998 | u32 page_addr; |
| 999 | u8 reg = 0; |
| 1000 | |
| 1001 | RTSX_DEBUGP("Init block 0x%x\n", phy_blk); |
| 1002 | |
| 1003 | if (start_page > end_page) |
| 1004 | TRACE_RET(chip, STATUS_FAIL); |
| 1005 | if (phy_blk == BLK_NOT_FOUND) |
| 1006 | TRACE_RET(chip, STATUS_FAIL); |
| 1007 | |
| 1008 | rtsx_init_cmd(chip); |
| 1009 | |
| 1010 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF); |
| 1011 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF); |
| 1012 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, |
| 1013 | 0xFF, (u8)(logoff >> 8)); |
| 1014 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)logoff); |
| 1015 | |
| 1016 | page_addr = (phy_blk << xd_card->block_shift) + start_page; |
| 1017 | |
| 1018 | xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); |
| 1019 | |
| 1020 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, |
| 1021 | XD_BA_TRANSFORM, XD_BA_TRANSFORM); |
| 1022 | |
| 1023 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, |
| 1024 | 0xFF, (end_page - start_page)); |
| 1025 | |
| 1026 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, |
| 1027 | 0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT); |
| 1028 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
| 1029 | XD_TRANSFER_END, XD_TRANSFER_END); |
| 1030 | |
| 1031 | retval = rtsx_send_cmd(chip, XD_CARD, 500); |
| 1032 | if (retval < 0) { |
| 1033 | rtsx_clear_xd_error(chip); |
| 1034 | rtsx_read_register(chip, XD_DAT, ®); |
| 1035 | if (reg & PROGRAM_ERROR) { |
| 1036 | xd_mark_bad_block(chip, phy_blk); |
| 1037 | xd_set_err_code(chip, XD_PRG_ERROR); |
| 1038 | } else { |
| 1039 | xd_set_err_code(chip, XD_TO_ERROR); |
| 1040 | } |
| 1041 | TRACE_RET(chip, STATUS_FAIL); |
| 1042 | } |
| 1043 | |
| 1044 | return STATUS_SUCCESS; |
| 1045 | } |
| 1046 | |
| 1047 | static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk, |
| 1048 | u8 start_page, u8 end_page) |
| 1049 | { |
| 1050 | struct xd_info *xd_card = &(chip->xd_card); |
| 1051 | u32 old_page, new_page; |
| 1052 | u8 i, reg = 0; |
| 1053 | int retval; |
| 1054 | |
| 1055 | RTSX_DEBUGP("Copy page from block 0x%x to block 0x%x\n", |
| 1056 | old_blk, new_blk); |
| 1057 | |
| 1058 | if (start_page > end_page) |
| 1059 | TRACE_RET(chip, STATUS_FAIL); |
| 1060 | |
| 1061 | if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND)) |
| 1062 | TRACE_RET(chip, STATUS_FAIL); |
| 1063 | |
| 1064 | old_page = (old_blk << xd_card->block_shift) + start_page; |
| 1065 | new_page = (new_blk << xd_card->block_shift) + start_page; |
| 1066 | |
| 1067 | XD_CLR_BAD_NEWBLK(xd_card); |
| 1068 | |
| 1069 | RTSX_WRITE_REG(chip, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); |
| 1070 | |
| 1071 | for (i = start_page; i < end_page; i++) { |
| 1072 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { |
| 1073 | rtsx_clear_xd_error(chip); |
| 1074 | xd_set_err_code(chip, XD_NO_CARD); |
| 1075 | TRACE_RET(chip, STATUS_FAIL); |
| 1076 | } |
| 1077 | |
| 1078 | rtsx_init_cmd(chip); |
| 1079 | |
| 1080 | xd_assign_phy_addr(chip, old_page, XD_RW_ADDR); |
| 1081 | |
| 1082 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1); |
| 1083 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, |
| 1084 | XD_AUTO_CHK_DATA_STATUS, 0); |
| 1085 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, |
| 1086 | XD_TRANSFER_START | XD_READ_PAGES); |
| 1087 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
| 1088 | XD_TRANSFER_END, XD_TRANSFER_END); |
| 1089 | |
| 1090 | retval = rtsx_send_cmd(chip, XD_CARD, 500); |
| 1091 | if (retval < 0) { |
| 1092 | rtsx_clear_xd_error(chip); |
| 1093 | reg = 0; |
| 1094 | rtsx_read_register(chip, XD_CTL, ®); |
| 1095 | if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) { |
| 1096 | wait_timeout(100); |
| 1097 | |
| 1098 | if (detect_card_cd(chip, |
| 1099 | XD_CARD) != STATUS_SUCCESS) { |
| 1100 | xd_set_err_code(chip, XD_NO_CARD); |
| 1101 | TRACE_RET(chip, STATUS_FAIL); |
| 1102 | } |
| 1103 | |
| 1104 | if (((reg & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) == |
| 1105 | (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) |
| 1106 | || ((reg & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) == |
| 1107 | (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) { |
| 1108 | rtsx_write_register(chip, |
| 1109 | XD_PAGE_STATUS, 0xFF, |
| 1110 | XD_BPG); |
| 1111 | rtsx_write_register(chip, |
| 1112 | XD_BLOCK_STATUS, 0xFF, |
| 1113 | XD_GBLK); |
| 1114 | XD_SET_BAD_OLDBLK(xd_card); |
| 1115 | RTSX_DEBUGP("old block 0x%x ecc error\n", old_blk); |
| 1116 | } |
| 1117 | } else { |
| 1118 | xd_set_err_code(chip, XD_TO_ERROR); |
| 1119 | TRACE_RET(chip, STATUS_FAIL); |
| 1120 | } |
| 1121 | } |
| 1122 | |
| 1123 | if (XD_CHK_BAD_OLDBLK(xd_card)) |
| 1124 | rtsx_clear_xd_error(chip); |
| 1125 | |
| 1126 | rtsx_init_cmd(chip); |
| 1127 | |
| 1128 | xd_assign_phy_addr(chip, new_page, XD_RW_ADDR); |
| 1129 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1); |
| 1130 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, |
| 1131 | XD_TRANSFER_START | XD_WRITE_PAGES); |
| 1132 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
| 1133 | XD_TRANSFER_END, XD_TRANSFER_END); |
| 1134 | |
| 1135 | retval = rtsx_send_cmd(chip, XD_CARD, 300); |
| 1136 | if (retval < 0) { |
| 1137 | rtsx_clear_xd_error(chip); |
| 1138 | reg = 0; |
| 1139 | rtsx_read_register(chip, XD_DAT, ®); |
| 1140 | if (reg & PROGRAM_ERROR) { |
| 1141 | xd_mark_bad_block(chip, new_blk); |
| 1142 | xd_set_err_code(chip, XD_PRG_ERROR); |
| 1143 | XD_SET_BAD_NEWBLK(xd_card); |
| 1144 | } else { |
| 1145 | xd_set_err_code(chip, XD_TO_ERROR); |
| 1146 | } |
| 1147 | TRACE_RET(chip, STATUS_FAIL); |
| 1148 | } |
| 1149 | |
| 1150 | old_page++; |
| 1151 | new_page++; |
| 1152 | } |
| 1153 | |
| 1154 | return STATUS_SUCCESS; |
| 1155 | } |
| 1156 | |
| 1157 | static int xd_reset_cmd(struct rtsx_chip *chip) |
| 1158 | { |
| 1159 | int retval; |
| 1160 | u8 *ptr; |
| 1161 | |
| 1162 | rtsx_init_cmd(chip); |
| 1163 | |
| 1164 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, |
| 1165 | 0xFF, XD_TRANSFER_START | XD_RESET); |
| 1166 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
| 1167 | XD_TRANSFER_END, XD_TRANSFER_END); |
| 1168 | rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0); |
| 1169 | rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0); |
| 1170 | |
| 1171 | retval = rtsx_send_cmd(chip, XD_CARD, 100); |
| 1172 | if (retval < 0) |
| 1173 | TRACE_RET(chip, STATUS_FAIL); |
| 1174 | |
| 1175 | ptr = rtsx_get_cmd_data(chip) + 1; |
| 1176 | if (((ptr[0] & READY_FLAG) == READY_STATE) && (ptr[1] & XD_RDY)) |
| 1177 | return STATUS_SUCCESS; |
| 1178 | |
| 1179 | TRACE_RET(chip, STATUS_FAIL); |
| 1180 | } |
| 1181 | |
| 1182 | static int xd_erase_block(struct rtsx_chip *chip, u32 phy_blk) |
| 1183 | { |
| 1184 | struct xd_info *xd_card = &(chip->xd_card); |
| 1185 | u32 page_addr; |
| 1186 | u8 reg = 0, *ptr; |
| 1187 | int i, retval; |
| 1188 | |
| 1189 | if (phy_blk == BLK_NOT_FOUND) |
| 1190 | TRACE_RET(chip, STATUS_FAIL); |
| 1191 | |
| 1192 | page_addr = phy_blk << xd_card->block_shift; |
| 1193 | |
| 1194 | for (i = 0; i < 3; i++) { |
| 1195 | rtsx_init_cmd(chip); |
| 1196 | |
| 1197 | xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR); |
| 1198 | |
| 1199 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, |
| 1200 | XD_TRANSFER_START | XD_ERASE); |
| 1201 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
| 1202 | XD_TRANSFER_END, XD_TRANSFER_END); |
| 1203 | rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0); |
| 1204 | |
| 1205 | retval = rtsx_send_cmd(chip, XD_CARD, 250); |
| 1206 | if (retval < 0) { |
| 1207 | rtsx_clear_xd_error(chip); |
| 1208 | rtsx_read_register(chip, XD_DAT, ®); |
| 1209 | if (reg & PROGRAM_ERROR) { |
| 1210 | xd_mark_bad_block(chip, phy_blk); |
| 1211 | xd_set_err_code(chip, XD_PRG_ERROR); |
| 1212 | TRACE_RET(chip, STATUS_FAIL); |
| 1213 | } else { |
| 1214 | xd_set_err_code(chip, XD_ERASE_FAIL); |
| 1215 | } |
| 1216 | retval = xd_reset_cmd(chip); |
| 1217 | if (retval != STATUS_SUCCESS) |
| 1218 | TRACE_RET(chip, STATUS_FAIL); |
| 1219 | continue; |
| 1220 | } |
| 1221 | |
| 1222 | ptr = rtsx_get_cmd_data(chip) + 1; |
| 1223 | if (*ptr & PROGRAM_ERROR) { |
| 1224 | xd_mark_bad_block(chip, phy_blk); |
| 1225 | xd_set_err_code(chip, XD_PRG_ERROR); |
| 1226 | TRACE_RET(chip, STATUS_FAIL); |
| 1227 | } |
| 1228 | |
| 1229 | return STATUS_SUCCESS; |
| 1230 | } |
| 1231 | |
| 1232 | xd_mark_bad_block(chip, phy_blk); |
| 1233 | xd_set_err_code(chip, XD_ERASE_FAIL); |
| 1234 | TRACE_RET(chip, STATUS_FAIL); |
| 1235 | } |
| 1236 | |
| 1237 | |
| 1238 | static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no) |
| 1239 | { |
| 1240 | struct xd_info *xd_card = &(chip->xd_card); |
| 1241 | struct zone_entry *zone; |
| 1242 | int retval; |
| 1243 | u32 start, end, i; |
| 1244 | u16 max_logoff, cur_fst_page_logoff; |
| 1245 | u16 cur_lst_page_logoff, ent_lst_page_logoff; |
| 1246 | u8 redunt[11]; |
| 1247 | |
| 1248 | RTSX_DEBUGP("xd_build_l2p_tbl: %d\n", zone_no); |
| 1249 | |
| 1250 | if (xd_card->zone == NULL) { |
| 1251 | retval = xd_init_l2p_tbl(chip); |
| 1252 | if (retval != STATUS_SUCCESS) |
| 1253 | return retval; |
| 1254 | } |
| 1255 | |
| 1256 | if (xd_card->zone[zone_no].build_flag) { |
| 1257 | RTSX_DEBUGP("l2p table of zone %d has been built\n", zone_no); |
| 1258 | return STATUS_SUCCESS; |
| 1259 | } |
| 1260 | |
| 1261 | zone = &(xd_card->zone[zone_no]); |
| 1262 | |
| 1263 | if (zone->l2p_table == NULL) { |
| 1264 | zone->l2p_table = vmalloc(2000); |
| 1265 | if (zone->l2p_table == NULL) |
| 1266 | TRACE_GOTO(chip, Build_Fail); |
| 1267 | } |
| 1268 | memset((u8 *)(zone->l2p_table), 0xff, 2000); |
| 1269 | |
| 1270 | if (zone->free_table == NULL) { |
| 1271 | zone->free_table = vmalloc(XD_FREE_TABLE_CNT * 2); |
| 1272 | if (zone->free_table == NULL) |
| 1273 | TRACE_GOTO(chip, Build_Fail); |
| 1274 | } |
| 1275 | memset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2); |
| 1276 | |
| 1277 | if (zone_no == 0) { |
| 1278 | if (xd_card->cis_block == 0xFFFF) |
| 1279 | start = 0; |
| 1280 | else |
| 1281 | start = xd_card->cis_block + 1; |
| 1282 | if (XD_CHK_4MB(xd_card)) { |
| 1283 | end = 0x200; |
| 1284 | max_logoff = 499; |
| 1285 | } else { |
| 1286 | end = 0x400; |
| 1287 | max_logoff = 999; |
| 1288 | } |
| 1289 | } else { |
| 1290 | start = (u32)(zone_no) << 10; |
| 1291 | end = (u32)(zone_no + 1) << 10; |
| 1292 | max_logoff = 999; |
| 1293 | } |
| 1294 | |
| 1295 | RTSX_DEBUGP("start block 0x%x, end block 0x%x\n", start, end); |
| 1296 | |
| 1297 | zone->set_index = zone->get_index = 0; |
| 1298 | zone->unused_blk_cnt = 0; |
| 1299 | |
| 1300 | for (i = start; i < end; i++) { |
| 1301 | u32 page_addr = i << xd_card->block_shift; |
| 1302 | u32 phy_block; |
| 1303 | |
| 1304 | retval = xd_read_redundant(chip, page_addr, redunt, 11); |
| 1305 | if (retval != STATUS_SUCCESS) |
| 1306 | continue; |
| 1307 | |
| 1308 | if (redunt[BLOCK_STATUS] != 0xFF) { |
| 1309 | RTSX_DEBUGP("bad block\n"); |
| 1310 | continue; |
| 1311 | } |
| 1312 | |
| 1313 | if (xd_check_data_blank(redunt)) { |
| 1314 | RTSX_DEBUGP("blank block\n"); |
| 1315 | xd_set_unused_block(chip, i); |
| 1316 | continue; |
| 1317 | } |
| 1318 | |
| 1319 | cur_fst_page_logoff = xd_load_log_block_addr(redunt); |
| 1320 | if ((cur_fst_page_logoff == 0xFFFF) || |
| 1321 | (cur_fst_page_logoff > max_logoff)) { |
| 1322 | retval = xd_erase_block(chip, i); |
| 1323 | if (retval == STATUS_SUCCESS) |
| 1324 | xd_set_unused_block(chip, i); |
| 1325 | continue; |
| 1326 | } |
| 1327 | |
| 1328 | if ((zone_no == 0) && (cur_fst_page_logoff == 0) && |
| 1329 | (redunt[PAGE_STATUS] != XD_GPG)) |
| 1330 | XD_SET_MBR_FAIL(xd_card); |
| 1331 | |
| 1332 | if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) { |
| 1333 | zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF); |
| 1334 | continue; |
| 1335 | } |
| 1336 | |
| 1337 | phy_block = zone->l2p_table[cur_fst_page_logoff] + |
| 1338 | ((u32)((zone_no) << 10)); |
| 1339 | |
| 1340 | page_addr = ((i + 1) << xd_card->block_shift) - 1; |
| 1341 | |
| 1342 | retval = xd_read_redundant(chip, page_addr, redunt, 11); |
| 1343 | if (retval != STATUS_SUCCESS) |
| 1344 | continue; |
| 1345 | |
| 1346 | cur_lst_page_logoff = xd_load_log_block_addr(redunt); |
| 1347 | if (cur_lst_page_logoff == cur_fst_page_logoff) { |
| 1348 | int m; |
| 1349 | |
| 1350 | page_addr = ((phy_block + 1) << |
| 1351 | xd_card->block_shift) - 1; |
| 1352 | |
| 1353 | for (m = 0; m < 3; m++) { |
| 1354 | retval = xd_read_redundant(chip, page_addr, |
| 1355 | redunt, 11); |
| 1356 | if (retval == STATUS_SUCCESS) |
| 1357 | break; |
| 1358 | } |
| 1359 | |
| 1360 | if (m == 3) { |
| 1361 | zone->l2p_table[cur_fst_page_logoff] = |
| 1362 | (u16)(i & 0x3FF); |
| 1363 | retval = xd_erase_block(chip, phy_block); |
| 1364 | if (retval == STATUS_SUCCESS) |
| 1365 | xd_set_unused_block(chip, phy_block); |
| 1366 | continue; |
| 1367 | } |
| 1368 | |
| 1369 | ent_lst_page_logoff = xd_load_log_block_addr(redunt); |
| 1370 | if (ent_lst_page_logoff != cur_fst_page_logoff) { |
| 1371 | zone->l2p_table[cur_fst_page_logoff] = |
| 1372 | (u16)(i & 0x3FF); |
| 1373 | retval = xd_erase_block(chip, phy_block); |
| 1374 | if (retval == STATUS_SUCCESS) |
| 1375 | xd_set_unused_block(chip, phy_block); |
| 1376 | continue; |
| 1377 | } else { |
| 1378 | retval = xd_erase_block(chip, i); |
| 1379 | if (retval == STATUS_SUCCESS) |
| 1380 | xd_set_unused_block(chip, i); |
| 1381 | } |
| 1382 | } else { |
| 1383 | retval = xd_erase_block(chip, i); |
| 1384 | if (retval == STATUS_SUCCESS) |
| 1385 | xd_set_unused_block(chip, i); |
| 1386 | } |
| 1387 | } |
| 1388 | |
| 1389 | if (XD_CHK_4MB(xd_card)) |
| 1390 | end = 500; |
| 1391 | else |
| 1392 | end = 1000; |
| 1393 | |
| 1394 | i = 0; |
| 1395 | for (start = 0; start < end; start++) { |
| 1396 | if (zone->l2p_table[start] == 0xFFFF) |
| 1397 | i++; |
| 1398 | } |
| 1399 | |
| 1400 | RTSX_DEBUGP("Block count %d, invalid L2P entry %d\n", end, i); |
| 1401 | RTSX_DEBUGP("Total unused block: %d\n", zone->unused_blk_cnt); |
| 1402 | |
| 1403 | if ((zone->unused_blk_cnt - i) < 1) |
| 1404 | chip->card_wp |= XD_CARD; |
| 1405 | |
| 1406 | zone->build_flag = 1; |
| 1407 | |
| 1408 | return STATUS_SUCCESS; |
| 1409 | |
| 1410 | Build_Fail: |
| 1411 | if (zone->l2p_table) { |
| 1412 | vfree(zone->l2p_table); |
| 1413 | zone->l2p_table = NULL; |
| 1414 | } |
| 1415 | if (zone->free_table) { |
| 1416 | vfree(zone->free_table); |
| 1417 | zone->free_table = NULL; |
| 1418 | } |
| 1419 | |
| 1420 | return STATUS_FAIL; |
| 1421 | } |
| 1422 | |
| 1423 | static int xd_send_cmd(struct rtsx_chip *chip, u8 cmd) |
| 1424 | { |
| 1425 | int retval; |
| 1426 | |
| 1427 | rtsx_init_cmd(chip); |
| 1428 | |
| 1429 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd); |
| 1430 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, |
| 1431 | XD_TRANSFER_START | XD_SET_CMD); |
| 1432 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
| 1433 | XD_TRANSFER_END, XD_TRANSFER_END); |
| 1434 | |
| 1435 | retval = rtsx_send_cmd(chip, XD_CARD, 200); |
| 1436 | if (retval < 0) |
| 1437 | TRACE_RET(chip, STATUS_FAIL); |
| 1438 | |
| 1439 | return STATUS_SUCCESS; |
| 1440 | } |
| 1441 | |
| 1442 | static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk, |
| 1443 | u32 log_blk, u8 start_page, u8 end_page, |
| 1444 | u8 *buf, unsigned int *index, |
| 1445 | unsigned int *offset) |
| 1446 | { |
| 1447 | struct xd_info *xd_card = &(chip->xd_card); |
| 1448 | u32 page_addr, new_blk; |
| 1449 | u16 log_off; |
| 1450 | u8 reg_val, page_cnt; |
| 1451 | int zone_no, retval, i; |
| 1452 | |
| 1453 | if (start_page > end_page) |
| 1454 | TRACE_RET(chip, STATUS_FAIL); |
| 1455 | |
| 1456 | page_cnt = end_page - start_page; |
| 1457 | zone_no = (int)(log_blk / 1000); |
| 1458 | log_off = (u16)(log_blk % 1000); |
| 1459 | |
| 1460 | if ((phy_blk & 0x3FF) == 0x3FF) { |
| 1461 | for (i = 0; i < 256; i++) { |
| 1462 | page_addr = ((u32)i) << xd_card->block_shift; |
| 1463 | |
| 1464 | retval = xd_read_redundant(chip, page_addr, NULL, 0); |
| 1465 | if (retval == STATUS_SUCCESS) |
| 1466 | break; |
| 1467 | |
| 1468 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { |
| 1469 | xd_set_err_code(chip, XD_NO_CARD); |
| 1470 | TRACE_RET(chip, STATUS_FAIL); |
| 1471 | } |
| 1472 | } |
| 1473 | } |
| 1474 | |
| 1475 | page_addr = (phy_blk << xd_card->block_shift) + start_page; |
| 1476 | |
| 1477 | rtsx_init_cmd(chip); |
| 1478 | |
| 1479 | xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); |
| 1480 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE, XD_PPB_TO_SIE); |
| 1481 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); |
| 1482 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt); |
| 1483 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, |
| 1484 | XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS); |
| 1485 | |
| 1486 | trans_dma_enable(chip->srb->sc_data_direction, chip, |
| 1487 | page_cnt * 512, DMA_512); |
| 1488 | |
| 1489 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, |
| 1490 | XD_TRANSFER_START | XD_READ_PAGES); |
| 1491 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
| 1492 | XD_TRANSFER_END | XD_PPB_EMPTY, XD_TRANSFER_END | XD_PPB_EMPTY); |
| 1493 | |
| 1494 | rtsx_send_cmd_no_wait(chip); |
| 1495 | |
| 1496 | retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, |
| 1497 | scsi_sg_count(chip->srb), |
| 1498 | index, offset, DMA_FROM_DEVICE, |
| 1499 | chip->xd_timeout); |
| 1500 | if (retval < 0) { |
| 1501 | rtsx_clear_xd_error(chip); |
| 1502 | |
| 1503 | if (retval == -ETIMEDOUT) { |
| 1504 | xd_set_err_code(chip, XD_TO_ERROR); |
| 1505 | TRACE_RET(chip, STATUS_FAIL); |
| 1506 | } else { |
| 1507 | TRACE_GOTO(chip, Fail); |
| 1508 | } |
| 1509 | } |
| 1510 | |
| 1511 | return STATUS_SUCCESS; |
| 1512 | |
| 1513 | Fail: |
| 1514 | RTSX_READ_REG(chip, XD_PAGE_STATUS, ®_val); |
| 1515 | |
| 1516 | if (reg_val != XD_GPG) |
| 1517 | xd_set_err_code(chip, XD_PRG_ERROR); |
| 1518 | |
| 1519 | RTSX_READ_REG(chip, XD_CTL, ®_val); |
| 1520 | |
| 1521 | if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) |
| 1522 | == (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) |
| 1523 | || ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) |
| 1524 | == (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) { |
| 1525 | wait_timeout(100); |
| 1526 | |
| 1527 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { |
| 1528 | xd_set_err_code(chip, XD_NO_CARD); |
| 1529 | TRACE_RET(chip, STATUS_FAIL); |
| 1530 | } |
| 1531 | |
| 1532 | xd_set_err_code(chip, XD_ECC_ERROR); |
| 1533 | |
| 1534 | new_blk = xd_get_unused_block(chip, zone_no); |
| 1535 | if (new_blk == NO_NEW_BLK) { |
| 1536 | XD_CLR_BAD_OLDBLK(xd_card); |
| 1537 | TRACE_RET(chip, STATUS_FAIL); |
| 1538 | } |
| 1539 | |
| 1540 | retval = xd_copy_page(chip, phy_blk, new_blk, 0, |
| 1541 | xd_card->page_off + 1); |
| 1542 | if (retval != STATUS_SUCCESS) { |
| 1543 | if (!XD_CHK_BAD_NEWBLK(xd_card)) { |
| 1544 | retval = xd_erase_block(chip, new_blk); |
| 1545 | if (retval == STATUS_SUCCESS) |
| 1546 | xd_set_unused_block(chip, new_blk); |
| 1547 | } else { |
| 1548 | XD_CLR_BAD_NEWBLK(xd_card); |
| 1549 | } |
| 1550 | XD_CLR_BAD_OLDBLK(xd_card); |
| 1551 | TRACE_RET(chip, STATUS_FAIL); |
| 1552 | } |
| 1553 | xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF)); |
| 1554 | xd_erase_block(chip, phy_blk); |
| 1555 | xd_mark_bad_block(chip, phy_blk); |
| 1556 | XD_CLR_BAD_OLDBLK(xd_card); |
| 1557 | } |
| 1558 | |
| 1559 | TRACE_RET(chip, STATUS_FAIL); |
| 1560 | } |
| 1561 | |
| 1562 | static int xd_finish_write(struct rtsx_chip *chip, |
| 1563 | u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off) |
| 1564 | { |
| 1565 | struct xd_info *xd_card = &(chip->xd_card); |
| 1566 | int retval, zone_no; |
| 1567 | u16 log_off; |
| 1568 | |
| 1569 | RTSX_DEBUGP("xd_finish_write, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n", |
| 1570 | old_blk, new_blk, log_blk); |
| 1571 | |
| 1572 | if (page_off > xd_card->page_off) |
| 1573 | TRACE_RET(chip, STATUS_FAIL); |
| 1574 | |
| 1575 | zone_no = (int)(log_blk / 1000); |
| 1576 | log_off = (u16)(log_blk % 1000); |
| 1577 | |
| 1578 | if (old_blk == BLK_NOT_FOUND) { |
| 1579 | retval = xd_init_page(chip, new_blk, log_off, |
| 1580 | page_off, xd_card->page_off + 1); |
| 1581 | if (retval != STATUS_SUCCESS) { |
| 1582 | retval = xd_erase_block(chip, new_blk); |
| 1583 | if (retval == STATUS_SUCCESS) |
| 1584 | xd_set_unused_block(chip, new_blk); |
| 1585 | TRACE_RET(chip, STATUS_FAIL); |
| 1586 | } |
| 1587 | } else { |
| 1588 | retval = xd_copy_page(chip, old_blk, new_blk, |
| 1589 | page_off, xd_card->page_off + 1); |
| 1590 | if (retval != STATUS_SUCCESS) { |
| 1591 | if (!XD_CHK_BAD_NEWBLK(xd_card)) { |
| 1592 | retval = xd_erase_block(chip, new_blk); |
| 1593 | if (retval == STATUS_SUCCESS) |
| 1594 | xd_set_unused_block(chip, new_blk); |
| 1595 | } |
| 1596 | XD_CLR_BAD_NEWBLK(xd_card); |
| 1597 | TRACE_RET(chip, STATUS_FAIL); |
| 1598 | } |
| 1599 | |
| 1600 | retval = xd_erase_block(chip, old_blk); |
| 1601 | if (retval == STATUS_SUCCESS) { |
| 1602 | if (XD_CHK_BAD_OLDBLK(xd_card)) { |
| 1603 | xd_mark_bad_block(chip, old_blk); |
| 1604 | XD_CLR_BAD_OLDBLK(xd_card); |
| 1605 | } else { |
| 1606 | xd_set_unused_block(chip, old_blk); |
| 1607 | } |
| 1608 | } else { |
| 1609 | xd_set_err_code(chip, XD_NO_ERROR); |
| 1610 | XD_CLR_BAD_OLDBLK(xd_card); |
| 1611 | } |
| 1612 | } |
| 1613 | |
| 1614 | xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF)); |
| 1615 | |
| 1616 | return STATUS_SUCCESS; |
| 1617 | } |
| 1618 | |
| 1619 | static int xd_prepare_write(struct rtsx_chip *chip, |
| 1620 | u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off) |
| 1621 | { |
| 1622 | int retval; |
| 1623 | |
| 1624 | RTSX_DEBUGP("%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x, page_off = %d\n", |
| 1625 | __func__, old_blk, new_blk, log_blk, (int)page_off); |
| 1626 | |
| 1627 | if (page_off) { |
| 1628 | retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off); |
| 1629 | if (retval != STATUS_SUCCESS) |
| 1630 | TRACE_RET(chip, STATUS_FAIL); |
| 1631 | } |
| 1632 | |
| 1633 | return STATUS_SUCCESS; |
| 1634 | } |
| 1635 | |
| 1636 | |
| 1637 | static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk, |
| 1638 | u32 new_blk, u32 log_blk, u8 start_page, |
| 1639 | u8 end_page, u8 *buf, unsigned int *index, |
| 1640 | unsigned int *offset) |
| 1641 | { |
| 1642 | struct xd_info *xd_card = &(chip->xd_card); |
| 1643 | u32 page_addr; |
| 1644 | int zone_no, retval; |
| 1645 | u16 log_off; |
| 1646 | u8 page_cnt, reg_val; |
| 1647 | |
| 1648 | RTSX_DEBUGP("%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n", |
| 1649 | __func__, old_blk, new_blk, log_blk); |
| 1650 | |
| 1651 | if (start_page > end_page) |
| 1652 | TRACE_RET(chip, STATUS_FAIL); |
| 1653 | |
| 1654 | page_cnt = end_page - start_page; |
| 1655 | zone_no = (int)(log_blk / 1000); |
| 1656 | log_off = (u16)(log_blk % 1000); |
| 1657 | |
| 1658 | page_addr = (new_blk << xd_card->block_shift) + start_page; |
| 1659 | |
| 1660 | retval = xd_send_cmd(chip, READ1_1); |
| 1661 | if (retval != STATUS_SUCCESS) |
| 1662 | TRACE_RET(chip, STATUS_FAIL); |
| 1663 | |
| 1664 | rtsx_init_cmd(chip); |
| 1665 | |
| 1666 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, |
| 1667 | 0xFF, (u8)(log_off >> 8)); |
| 1668 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)log_off); |
| 1669 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK); |
| 1670 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG); |
| 1671 | |
| 1672 | xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); |
| 1673 | |
| 1674 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM, |
| 1675 | XD_BA_TRANSFORM); |
| 1676 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt); |
| 1677 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); |
| 1678 | |
| 1679 | trans_dma_enable(chip->srb->sc_data_direction, chip, |
| 1680 | page_cnt * 512, DMA_512); |
| 1681 | |
| 1682 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, |
| 1683 | 0xFF, XD_TRANSFER_START | XD_WRITE_PAGES); |
| 1684 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
| 1685 | XD_TRANSFER_END, XD_TRANSFER_END); |
| 1686 | |
| 1687 | rtsx_send_cmd_no_wait(chip); |
| 1688 | |
| 1689 | retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, |
| 1690 | scsi_sg_count(chip->srb), |
| 1691 | index, offset, DMA_TO_DEVICE, chip->xd_timeout); |
| 1692 | if (retval < 0) { |
| 1693 | rtsx_clear_xd_error(chip); |
| 1694 | |
| 1695 | if (retval == -ETIMEDOUT) { |
| 1696 | xd_set_err_code(chip, XD_TO_ERROR); |
| 1697 | TRACE_RET(chip, STATUS_FAIL); |
| 1698 | } else { |
| 1699 | TRACE_GOTO(chip, Fail); |
| 1700 | } |
| 1701 | } |
| 1702 | |
| 1703 | if (end_page == (xd_card->page_off + 1)) { |
| 1704 | xd_card->delay_write.delay_write_flag = 0; |
| 1705 | |
| 1706 | if (old_blk != BLK_NOT_FOUND) { |
| 1707 | retval = xd_erase_block(chip, old_blk); |
| 1708 | if (retval == STATUS_SUCCESS) { |
| 1709 | if (XD_CHK_BAD_OLDBLK(xd_card)) { |
| 1710 | xd_mark_bad_block(chip, old_blk); |
| 1711 | XD_CLR_BAD_OLDBLK(xd_card); |
| 1712 | } else { |
| 1713 | xd_set_unused_block(chip, old_blk); |
| 1714 | } |
| 1715 | } else { |
| 1716 | xd_set_err_code(chip, XD_NO_ERROR); |
| 1717 | XD_CLR_BAD_OLDBLK(xd_card); |
| 1718 | } |
| 1719 | } |
| 1720 | xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF)); |
| 1721 | } |
| 1722 | |
| 1723 | return STATUS_SUCCESS; |
| 1724 | |
| 1725 | Fail: |
| 1726 | RTSX_READ_REG(chip, XD_DAT, ®_val); |
| 1727 | if (reg_val & PROGRAM_ERROR) { |
| 1728 | xd_set_err_code(chip, XD_PRG_ERROR); |
| 1729 | xd_mark_bad_block(chip, new_blk); |
| 1730 | } |
| 1731 | |
| 1732 | TRACE_RET(chip, STATUS_FAIL); |
| 1733 | } |
| 1734 | |
| 1735 | #ifdef XD_DELAY_WRITE |
| 1736 | int xd_delay_write(struct rtsx_chip *chip) |
| 1737 | { |
| 1738 | struct xd_info *xd_card = &(chip->xd_card); |
| 1739 | struct xd_delay_write_tag *delay_write = &(xd_card->delay_write); |
| 1740 | int retval; |
| 1741 | |
| 1742 | if (delay_write->delay_write_flag) { |
| 1743 | RTSX_DEBUGP("xd_delay_write\n"); |
| 1744 | retval = xd_switch_clock(chip); |
| 1745 | if (retval != STATUS_SUCCESS) |
| 1746 | TRACE_RET(chip, STATUS_FAIL); |
| 1747 | |
| 1748 | delay_write->delay_write_flag = 0; |
| 1749 | retval = xd_finish_write(chip, |
| 1750 | delay_write->old_phyblock, |
| 1751 | delay_write->new_phyblock, |
| 1752 | delay_write->logblock, delay_write->pageoff); |
| 1753 | if (retval != STATUS_SUCCESS) |
| 1754 | TRACE_RET(chip, STATUS_FAIL); |
| 1755 | } |
| 1756 | |
| 1757 | return STATUS_SUCCESS; |
| 1758 | } |
| 1759 | #endif |
| 1760 | |
| 1761 | int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, |
| 1762 | u32 start_sector, u16 sector_cnt) |
| 1763 | { |
| 1764 | struct xd_info *xd_card = &(chip->xd_card); |
| 1765 | unsigned int lun = SCSI_LUN(srb); |
| 1766 | #ifdef XD_DELAY_WRITE |
| 1767 | struct xd_delay_write_tag *delay_write = &(xd_card->delay_write); |
| 1768 | #endif |
| 1769 | int retval, zone_no; |
| 1770 | unsigned int index = 0, offset = 0; |
| 1771 | u32 log_blk, old_blk = 0, new_blk = 0; |
| 1772 | u16 log_off, total_sec_cnt = sector_cnt; |
| 1773 | u8 start_page, end_page = 0, page_cnt; |
| 1774 | u8 *ptr; |
| 1775 | |
| 1776 | xd_set_err_code(chip, XD_NO_ERROR); |
| 1777 | |
| 1778 | xd_card->cleanup_counter = 0; |
| 1779 | |
| 1780 | RTSX_DEBUGP("xd_rw: scsi_sg_count = %d\n", scsi_sg_count(srb)); |
| 1781 | |
| 1782 | ptr = (u8 *)scsi_sglist(srb); |
| 1783 | |
| 1784 | retval = xd_switch_clock(chip); |
| 1785 | if (retval != STATUS_SUCCESS) |
| 1786 | TRACE_RET(chip, STATUS_FAIL); |
| 1787 | |
| 1788 | |
| 1789 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { |
| 1790 | chip->card_fail |= XD_CARD; |
| 1791 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); |
| 1792 | TRACE_RET(chip, STATUS_FAIL); |
| 1793 | } |
| 1794 | |
| 1795 | log_blk = start_sector >> xd_card->block_shift; |
| 1796 | start_page = (u8)start_sector & xd_card->page_off; |
| 1797 | zone_no = (int)(log_blk / 1000); |
| 1798 | log_off = (u16)(log_blk % 1000); |
| 1799 | |
| 1800 | if (xd_card->zone[zone_no].build_flag == 0) { |
| 1801 | retval = xd_build_l2p_tbl(chip, zone_no); |
| 1802 | if (retval != STATUS_SUCCESS) { |
| 1803 | chip->card_fail |= XD_CARD; |
| 1804 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); |
| 1805 | TRACE_RET(chip, STATUS_FAIL); |
| 1806 | } |
| 1807 | } |
| 1808 | |
| 1809 | if (srb->sc_data_direction == DMA_TO_DEVICE) { |
| 1810 | #ifdef XD_DELAY_WRITE |
| 1811 | if (delay_write->delay_write_flag && |
| 1812 | (delay_write->logblock == log_blk) && |
| 1813 | (start_page > delay_write->pageoff)) { |
| 1814 | delay_write->delay_write_flag = 0; |
| 1815 | if (delay_write->old_phyblock != BLK_NOT_FOUND) { |
| 1816 | retval = xd_copy_page(chip, |
| 1817 | delay_write->old_phyblock, |
| 1818 | delay_write->new_phyblock, |
| 1819 | delay_write->pageoff, start_page); |
| 1820 | if (retval != STATUS_SUCCESS) { |
| 1821 | set_sense_type(chip, lun, |
| 1822 | SENSE_TYPE_MEDIA_WRITE_ERR); |
| 1823 | TRACE_RET(chip, STATUS_FAIL); |
| 1824 | } |
| 1825 | } |
| 1826 | old_blk = delay_write->old_phyblock; |
| 1827 | new_blk = delay_write->new_phyblock; |
| 1828 | } else if (delay_write->delay_write_flag && |
| 1829 | (delay_write->logblock == log_blk) && |
| 1830 | (start_page == delay_write->pageoff)) { |
| 1831 | delay_write->delay_write_flag = 0; |
| 1832 | old_blk = delay_write->old_phyblock; |
| 1833 | new_blk = delay_write->new_phyblock; |
| 1834 | } else { |
| 1835 | retval = xd_delay_write(chip); |
| 1836 | if (retval != STATUS_SUCCESS) { |
| 1837 | set_sense_type(chip, lun, |
| 1838 | SENSE_TYPE_MEDIA_WRITE_ERR); |
| 1839 | TRACE_RET(chip, STATUS_FAIL); |
| 1840 | } |
| 1841 | #endif |
| 1842 | old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); |
| 1843 | new_blk = xd_get_unused_block(chip, zone_no); |
| 1844 | if ((old_blk == BLK_NOT_FOUND) || |
| 1845 | (new_blk == BLK_NOT_FOUND)) { |
| 1846 | set_sense_type(chip, lun, |
| 1847 | SENSE_TYPE_MEDIA_WRITE_ERR); |
| 1848 | TRACE_RET(chip, STATUS_FAIL); |
| 1849 | } |
| 1850 | |
| 1851 | retval = xd_prepare_write(chip, old_blk, new_blk, |
| 1852 | log_blk, start_page); |
| 1853 | if (retval != STATUS_SUCCESS) { |
| 1854 | if (detect_card_cd(chip, XD_CARD) != |
| 1855 | STATUS_SUCCESS) { |
| 1856 | set_sense_type(chip, lun, |
| 1857 | SENSE_TYPE_MEDIA_NOT_PRESENT); |
| 1858 | TRACE_RET(chip, STATUS_FAIL); |
| 1859 | } |
| 1860 | set_sense_type(chip, lun, |
| 1861 | SENSE_TYPE_MEDIA_WRITE_ERR); |
| 1862 | TRACE_RET(chip, STATUS_FAIL); |
| 1863 | } |
| 1864 | #ifdef XD_DELAY_WRITE |
| 1865 | } |
| 1866 | #endif |
| 1867 | } else { |
| 1868 | #ifdef XD_DELAY_WRITE |
| 1869 | retval = xd_delay_write(chip); |
| 1870 | if (retval != STATUS_SUCCESS) { |
| 1871 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { |
| 1872 | set_sense_type(chip, lun, |
| 1873 | SENSE_TYPE_MEDIA_NOT_PRESENT); |
| 1874 | TRACE_RET(chip, STATUS_FAIL); |
| 1875 | } |
| 1876 | set_sense_type(chip, lun, |
| 1877 | SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); |
| 1878 | TRACE_RET(chip, STATUS_FAIL); |
| 1879 | } |
| 1880 | #endif |
| 1881 | |
| 1882 | old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); |
| 1883 | if (old_blk == BLK_NOT_FOUND) { |
| 1884 | set_sense_type(chip, lun, |
| 1885 | SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); |
| 1886 | TRACE_RET(chip, STATUS_FAIL); |
| 1887 | } |
| 1888 | } |
| 1889 | |
| 1890 | RTSX_DEBUGP("old_blk = 0x%x\n", old_blk); |
| 1891 | |
| 1892 | while (total_sec_cnt) { |
| 1893 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { |
| 1894 | chip->card_fail |= XD_CARD; |
| 1895 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); |
| 1896 | TRACE_RET(chip, STATUS_FAIL); |
| 1897 | } |
| 1898 | |
| 1899 | if ((start_page + total_sec_cnt) > (xd_card->page_off + 1)) |
| 1900 | end_page = xd_card->page_off + 1; |
| 1901 | else |
| 1902 | end_page = start_page + (u8)total_sec_cnt; |
| 1903 | |
| 1904 | page_cnt = end_page - start_page; |
| 1905 | if (srb->sc_data_direction == DMA_FROM_DEVICE) { |
| 1906 | retval = xd_read_multiple_pages(chip, old_blk, log_blk, |
| 1907 | start_page, end_page, ptr, |
| 1908 | &index, &offset); |
| 1909 | if (retval != STATUS_SUCCESS) { |
| 1910 | set_sense_type(chip, lun, |
| 1911 | SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); |
| 1912 | TRACE_RET(chip, STATUS_FAIL); |
| 1913 | } |
| 1914 | } else { |
| 1915 | retval = xd_write_multiple_pages(chip, old_blk, |
| 1916 | new_blk, log_blk, |
| 1917 | start_page, end_page, ptr, |
| 1918 | &index, &offset); |
| 1919 | if (retval != STATUS_SUCCESS) { |
| 1920 | set_sense_type(chip, lun, |
| 1921 | SENSE_TYPE_MEDIA_WRITE_ERR); |
| 1922 | TRACE_RET(chip, STATUS_FAIL); |
| 1923 | } |
| 1924 | } |
| 1925 | |
| 1926 | total_sec_cnt -= page_cnt; |
| 1927 | if (scsi_sg_count(srb) == 0) |
| 1928 | ptr += page_cnt * 512; |
| 1929 | |
| 1930 | if (total_sec_cnt == 0) |
| 1931 | break; |
| 1932 | |
| 1933 | log_blk++; |
| 1934 | zone_no = (int)(log_blk / 1000); |
| 1935 | log_off = (u16)(log_blk % 1000); |
| 1936 | |
| 1937 | if (xd_card->zone[zone_no].build_flag == 0) { |
| 1938 | retval = xd_build_l2p_tbl(chip, zone_no); |
| 1939 | if (retval != STATUS_SUCCESS) { |
| 1940 | chip->card_fail |= XD_CARD; |
| 1941 | set_sense_type(chip, lun, |
| 1942 | SENSE_TYPE_MEDIA_NOT_PRESENT); |
| 1943 | TRACE_RET(chip, STATUS_FAIL); |
| 1944 | } |
| 1945 | } |
| 1946 | |
| 1947 | old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); |
| 1948 | if (old_blk == BLK_NOT_FOUND) { |
| 1949 | if (srb->sc_data_direction == DMA_FROM_DEVICE) |
| 1950 | set_sense_type(chip, lun, |
| 1951 | SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); |
| 1952 | else |
| 1953 | set_sense_type(chip, lun, |
| 1954 | SENSE_TYPE_MEDIA_WRITE_ERR); |
| 1955 | |
| 1956 | TRACE_RET(chip, STATUS_FAIL); |
| 1957 | } |
| 1958 | |
| 1959 | if (srb->sc_data_direction == DMA_TO_DEVICE) { |
| 1960 | new_blk = xd_get_unused_block(chip, zone_no); |
| 1961 | if (new_blk == BLK_NOT_FOUND) { |
| 1962 | set_sense_type(chip, lun, |
| 1963 | SENSE_TYPE_MEDIA_WRITE_ERR); |
| 1964 | TRACE_RET(chip, STATUS_FAIL); |
| 1965 | } |
| 1966 | } |
| 1967 | |
| 1968 | start_page = 0; |
| 1969 | } |
| 1970 | |
| 1971 | if ((srb->sc_data_direction == DMA_TO_DEVICE) && |
| 1972 | (end_page != (xd_card->page_off + 1))) { |
| 1973 | #ifdef XD_DELAY_WRITE |
| 1974 | delay_write->delay_write_flag = 1; |
| 1975 | delay_write->old_phyblock = old_blk; |
| 1976 | delay_write->new_phyblock = new_blk; |
| 1977 | delay_write->logblock = log_blk; |
| 1978 | delay_write->pageoff = end_page; |
| 1979 | #else |
| 1980 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { |
| 1981 | chip->card_fail |= XD_CARD; |
| 1982 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); |
| 1983 | TRACE_RET(chip, STATUS_FAIL); |
| 1984 | } |
| 1985 | |
| 1986 | retval = xd_finish_write(chip, old_blk, new_blk, |
| 1987 | log_blk, end_page); |
| 1988 | if (retval != STATUS_SUCCESS) { |
| 1989 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { |
| 1990 | set_sense_type(chip, lun, |
| 1991 | SENSE_TYPE_MEDIA_NOT_PRESENT); |
| 1992 | TRACE_RET(chip, STATUS_FAIL); |
| 1993 | } |
| 1994 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR); |
| 1995 | TRACE_RET(chip, STATUS_FAIL); |
| 1996 | } |
| 1997 | #endif |
| 1998 | } |
| 1999 | |
| 2000 | scsi_set_resid(srb, 0); |
| 2001 | |
| 2002 | return STATUS_SUCCESS; |
| 2003 | } |
| 2004 | |
| 2005 | void xd_free_l2p_tbl(struct rtsx_chip *chip) |
| 2006 | { |
| 2007 | struct xd_info *xd_card = &(chip->xd_card); |
| 2008 | int i = 0; |
| 2009 | |
| 2010 | if (xd_card->zone != NULL) { |
| 2011 | for (i = 0; i < xd_card->zone_cnt; i++) { |
| 2012 | if (xd_card->zone[i].l2p_table != NULL) { |
| 2013 | vfree(xd_card->zone[i].l2p_table); |
| 2014 | xd_card->zone[i].l2p_table = NULL; |
| 2015 | } |
| 2016 | if (xd_card->zone[i].free_table != NULL) { |
| 2017 | vfree(xd_card->zone[i].free_table); |
| 2018 | xd_card->zone[i].free_table = NULL; |
| 2019 | } |
| 2020 | } |
| 2021 | vfree(xd_card->zone); |
| 2022 | xd_card->zone = NULL; |
| 2023 | } |
| 2024 | } |
| 2025 | |
| 2026 | void xd_cleanup_work(struct rtsx_chip *chip) |
| 2027 | { |
| 2028 | #ifdef XD_DELAY_WRITE |
| 2029 | struct xd_info *xd_card = &(chip->xd_card); |
| 2030 | |
| 2031 | if (xd_card->delay_write.delay_write_flag) { |
| 2032 | RTSX_DEBUGP("xD: delay write\n"); |
| 2033 | xd_delay_write(chip); |
| 2034 | xd_card->cleanup_counter = 0; |
| 2035 | } |
| 2036 | #endif |
| 2037 | } |
| 2038 | |
| 2039 | int xd_power_off_card3v3(struct rtsx_chip *chip) |
| 2040 | { |
| 2041 | int retval; |
| 2042 | |
| 2043 | retval = disable_card_clock(chip, XD_CARD); |
| 2044 | if (retval != STATUS_SUCCESS) |
| 2045 | TRACE_RET(chip, STATUS_FAIL); |
| 2046 | |
| 2047 | RTSX_WRITE_REG(chip, CARD_OE, XD_OUTPUT_EN, 0); |
| 2048 | |
| 2049 | if (!chip->ft2_fast_mode) { |
| 2050 | retval = card_power_off(chip, XD_CARD); |
| 2051 | if (retval != STATUS_SUCCESS) |
| 2052 | TRACE_RET(chip, STATUS_FAIL); |
| 2053 | |
| 2054 | wait_timeout(50); |
| 2055 | } |
| 2056 | |
| 2057 | if (chip->asic_code) { |
| 2058 | retval = xd_pull_ctl_disable(chip); |
| 2059 | if (retval != STATUS_SUCCESS) |
| 2060 | TRACE_RET(chip, STATUS_FAIL); |
| 2061 | } else { |
| 2062 | RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, 0xDF); |
| 2063 | } |
| 2064 | |
| 2065 | return STATUS_SUCCESS; |
| 2066 | } |
| 2067 | |
| 2068 | int release_xd_card(struct rtsx_chip *chip) |
| 2069 | { |
| 2070 | struct xd_info *xd_card = &(chip->xd_card); |
| 2071 | int retval; |
| 2072 | |
| 2073 | RTSX_DEBUGP("release_xd_card\n"); |
| 2074 | |
| 2075 | chip->card_ready &= ~XD_CARD; |
| 2076 | chip->card_fail &= ~XD_CARD; |
| 2077 | chip->card_wp &= ~XD_CARD; |
| 2078 | |
| 2079 | xd_card->delay_write.delay_write_flag = 0; |
| 2080 | |
| 2081 | xd_free_l2p_tbl(chip); |
| 2082 | |
| 2083 | retval = xd_power_off_card3v3(chip); |
| 2084 | if (retval != STATUS_SUCCESS) |
| 2085 | TRACE_RET(chip, STATUS_FAIL); |
| 2086 | |
| 2087 | return STATUS_SUCCESS; |
| 2088 | } |