Steven Rostedt | 68a8129 | 2012-11-16 09:28:49 -0500 | [diff] [blame] | 1 | |
| 2 | /* |
| 3 | * SB105X_UART.h |
| 4 | * |
| 5 | * Copyright (C) 2008 systembase |
| 6 | * |
| 7 | * UART registers. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | */ |
| 14 | |
| 15 | #ifndef UART_SB105X_H |
| 16 | #define UART_SB105X_H |
| 17 | |
Ashvini Varatharaj | 8cedb1b | 2013-10-17 21:36:43 +0530 | [diff] [blame] | 18 | /* |
| 19 | * option register |
Steven Rostedt | 68a8129 | 2012-11-16 09:28:49 -0500 | [diff] [blame] | 20 | */ |
| 21 | |
Masanari Iida | 6198312 | 2013-03-24 23:24:00 +0900 | [diff] [blame] | 22 | /* Device Information Register */ |
Steven Rostedt | 68a8129 | 2012-11-16 09:28:49 -0500 | [diff] [blame] | 23 | #define MP_OPTR_DIR0 0x04 /* port0 ~ port8 */ |
| 24 | #define MP_OPTR_DIR1 0x05 /* port8 ~ port15 */ |
| 25 | #define MP_OPTR_DIR2 0x06 /* port16 ~ port23 */ |
| 26 | #define MP_OPTR_DIR3 0x07 /* port24 ~ port31 */ |
| 27 | |
| 28 | #define DIR_UART_16C550 0 |
| 29 | #define DIR_UART_16C1050 1 |
| 30 | #define DIR_UART_16C1050A 2 |
| 31 | |
| 32 | #define DIR_CLK_1843200 0x0 /* input clock 1843200 Hz */ |
| 33 | #define DIR_CLK_3686400 0x1 /* input clock 3686400 Hz */ |
| 34 | #define DIR_CLK_7372800 0x2 /* input clock 7372800 Hz */ |
| 35 | #define DIR_CLK_14745600 0x3 /* input clock 14745600 Hz */ |
| 36 | #define DIR_CLK_29491200 0x4 /* input clock 29491200 Hz */ |
| 37 | #define DIR_CLK_58985400 0x5 /* input clock 58985400 Hz */ |
| 38 | |
| 39 | /* Interface Information Register */ |
| 40 | #define MP_OPTR_IIR0 0x08 /* port0 ~ port8 */ |
| 41 | #define MP_OPTR_IIR1 0x09 /* port8 ~ port15 */ |
| 42 | #define MP_OPTR_IIR2 0x0A /* port16 ~ port23 */ |
| 43 | #define MP_OPTR_IIR3 0x0B /* port24 ~ port31 */ |
| 44 | |
| 45 | #define IIR_RS232 0x00 /* RS232 type */ |
| 46 | #define IIR_RS422 0x10 /* RS422 type */ |
| 47 | #define IIR_RS485 0x20 /* RS485 type */ |
Dan Carpenter | c803dd4 | 2013-01-09 10:12:14 +0300 | [diff] [blame] | 48 | #define IIR_TYPE_MASK 0x30 |
Steven Rostedt | 68a8129 | 2012-11-16 09:28:49 -0500 | [diff] [blame] | 49 | |
Masanari Iida | 6198312 | 2013-03-24 23:24:00 +0900 | [diff] [blame] | 50 | /* Interrupt Mask Register */ |
Steven Rostedt | 68a8129 | 2012-11-16 09:28:49 -0500 | [diff] [blame] | 51 | #define MP_OPTR_IMR0 0x0C /* port0 ~ port8 */ |
| 52 | #define MP_OPTR_IMR1 0x0D /* port8 ~ port15 */ |
| 53 | #define MP_OPTR_IMR2 0x0E /* port16 ~ port23 */ |
| 54 | #define MP_OPTR_IMR3 0x0F /* port24 ~ port31 */ |
| 55 | |
| 56 | /* Interrupt Poll Register */ |
| 57 | #define MP_OPTR_IPR0 0x10 /* port0 ~ port8 */ |
| 58 | #define MP_OPTR_IPR1 0x11 /* port8 ~ port15 */ |
| 59 | #define MP_OPTR_IPR2 0x12 /* port16 ~ port23 */ |
| 60 | #define MP_OPTR_IPR3 0x13 /* port24 ~ port31 */ |
| 61 | |
| 62 | /* General Purpose Output Control Register */ |
| 63 | #define MP_OPTR_GPOCR 0x20 |
| 64 | |
| 65 | /* General Purpose Output Data Register */ |
| 66 | #define MP_OPTR_GPODR 0x21 |
| 67 | |
| 68 | /* Parallel Additional Function Register */ |
| 69 | #define MP_OPTR_PAFR 0x23 |
| 70 | |
| 71 | /* |
| 72 | * systembase 16c105x UART register |
| 73 | */ |
| 74 | |
| 75 | #define PAGE_0 0 |
| 76 | #define PAGE_1 1 |
| 77 | #define PAGE_2 2 |
| 78 | #define PAGE_3 3 |
| 79 | #define PAGE_4 4 |
| 80 | |
| 81 | /* |
| 82 | * ****************************************************************** |
| 83 | * * DLAB=0 =============== Page 0 Registers * |
| 84 | * ****************************************************************** |
| 85 | */ |
| 86 | |
| 87 | #define SB105X_RX 0 /* In: Receive buffer */ |
| 88 | #define SB105X_TX 0 /* Out: Transmit buffer */ |
| 89 | |
| 90 | #define SB105X_IER 1 /* Out: Interrupt Enable Register */ |
| 91 | |
| 92 | #define SB105X_IER_CTSI 0x80 /* CTS# Interrupt Enable (Requires EFR[4] = 1) */ |
| 93 | #define SB105X_IER_RTSI 0x40 /* RTS# Interrupt Enable (Requires EFR[4] = 1) */ |
| 94 | #define SB105X_IER_XOI 0x20 /* Xoff Interrupt Enable (Requires EFR[4] = 1) */ |
| 95 | #define SB105X_IER_SME 0x10 /* Sleep Mode Enable (Requires EFR[4] = 1) */ |
| 96 | #define SB105X_IER_MSI 0x08 /* Enable Modem status interrupt */ |
| 97 | #define SB105X_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
| 98 | #define SB105X_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
| 99 | #define SB105X_IER_RDI 0x01 /* Enable receiver data interrupt */ |
| 100 | |
| 101 | #define SB105X_ISR 2 /* In: Interrupt ID Register */ |
| 102 | |
| 103 | #define SB105X_ISR_NOINT 0x01 /* No interrupts pending */ |
| 104 | #define SB105X_ISR_RLSI 0x06 /* Receiver line status interrupt (Priority = 1)*/ |
| 105 | #define SB105X_ISR_RDAI 0x0c /* Receive Data Available interrupt */ |
| 106 | #define SB105X_ISR_CTII 0x04 /* Character Timeout Indication interrupt */ |
| 107 | #define SB105X_ISR_THRI 0x02 /* Transmitter holding register empty */ |
| 108 | #define SB105X_ISR_MSI 0x00 /* Modem status interrupt */ |
| 109 | #define SB105X_ISR_RXCI 0x10 /* Receive Xoff or Special Character interrupt */ |
| 110 | #define SB105X_ISR_RCSI 0x20 /* RTS#, CTS# status interrupt during Auto RTS/CTS flow control */ |
| 111 | |
| 112 | #define SB105X_FCR 2 /* Out: FIFO Control Register */ |
| 113 | |
| 114 | #define SB105X_FCR_FEN 0x01 /* FIFO Enable */ |
| 115 | #define SB105X_FCR_RXFR 0x02 /* RX FIFO Reset */ |
| 116 | #define SB105X_FCR_TXFR 0x04 /* TX FIFO Reset */ |
| 117 | #define SB105X_FCR_DMS 0x08 /* DMA Mode Select */ |
| 118 | |
Masanari Iida | e8c794d | 2013-11-26 23:55:13 +0900 | [diff] [blame] | 119 | #define SB105X_FCR_RTR08 0x00 /* Receive Trigger Level set at 8 */ |
| 120 | #define SB105X_FCR_RTR16 0x40 /* Receive Trigger Level set at 16 */ |
| 121 | #define SB105X_FCR_RTR56 0x80 /* Receive Trigger Level set at 56 */ |
| 122 | #define SB105X_FCR_RTR60 0xc0 /* Receive Trigger Level set at 60 */ |
Steven Rostedt | 68a8129 | 2012-11-16 09:28:49 -0500 | [diff] [blame] | 123 | #define SB105X_FCR_TTR08 0x00 /* Transmit Trigger Level set at 8 */ |
| 124 | #define SB105X_FCR_TTR16 0x10 /* Transmit Trigger Level set at 16 */ |
| 125 | #define SB105X_FCR_TTR32 0x20 /* Transmit Trigger Level set at 32 */ |
| 126 | #define SB105X_FCR_TTR56 0x30 /* Transmit Trigger Level set at 56 */ |
| 127 | |
| 128 | #define SB105X_LCR 3 /* Out: Line Control Register */ |
| 129 | /* |
| 130 | * * Note: if the word length is 5 bits (SB105X_LCR_WLEN5), then setting |
| 131 | * * SB105X_LCR_STOP will select 1.5 stop bits, not 2 stop bits. |
| 132 | */ |
| 133 | #define SB105X_LCR_DLAB 0x80 /* Divisor Latch Enable */ |
| 134 | #define SB105X_LCR_SBC 0x40 /* Break Enable*/ |
| 135 | #define SB105X_LCR_SPAR 0x20 /* Set Stick parity */ |
| 136 | #define SB105X_LCR_EPAR 0x10 /* Even parity select */ |
| 137 | #define SB105X_LCR_PAREN 0x08 /* Parity Enable */ |
| 138 | #define SB105X_LCR_STOP 0x04 /* Stop bits: 0->1 bit, 1->2 bits, 1 and SB105X_LCR_WLEN5 -> 1.5 bit */ |
| 139 | #define SB105X_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ |
| 140 | #define SB105X_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ |
| 141 | #define SB105X_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ |
| 142 | #define SB105X_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ |
| 143 | |
| 144 | #define SB105X_LCR_BF 0xBF |
| 145 | |
| 146 | #define SB105X_MCR 4 /* Out: Modem Control Register */ |
| 147 | #define SB105X_MCR_CPS 0x80 /* Clock Prescaler Select */ |
| 148 | #define SB105X_MCR_P2S 0x40 /* Page 2 Select /Xoff Re-Transmit Access Enable */ |
| 149 | #define SB105X_MCR_XOA 0x20 /* Xon Any Enable */ |
| 150 | #define SB105X_MCR_ILB 0x10 /* Internal Loopback Enable */ |
| 151 | #define SB105X_MCR_OUT2 0x08 /* Out2/Interrupt Output Enable*/ |
| 152 | #define SB105X_MCR_OUT1 0x04 /* Out1/Interrupt Output Enable */ |
| 153 | #define SB105X_MCR_RTS 0x02 /* RTS# Output */ |
| 154 | #define SB105X_MCR_DTR 0x01 /* DTR# Output */ |
| 155 | |
| 156 | #define SB105X_LSR 5 /* In: Line Status Register */ |
| 157 | #define SB105X_LSR_RFEI 0x80 /* Receive FIFO data error Indicator */ |
| 158 | #define SB105X_LSR_TEMI 0x40 /* THR and TSR Empty Indicator */ |
| 159 | #define SB105X_LSR_THRE 0x20 /* THR Empty Indicator */ |
| 160 | #define SB105X_LSR_BII 0x10 /* Break interrupt indicator */ |
| 161 | #define SB105X_LSR_FEI 0x08 /* Frame error indicator */ |
| 162 | #define SB105X_LSR_PEI 0x04 /* Parity error indicator */ |
| 163 | #define SB105X_LSR_OEI 0x02 /* Overrun error indicator */ |
| 164 | #define SB105X_LSR_RDRI 0x01 /* Receive data ready Indicator*/ |
| 165 | |
| 166 | #define SB105X_MSR 6 /* In: Modem Status Register */ |
| 167 | #define SB105X_MSR_DCD 0x80 /* Data Carrier Detect */ |
| 168 | #define SB105X_MSR_RI 0x40 /* Ring Indicator */ |
| 169 | #define SB105X_MSR_DSR 0x20 /* Data Set Ready */ |
| 170 | #define SB105X_MSR_CTS 0x10 /* Clear to Send */ |
| 171 | #define SB105X_MSR_DDCD 0x08 /* Delta DCD */ |
| 172 | #define SB105X_MSR_DRI 0x04 /* Delta ring indicator */ |
| 173 | #define SB105X_MSR_DDSR 0x02 /* Delta DSR */ |
| 174 | #define SB105X_MSR_DCTS 0x01 /* Delta CTS */ |
| 175 | |
| 176 | #define SB105XA_MDR 6 /* Out: Multi Drop mode Register */ |
| 177 | #define SB105XA_MDR_NPS 0x08 /* 9th Bit Polarity Select */ |
| 178 | #define SB105XA_MDR_AME 0x02 /* Auto Multi-drop Enable */ |
| 179 | #define SB105XA_MDR_MDE 0x01 /* Multi Drop Enable */ |
| 180 | |
| 181 | #define SB105X_SPR 7 /* I/O: Scratch Register */ |
| 182 | |
| 183 | /* |
| 184 | * DLAB=1 |
| 185 | */ |
| 186 | #define SB105X_DLL 0 /* Out: Divisor Latch Low */ |
| 187 | #define SB105X_DLM 1 /* Out: Divisor Latch High */ |
| 188 | |
| 189 | /* |
| 190 | * ****************************************************************** |
| 191 | * * DLAB(LCR[7]) = 0 , MCR[6] = 1 ============= Page 2 Registers * |
| 192 | * ****************************************************************** |
| 193 | */ |
| 194 | #define SB105X_GICR 1 /* Global Interrupt Control Register */ |
| 195 | #define SB105X_GICR_GIM 0x01 /* Global Interrupt Mask */ |
| 196 | |
| 197 | #define SB105X_GISR 2 /* Global Interrupt Status Register */ |
| 198 | #define SB105X_GISR_MGICR0 0x80 /* Mirror the content of GICR[0] */ |
| 199 | #define SB105X_GISR_CS3IS 0x08 /* SB105X of CS3# Interrupt Status */ |
| 200 | #define SB105X_GISR_CS2IS 0x04 /* SB105X of CS2# Interrupt Status */ |
| 201 | #define SB105X_GISR_CS1IS 0x02 /* SB105X of CS1# Interrupt Status */ |
| 202 | #define SB105X_GISR_CS0IS 0x01 /* SB105X of CS0# Interrupt Status */ |
| 203 | |
| 204 | #define SB105X_TFCR 5 /* Transmit FIFO Count Register */ |
| 205 | |
| 206 | #define SB105X_RFCR 6 /* Receive FIFO Count Register */ |
| 207 | |
| 208 | #define SB105X_FSR 7 /* Flow Control Status Register */ |
| 209 | #define SB105X_FSR_THFS 0x20 /* Transmit Hardware Flow Control Status */ |
| 210 | #define SB105X_FSR_TSFS 0x10 /* Transmit Software Flow Control Status */ |
| 211 | #define SB105X_FSR_RHFS 0x02 /* Receive Hardware Flow Control Status */ |
| 212 | #define SB105X_FSR_RSFS 0x01 /* Receive Software Flow Control Status */ |
| 213 | |
| 214 | /* |
| 215 | * ****************************************************************** |
| 216 | * * LCR = 0xBF, PSR[0] = 0 ============= Page 3 Registers * |
| 217 | * ****************************************************************** |
| 218 | */ |
| 219 | |
| 220 | #define SB105X_PSR 0 /* Page Select Register */ |
| 221 | #define SB105X_PSR_P3KEY 0xA4 /* Page 3 Select Key */ |
| 222 | #define SB105X_PSR_P4KEY 0xA5 /* Page 5 Select Key */ |
| 223 | |
| 224 | #define SB105X_ATR 1 /* Auto Toggle Control Register */ |
| 225 | #define SB105X_ATR_RPS 0x80 /* RXEN Polarity Select */ |
| 226 | #define SB105X_ATR_RCMS 0x40 /* RXEN Control Mode Select */ |
| 227 | #define SB105X_ATR_TPS 0x20 /* TXEN Polarity Select */ |
| 228 | #define SB105X_ATR_TCMS 0x10 /* TXEN Control Mode Select */ |
| 229 | #define SB105X_ATR_ATDIS 0x00 /* Auto Toggle is disabled */ |
| 230 | #define SB105X_ATR_ART 0x01 /* RTS#/TXEN pin operates as TXEN */ |
| 231 | #define SB105X_ATR_ADT 0x02 /* DTR#/TXEN pin operates as TXEN */ |
| 232 | #define SB105X_ATR_A80 0x03 /* only in 80 pin use */ |
| 233 | |
| 234 | #define SB105X_EFR 2 /* (Auto) Enhanced Feature Register */ |
| 235 | #define SB105X_EFR_ACTS 0x80 /* Auto-CTS Flow Control Enable */ |
| 236 | #define SB105X_EFR_ARTS 0x40 /* Auto-RTS Flow Control Enable */ |
| 237 | #define SB105X_EFR_SCD 0x20 /* Special Character Detect */ |
| 238 | #define SB105X_EFR_EFBEN 0x10 /* Enhanced Function Bits Enable */ |
| 239 | |
| 240 | #define SB105X_XON1 4 /* Xon1 Character Register */ |
| 241 | #define SB105X_XON2 5 /* Xon2 Character Register */ |
| 242 | #define SB105X_XOFF1 6 /* Xoff1 Character Register */ |
| 243 | #define SB105X_XOFF2 7 /* Xoff2 Character Register */ |
| 244 | |
| 245 | /* |
| 246 | * ****************************************************************** |
| 247 | * * LCR = 0xBF, PSR[0] = 1 ============ Page 4 Registers * |
| 248 | * ****************************************************************** |
| 249 | */ |
| 250 | |
| 251 | #define SB105X_AFR 1 /* Additional Feature Register */ |
| 252 | #define SB105X_AFR_GIPS 0x20 /* Global Interrupt Polarity Select */ |
| 253 | #define SB105X_AFR_GIEN 0x10 /* Global Interrupt Enable */ |
| 254 | #define SB105X_AFR_AFEN 0x01 /* 256-byte FIFO Enable */ |
| 255 | |
| 256 | #define SB105X_XRCR 2 /* Xoff Re-transmit Count Register */ |
| 257 | #define SB105X_XRCR_NRC1 0x00 /* Transmits Xoff Character whenever the number of received data is 1 during XOFF status */ |
| 258 | #define SB105X_XRCR_NRC4 0x01 /* Transmits Xoff Character whenever the number of received data is 4 during XOFF status */ |
| 259 | #define SB105X_XRCR_NRC8 0x02 /* Transmits Xoff Character whenever the number of received data is 8 during XOFF status */ |
| 260 | #define SB105X_XRCR_NRC16 0x03 /* Transmits Xoff Character whenever the number of received data is 16 during XOFF status */ |
| 261 | |
| 262 | #define SB105X_TTR 4 /* Transmit FIFO Trigger Level Register */ |
| 263 | #define SB105X_RTR 5 /* Receive FIFO Trigger Level Register */ |
| 264 | #define SB105X_FUR 6 /* Flow Control Upper Threshold Register */ |
| 265 | #define SB105X_FLR 7 /* Flow Control Lower Threshold Register */ |
| 266 | |
| 267 | |
| 268 | /* page 0 */ |
| 269 | |
| 270 | #define SB105X_GET_CHAR(port) inb((port)->iobase + SB105X_RX) |
| 271 | #define SB105X_GET_IER(port) inb((port)->iobase + SB105X_IER) |
| 272 | #define SB105X_GET_ISR(port) inb((port)->iobase + SB105X_ISR) |
| 273 | #define SB105X_GET_LCR(port) inb((port)->iobase + SB105X_LCR) |
| 274 | #define SB105X_GET_MCR(port) inb((port)->iobase + SB105X_MCR) |
| 275 | #define SB105X_GET_LSR(port) inb((port)->iobase + SB105X_LSR) |
| 276 | #define SB105X_GET_MSR(port) inb((port)->iobase + SB105X_MSR) |
| 277 | #define SB105X_GET_SPR(port) inb((port)->iobase + SB105X_SPR) |
| 278 | |
| 279 | #define SB105X_PUT_CHAR(port,v) outb((v),(port)->iobase + SB105X_TX ) |
| 280 | #define SB105X_PUT_IER(port,v) outb((v),(port)->iobase + SB105X_IER ) |
| 281 | #define SB105X_PUT_FCR(port,v) outb((v),(port)->iobase + SB105X_FCR ) |
| 282 | #define SB105X_PUT_LCR(port,v) outb((v),(port)->iobase + SB105X_LCR ) |
| 283 | #define SB105X_PUT_MCR(port,v) outb((v),(port)->iobase + SB105X_MCR ) |
| 284 | #define SB105X_PUT_SPR(port,v) outb((v),(port)->iobase + SB105X_SPR ) |
| 285 | |
| 286 | |
| 287 | /* page 1 */ |
| 288 | #define SB105X_GET_REG(port,reg) inb((port)->iobase + (reg)) |
| 289 | #define SB105X_PUT_REG(port,reg,v) outb((v),(port)->iobase + (reg)) |
| 290 | |
| 291 | /* page 2 */ |
| 292 | |
| 293 | #define SB105X_PUT_PSR(port,v) outb((v),(port)->iobase + SB105X_PSR ) |
| 294 | |
| 295 | #endif |