| Michael Hennerich | cd1678f | 2012-05-29 12:41:19 +0200 | [diff] [blame] | 1 | What: /sys/bus/iio/devices/iio:deviceX/pll2_feedback_clk_present |
| 2 | What: /sys/bus/iio/devices/iio:deviceX/pll2_reference_clk_present |
| 3 | What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_a_present |
| 4 | What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_b_present |
| 5 | What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_test_present |
| 6 | What: /sys/bus/iio/devices/iio:deviceX/vcxo_clk_present |
| 7 | KernelVersion: 3.4.0 |
| 8 | Contact: linux-iio@vger.kernel.org |
| 9 | Description: |
| 10 | Reading returns either '1' or '0'. |
| 11 | '1' means that the clock in question is present. |
| 12 | '0' means that the clock is missing. |
| 13 | |
| 14 | What: /sys/bus/iio/devices/iio:deviceX/pllY_locked |
| 15 | KernelVersion: 3.4.0 |
| 16 | Contact: linux-iio@vger.kernel.org |
| 17 | Description: |
| 18 | Reading returns either '1' or '0'. '1' means that the |
| 19 | pllY is locked. |
| 20 | |
| Michael Hennerich | cd1678f | 2012-05-29 12:41:19 +0200 | [diff] [blame] | 21 | What: /sys/bus/iio/devices/iio:deviceX/sync_dividers |
| 22 | KernelVersion: 3.4.0 |
| 23 | Contact: linux-iio@vger.kernel.org |
| 24 | Description: |
| 25 | Writing '1' triggers the clock distribution synchronization |
| 26 | functionality. All dividers are reset and the channels start |
| 27 | with their predefined phase offsets (out_altvoltageY_phase). |
| 28 | Writing this file has the effect as driving the external |
| 29 | /SYNC pin low. |