Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/slab.h> |
| 17 | #include <linux/cpu.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/dma-mapping.h> |
| 20 | #include <linux/dmapool.h> |
| 21 | #include <linux/pm_runtime.h> |
| 22 | #include <linux/ratelimit.h> |
| 23 | #include <linux/interrupt.h> |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 24 | #include <asm/dma-iommu.h> |
| 25 | #include <linux/iommu.h> |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 26 | #include <linux/ioport.h> |
| 27 | #include <linux/clk.h> |
| 28 | #include <linux/io.h> |
| 29 | #include <linux/module.h> |
| 30 | #include <linux/types.h> |
| 31 | #include <linux/delay.h> |
| 32 | #include <linux/of.h> |
| 33 | #include <linux/of_platform.h> |
| 34 | #include <linux/of_gpio.h> |
| 35 | #include <linux/list.h> |
| 36 | #include <linux/uaccess.h> |
| 37 | #include <linux/usb/ch9.h> |
| 38 | #include <linux/usb/gadget.h> |
| 39 | #include <linux/usb/of.h> |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 40 | #include <linux/regulator/consumer.h> |
| 41 | #include <linux/pm_wakeup.h> |
| 42 | #include <linux/power_supply.h> |
| 43 | #include <linux/cdev.h> |
| 44 | #include <linux/completion.h> |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 45 | #include <linux/msm-bus.h> |
| 46 | #include <linux/irq.h> |
| 47 | #include <linux/extcon.h> |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 48 | #include <linux/reset.h> |
Hemant Kumar | 633dc33 | 2016-08-10 13:41:05 -0700 | [diff] [blame] | 49 | #include <linux/clk/qcom.h> |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 50 | |
| 51 | #include "power.h" |
| 52 | #include "core.h" |
| 53 | #include "gadget.h" |
| 54 | #include "dbm.h" |
| 55 | #include "debug.h" |
| 56 | #include "xhci.h" |
| 57 | |
| 58 | /* time out to wait for USB cable status notification (in ms)*/ |
| 59 | #define SM_INIT_TIMEOUT 30000 |
| 60 | |
| 61 | /* AHB2PHY register offsets */ |
| 62 | #define PERIPH_SS_AHB2PHY_TOP_CFG 0x10 |
| 63 | |
| 64 | /* AHB2PHY read/write waite value */ |
| 65 | #define ONE_READ_WRITE_WAIT 0x11 |
| 66 | |
| 67 | /* cpu to fix usb interrupt */ |
| 68 | static int cpu_to_affin; |
| 69 | module_param(cpu_to_affin, int, S_IRUGO|S_IWUSR); |
| 70 | MODULE_PARM_DESC(cpu_to_affin, "affin usb irq to this cpu"); |
| 71 | |
Mayank Rana | f70d821 | 2017-06-12 14:02:07 -0700 | [diff] [blame] | 72 | /* override for USB speed */ |
| 73 | static int override_usb_speed; |
| 74 | module_param(override_usb_speed, int, 0644); |
| 75 | MODULE_PARM_DESC(override_usb_speed, "override for USB speed"); |
| 76 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 77 | /* XHCI registers */ |
| 78 | #define USB3_HCSPARAMS1 (0x4) |
| 79 | #define USB3_PORTSC (0x420) |
| 80 | |
| 81 | /** |
| 82 | * USB QSCRATCH Hardware registers |
| 83 | * |
| 84 | */ |
| 85 | #define QSCRATCH_REG_OFFSET (0x000F8800) |
| 86 | #define QSCRATCH_GENERAL_CFG (QSCRATCH_REG_OFFSET + 0x08) |
| 87 | #define CGCTL_REG (QSCRATCH_REG_OFFSET + 0x28) |
| 88 | #define PWR_EVNT_IRQ_STAT_REG (QSCRATCH_REG_OFFSET + 0x58) |
| 89 | #define PWR_EVNT_IRQ_MASK_REG (QSCRATCH_REG_OFFSET + 0x5C) |
| 90 | |
| 91 | #define PWR_EVNT_POWERDOWN_IN_P3_MASK BIT(2) |
| 92 | #define PWR_EVNT_POWERDOWN_OUT_P3_MASK BIT(3) |
| 93 | #define PWR_EVNT_LPM_IN_L2_MASK BIT(4) |
| 94 | #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) |
| 95 | #define PWR_EVNT_LPM_OUT_L1_MASK BIT(13) |
| 96 | |
| 97 | /* QSCRATCH_GENERAL_CFG register bit offset */ |
| 98 | #define PIPE_UTMI_CLK_SEL BIT(0) |
| 99 | #define PIPE3_PHYSTATUS_SW BIT(3) |
| 100 | #define PIPE_UTMI_CLK_DIS BIT(8) |
| 101 | |
| 102 | #define HS_PHY_CTRL_REG (QSCRATCH_REG_OFFSET + 0x10) |
| 103 | #define UTMI_OTG_VBUS_VALID BIT(20) |
| 104 | #define SW_SESSVLD_SEL BIT(28) |
| 105 | |
| 106 | #define SS_PHY_CTRL_REG (QSCRATCH_REG_OFFSET + 0x30) |
| 107 | #define LANE0_PWR_PRESENT BIT(24) |
| 108 | |
| 109 | /* GSI related registers */ |
| 110 | #define GSI_TRB_ADDR_BIT_53_MASK (1 << 21) |
| 111 | #define GSI_TRB_ADDR_BIT_55_MASK (1 << 23) |
| 112 | |
| 113 | #define GSI_GENERAL_CFG_REG (QSCRATCH_REG_OFFSET + 0xFC) |
| 114 | #define GSI_RESTART_DBL_PNTR_MASK BIT(20) |
| 115 | #define GSI_CLK_EN_MASK BIT(12) |
| 116 | #define BLOCK_GSI_WR_GO_MASK BIT(1) |
| 117 | #define GSI_EN_MASK BIT(0) |
| 118 | |
| 119 | #define GSI_DBL_ADDR_L(n) ((QSCRATCH_REG_OFFSET + 0x110) + (n*4)) |
| 120 | #define GSI_DBL_ADDR_H(n) ((QSCRATCH_REG_OFFSET + 0x120) + (n*4)) |
| 121 | #define GSI_RING_BASE_ADDR_L(n) ((QSCRATCH_REG_OFFSET + 0x130) + (n*4)) |
| 122 | #define GSI_RING_BASE_ADDR_H(n) ((QSCRATCH_REG_OFFSET + 0x140) + (n*4)) |
| 123 | |
| 124 | #define GSI_IF_STS (QSCRATCH_REG_OFFSET + 0x1A4) |
| 125 | #define GSI_WR_CTRL_STATE_MASK BIT(15) |
| 126 | |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 127 | #define DWC3_GEVNTCOUNT_EVNTINTRPTMASK (1 << 31) |
| 128 | #define DWC3_GEVNTADRHI_EVNTADRHI_GSI_EN(n) (n << 22) |
| 129 | #define DWC3_GEVNTADRHI_EVNTADRHI_GSI_IDX(n) (n << 16) |
| 130 | #define DWC3_GEVENT_TYPE_GSI 0x3 |
| 131 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 132 | struct dwc3_msm_req_complete { |
| 133 | struct list_head list_item; |
| 134 | struct usb_request *req; |
| 135 | void (*orig_complete)(struct usb_ep *ep, |
| 136 | struct usb_request *req); |
| 137 | }; |
| 138 | |
| 139 | enum dwc3_id_state { |
| 140 | DWC3_ID_GROUND = 0, |
| 141 | DWC3_ID_FLOAT, |
| 142 | }; |
| 143 | |
| 144 | /* for type c cable */ |
| 145 | enum plug_orientation { |
| 146 | ORIENTATION_NONE, |
| 147 | ORIENTATION_CC1, |
| 148 | ORIENTATION_CC2, |
| 149 | }; |
| 150 | |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 151 | enum msm_usb_irq { |
| 152 | HS_PHY_IRQ, |
| 153 | PWR_EVNT_IRQ, |
| 154 | DP_HS_PHY_IRQ, |
| 155 | DM_HS_PHY_IRQ, |
| 156 | SS_PHY_IRQ, |
| 157 | USB_MAX_IRQ |
| 158 | }; |
| 159 | |
| 160 | struct usb_irq { |
| 161 | char *name; |
| 162 | int irq; |
| 163 | bool enable; |
| 164 | }; |
| 165 | |
| 166 | static const struct usb_irq usb_irq_info[USB_MAX_IRQ] = { |
| 167 | {"hs_phy_irq", 0}, |
| 168 | {"pwr_event_irq", 0}, |
| 169 | {"dp_hs_phy_irq", 0}, |
| 170 | {"dm_hs_phy_irq", 0}, |
| 171 | {"ss_phy_irq", 0}, |
| 172 | }; |
| 173 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 174 | /* Input bits to state machine (mdwc->inputs) */ |
| 175 | |
| 176 | #define ID 0 |
| 177 | #define B_SESS_VLD 1 |
| 178 | #define B_SUSPEND 2 |
| 179 | |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame] | 180 | #define PM_QOS_SAMPLE_SEC 2 |
| 181 | #define PM_QOS_THRESHOLD 400 |
| 182 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 183 | struct dwc3_msm { |
| 184 | struct device *dev; |
| 185 | void __iomem *base; |
| 186 | void __iomem *ahb2phy_base; |
| 187 | struct platform_device *dwc3; |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 188 | struct dma_iommu_mapping *iommu_map; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 189 | const struct usb_ep_ops *original_ep_ops[DWC3_ENDPOINTS_NUM]; |
| 190 | struct list_head req_complete_list; |
| 191 | struct clk *xo_clk; |
| 192 | struct clk *core_clk; |
| 193 | long core_clk_rate; |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 194 | long core_clk_rate_hs; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 195 | struct clk *iface_clk; |
| 196 | struct clk *sleep_clk; |
| 197 | struct clk *utmi_clk; |
| 198 | unsigned int utmi_clk_rate; |
| 199 | struct clk *utmi_clk_src; |
| 200 | struct clk *bus_aggr_clk; |
Vijayavardhan Vennapusa | 934d9cd | 2016-11-30 13:10:01 +0530 | [diff] [blame] | 201 | struct clk *noc_aggr_clk; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 202 | struct clk *cfg_ahb_clk; |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 203 | struct reset_control *core_reset; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 204 | struct regulator *dwc3_gdsc; |
| 205 | |
| 206 | struct usb_phy *hs_phy, *ss_phy; |
| 207 | |
| 208 | struct dbm *dbm; |
| 209 | |
| 210 | /* VBUS regulator for host mode */ |
| 211 | struct regulator *vbus_reg; |
| 212 | int vbus_retry_count; |
| 213 | bool resume_pending; |
| 214 | atomic_t pm_suspended; |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 215 | struct usb_irq wakeup_irq[USB_MAX_IRQ]; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 216 | struct work_struct resume_work; |
| 217 | struct work_struct restart_usb_work; |
| 218 | bool in_restart; |
| 219 | struct workqueue_struct *dwc3_wq; |
| 220 | struct delayed_work sm_work; |
| 221 | unsigned long inputs; |
| 222 | unsigned int max_power; |
| 223 | bool charging_disabled; |
| 224 | enum usb_otg_state otg_state; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 225 | u32 bus_perf_client; |
| 226 | struct msm_bus_scale_pdata *bus_scale_table; |
| 227 | struct power_supply *usb_psy; |
Jack Pham | 4b8b4ae | 2016-08-09 11:36:34 -0700 | [diff] [blame] | 228 | struct work_struct vbus_draw_work; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 229 | bool in_host_mode; |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 230 | enum usb_device_speed max_rh_port_speed; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 231 | unsigned int tx_fifo_size; |
| 232 | bool vbus_active; |
| 233 | bool suspend; |
| 234 | bool disable_host_mode_pm; |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 235 | bool use_pdc_interrupts; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 236 | enum dwc3_id_state id_state; |
| 237 | unsigned long lpm_flags; |
| 238 | #define MDWC3_SS_PHY_SUSPEND BIT(0) |
| 239 | #define MDWC3_ASYNC_IRQ_WAKE_CAPABILITY BIT(1) |
| 240 | #define MDWC3_POWER_COLLAPSE BIT(2) |
| 241 | |
| 242 | unsigned int irq_to_affin; |
| 243 | struct notifier_block dwc3_cpu_notifier; |
Manu Gautam | 976fdfc | 2016-08-18 09:27:35 +0530 | [diff] [blame] | 244 | struct notifier_block usbdev_nb; |
| 245 | bool hc_died; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 246 | |
| 247 | struct extcon_dev *extcon_vbus; |
| 248 | struct extcon_dev *extcon_id; |
Mayank Rana | 5195817 | 2017-02-28 14:49:21 -0800 | [diff] [blame] | 249 | struct extcon_dev *extcon_eud; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 250 | struct notifier_block vbus_nb; |
| 251 | struct notifier_block id_nb; |
Mayank Rana | 5195817 | 2017-02-28 14:49:21 -0800 | [diff] [blame] | 252 | struct notifier_block eud_event_nb; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 253 | |
Jack Pham | 4d4e934 | 2016-12-07 19:25:02 -0800 | [diff] [blame] | 254 | struct notifier_block host_nb; |
| 255 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 256 | atomic_t in_p3; |
| 257 | unsigned int lpm_to_suspend_delay; |
| 258 | bool init; |
| 259 | enum plug_orientation typec_orientation; |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 260 | u32 num_gsi_event_buffers; |
| 261 | struct dwc3_event_buffer **gsi_ev_buff; |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame] | 262 | int pm_qos_latency; |
| 263 | struct pm_qos_request pm_qos_req_dma; |
| 264 | struct delayed_work perf_vote_work; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 265 | }; |
| 266 | |
| 267 | #define USB_HSPHY_3P3_VOL_MIN 3050000 /* uV */ |
| 268 | #define USB_HSPHY_3P3_VOL_MAX 3300000 /* uV */ |
| 269 | #define USB_HSPHY_3P3_HPM_LOAD 16000 /* uA */ |
| 270 | |
| 271 | #define USB_HSPHY_1P8_VOL_MIN 1800000 /* uV */ |
| 272 | #define USB_HSPHY_1P8_VOL_MAX 1800000 /* uV */ |
| 273 | #define USB_HSPHY_1P8_HPM_LOAD 19000 /* uA */ |
| 274 | |
| 275 | #define USB_SSPHY_1P8_VOL_MIN 1800000 /* uV */ |
| 276 | #define USB_SSPHY_1P8_VOL_MAX 1800000 /* uV */ |
| 277 | #define USB_SSPHY_1P8_HPM_LOAD 23000 /* uA */ |
| 278 | |
| 279 | #define DSTS_CONNECTSPD_SS 0x4 |
| 280 | |
| 281 | |
| 282 | static void dwc3_pwr_event_handler(struct dwc3_msm *mdwc); |
| 283 | static int dwc3_msm_gadget_vbus_draw(struct dwc3_msm *mdwc, unsigned int mA); |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 284 | static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event); |
Mayank Rana | f70d821 | 2017-06-12 14:02:07 -0700 | [diff] [blame] | 285 | |
| 286 | static inline bool is_valid_usb_speed(struct dwc3 *dwc, int speed) |
| 287 | { |
| 288 | |
| 289 | return (((speed == USB_SPEED_FULL) || (speed == USB_SPEED_HIGH) || |
| 290 | (speed == USB_SPEED_SUPER) || (speed == USB_SPEED_SUPER_PLUS)) |
| 291 | && (speed <= dwc->maximum_speed)); |
| 292 | } |
| 293 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 294 | /** |
| 295 | * |
| 296 | * Read register with debug info. |
| 297 | * |
| 298 | * @base - DWC3 base virtual address. |
| 299 | * @offset - register offset. |
| 300 | * |
| 301 | * @return u32 |
| 302 | */ |
Stephen Boyd | a247bae | 2017-06-15 14:09:08 -0700 | [diff] [blame] | 303 | static inline u32 dwc3_msm_read_reg(void __iomem *base, u32 offset) |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 304 | { |
| 305 | u32 val = ioread32(base + offset); |
| 306 | return val; |
| 307 | } |
| 308 | |
| 309 | /** |
| 310 | * Read register masked field with debug info. |
| 311 | * |
| 312 | * @base - DWC3 base virtual address. |
| 313 | * @offset - register offset. |
| 314 | * @mask - register bitmask. |
| 315 | * |
| 316 | * @return u32 |
| 317 | */ |
Stephen Boyd | a247bae | 2017-06-15 14:09:08 -0700 | [diff] [blame] | 318 | static inline u32 dwc3_msm_read_reg_field(void __iomem *base, |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 319 | u32 offset, |
| 320 | const u32 mask) |
| 321 | { |
Stephen Boyd | a247bae | 2017-06-15 14:09:08 -0700 | [diff] [blame] | 322 | u32 shift = ffs(mask); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 323 | u32 val = ioread32(base + offset); |
| 324 | |
| 325 | val &= mask; /* clear other bits */ |
| 326 | val >>= shift; |
| 327 | return val; |
| 328 | } |
| 329 | |
| 330 | /** |
| 331 | * |
| 332 | * Write register with debug info. |
| 333 | * |
| 334 | * @base - DWC3 base virtual address. |
| 335 | * @offset - register offset. |
| 336 | * @val - value to write. |
| 337 | * |
| 338 | */ |
Stephen Boyd | a247bae | 2017-06-15 14:09:08 -0700 | [diff] [blame] | 339 | static inline void dwc3_msm_write_reg(void __iomem *base, u32 offset, u32 val) |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 340 | { |
| 341 | iowrite32(val, base + offset); |
| 342 | } |
| 343 | |
| 344 | /** |
| 345 | * Write register masked field with debug info. |
| 346 | * |
| 347 | * @base - DWC3 base virtual address. |
| 348 | * @offset - register offset. |
| 349 | * @mask - register bitmask. |
| 350 | * @val - value to write. |
| 351 | * |
| 352 | */ |
Stephen Boyd | a247bae | 2017-06-15 14:09:08 -0700 | [diff] [blame] | 353 | static inline void dwc3_msm_write_reg_field(void __iomem *base, u32 offset, |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 354 | const u32 mask, u32 val) |
| 355 | { |
| 356 | u32 shift = find_first_bit((void *)&mask, 32); |
| 357 | u32 tmp = ioread32(base + offset); |
| 358 | |
| 359 | tmp &= ~mask; /* clear written bits */ |
| 360 | val = tmp | (val << shift); |
| 361 | iowrite32(val, base + offset); |
| 362 | } |
| 363 | |
| 364 | /** |
| 365 | * Write register and read back masked value to confirm it is written |
| 366 | * |
| 367 | * @base - DWC3 base virtual address. |
| 368 | * @offset - register offset. |
| 369 | * @mask - register bitmask specifying what should be updated |
| 370 | * @val - value to write. |
| 371 | * |
| 372 | */ |
Stephen Boyd | a247bae | 2017-06-15 14:09:08 -0700 | [diff] [blame] | 373 | static inline void dwc3_msm_write_readback(void __iomem *base, u32 offset, |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 374 | const u32 mask, u32 val) |
| 375 | { |
| 376 | u32 write_val, tmp = ioread32(base + offset); |
| 377 | |
| 378 | tmp &= ~mask; /* retain other bits */ |
| 379 | write_val = tmp | val; |
| 380 | |
| 381 | iowrite32(write_val, base + offset); |
| 382 | |
| 383 | /* Read back to see if val was written */ |
| 384 | tmp = ioread32(base + offset); |
| 385 | tmp &= mask; /* clear other bits */ |
| 386 | |
| 387 | if (tmp != val) |
| 388 | pr_err("%s: write: %x to QSCRATCH: %x FAILED\n", |
| 389 | __func__, val, offset); |
| 390 | } |
| 391 | |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 392 | static bool dwc3_msm_is_ss_rhport_connected(struct dwc3_msm *mdwc) |
| 393 | { |
| 394 | int i, num_ports; |
| 395 | u32 reg; |
| 396 | |
| 397 | reg = dwc3_msm_read_reg(mdwc->base, USB3_HCSPARAMS1); |
| 398 | num_ports = HCS_MAX_PORTS(reg); |
| 399 | |
| 400 | for (i = 0; i < num_ports; i++) { |
| 401 | reg = dwc3_msm_read_reg(mdwc->base, USB3_PORTSC + i*0x10); |
| 402 | if ((reg & PORT_CONNECT) && DEV_SUPERSPEED(reg)) |
| 403 | return true; |
| 404 | } |
| 405 | |
| 406 | return false; |
| 407 | } |
| 408 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 409 | static bool dwc3_msm_is_host_superspeed(struct dwc3_msm *mdwc) |
| 410 | { |
| 411 | int i, num_ports; |
| 412 | u32 reg; |
| 413 | |
| 414 | reg = dwc3_msm_read_reg(mdwc->base, USB3_HCSPARAMS1); |
| 415 | num_ports = HCS_MAX_PORTS(reg); |
| 416 | |
| 417 | for (i = 0; i < num_ports; i++) { |
| 418 | reg = dwc3_msm_read_reg(mdwc->base, USB3_PORTSC + i*0x10); |
| 419 | if ((reg & PORT_PE) && DEV_SUPERSPEED(reg)) |
| 420 | return true; |
| 421 | } |
| 422 | |
| 423 | return false; |
| 424 | } |
| 425 | |
| 426 | static inline bool dwc3_msm_is_dev_superspeed(struct dwc3_msm *mdwc) |
| 427 | { |
| 428 | u8 speed; |
| 429 | |
| 430 | speed = dwc3_msm_read_reg(mdwc->base, DWC3_DSTS) & DWC3_DSTS_CONNECTSPD; |
| 431 | return !!(speed & DSTS_CONNECTSPD_SS); |
| 432 | } |
| 433 | |
| 434 | static inline bool dwc3_msm_is_superspeed(struct dwc3_msm *mdwc) |
| 435 | { |
| 436 | if (mdwc->in_host_mode) |
| 437 | return dwc3_msm_is_host_superspeed(mdwc); |
| 438 | |
| 439 | return dwc3_msm_is_dev_superspeed(mdwc); |
| 440 | } |
| 441 | |
| 442 | #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
| 443 | /** |
| 444 | * Configure the DBM with the BAM's data fifo. |
| 445 | * This function is called by the USB BAM Driver |
| 446 | * upon initialization. |
| 447 | * |
| 448 | * @ep - pointer to usb endpoint. |
| 449 | * @addr - address of data fifo. |
| 450 | * @size - size of data fifo. |
| 451 | * |
| 452 | */ |
| 453 | int msm_data_fifo_config(struct usb_ep *ep, phys_addr_t addr, |
| 454 | u32 size, u8 dst_pipe_idx) |
| 455 | { |
| 456 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 457 | struct dwc3 *dwc = dep->dwc; |
| 458 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 459 | |
| 460 | dev_dbg(mdwc->dev, "%s\n", __func__); |
| 461 | |
| 462 | return dbm_data_fifo_config(mdwc->dbm, dep->number, addr, size, |
| 463 | dst_pipe_idx); |
| 464 | } |
| 465 | |
| 466 | |
| 467 | /** |
| 468 | * Cleanups for msm endpoint on request complete. |
| 469 | * |
| 470 | * Also call original request complete. |
| 471 | * |
| 472 | * @usb_ep - pointer to usb_ep instance. |
| 473 | * @request - pointer to usb_request instance. |
| 474 | * |
| 475 | * @return int - 0 on success, negative on error. |
| 476 | */ |
| 477 | static void dwc3_msm_req_complete_func(struct usb_ep *ep, |
| 478 | struct usb_request *request) |
| 479 | { |
| 480 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 481 | struct dwc3 *dwc = dep->dwc; |
| 482 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 483 | struct dwc3_msm_req_complete *req_complete = NULL; |
| 484 | |
| 485 | /* Find original request complete function and remove it from list */ |
| 486 | list_for_each_entry(req_complete, &mdwc->req_complete_list, list_item) { |
| 487 | if (req_complete->req == request) |
| 488 | break; |
| 489 | } |
| 490 | if (!req_complete || req_complete->req != request) { |
| 491 | dev_err(dep->dwc->dev, "%s: could not find the request\n", |
| 492 | __func__); |
| 493 | return; |
| 494 | } |
| 495 | list_del(&req_complete->list_item); |
| 496 | |
| 497 | /* |
| 498 | * Release another one TRB to the pool since DBM queue took 2 TRBs |
| 499 | * (normal and link), and the dwc3/gadget.c :: dwc3_gadget_giveback |
| 500 | * released only one. |
| 501 | */ |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 502 | dep->trb_dequeue++; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 503 | |
| 504 | /* Unconfigure dbm ep */ |
| 505 | dbm_ep_unconfig(mdwc->dbm, dep->number); |
| 506 | |
| 507 | /* |
| 508 | * If this is the last endpoint we unconfigured, than reset also |
| 509 | * the event buffers; unless unconfiguring the ep due to lpm, |
| 510 | * in which case the event buffer only gets reset during the |
| 511 | * block reset. |
| 512 | */ |
| 513 | if (dbm_get_num_of_eps_configured(mdwc->dbm) == 0 && |
| 514 | !dbm_reset_ep_after_lpm(mdwc->dbm)) |
| 515 | dbm_event_buffer_config(mdwc->dbm, 0, 0, 0); |
| 516 | |
| 517 | /* |
| 518 | * Call original complete function, notice that dwc->lock is already |
| 519 | * taken by the caller of this function (dwc3_gadget_giveback()). |
| 520 | */ |
| 521 | request->complete = req_complete->orig_complete; |
| 522 | if (request->complete) |
| 523 | request->complete(ep, request); |
| 524 | |
| 525 | kfree(req_complete); |
| 526 | } |
| 527 | |
| 528 | |
| 529 | /** |
| 530 | * Helper function |
| 531 | * |
| 532 | * Reset DBM endpoint. |
| 533 | * |
| 534 | * @mdwc - pointer to dwc3_msm instance. |
| 535 | * @dep - pointer to dwc3_ep instance. |
| 536 | * |
| 537 | * @return int - 0 on success, negative on error. |
| 538 | */ |
| 539 | static int __dwc3_msm_dbm_ep_reset(struct dwc3_msm *mdwc, struct dwc3_ep *dep) |
| 540 | { |
| 541 | int ret; |
| 542 | |
| 543 | dev_dbg(mdwc->dev, "Resetting dbm endpoint %d\n", dep->number); |
| 544 | |
| 545 | /* Reset the dbm endpoint */ |
| 546 | ret = dbm_ep_soft_reset(mdwc->dbm, dep->number, true); |
| 547 | if (ret) { |
| 548 | dev_err(mdwc->dev, "%s: failed to assert dbm ep reset\n", |
| 549 | __func__); |
| 550 | return ret; |
| 551 | } |
| 552 | |
| 553 | /* |
| 554 | * The necessary delay between asserting and deasserting the dbm ep |
| 555 | * reset is based on the number of active endpoints. If there is more |
| 556 | * than one endpoint, a 1 msec delay is required. Otherwise, a shorter |
| 557 | * delay will suffice. |
| 558 | */ |
| 559 | if (dbm_get_num_of_eps_configured(mdwc->dbm) > 1) |
| 560 | usleep_range(1000, 1200); |
| 561 | else |
| 562 | udelay(10); |
| 563 | ret = dbm_ep_soft_reset(mdwc->dbm, dep->number, false); |
| 564 | if (ret) { |
| 565 | dev_err(mdwc->dev, "%s: failed to deassert dbm ep reset\n", |
| 566 | __func__); |
| 567 | return ret; |
| 568 | } |
| 569 | |
| 570 | return 0; |
| 571 | } |
| 572 | |
| 573 | /** |
| 574 | * Reset the DBM endpoint which is linked to the given USB endpoint. |
| 575 | * |
| 576 | * @usb_ep - pointer to usb_ep instance. |
| 577 | * |
| 578 | * @return int - 0 on success, negative on error. |
| 579 | */ |
| 580 | |
| 581 | int msm_dwc3_reset_dbm_ep(struct usb_ep *ep) |
| 582 | { |
| 583 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 584 | struct dwc3 *dwc = dep->dwc; |
| 585 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 586 | |
| 587 | return __dwc3_msm_dbm_ep_reset(mdwc, dep); |
| 588 | } |
| 589 | EXPORT_SYMBOL(msm_dwc3_reset_dbm_ep); |
| 590 | |
| 591 | |
| 592 | /** |
| 593 | * Helper function. |
| 594 | * See the header of the dwc3_msm_ep_queue function. |
| 595 | * |
| 596 | * @dwc3_ep - pointer to dwc3_ep instance. |
| 597 | * @req - pointer to dwc3_request instance. |
| 598 | * |
| 599 | * @return int - 0 on success, negative on error. |
| 600 | */ |
| 601 | static int __dwc3_msm_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
| 602 | { |
| 603 | struct dwc3_trb *trb; |
| 604 | struct dwc3_trb *trb_link; |
| 605 | struct dwc3_gadget_ep_cmd_params params; |
| 606 | u32 cmd; |
| 607 | int ret = 0; |
| 608 | |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 609 | /* We push the request to the dep->started_list list to indicate that |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 610 | * this request is issued with start transfer. The request will be out |
| 611 | * from this list in 2 cases. The first is that the transfer will be |
| 612 | * completed (not if the transfer is endless using a circular TRBs with |
| 613 | * with link TRB). The second case is an option to do stop stransfer, |
| 614 | * this can be initiated by the function driver when calling dequeue. |
| 615 | */ |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 616 | req->started = true; |
| 617 | list_add_tail(&req->list, &dep->started_list); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 618 | |
| 619 | /* First, prepare a normal TRB, point to the fake buffer */ |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 620 | trb = &dep->trb_pool[dep->trb_enqueue & DWC3_TRB_NUM]; |
| 621 | dep->trb_enqueue++; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 622 | memset(trb, 0, sizeof(*trb)); |
| 623 | |
| 624 | req->trb = trb; |
| 625 | trb->bph = DBM_TRB_BIT | DBM_TRB_DMA | DBM_TRB_EP_NUM(dep->number); |
| 626 | trb->size = DWC3_TRB_SIZE_LENGTH(req->request.length); |
| 627 | trb->ctrl = DWC3_TRBCTL_NORMAL | DWC3_TRB_CTRL_HWO | |
| 628 | DWC3_TRB_CTRL_CHN | (req->direction ? 0 : DWC3_TRB_CTRL_CSP); |
| 629 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); |
| 630 | |
| 631 | /* Second, prepare a Link TRB that points to the first TRB*/ |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 632 | trb_link = &dep->trb_pool[dep->trb_enqueue & DWC3_TRB_NUM]; |
| 633 | dep->trb_enqueue++; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 634 | memset(trb_link, 0, sizeof(*trb_link)); |
| 635 | |
| 636 | trb_link->bpl = lower_32_bits(req->trb_dma); |
| 637 | trb_link->bph = DBM_TRB_BIT | |
| 638 | DBM_TRB_DMA | DBM_TRB_EP_NUM(dep->number); |
| 639 | trb_link->size = 0; |
| 640 | trb_link->ctrl = DWC3_TRBCTL_LINK_TRB | DWC3_TRB_CTRL_HWO; |
| 641 | |
| 642 | /* |
| 643 | * Now start the transfer |
| 644 | */ |
| 645 | memset(¶ms, 0, sizeof(params)); |
| 646 | params.param0 = 0; /* TDAddr High */ |
| 647 | params.param1 = lower_32_bits(req->trb_dma); /* DAddr Low */ |
| 648 | |
| 649 | /* DBM requires IOC to be set */ |
| 650 | cmd = DWC3_DEPCMD_STARTTRANSFER | DWC3_DEPCMD_CMDIOC; |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 651 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 652 | if (ret < 0) { |
| 653 | dev_dbg(dep->dwc->dev, |
| 654 | "%s: failed to send STARTTRANSFER command\n", |
| 655 | __func__); |
| 656 | |
| 657 | list_del(&req->list); |
| 658 | return ret; |
| 659 | } |
| 660 | dep->flags |= DWC3_EP_BUSY; |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 661 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 662 | |
| 663 | return ret; |
| 664 | } |
| 665 | |
| 666 | /** |
| 667 | * Queue a usb request to the DBM endpoint. |
| 668 | * This function should be called after the endpoint |
| 669 | * was enabled by the ep_enable. |
| 670 | * |
| 671 | * This function prepares special structure of TRBs which |
| 672 | * is familiar with the DBM HW, so it will possible to use |
| 673 | * this endpoint in DBM mode. |
| 674 | * |
| 675 | * The TRBs prepared by this function, is one normal TRB |
| 676 | * which point to a fake buffer, followed by a link TRB |
| 677 | * that points to the first TRB. |
| 678 | * |
| 679 | * The API of this function follow the regular API of |
| 680 | * usb_ep_queue (see usb_ep_ops in include/linuk/usb/gadget.h). |
| 681 | * |
| 682 | * @usb_ep - pointer to usb_ep instance. |
| 683 | * @request - pointer to usb_request instance. |
| 684 | * @gfp_flags - possible flags. |
| 685 | * |
| 686 | * @return int - 0 on success, negative on error. |
| 687 | */ |
| 688 | static int dwc3_msm_ep_queue(struct usb_ep *ep, |
| 689 | struct usb_request *request, gfp_t gfp_flags) |
| 690 | { |
| 691 | struct dwc3_request *req = to_dwc3_request(request); |
| 692 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 693 | struct dwc3 *dwc = dep->dwc; |
| 694 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 695 | struct dwc3_msm_req_complete *req_complete; |
| 696 | unsigned long flags; |
| 697 | int ret = 0, size; |
| 698 | u8 bam_pipe; |
| 699 | bool producer; |
| 700 | bool disable_wb; |
| 701 | bool internal_mem; |
| 702 | bool ioc; |
| 703 | bool superspeed; |
| 704 | |
| 705 | if (!(request->udc_priv & MSM_SPS_MODE)) { |
| 706 | /* Not SPS mode, call original queue */ |
| 707 | dev_vdbg(mdwc->dev, "%s: not sps mode, use regular queue\n", |
| 708 | __func__); |
| 709 | |
| 710 | return (mdwc->original_ep_ops[dep->number])->queue(ep, |
| 711 | request, |
| 712 | gfp_flags); |
| 713 | } |
| 714 | |
| 715 | /* HW restriction regarding TRB size (8KB) */ |
| 716 | if (req->request.length < 0x2000) { |
| 717 | dev_err(mdwc->dev, "%s: Min TRB size is 8KB\n", __func__); |
| 718 | return -EINVAL; |
| 719 | } |
| 720 | |
| 721 | /* |
| 722 | * Override req->complete function, but before doing that, |
| 723 | * store it's original pointer in the req_complete_list. |
| 724 | */ |
| 725 | req_complete = kzalloc(sizeof(*req_complete), gfp_flags); |
| 726 | if (!req_complete) |
| 727 | return -ENOMEM; |
| 728 | |
| 729 | req_complete->req = request; |
| 730 | req_complete->orig_complete = request->complete; |
| 731 | list_add_tail(&req_complete->list_item, &mdwc->req_complete_list); |
| 732 | request->complete = dwc3_msm_req_complete_func; |
| 733 | |
| 734 | /* |
| 735 | * Configure the DBM endpoint |
| 736 | */ |
| 737 | bam_pipe = request->udc_priv & MSM_PIPE_ID_MASK; |
| 738 | producer = ((request->udc_priv & MSM_PRODUCER) ? true : false); |
| 739 | disable_wb = ((request->udc_priv & MSM_DISABLE_WB) ? true : false); |
| 740 | internal_mem = ((request->udc_priv & MSM_INTERNAL_MEM) ? true : false); |
| 741 | ioc = ((request->udc_priv & MSM_ETD_IOC) ? true : false); |
| 742 | |
| 743 | ret = dbm_ep_config(mdwc->dbm, dep->number, bam_pipe, producer, |
| 744 | disable_wb, internal_mem, ioc); |
| 745 | if (ret < 0) { |
| 746 | dev_err(mdwc->dev, |
| 747 | "error %d after calling dbm_ep_config\n", ret); |
| 748 | return ret; |
| 749 | } |
| 750 | |
| 751 | dev_vdbg(dwc->dev, "%s: queing request %p to ep %s length %d\n", |
| 752 | __func__, request, ep->name, request->length); |
| 753 | size = dwc3_msm_read_reg(mdwc->base, DWC3_GEVNTSIZ(0)); |
| 754 | dbm_event_buffer_config(mdwc->dbm, |
| 755 | dwc3_msm_read_reg(mdwc->base, DWC3_GEVNTADRLO(0)), |
| 756 | dwc3_msm_read_reg(mdwc->base, DWC3_GEVNTADRHI(0)), |
| 757 | DWC3_GEVNTSIZ_SIZE(size)); |
| 758 | |
| 759 | /* |
| 760 | * We must obtain the lock of the dwc3 core driver, |
| 761 | * including disabling interrupts, so we will be sure |
| 762 | * that we are the only ones that configure the HW device |
| 763 | * core and ensure that we queuing the request will finish |
| 764 | * as soon as possible so we will release back the lock. |
| 765 | */ |
| 766 | spin_lock_irqsave(&dwc->lock, flags); |
| 767 | if (!dep->endpoint.desc) { |
| 768 | dev_err(mdwc->dev, |
| 769 | "%s: trying to queue request %p to disabled ep %s\n", |
| 770 | __func__, request, ep->name); |
| 771 | ret = -EPERM; |
| 772 | goto err; |
| 773 | } |
| 774 | |
| 775 | if (dep->number == 0 || dep->number == 1) { |
| 776 | dev_err(mdwc->dev, |
| 777 | "%s: trying to queue dbm request %p to control ep %s\n", |
| 778 | __func__, request, ep->name); |
| 779 | ret = -EPERM; |
| 780 | goto err; |
| 781 | } |
| 782 | |
| 783 | |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 784 | if (dep->trb_dequeue != dep->trb_enqueue || |
| 785 | !list_empty(&dep->pending_list) |
| 786 | || !list_empty(&dep->started_list)) { |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 787 | dev_err(mdwc->dev, |
| 788 | "%s: trying to queue dbm request %p tp ep %s\n", |
| 789 | __func__, request, ep->name); |
| 790 | ret = -EPERM; |
| 791 | goto err; |
| 792 | } else { |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 793 | dep->trb_dequeue = 0; |
| 794 | dep->trb_enqueue = 0; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 795 | } |
| 796 | |
| 797 | ret = __dwc3_msm_ep_queue(dep, req); |
| 798 | if (ret < 0) { |
| 799 | dev_err(mdwc->dev, |
| 800 | "error %d after calling __dwc3_msm_ep_queue\n", ret); |
| 801 | goto err; |
| 802 | } |
| 803 | |
| 804 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 805 | superspeed = dwc3_msm_is_dev_superspeed(mdwc); |
| 806 | dbm_set_speed(mdwc->dbm, (u8)superspeed); |
| 807 | |
| 808 | return 0; |
| 809 | |
| 810 | err: |
| 811 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 812 | kfree(req_complete); |
| 813 | return ret; |
| 814 | } |
| 815 | |
| 816 | /* |
| 817 | * Returns XferRscIndex for the EP. This is stored at StartXfer GSI EP OP |
| 818 | * |
| 819 | * @usb_ep - pointer to usb_ep instance. |
| 820 | * |
| 821 | * @return int - XferRscIndex |
| 822 | */ |
| 823 | static inline int gsi_get_xfer_index(struct usb_ep *ep) |
| 824 | { |
| 825 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 826 | |
| 827 | return dep->resource_index; |
| 828 | } |
| 829 | |
| 830 | /* |
| 831 | * Fills up the GSI channel information needed in call to IPA driver |
| 832 | * for GSI channel creation. |
| 833 | * |
| 834 | * @usb_ep - pointer to usb_ep instance. |
| 835 | * @ch_info - output parameter with requested channel info |
| 836 | */ |
| 837 | static void gsi_get_channel_info(struct usb_ep *ep, |
| 838 | struct gsi_channel_info *ch_info) |
| 839 | { |
| 840 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 841 | int last_trb_index = 0; |
| 842 | struct dwc3 *dwc = dep->dwc; |
| 843 | struct usb_gsi_request *request = ch_info->ch_req; |
| 844 | |
| 845 | /* Provide physical USB addresses for DEPCMD and GEVENTCNT registers */ |
| 846 | ch_info->depcmd_low_addr = (u32)(dwc->reg_phys + |
Mayank Rana | ac776d1 | 2017-04-18 16:56:13 -0700 | [diff] [blame] | 847 | DWC3_DEP_BASE(dep->number) + DWC3_DEPCMD); |
| 848 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 849 | ch_info->depcmd_hi_addr = 0; |
| 850 | |
| 851 | ch_info->xfer_ring_base_addr = dwc3_trb_dma_offset(dep, |
| 852 | &dep->trb_pool[0]); |
| 853 | /* Convert to multipled of 1KB */ |
| 854 | ch_info->const_buffer_size = request->buf_len/1024; |
| 855 | |
| 856 | /* IN direction */ |
| 857 | if (dep->direction) { |
| 858 | /* |
| 859 | * Multiply by size of each TRB for xfer_ring_len in bytes. |
| 860 | * 2n + 2 TRBs as per GSI h/w requirement. n Xfer TRBs + 1 |
| 861 | * extra Xfer TRB followed by n ZLP TRBs + 1 LINK TRB. |
| 862 | */ |
| 863 | ch_info->xfer_ring_len = (2 * request->num_bufs + 2) * 0x10; |
| 864 | last_trb_index = 2 * request->num_bufs + 2; |
| 865 | } else { /* OUT direction */ |
| 866 | /* |
| 867 | * Multiply by size of each TRB for xfer_ring_len in bytes. |
| 868 | * n + 1 TRBs as per GSI h/w requirement. n Xfer TRBs + 1 |
| 869 | * LINK TRB. |
| 870 | */ |
Mayank Rana | 64d136b | 2016-11-01 21:01:34 -0700 | [diff] [blame^] | 871 | ch_info->xfer_ring_len = (request->num_bufs + 2) * 0x10; |
| 872 | last_trb_index = request->num_bufs + 2; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 873 | } |
| 874 | |
| 875 | /* Store last 16 bits of LINK TRB address as per GSI hw requirement */ |
| 876 | ch_info->last_trb_addr = (dwc3_trb_dma_offset(dep, |
| 877 | &dep->trb_pool[last_trb_index - 1]) & 0x0000FFFF); |
| 878 | ch_info->gevntcount_low_addr = (u32)(dwc->reg_phys + |
| 879 | DWC3_GEVNTCOUNT(ep->ep_intr_num)); |
| 880 | ch_info->gevntcount_hi_addr = 0; |
| 881 | |
| 882 | dev_dbg(dwc->dev, |
| 883 | "depcmd_laddr=%x last_trb_addr=%x gevtcnt_laddr=%x gevtcnt_haddr=%x", |
| 884 | ch_info->depcmd_low_addr, ch_info->last_trb_addr, |
| 885 | ch_info->gevntcount_low_addr, ch_info->gevntcount_hi_addr); |
| 886 | } |
| 887 | |
| 888 | /* |
| 889 | * Perform StartXfer on GSI EP. Stores XferRscIndex. |
| 890 | * |
| 891 | * @usb_ep - pointer to usb_ep instance. |
| 892 | * |
| 893 | * @return int - 0 on success |
| 894 | */ |
| 895 | static int gsi_startxfer_for_ep(struct usb_ep *ep) |
| 896 | { |
| 897 | int ret; |
| 898 | struct dwc3_gadget_ep_cmd_params params; |
| 899 | u32 cmd; |
| 900 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 901 | struct dwc3 *dwc = dep->dwc; |
| 902 | |
| 903 | memset(¶ms, 0, sizeof(params)); |
| 904 | params.param0 = GSI_TRB_ADDR_BIT_53_MASK | GSI_TRB_ADDR_BIT_55_MASK; |
| 905 | params.param0 |= (ep->ep_intr_num << 16); |
| 906 | params.param1 = lower_32_bits(dwc3_trb_dma_offset(dep, |
| 907 | &dep->trb_pool[0])); |
| 908 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
| 909 | cmd |= DWC3_DEPCMD_PARAM(0); |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 910 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 911 | |
| 912 | if (ret < 0) |
| 913 | dev_dbg(dwc->dev, "Fail StrtXfr on GSI EP#%d\n", dep->number); |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 914 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 915 | dev_dbg(dwc->dev, "XferRsc = %x", dep->resource_index); |
| 916 | return ret; |
| 917 | } |
| 918 | |
| 919 | /* |
| 920 | * Store Ring Base and Doorbell Address for GSI EP |
| 921 | * for GSI channel creation. |
| 922 | * |
| 923 | * @usb_ep - pointer to usb_ep instance. |
| 924 | * @dbl_addr - Doorbell address obtained from IPA driver |
| 925 | */ |
| 926 | static void gsi_store_ringbase_dbl_info(struct usb_ep *ep, u32 dbl_addr) |
| 927 | { |
| 928 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 929 | struct dwc3 *dwc = dep->dwc; |
| 930 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 931 | int n = ep->ep_intr_num - 1; |
| 932 | |
| 933 | dwc3_msm_write_reg(mdwc->base, GSI_RING_BASE_ADDR_L(n), |
| 934 | dwc3_trb_dma_offset(dep, &dep->trb_pool[0])); |
| 935 | dwc3_msm_write_reg(mdwc->base, GSI_DBL_ADDR_L(n), dbl_addr); |
| 936 | |
| 937 | dev_dbg(mdwc->dev, "Ring Base Addr %d = %x", n, |
| 938 | dwc3_msm_read_reg(mdwc->base, GSI_RING_BASE_ADDR_L(n))); |
| 939 | dev_dbg(mdwc->dev, "GSI DB Addr %d = %x", n, |
| 940 | dwc3_msm_read_reg(mdwc->base, GSI_DBL_ADDR_L(n))); |
| 941 | } |
| 942 | |
| 943 | /* |
Mayank Rana | 64d136b | 2016-11-01 21:01:34 -0700 | [diff] [blame^] | 944 | * Rings Doorbell for GSI Channel |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 945 | * |
| 946 | * @usb_ep - pointer to usb_ep instance. |
| 947 | * @request - pointer to GSI request. This is used to pass in the |
| 948 | * address of the GSI doorbell obtained from IPA driver |
| 949 | */ |
Mayank Rana | 64d136b | 2016-11-01 21:01:34 -0700 | [diff] [blame^] | 950 | static void gsi_ring_db(struct usb_ep *ep, struct usb_gsi_request *request) |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 951 | { |
| 952 | void __iomem *gsi_dbl_address_lsb; |
| 953 | void __iomem *gsi_dbl_address_msb; |
| 954 | dma_addr_t offset; |
| 955 | u64 dbl_addr = *((u64 *)request->buf_base_addr); |
| 956 | u32 dbl_lo_addr = (dbl_addr & 0xFFFFFFFF); |
| 957 | u32 dbl_hi_addr = (dbl_addr >> 32); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 958 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 959 | struct dwc3 *dwc = dep->dwc; |
| 960 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
Mayank Rana | 64d136b | 2016-11-01 21:01:34 -0700 | [diff] [blame^] | 961 | int num_trbs = (dep->direction) ? (2 * (request->num_bufs) + 2) |
| 962 | : (request->num_bufs + 2); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 963 | |
| 964 | gsi_dbl_address_lsb = devm_ioremap_nocache(mdwc->dev, |
| 965 | dbl_lo_addr, sizeof(u32)); |
| 966 | if (!gsi_dbl_address_lsb) |
| 967 | dev_dbg(mdwc->dev, "Failed to get GSI DBL address LSB\n"); |
| 968 | |
| 969 | gsi_dbl_address_msb = devm_ioremap_nocache(mdwc->dev, |
| 970 | dbl_hi_addr, sizeof(u32)); |
| 971 | if (!gsi_dbl_address_msb) |
| 972 | dev_dbg(mdwc->dev, "Failed to get GSI DBL address MSB\n"); |
| 973 | |
| 974 | offset = dwc3_trb_dma_offset(dep, &dep->trb_pool[num_trbs-1]); |
Mayank Rana | 64d136b | 2016-11-01 21:01:34 -0700 | [diff] [blame^] | 975 | dev_dbg(mdwc->dev, "Writing link TRB addr: %pa to %p (%x) for ep:%s\n", |
| 976 | &offset, gsi_dbl_address_lsb, dbl_lo_addr, ep->name); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 977 | |
| 978 | writel_relaxed(offset, gsi_dbl_address_lsb); |
| 979 | writel_relaxed(0, gsi_dbl_address_msb); |
| 980 | } |
| 981 | |
| 982 | /* |
| 983 | * Sets HWO bit for TRBs and performs UpdateXfer for OUT EP. |
| 984 | * |
| 985 | * @usb_ep - pointer to usb_ep instance. |
| 986 | * @request - pointer to GSI request. Used to determine num of TRBs for OUT EP. |
| 987 | * |
| 988 | * @return int - 0 on success |
| 989 | */ |
| 990 | static int gsi_updatexfer_for_ep(struct usb_ep *ep, |
| 991 | struct usb_gsi_request *request) |
| 992 | { |
| 993 | int i; |
| 994 | int ret; |
| 995 | u32 cmd; |
| 996 | int num_trbs = request->num_bufs + 1; |
| 997 | struct dwc3_trb *trb; |
| 998 | struct dwc3_gadget_ep_cmd_params params; |
| 999 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1000 | struct dwc3 *dwc = dep->dwc; |
| 1001 | |
| 1002 | for (i = 0; i < num_trbs - 1; i++) { |
| 1003 | trb = &dep->trb_pool[i]; |
| 1004 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
| 1005 | } |
| 1006 | |
| 1007 | memset(¶ms, 0, sizeof(params)); |
| 1008 | cmd = DWC3_DEPCMD_UPDATETRANSFER; |
| 1009 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 1010 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1011 | dep->flags |= DWC3_EP_BUSY; |
| 1012 | if (ret < 0) |
| 1013 | dev_dbg(dwc->dev, "UpdateXfr fail on GSI EP#%d\n", dep->number); |
| 1014 | return ret; |
| 1015 | } |
| 1016 | |
| 1017 | /* |
| 1018 | * Perform EndXfer on particular GSI EP. |
| 1019 | * |
| 1020 | * @usb_ep - pointer to usb_ep instance. |
| 1021 | */ |
| 1022 | static void gsi_endxfer_for_ep(struct usb_ep *ep) |
| 1023 | { |
| 1024 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1025 | struct dwc3 *dwc = dep->dwc; |
| 1026 | |
| 1027 | dwc3_stop_active_transfer(dwc, dep->number, true); |
| 1028 | } |
| 1029 | |
| 1030 | /* |
| 1031 | * Allocates and configures TRBs for GSI EPs. |
| 1032 | * |
| 1033 | * @usb_ep - pointer to usb_ep instance. |
| 1034 | * @request - pointer to GSI request. |
| 1035 | * |
| 1036 | * @return int - 0 on success |
| 1037 | */ |
| 1038 | static int gsi_prepare_trbs(struct usb_ep *ep, struct usb_gsi_request *req) |
| 1039 | { |
| 1040 | int i = 0; |
| 1041 | dma_addr_t buffer_addr = req->dma; |
| 1042 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1043 | struct dwc3 *dwc = dep->dwc; |
| 1044 | struct dwc3_trb *trb; |
| 1045 | int num_trbs = (dep->direction) ? (2 * (req->num_bufs) + 2) |
Mayank Rana | 64d136b | 2016-11-01 21:01:34 -0700 | [diff] [blame^] | 1046 | : (req->num_bufs + 2); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1047 | |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 1048 | dep->trb_dma_pool = dma_pool_create(ep->name, dwc->sysdev, |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1049 | num_trbs * sizeof(struct dwc3_trb), |
| 1050 | num_trbs * sizeof(struct dwc3_trb), 0); |
| 1051 | if (!dep->trb_dma_pool) { |
| 1052 | dev_err(dep->dwc->dev, "failed to alloc trb dma pool for %s\n", |
| 1053 | dep->name); |
| 1054 | return -ENOMEM; |
| 1055 | } |
| 1056 | |
| 1057 | dep->num_trbs = num_trbs; |
| 1058 | |
| 1059 | dep->trb_pool = dma_pool_alloc(dep->trb_dma_pool, |
| 1060 | GFP_KERNEL, &dep->trb_pool_dma); |
| 1061 | if (!dep->trb_pool) { |
| 1062 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", |
| 1063 | dep->name); |
| 1064 | return -ENOMEM; |
| 1065 | } |
| 1066 | |
| 1067 | /* IN direction */ |
| 1068 | if (dep->direction) { |
| 1069 | for (i = 0; i < num_trbs ; i++) { |
| 1070 | trb = &dep->trb_pool[i]; |
| 1071 | memset(trb, 0, sizeof(*trb)); |
| 1072 | /* Set up first n+1 TRBs for ZLPs */ |
| 1073 | if (i < (req->num_bufs + 1)) { |
| 1074 | trb->bpl = 0; |
| 1075 | trb->bph = 0; |
| 1076 | trb->size = 0; |
| 1077 | trb->ctrl = DWC3_TRBCTL_NORMAL |
| 1078 | | DWC3_TRB_CTRL_IOC; |
| 1079 | continue; |
| 1080 | } |
| 1081 | |
| 1082 | /* Setup n TRBs pointing to valid buffers */ |
| 1083 | trb->bpl = lower_32_bits(buffer_addr); |
| 1084 | trb->bph = 0; |
| 1085 | trb->size = 0; |
| 1086 | trb->ctrl = DWC3_TRBCTL_NORMAL |
| 1087 | | DWC3_TRB_CTRL_IOC; |
| 1088 | buffer_addr += req->buf_len; |
| 1089 | |
| 1090 | /* Set up the Link TRB at the end */ |
| 1091 | if (i == (num_trbs - 1)) { |
| 1092 | trb->bpl = dwc3_trb_dma_offset(dep, |
| 1093 | &dep->trb_pool[0]); |
| 1094 | trb->bph = (1 << 23) | (1 << 21) |
| 1095 | | (ep->ep_intr_num << 16); |
| 1096 | trb->size = 0; |
| 1097 | trb->ctrl = DWC3_TRBCTL_LINK_TRB |
| 1098 | | DWC3_TRB_CTRL_HWO; |
| 1099 | } |
| 1100 | } |
| 1101 | } else { /* OUT direction */ |
| 1102 | |
| 1103 | for (i = 0; i < num_trbs ; i++) { |
| 1104 | |
| 1105 | trb = &dep->trb_pool[i]; |
| 1106 | memset(trb, 0, sizeof(*trb)); |
Mayank Rana | 64d136b | 2016-11-01 21:01:34 -0700 | [diff] [blame^] | 1107 | /* Setup LINK TRB to start with TRB ring */ |
| 1108 | if (i == 0) { |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1109 | trb->bpl = dwc3_trb_dma_offset(dep, |
Mayank Rana | 64d136b | 2016-11-01 21:01:34 -0700 | [diff] [blame^] | 1110 | &dep->trb_pool[1]); |
| 1111 | trb->ctrl = DWC3_TRBCTL_LINK_TRB; |
| 1112 | } else if (i == (num_trbs - 1)) { |
| 1113 | /* Set up the Link TRB at the end */ |
| 1114 | trb->bpl = dwc3_trb_dma_offset(dep, |
| 1115 | &dep->trb_pool[0]); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1116 | trb->bph = (1 << 23) | (1 << 21) |
| 1117 | | (ep->ep_intr_num << 16); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1118 | trb->ctrl = DWC3_TRBCTL_LINK_TRB |
| 1119 | | DWC3_TRB_CTRL_HWO; |
Mayank Rana | 64d136b | 2016-11-01 21:01:34 -0700 | [diff] [blame^] | 1120 | } else { |
| 1121 | trb->bpl = lower_32_bits(buffer_addr); |
| 1122 | trb->size = req->buf_len; |
| 1123 | buffer_addr += req->buf_len; |
| 1124 | trb->ctrl = DWC3_TRBCTL_NORMAL |
| 1125 | | DWC3_TRB_CTRL_IOC |
| 1126 | | DWC3_TRB_CTRL_CSP |
| 1127 | | DWC3_TRB_CTRL_ISP_IMI; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1128 | } |
| 1129 | } |
| 1130 | } |
Mayank Rana | 64d136b | 2016-11-01 21:01:34 -0700 | [diff] [blame^] | 1131 | |
| 1132 | pr_debug("%s: Initialized TRB Ring for %s\n", __func__, dep->name); |
| 1133 | trb = &dep->trb_pool[0]; |
| 1134 | if (trb) { |
| 1135 | for (i = 0; i < num_trbs; i++) { |
| 1136 | pr_debug("TRB(%d): ADDRESS:%lx bpl:%x bph:%x size:%x ctrl:%x\n", |
| 1137 | i, (unsigned long)dwc3_trb_dma_offset(dep, |
| 1138 | &dep->trb_pool[i]), trb->bpl, trb->bph, |
| 1139 | trb->size, trb->ctrl); |
| 1140 | trb++; |
| 1141 | } |
| 1142 | } |
| 1143 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1144 | return 0; |
| 1145 | } |
| 1146 | |
| 1147 | /* |
| 1148 | * Frees TRBs for GSI EPs. |
| 1149 | * |
| 1150 | * @usb_ep - pointer to usb_ep instance. |
| 1151 | * |
| 1152 | */ |
| 1153 | static void gsi_free_trbs(struct usb_ep *ep) |
| 1154 | { |
| 1155 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1156 | |
| 1157 | if (dep->endpoint.ep_type == EP_TYPE_NORMAL) |
| 1158 | return; |
| 1159 | |
| 1160 | /* Free TRBs and TRB pool for EP */ |
| 1161 | if (dep->trb_dma_pool) { |
| 1162 | dma_pool_free(dep->trb_dma_pool, dep->trb_pool, |
| 1163 | dep->trb_pool_dma); |
| 1164 | dma_pool_destroy(dep->trb_dma_pool); |
| 1165 | dep->trb_pool = NULL; |
| 1166 | dep->trb_pool_dma = 0; |
| 1167 | dep->trb_dma_pool = NULL; |
| 1168 | } |
| 1169 | } |
| 1170 | /* |
| 1171 | * Configures GSI EPs. For GSI EPs we need to set interrupter numbers. |
| 1172 | * |
| 1173 | * @usb_ep - pointer to usb_ep instance. |
| 1174 | * @request - pointer to GSI request. |
| 1175 | */ |
| 1176 | static void gsi_configure_ep(struct usb_ep *ep, struct usb_gsi_request *request) |
| 1177 | { |
| 1178 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1179 | struct dwc3 *dwc = dep->dwc; |
| 1180 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1181 | struct dwc3_gadget_ep_cmd_params params; |
| 1182 | const struct usb_endpoint_descriptor *desc = ep->desc; |
| 1183 | const struct usb_ss_ep_comp_descriptor *comp_desc = ep->comp_desc; |
| 1184 | u32 reg; |
| 1185 | |
| 1186 | memset(¶ms, 0x00, sizeof(params)); |
| 1187 | |
| 1188 | /* Configure GSI EP */ |
| 1189 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
| 1190 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
| 1191 | |
| 1192 | /* Burst size is only needed in SuperSpeed mode */ |
| 1193 | if (dwc->gadget.speed == USB_SPEED_SUPER) { |
| 1194 | u32 burst = dep->endpoint.maxburst - 1; |
| 1195 | |
| 1196 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst); |
| 1197 | } |
| 1198 | |
| 1199 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
| 1200 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
| 1201 | | DWC3_DEPCFG_STREAM_EVENT_EN; |
| 1202 | dep->stream_capable = true; |
| 1203 | } |
| 1204 | |
| 1205 | /* Set EP number */ |
| 1206 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
| 1207 | |
| 1208 | /* Set interrupter number for GSI endpoints */ |
| 1209 | params.param1 |= DWC3_DEPCFG_INT_NUM(ep->ep_intr_num); |
| 1210 | |
| 1211 | /* Enable XferInProgress and XferComplete Interrupts */ |
| 1212 | params.param1 |= DWC3_DEPCFG_XFER_COMPLETE_EN; |
| 1213 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
| 1214 | params.param1 |= DWC3_DEPCFG_FIFO_ERROR_EN; |
| 1215 | /* |
| 1216 | * We must use the lower 16 TX FIFOs even though |
| 1217 | * HW might have more |
| 1218 | */ |
| 1219 | /* Remove FIFO Number for GSI EP*/ |
| 1220 | if (dep->direction) |
| 1221 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
| 1222 | |
| 1223 | params.param0 |= DWC3_DEPCFG_ACTION_INIT; |
| 1224 | |
| 1225 | dev_dbg(mdwc->dev, "Set EP config to params = %x %x %x, for %s\n", |
| 1226 | params.param0, params.param1, params.param2, dep->name); |
| 1227 | |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 1228 | dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1229 | |
| 1230 | /* Set XferRsc Index for GSI EP */ |
| 1231 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
| 1232 | memset(¶ms, 0x00, sizeof(params)); |
| 1233 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 1234 | dwc3_send_gadget_ep_cmd(dep, |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1235 | DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); |
| 1236 | |
| 1237 | dep->endpoint.desc = desc; |
| 1238 | dep->comp_desc = comp_desc; |
| 1239 | dep->type = usb_endpoint_type(desc); |
| 1240 | dep->flags |= DWC3_EP_ENABLED; |
| 1241 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
| 1242 | reg |= DWC3_DALEPENA_EP(dep->number); |
| 1243 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); |
| 1244 | } |
| 1245 | |
| 1246 | } |
| 1247 | |
| 1248 | /* |
| 1249 | * Enables USB wrapper for GSI |
| 1250 | * |
| 1251 | * @usb_ep - pointer to usb_ep instance. |
| 1252 | */ |
| 1253 | static void gsi_enable(struct usb_ep *ep) |
| 1254 | { |
| 1255 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1256 | struct dwc3 *dwc = dep->dwc; |
| 1257 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1258 | |
| 1259 | dwc3_msm_write_reg_field(mdwc->base, |
| 1260 | GSI_GENERAL_CFG_REG, GSI_CLK_EN_MASK, 1); |
| 1261 | dwc3_msm_write_reg_field(mdwc->base, |
| 1262 | GSI_GENERAL_CFG_REG, GSI_RESTART_DBL_PNTR_MASK, 1); |
| 1263 | dwc3_msm_write_reg_field(mdwc->base, |
| 1264 | GSI_GENERAL_CFG_REG, GSI_RESTART_DBL_PNTR_MASK, 0); |
| 1265 | dev_dbg(mdwc->dev, "%s: Enable GSI\n", __func__); |
| 1266 | dwc3_msm_write_reg_field(mdwc->base, |
| 1267 | GSI_GENERAL_CFG_REG, GSI_EN_MASK, 1); |
| 1268 | } |
| 1269 | |
| 1270 | /* |
| 1271 | * Block or allow doorbell towards GSI |
| 1272 | * |
| 1273 | * @usb_ep - pointer to usb_ep instance. |
| 1274 | * @request - pointer to GSI request. In this case num_bufs is used as a bool |
| 1275 | * to set or clear the doorbell bit |
| 1276 | */ |
| 1277 | static void gsi_set_clear_dbell(struct usb_ep *ep, |
| 1278 | bool block_db) |
| 1279 | { |
| 1280 | |
| 1281 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1282 | struct dwc3 *dwc = dep->dwc; |
| 1283 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1284 | |
| 1285 | dwc3_msm_write_reg_field(mdwc->base, |
| 1286 | GSI_GENERAL_CFG_REG, BLOCK_GSI_WR_GO_MASK, block_db); |
| 1287 | } |
| 1288 | |
| 1289 | /* |
| 1290 | * Performs necessary checks before stopping GSI channels |
| 1291 | * |
| 1292 | * @usb_ep - pointer to usb_ep instance to access DWC3 regs |
| 1293 | */ |
| 1294 | static bool gsi_check_ready_to_suspend(struct usb_ep *ep, bool f_suspend) |
| 1295 | { |
| 1296 | u32 timeout = 1500; |
| 1297 | u32 reg = 0; |
| 1298 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1299 | struct dwc3 *dwc = dep->dwc; |
| 1300 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1301 | |
| 1302 | while (dwc3_msm_read_reg_field(mdwc->base, |
| 1303 | GSI_IF_STS, GSI_WR_CTRL_STATE_MASK)) { |
| 1304 | if (!timeout--) { |
| 1305 | dev_err(mdwc->dev, |
| 1306 | "Unable to suspend GSI ch. WR_CTRL_STATE != 0\n"); |
| 1307 | return false; |
| 1308 | } |
| 1309 | } |
| 1310 | /* Check for U3 only if we are not handling Function Suspend */ |
| 1311 | if (!f_suspend) { |
| 1312 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
| 1313 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U3) { |
| 1314 | dev_err(mdwc->dev, "Unable to suspend GSI ch\n"); |
| 1315 | return false; |
| 1316 | } |
| 1317 | } |
| 1318 | |
| 1319 | return true; |
| 1320 | } |
| 1321 | |
| 1322 | |
| 1323 | /** |
| 1324 | * Performs GSI operations or GSI EP related operations. |
| 1325 | * |
| 1326 | * @usb_ep - pointer to usb_ep instance. |
| 1327 | * @op_data - pointer to opcode related data. |
| 1328 | * @op - GSI related or GSI EP related op code. |
| 1329 | * |
| 1330 | * @return int - 0 on success, negative on error. |
| 1331 | * Also returns XferRscIdx for GSI_EP_OP_GET_XFER_IDX. |
| 1332 | */ |
| 1333 | static int dwc3_msm_gsi_ep_op(struct usb_ep *ep, |
| 1334 | void *op_data, enum gsi_ep_op op) |
| 1335 | { |
| 1336 | u32 ret = 0; |
| 1337 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1338 | struct dwc3 *dwc = dep->dwc; |
| 1339 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1340 | struct usb_gsi_request *request; |
| 1341 | struct gsi_channel_info *ch_info; |
| 1342 | bool block_db, f_suspend; |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1343 | unsigned long flags; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1344 | |
| 1345 | switch (op) { |
| 1346 | case GSI_EP_OP_PREPARE_TRBS: |
| 1347 | request = (struct usb_gsi_request *)op_data; |
| 1348 | dev_dbg(mdwc->dev, "EP_OP_PREPARE_TRBS for %s\n", ep->name); |
| 1349 | ret = gsi_prepare_trbs(ep, request); |
| 1350 | break; |
| 1351 | case GSI_EP_OP_FREE_TRBS: |
| 1352 | dev_dbg(mdwc->dev, "EP_OP_FREE_TRBS for %s\n", ep->name); |
| 1353 | gsi_free_trbs(ep); |
| 1354 | break; |
| 1355 | case GSI_EP_OP_CONFIG: |
| 1356 | request = (struct usb_gsi_request *)op_data; |
| 1357 | dev_dbg(mdwc->dev, "EP_OP_CONFIG for %s\n", ep->name); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1358 | spin_lock_irqsave(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1359 | gsi_configure_ep(ep, request); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1360 | spin_unlock_irqrestore(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1361 | break; |
| 1362 | case GSI_EP_OP_STARTXFER: |
| 1363 | dev_dbg(mdwc->dev, "EP_OP_STARTXFER for %s\n", ep->name); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1364 | spin_lock_irqsave(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1365 | ret = gsi_startxfer_for_ep(ep); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1366 | spin_unlock_irqrestore(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1367 | break; |
| 1368 | case GSI_EP_OP_GET_XFER_IDX: |
| 1369 | dev_dbg(mdwc->dev, "EP_OP_GET_XFER_IDX for %s\n", ep->name); |
| 1370 | ret = gsi_get_xfer_index(ep); |
| 1371 | break; |
| 1372 | case GSI_EP_OP_STORE_DBL_INFO: |
| 1373 | dev_dbg(mdwc->dev, "EP_OP_STORE_DBL_INFO\n"); |
| 1374 | gsi_store_ringbase_dbl_info(ep, *((u32 *)op_data)); |
| 1375 | break; |
| 1376 | case GSI_EP_OP_ENABLE_GSI: |
| 1377 | dev_dbg(mdwc->dev, "EP_OP_ENABLE_GSI\n"); |
| 1378 | gsi_enable(ep); |
| 1379 | break; |
| 1380 | case GSI_EP_OP_GET_CH_INFO: |
| 1381 | ch_info = (struct gsi_channel_info *)op_data; |
| 1382 | gsi_get_channel_info(ep, ch_info); |
| 1383 | break; |
Mayank Rana | 64d136b | 2016-11-01 21:01:34 -0700 | [diff] [blame^] | 1384 | case GSI_EP_OP_RING_DB: |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1385 | request = (struct usb_gsi_request *)op_data; |
Mayank Rana | 64d136b | 2016-11-01 21:01:34 -0700 | [diff] [blame^] | 1386 | dbg_print(0xFF, "RING_DB", 0, ep->name); |
| 1387 | gsi_ring_db(ep, request); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1388 | break; |
| 1389 | case GSI_EP_OP_UPDATEXFER: |
| 1390 | request = (struct usb_gsi_request *)op_data; |
| 1391 | dev_dbg(mdwc->dev, "EP_OP_UPDATEXFER\n"); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1392 | spin_lock_irqsave(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1393 | ret = gsi_updatexfer_for_ep(ep, request); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1394 | spin_unlock_irqrestore(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1395 | break; |
| 1396 | case GSI_EP_OP_ENDXFER: |
| 1397 | request = (struct usb_gsi_request *)op_data; |
| 1398 | dev_dbg(mdwc->dev, "EP_OP_ENDXFER for %s\n", ep->name); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1399 | spin_lock_irqsave(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1400 | gsi_endxfer_for_ep(ep); |
Mayank Rana | 8432c36 | 2016-09-30 18:41:17 -0700 | [diff] [blame] | 1401 | spin_unlock_irqrestore(&dwc->lock, flags); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1402 | break; |
| 1403 | case GSI_EP_OP_SET_CLR_BLOCK_DBL: |
| 1404 | block_db = *((bool *)op_data); |
| 1405 | dev_dbg(mdwc->dev, "EP_OP_SET_CLR_BLOCK_DBL %d\n", |
| 1406 | block_db); |
| 1407 | gsi_set_clear_dbell(ep, block_db); |
| 1408 | break; |
| 1409 | case GSI_EP_OP_CHECK_FOR_SUSPEND: |
| 1410 | dev_dbg(mdwc->dev, "EP_OP_CHECK_FOR_SUSPEND\n"); |
| 1411 | f_suspend = *((bool *)op_data); |
| 1412 | ret = gsi_check_ready_to_suspend(ep, f_suspend); |
| 1413 | break; |
| 1414 | case GSI_EP_OP_DISABLE: |
| 1415 | dev_dbg(mdwc->dev, "EP_OP_DISABLE\n"); |
| 1416 | ret = ep->ops->disable(ep); |
| 1417 | break; |
| 1418 | default: |
| 1419 | dev_err(mdwc->dev, "%s: Invalid opcode GSI EP\n", __func__); |
| 1420 | } |
| 1421 | |
| 1422 | return ret; |
| 1423 | } |
| 1424 | |
| 1425 | /** |
| 1426 | * Configure MSM endpoint. |
| 1427 | * This function do specific configurations |
| 1428 | * to an endpoint which need specific implementaion |
| 1429 | * in the MSM architecture. |
| 1430 | * |
| 1431 | * This function should be called by usb function/class |
| 1432 | * layer which need a support from the specific MSM HW |
| 1433 | * which wrap the USB3 core. (like GSI or DBM specific endpoints) |
| 1434 | * |
| 1435 | * @ep - a pointer to some usb_ep instance |
| 1436 | * |
| 1437 | * @return int - 0 on success, negetive on error. |
| 1438 | */ |
| 1439 | int msm_ep_config(struct usb_ep *ep) |
| 1440 | { |
| 1441 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1442 | struct dwc3 *dwc = dep->dwc; |
| 1443 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1444 | struct usb_ep_ops *new_ep_ops; |
| 1445 | |
| 1446 | |
| 1447 | /* Save original ep ops for future restore*/ |
| 1448 | if (mdwc->original_ep_ops[dep->number]) { |
| 1449 | dev_err(mdwc->dev, |
| 1450 | "ep [%s,%d] already configured as msm endpoint\n", |
| 1451 | ep->name, dep->number); |
| 1452 | return -EPERM; |
| 1453 | } |
| 1454 | mdwc->original_ep_ops[dep->number] = ep->ops; |
| 1455 | |
| 1456 | /* Set new usb ops as we like */ |
| 1457 | new_ep_ops = kzalloc(sizeof(struct usb_ep_ops), GFP_ATOMIC); |
| 1458 | if (!new_ep_ops) |
| 1459 | return -ENOMEM; |
| 1460 | |
| 1461 | (*new_ep_ops) = (*ep->ops); |
| 1462 | new_ep_ops->queue = dwc3_msm_ep_queue; |
| 1463 | new_ep_ops->gsi_ep_op = dwc3_msm_gsi_ep_op; |
| 1464 | ep->ops = new_ep_ops; |
| 1465 | |
| 1466 | /* |
| 1467 | * Do HERE more usb endpoint configurations |
| 1468 | * which are specific to MSM. |
| 1469 | */ |
| 1470 | |
| 1471 | return 0; |
| 1472 | } |
| 1473 | EXPORT_SYMBOL(msm_ep_config); |
| 1474 | |
| 1475 | /** |
| 1476 | * Un-configure MSM endpoint. |
| 1477 | * Tear down configurations done in the |
| 1478 | * dwc3_msm_ep_config function. |
| 1479 | * |
| 1480 | * @ep - a pointer to some usb_ep instance |
| 1481 | * |
| 1482 | * @return int - 0 on success, negative on error. |
| 1483 | */ |
| 1484 | int msm_ep_unconfig(struct usb_ep *ep) |
| 1485 | { |
| 1486 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
| 1487 | struct dwc3 *dwc = dep->dwc; |
| 1488 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1489 | struct usb_ep_ops *old_ep_ops; |
| 1490 | |
| 1491 | /* Restore original ep ops */ |
| 1492 | if (!mdwc->original_ep_ops[dep->number]) { |
| 1493 | dev_err(mdwc->dev, |
| 1494 | "ep [%s,%d] was not configured as msm endpoint\n", |
| 1495 | ep->name, dep->number); |
| 1496 | return -EINVAL; |
| 1497 | } |
| 1498 | old_ep_ops = (struct usb_ep_ops *)ep->ops; |
| 1499 | ep->ops = mdwc->original_ep_ops[dep->number]; |
| 1500 | mdwc->original_ep_ops[dep->number] = NULL; |
| 1501 | kfree(old_ep_ops); |
| 1502 | |
| 1503 | /* |
| 1504 | * Do HERE more usb endpoint un-configurations |
| 1505 | * which are specific to MSM. |
| 1506 | */ |
| 1507 | |
| 1508 | return 0; |
| 1509 | } |
| 1510 | EXPORT_SYMBOL(msm_ep_unconfig); |
| 1511 | #endif /* (CONFIG_USB_DWC3_GADGET) || (CONFIG_USB_DWC3_DUAL_ROLE) */ |
| 1512 | |
| 1513 | static void dwc3_resume_work(struct work_struct *w); |
| 1514 | |
| 1515 | static void dwc3_restart_usb_work(struct work_struct *w) |
| 1516 | { |
| 1517 | struct dwc3_msm *mdwc = container_of(w, struct dwc3_msm, |
| 1518 | restart_usb_work); |
| 1519 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 1520 | unsigned int timeout = 50; |
| 1521 | |
| 1522 | dev_dbg(mdwc->dev, "%s\n", __func__); |
| 1523 | |
| 1524 | if (atomic_read(&dwc->in_lpm) || !dwc->is_drd) { |
| 1525 | dev_dbg(mdwc->dev, "%s failed!!!\n", __func__); |
| 1526 | return; |
| 1527 | } |
| 1528 | |
| 1529 | /* guard against concurrent VBUS handling */ |
| 1530 | mdwc->in_restart = true; |
| 1531 | |
| 1532 | if (!mdwc->vbus_active) { |
| 1533 | dev_dbg(mdwc->dev, "%s bailing out in disconnect\n", __func__); |
| 1534 | dwc->err_evt_seen = false; |
| 1535 | mdwc->in_restart = false; |
| 1536 | return; |
| 1537 | } |
| 1538 | |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 1539 | dbg_event(0xFF, "RestartUSB", 0); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1540 | /* Reset active USB connection */ |
| 1541 | dwc3_resume_work(&mdwc->resume_work); |
| 1542 | |
| 1543 | /* Make sure disconnect is processed before sending connect */ |
| 1544 | while (--timeout && !pm_runtime_suspended(mdwc->dev)) |
| 1545 | msleep(20); |
| 1546 | |
| 1547 | if (!timeout) { |
| 1548 | dev_dbg(mdwc->dev, |
| 1549 | "Not in LPM after disconnect, forcing suspend...\n"); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 1550 | dbg_event(0xFF, "ReStart:RT SUSP", |
| 1551 | atomic_read(&mdwc->dev->power.usage_count)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1552 | pm_runtime_suspend(mdwc->dev); |
| 1553 | } |
| 1554 | |
Vijayavardhan Vennapusa | 5e5680e | 2016-11-25 11:25:35 +0530 | [diff] [blame] | 1555 | mdwc->in_restart = false; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1556 | /* Force reconnect only if cable is still connected */ |
Vijayavardhan Vennapusa | 5e5680e | 2016-11-25 11:25:35 +0530 | [diff] [blame] | 1557 | if (mdwc->vbus_active) |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1558 | dwc3_resume_work(&mdwc->resume_work); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1559 | |
| 1560 | dwc->err_evt_seen = false; |
| 1561 | flush_delayed_work(&mdwc->sm_work); |
| 1562 | } |
| 1563 | |
Manu Gautam | 976fdfc | 2016-08-18 09:27:35 +0530 | [diff] [blame] | 1564 | static int msm_dwc3_usbdev_notify(struct notifier_block *self, |
| 1565 | unsigned long action, void *priv) |
| 1566 | { |
| 1567 | struct dwc3_msm *mdwc = container_of(self, struct dwc3_msm, usbdev_nb); |
| 1568 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 1569 | struct usb_bus *bus = priv; |
| 1570 | |
| 1571 | /* Interested only in recovery when HC dies */ |
| 1572 | if (action != USB_BUS_DIED) |
| 1573 | return 0; |
| 1574 | |
| 1575 | dev_dbg(mdwc->dev, "%s initiate recovery from hc_died\n", __func__); |
| 1576 | /* Recovery already under process */ |
| 1577 | if (mdwc->hc_died) |
| 1578 | return 0; |
| 1579 | |
| 1580 | if (bus->controller != &dwc->xhci->dev) { |
| 1581 | dev_dbg(mdwc->dev, "%s event for diff HCD\n", __func__); |
| 1582 | return 0; |
| 1583 | } |
| 1584 | |
| 1585 | mdwc->hc_died = true; |
| 1586 | schedule_delayed_work(&mdwc->sm_work, 0); |
| 1587 | return 0; |
| 1588 | } |
| 1589 | |
| 1590 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1591 | /* |
| 1592 | * Check whether the DWC3 requires resetting the ep |
| 1593 | * after going to Low Power Mode (lpm) |
| 1594 | */ |
| 1595 | bool msm_dwc3_reset_ep_after_lpm(struct usb_gadget *gadget) |
| 1596 | { |
| 1597 | struct dwc3 *dwc = container_of(gadget, struct dwc3, gadget); |
| 1598 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
| 1599 | |
| 1600 | return dbm_reset_ep_after_lpm(mdwc->dbm); |
| 1601 | } |
| 1602 | EXPORT_SYMBOL(msm_dwc3_reset_ep_after_lpm); |
| 1603 | |
| 1604 | /* |
| 1605 | * Config Global Distributed Switch Controller (GDSC) |
| 1606 | * to support controller power collapse |
| 1607 | */ |
| 1608 | static int dwc3_msm_config_gdsc(struct dwc3_msm *mdwc, int on) |
| 1609 | { |
| 1610 | int ret; |
| 1611 | |
| 1612 | if (IS_ERR_OR_NULL(mdwc->dwc3_gdsc)) |
| 1613 | return -EPERM; |
| 1614 | |
| 1615 | if (on) { |
| 1616 | ret = regulator_enable(mdwc->dwc3_gdsc); |
| 1617 | if (ret) { |
| 1618 | dev_err(mdwc->dev, "unable to enable usb3 gdsc\n"); |
| 1619 | return ret; |
| 1620 | } |
| 1621 | } else { |
| 1622 | ret = regulator_disable(mdwc->dwc3_gdsc); |
| 1623 | if (ret) { |
| 1624 | dev_err(mdwc->dev, "unable to disable usb3 gdsc\n"); |
| 1625 | return ret; |
| 1626 | } |
| 1627 | } |
| 1628 | |
| 1629 | return ret; |
| 1630 | } |
| 1631 | |
| 1632 | static int dwc3_msm_link_clk_reset(struct dwc3_msm *mdwc, bool assert) |
| 1633 | { |
| 1634 | int ret = 0; |
| 1635 | |
| 1636 | if (assert) { |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 1637 | disable_irq(mdwc->wakeup_irq[PWR_EVNT_IRQ].irq); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1638 | /* Using asynchronous block reset to the hardware */ |
| 1639 | dev_dbg(mdwc->dev, "block_reset ASSERT\n"); |
| 1640 | clk_disable_unprepare(mdwc->utmi_clk); |
| 1641 | clk_disable_unprepare(mdwc->sleep_clk); |
| 1642 | clk_disable_unprepare(mdwc->core_clk); |
| 1643 | clk_disable_unprepare(mdwc->iface_clk); |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 1644 | ret = reset_control_assert(mdwc->core_reset); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1645 | if (ret) |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 1646 | dev_err(mdwc->dev, "dwc3 core_reset assert failed\n"); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1647 | } else { |
| 1648 | dev_dbg(mdwc->dev, "block_reset DEASSERT\n"); |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 1649 | ret = reset_control_deassert(mdwc->core_reset); |
| 1650 | if (ret) |
| 1651 | dev_err(mdwc->dev, "dwc3 core_reset deassert failed\n"); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1652 | ndelay(200); |
| 1653 | clk_prepare_enable(mdwc->iface_clk); |
| 1654 | clk_prepare_enable(mdwc->core_clk); |
| 1655 | clk_prepare_enable(mdwc->sleep_clk); |
| 1656 | clk_prepare_enable(mdwc->utmi_clk); |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 1657 | enable_irq(mdwc->wakeup_irq[PWR_EVNT_IRQ].irq); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1658 | } |
| 1659 | |
| 1660 | return ret; |
| 1661 | } |
| 1662 | |
| 1663 | static void dwc3_msm_update_ref_clk(struct dwc3_msm *mdwc) |
| 1664 | { |
| 1665 | u32 guctl, gfladj = 0; |
| 1666 | |
| 1667 | guctl = dwc3_msm_read_reg(mdwc->base, DWC3_GUCTL); |
| 1668 | guctl &= ~DWC3_GUCTL_REFCLKPER; |
| 1669 | |
| 1670 | /* GFLADJ register is used starting with revision 2.50a */ |
| 1671 | if (dwc3_msm_read_reg(mdwc->base, DWC3_GSNPSID) >= DWC3_REVISION_250A) { |
| 1672 | gfladj = dwc3_msm_read_reg(mdwc->base, DWC3_GFLADJ); |
| 1673 | gfladj &= ~DWC3_GFLADJ_REFCLK_240MHZDECR_PLS1; |
| 1674 | gfladj &= ~DWC3_GFLADJ_REFCLK_240MHZ_DECR; |
| 1675 | gfladj &= ~DWC3_GFLADJ_REFCLK_LPM_SEL; |
| 1676 | gfladj &= ~DWC3_GFLADJ_REFCLK_FLADJ; |
| 1677 | } |
| 1678 | |
| 1679 | /* Refer to SNPS Databook Table 6-55 for calculations used */ |
| 1680 | switch (mdwc->utmi_clk_rate) { |
| 1681 | case 19200000: |
| 1682 | guctl |= 52 << __ffs(DWC3_GUCTL_REFCLKPER); |
| 1683 | gfladj |= 12 << __ffs(DWC3_GFLADJ_REFCLK_240MHZ_DECR); |
| 1684 | gfladj |= DWC3_GFLADJ_REFCLK_240MHZDECR_PLS1; |
| 1685 | gfladj |= DWC3_GFLADJ_REFCLK_LPM_SEL; |
| 1686 | gfladj |= 200 << __ffs(DWC3_GFLADJ_REFCLK_FLADJ); |
| 1687 | break; |
| 1688 | case 24000000: |
| 1689 | guctl |= 41 << __ffs(DWC3_GUCTL_REFCLKPER); |
| 1690 | gfladj |= 10 << __ffs(DWC3_GFLADJ_REFCLK_240MHZ_DECR); |
| 1691 | gfladj |= DWC3_GFLADJ_REFCLK_LPM_SEL; |
| 1692 | gfladj |= 2032 << __ffs(DWC3_GFLADJ_REFCLK_FLADJ); |
| 1693 | break; |
| 1694 | default: |
| 1695 | dev_warn(mdwc->dev, "Unsupported utmi_clk_rate: %u\n", |
| 1696 | mdwc->utmi_clk_rate); |
| 1697 | break; |
| 1698 | } |
| 1699 | |
| 1700 | dwc3_msm_write_reg(mdwc->base, DWC3_GUCTL, guctl); |
| 1701 | if (gfladj) |
| 1702 | dwc3_msm_write_reg(mdwc->base, DWC3_GFLADJ, gfladj); |
| 1703 | } |
| 1704 | |
| 1705 | /* Initialize QSCRATCH registers for HSPHY and SSPHY operation */ |
| 1706 | static void dwc3_msm_qscratch_reg_init(struct dwc3_msm *mdwc) |
| 1707 | { |
| 1708 | if (dwc3_msm_read_reg(mdwc->base, DWC3_GSNPSID) < DWC3_REVISION_250A) |
| 1709 | /* On older cores set XHCI_REV bit to specify revision 1.0 */ |
| 1710 | dwc3_msm_write_reg_field(mdwc->base, QSCRATCH_GENERAL_CFG, |
| 1711 | BIT(2), 1); |
| 1712 | |
| 1713 | /* |
| 1714 | * Enable master clock for RAMs to allow BAM to access RAMs when |
| 1715 | * RAM clock gating is enabled via DWC3's GCTL. Otherwise issues |
| 1716 | * are seen where RAM clocks get turned OFF in SS mode |
| 1717 | */ |
| 1718 | dwc3_msm_write_reg(mdwc->base, CGCTL_REG, |
| 1719 | dwc3_msm_read_reg(mdwc->base, CGCTL_REG) | 0x18); |
| 1720 | |
| 1721 | } |
| 1722 | |
Jack Pham | 4b8b4ae | 2016-08-09 11:36:34 -0700 | [diff] [blame] | 1723 | static void dwc3_msm_vbus_draw_work(struct work_struct *w) |
| 1724 | { |
| 1725 | struct dwc3_msm *mdwc = container_of(w, struct dwc3_msm, |
| 1726 | vbus_draw_work); |
| 1727 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 1728 | |
| 1729 | dwc3_msm_gadget_vbus_draw(mdwc, dwc->vbus_draw); |
| 1730 | } |
| 1731 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1732 | static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event) |
| 1733 | { |
| 1734 | struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 1735 | struct dwc3_event_buffer *evt; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1736 | u32 reg; |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 1737 | int i; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1738 | |
| 1739 | switch (event) { |
| 1740 | case DWC3_CONTROLLER_ERROR_EVENT: |
| 1741 | dev_info(mdwc->dev, |
| 1742 | "DWC3_CONTROLLER_ERROR_EVENT received, irq cnt %lu\n", |
| 1743 | dwc->irq_cnt); |
| 1744 | |
| 1745 | dwc3_gadget_disable_irq(dwc); |
| 1746 | |
| 1747 | /* prevent core from generating interrupts until recovery */ |
| 1748 | reg = dwc3_msm_read_reg(mdwc->base, DWC3_GCTL); |
| 1749 | reg |= DWC3_GCTL_CORESOFTRESET; |
| 1750 | dwc3_msm_write_reg(mdwc->base, DWC3_GCTL, reg); |
| 1751 | |
| 1752 | /* restart USB which performs full reset and reconnect */ |
| 1753 | schedule_work(&mdwc->restart_usb_work); |
| 1754 | break; |
| 1755 | case DWC3_CONTROLLER_RESET_EVENT: |
| 1756 | dev_dbg(mdwc->dev, "DWC3_CONTROLLER_RESET_EVENT received\n"); |
| 1757 | /* HS & SSPHYs get reset as part of core soft reset */ |
| 1758 | dwc3_msm_qscratch_reg_init(mdwc); |
| 1759 | break; |
| 1760 | case DWC3_CONTROLLER_POST_RESET_EVENT: |
| 1761 | dev_dbg(mdwc->dev, |
| 1762 | "DWC3_CONTROLLER_POST_RESET_EVENT received\n"); |
| 1763 | |
| 1764 | /* |
| 1765 | * Below sequence is used when controller is working without |
| 1766 | * having ssphy and only USB high speed is supported. |
| 1767 | */ |
| 1768 | if (dwc->maximum_speed == USB_SPEED_HIGH) { |
| 1769 | dwc3_msm_write_reg(mdwc->base, QSCRATCH_GENERAL_CFG, |
| 1770 | dwc3_msm_read_reg(mdwc->base, |
| 1771 | QSCRATCH_GENERAL_CFG) |
| 1772 | | PIPE_UTMI_CLK_DIS); |
| 1773 | |
| 1774 | usleep_range(2, 5); |
| 1775 | |
| 1776 | |
| 1777 | dwc3_msm_write_reg(mdwc->base, QSCRATCH_GENERAL_CFG, |
| 1778 | dwc3_msm_read_reg(mdwc->base, |
| 1779 | QSCRATCH_GENERAL_CFG) |
| 1780 | | PIPE_UTMI_CLK_SEL |
| 1781 | | PIPE3_PHYSTATUS_SW); |
| 1782 | |
| 1783 | usleep_range(2, 5); |
| 1784 | |
| 1785 | dwc3_msm_write_reg(mdwc->base, QSCRATCH_GENERAL_CFG, |
| 1786 | dwc3_msm_read_reg(mdwc->base, |
| 1787 | QSCRATCH_GENERAL_CFG) |
| 1788 | & ~PIPE_UTMI_CLK_DIS); |
| 1789 | } |
| 1790 | |
| 1791 | dwc3_msm_update_ref_clk(mdwc); |
| 1792 | dwc->tx_fifo_size = mdwc->tx_fifo_size; |
| 1793 | break; |
| 1794 | case DWC3_CONTROLLER_CONNDONE_EVENT: |
| 1795 | dev_dbg(mdwc->dev, "DWC3_CONTROLLER_CONNDONE_EVENT received\n"); |
| 1796 | /* |
| 1797 | * Add power event if the dbm indicates coming out of L1 by |
| 1798 | * interrupt |
| 1799 | */ |
| 1800 | if (mdwc->dbm && dbm_l1_lpm_interrupt(mdwc->dbm)) |
| 1801 | dwc3_msm_write_reg_field(mdwc->base, |
| 1802 | PWR_EVNT_IRQ_MASK_REG, |
| 1803 | PWR_EVNT_LPM_OUT_L1_MASK, 1); |
| 1804 | |
| 1805 | atomic_set(&dwc->in_lpm, 0); |
| 1806 | break; |
| 1807 | case DWC3_CONTROLLER_NOTIFY_OTG_EVENT: |
| 1808 | dev_dbg(mdwc->dev, "DWC3_CONTROLLER_NOTIFY_OTG_EVENT received\n"); |
| 1809 | if (dwc->enable_bus_suspend) { |
| 1810 | mdwc->suspend = dwc->b_suspend; |
| 1811 | queue_work(mdwc->dwc3_wq, &mdwc->resume_work); |
| 1812 | } |
| 1813 | break; |
| 1814 | case DWC3_CONTROLLER_SET_CURRENT_DRAW_EVENT: |
| 1815 | dev_dbg(mdwc->dev, "DWC3_CONTROLLER_SET_CURRENT_DRAW_EVENT received\n"); |
Jack Pham | 4b8b4ae | 2016-08-09 11:36:34 -0700 | [diff] [blame] | 1816 | schedule_work(&mdwc->vbus_draw_work); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1817 | break; |
| 1818 | case DWC3_CONTROLLER_RESTART_USB_SESSION: |
| 1819 | dev_dbg(mdwc->dev, "DWC3_CONTROLLER_RESTART_USB_SESSION received\n"); |
Hemant Kumar | 4387417 | 2016-08-25 16:17:48 -0700 | [diff] [blame] | 1820 | schedule_work(&mdwc->restart_usb_work); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1821 | break; |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 1822 | case DWC3_GSI_EVT_BUF_ALLOC: |
| 1823 | dev_dbg(mdwc->dev, "DWC3_GSI_EVT_BUF_ALLOC\n"); |
| 1824 | |
| 1825 | if (!mdwc->num_gsi_event_buffers) |
| 1826 | break; |
| 1827 | |
| 1828 | mdwc->gsi_ev_buff = devm_kzalloc(dwc->dev, |
| 1829 | sizeof(*dwc->ev_buf) * mdwc->num_gsi_event_buffers, |
| 1830 | GFP_KERNEL); |
| 1831 | if (!mdwc->gsi_ev_buff) { |
| 1832 | dev_err(dwc->dev, "can't allocate gsi_ev_buff\n"); |
| 1833 | break; |
| 1834 | } |
| 1835 | |
| 1836 | for (i = 0; i < mdwc->num_gsi_event_buffers; i++) { |
| 1837 | |
| 1838 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
| 1839 | if (!evt) |
| 1840 | break; |
| 1841 | evt->dwc = dwc; |
| 1842 | evt->length = DWC3_EVENT_BUFFERS_SIZE; |
| 1843 | evt->buf = dma_alloc_coherent(dwc->dev, |
| 1844 | DWC3_EVENT_BUFFERS_SIZE, |
| 1845 | &evt->dma, GFP_KERNEL); |
| 1846 | if (!evt->buf) { |
| 1847 | dev_err(dwc->dev, |
| 1848 | "can't allocate gsi_evt_buf(%d)\n", i); |
| 1849 | break; |
| 1850 | } |
| 1851 | mdwc->gsi_ev_buff[i] = evt; |
| 1852 | } |
| 1853 | break; |
| 1854 | case DWC3_GSI_EVT_BUF_SETUP: |
| 1855 | dev_dbg(mdwc->dev, "DWC3_GSI_EVT_BUF_SETUP\n"); |
| 1856 | for (i = 0; i < mdwc->num_gsi_event_buffers; i++) { |
| 1857 | evt = mdwc->gsi_ev_buff[i]; |
| 1858 | dev_dbg(mdwc->dev, "Evt buf %p dma %08llx length %d\n", |
| 1859 | evt->buf, (unsigned long long) evt->dma, |
| 1860 | evt->length); |
| 1861 | memset(evt->buf, 0, evt->length); |
| 1862 | evt->lpos = 0; |
| 1863 | /* |
| 1864 | * Primary event buffer is programmed with registers |
| 1865 | * DWC3_GEVNT*(0). Hence use DWC3_GEVNT*(i+1) to |
| 1866 | * program USB GSI related event buffer with DWC3 |
| 1867 | * controller. |
| 1868 | */ |
| 1869 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO((i+1)), |
| 1870 | lower_32_bits(evt->dma)); |
| 1871 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI((i+1)), |
| 1872 | DWC3_GEVNTADRHI_EVNTADRHI_GSI_EN( |
| 1873 | DWC3_GEVENT_TYPE_GSI) | |
| 1874 | DWC3_GEVNTADRHI_EVNTADRHI_GSI_IDX((i+1))); |
| 1875 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ((i+1)), |
| 1876 | DWC3_GEVNTCOUNT_EVNTINTRPTMASK | |
| 1877 | ((evt->length) & 0xffff)); |
| 1878 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT((i+1)), 0); |
| 1879 | } |
| 1880 | break; |
| 1881 | case DWC3_GSI_EVT_BUF_CLEANUP: |
| 1882 | dev_dbg(mdwc->dev, "DWC3_GSI_EVT_BUF_CLEANUP\n"); |
| 1883 | for (i = 0; i < mdwc->num_gsi_event_buffers; i++) { |
| 1884 | evt = mdwc->gsi_ev_buff[i]; |
| 1885 | evt->lpos = 0; |
| 1886 | /* |
| 1887 | * Primary event buffer is programmed with registers |
| 1888 | * DWC3_GEVNT*(0). Hence use DWC3_GEVNT*(i+1) to |
| 1889 | * program USB GSI related event buffer with DWC3 |
| 1890 | * controller. |
| 1891 | */ |
| 1892 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO((i+1)), 0); |
| 1893 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI((i+1)), 0); |
| 1894 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ((i+1)), |
| 1895 | DWC3_GEVNTSIZ_INTMASK | |
| 1896 | DWC3_GEVNTSIZ_SIZE((i+1))); |
| 1897 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT((i+1)), 0); |
| 1898 | } |
| 1899 | break; |
| 1900 | case DWC3_GSI_EVT_BUF_FREE: |
| 1901 | dev_dbg(mdwc->dev, "DWC3_GSI_EVT_BUF_FREE\n"); |
| 1902 | for (i = 0; i < mdwc->num_gsi_event_buffers; i++) { |
| 1903 | evt = mdwc->gsi_ev_buff[i]; |
| 1904 | if (evt) |
| 1905 | dma_free_coherent(dwc->dev, evt->length, |
| 1906 | evt->buf, evt->dma); |
| 1907 | } |
| 1908 | break; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1909 | default: |
| 1910 | dev_dbg(mdwc->dev, "unknown dwc3 event\n"); |
| 1911 | break; |
| 1912 | } |
| 1913 | } |
| 1914 | |
| 1915 | static void dwc3_msm_block_reset(struct dwc3_msm *mdwc, bool core_reset) |
| 1916 | { |
| 1917 | int ret = 0; |
| 1918 | |
| 1919 | if (core_reset) { |
| 1920 | ret = dwc3_msm_link_clk_reset(mdwc, 1); |
| 1921 | if (ret) |
| 1922 | return; |
| 1923 | |
| 1924 | usleep_range(1000, 1200); |
| 1925 | ret = dwc3_msm_link_clk_reset(mdwc, 0); |
| 1926 | if (ret) |
| 1927 | return; |
| 1928 | |
| 1929 | usleep_range(10000, 12000); |
| 1930 | } |
| 1931 | |
| 1932 | if (mdwc->dbm) { |
| 1933 | /* Reset the DBM */ |
| 1934 | dbm_soft_reset(mdwc->dbm, 1); |
| 1935 | usleep_range(1000, 1200); |
| 1936 | dbm_soft_reset(mdwc->dbm, 0); |
| 1937 | |
| 1938 | /*enable DBM*/ |
| 1939 | dwc3_msm_write_reg_field(mdwc->base, QSCRATCH_GENERAL_CFG, |
| 1940 | DBM_EN_MASK, 0x1); |
| 1941 | dbm_enable(mdwc->dbm); |
| 1942 | } |
| 1943 | } |
| 1944 | |
| 1945 | static void dwc3_msm_power_collapse_por(struct dwc3_msm *mdwc) |
| 1946 | { |
| 1947 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 1948 | u32 val; |
Vijayavardhan Vennapusa | 8e6a11e | 2016-12-06 12:04:21 +0530 | [diff] [blame] | 1949 | int ret; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1950 | |
| 1951 | /* Configure AHB2PHY for one wait state read/write */ |
| 1952 | if (mdwc->ahb2phy_base) { |
| 1953 | clk_prepare_enable(mdwc->cfg_ahb_clk); |
| 1954 | val = readl_relaxed(mdwc->ahb2phy_base + |
| 1955 | PERIPH_SS_AHB2PHY_TOP_CFG); |
| 1956 | if (val != ONE_READ_WRITE_WAIT) { |
| 1957 | writel_relaxed(ONE_READ_WRITE_WAIT, |
| 1958 | mdwc->ahb2phy_base + PERIPH_SS_AHB2PHY_TOP_CFG); |
| 1959 | /* complete above write before configuring USB PHY. */ |
| 1960 | mb(); |
| 1961 | } |
| 1962 | clk_disable_unprepare(mdwc->cfg_ahb_clk); |
| 1963 | } |
| 1964 | |
| 1965 | if (!mdwc->init) { |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 1966 | dbg_event(0xFF, "dwc3 init", |
| 1967 | atomic_read(&mdwc->dev->power.usage_count)); |
Vijayavardhan Vennapusa | 8e6a11e | 2016-12-06 12:04:21 +0530 | [diff] [blame] | 1968 | ret = dwc3_core_pre_init(dwc); |
| 1969 | if (ret) { |
| 1970 | dev_err(mdwc->dev, "dwc3_core_pre_init failed\n"); |
| 1971 | return; |
| 1972 | } |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1973 | mdwc->init = true; |
| 1974 | } |
| 1975 | |
| 1976 | dwc3_core_init(dwc); |
| 1977 | /* Re-configure event buffers */ |
| 1978 | dwc3_event_buffers_setup(dwc); |
| 1979 | } |
| 1980 | |
| 1981 | static int dwc3_msm_prepare_suspend(struct dwc3_msm *mdwc) |
| 1982 | { |
| 1983 | unsigned long timeout; |
| 1984 | u32 reg = 0; |
| 1985 | |
| 1986 | if ((mdwc->in_host_mode || mdwc->vbus_active) |
Vijayavardhan Vennapusa | 8cf91a6 | 2016-09-01 12:05:50 +0530 | [diff] [blame] | 1987 | && dwc3_msm_is_superspeed(mdwc) && !mdwc->in_restart) { |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1988 | if (!atomic_read(&mdwc->in_p3)) { |
| 1989 | dev_err(mdwc->dev, "Not in P3,aborting LPM sequence\n"); |
| 1990 | return -EBUSY; |
| 1991 | } |
| 1992 | } |
| 1993 | |
| 1994 | /* Clear previous L2 events */ |
| 1995 | dwc3_msm_write_reg(mdwc->base, PWR_EVNT_IRQ_STAT_REG, |
| 1996 | PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); |
| 1997 | |
| 1998 | /* Prepare HSPHY for suspend */ |
| 1999 | reg = dwc3_msm_read_reg(mdwc->base, DWC3_GUSB2PHYCFG(0)); |
| 2000 | dwc3_msm_write_reg(mdwc->base, DWC3_GUSB2PHYCFG(0), |
| 2001 | reg | DWC3_GUSB2PHYCFG_ENBLSLPM | DWC3_GUSB2PHYCFG_SUSPHY); |
| 2002 | |
| 2003 | /* Wait for PHY to go into L2 */ |
| 2004 | timeout = jiffies + msecs_to_jiffies(5); |
| 2005 | while (!time_after(jiffies, timeout)) { |
| 2006 | reg = dwc3_msm_read_reg(mdwc->base, PWR_EVNT_IRQ_STAT_REG); |
| 2007 | if (reg & PWR_EVNT_LPM_IN_L2_MASK) |
| 2008 | break; |
| 2009 | } |
| 2010 | if (!(reg & PWR_EVNT_LPM_IN_L2_MASK)) |
| 2011 | dev_err(mdwc->dev, "could not transition HS PHY to L2\n"); |
| 2012 | |
| 2013 | /* Clear L2 event bit */ |
| 2014 | dwc3_msm_write_reg(mdwc->base, PWR_EVNT_IRQ_STAT_REG, |
| 2015 | PWR_EVNT_LPM_IN_L2_MASK); |
| 2016 | |
| 2017 | return 0; |
| 2018 | } |
| 2019 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2020 | static void dwc3_set_phy_speed_flags(struct dwc3_msm *mdwc) |
| 2021 | { |
| 2022 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 2023 | int i, num_ports; |
| 2024 | u32 reg; |
| 2025 | |
| 2026 | mdwc->hs_phy->flags &= ~(PHY_HSFS_MODE | PHY_LS_MODE); |
| 2027 | if (mdwc->in_host_mode) { |
| 2028 | reg = dwc3_msm_read_reg(mdwc->base, USB3_HCSPARAMS1); |
| 2029 | num_ports = HCS_MAX_PORTS(reg); |
| 2030 | for (i = 0; i < num_ports; i++) { |
| 2031 | reg = dwc3_msm_read_reg(mdwc->base, |
| 2032 | USB3_PORTSC + i*0x10); |
| 2033 | if (reg & PORT_PE) { |
| 2034 | if (DEV_HIGHSPEED(reg) || DEV_FULLSPEED(reg)) |
| 2035 | mdwc->hs_phy->flags |= PHY_HSFS_MODE; |
| 2036 | else if (DEV_LOWSPEED(reg)) |
| 2037 | mdwc->hs_phy->flags |= PHY_LS_MODE; |
| 2038 | } |
| 2039 | } |
| 2040 | } else { |
| 2041 | if (dwc->gadget.speed == USB_SPEED_HIGH || |
| 2042 | dwc->gadget.speed == USB_SPEED_FULL) |
| 2043 | mdwc->hs_phy->flags |= PHY_HSFS_MODE; |
| 2044 | else if (dwc->gadget.speed == USB_SPEED_LOW) |
| 2045 | mdwc->hs_phy->flags |= PHY_LS_MODE; |
| 2046 | } |
| 2047 | } |
| 2048 | |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame] | 2049 | static void msm_dwc3_perf_vote_update(struct dwc3_msm *mdwc, |
| 2050 | bool perf_mode); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2051 | |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 2052 | static void configure_usb_wakeup_interrupt(struct dwc3_msm *mdwc, |
| 2053 | struct usb_irq *uirq, unsigned int polarity, bool enable) |
| 2054 | { |
| 2055 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 2056 | |
| 2057 | if (uirq && enable && !uirq->enable) { |
| 2058 | dbg_event(0xFF, "PDC_IRQ_EN", uirq->irq); |
| 2059 | dbg_event(0xFF, "PDC_IRQ_POL", polarity); |
| 2060 | /* clear any pending interrupt */ |
| 2061 | irq_set_irqchip_state(uirq->irq, IRQCHIP_STATE_PENDING, 0); |
| 2062 | irq_set_irq_type(uirq->irq, polarity); |
| 2063 | enable_irq_wake(uirq->irq); |
| 2064 | enable_irq(uirq->irq); |
| 2065 | uirq->enable = true; |
| 2066 | } |
| 2067 | |
| 2068 | if (uirq && !enable && uirq->enable) { |
| 2069 | dbg_event(0xFF, "PDC_IRQ_DIS", uirq->irq); |
| 2070 | disable_irq_wake(uirq->irq); |
| 2071 | disable_irq_nosync(uirq->irq); |
| 2072 | uirq->enable = false; |
| 2073 | } |
| 2074 | } |
| 2075 | |
| 2076 | static void enable_usb_pdc_interrupt(struct dwc3_msm *mdwc, bool enable) |
| 2077 | { |
| 2078 | if (!enable) |
| 2079 | goto disable_usb_irq; |
| 2080 | |
| 2081 | if (mdwc->hs_phy->flags & PHY_LS_MODE) { |
| 2082 | configure_usb_wakeup_interrupt(mdwc, |
| 2083 | &mdwc->wakeup_irq[DM_HS_PHY_IRQ], |
| 2084 | IRQ_TYPE_EDGE_FALLING, enable); |
| 2085 | } else if (mdwc->hs_phy->flags & PHY_HSFS_MODE) { |
| 2086 | configure_usb_wakeup_interrupt(mdwc, |
| 2087 | &mdwc->wakeup_irq[DP_HS_PHY_IRQ], |
| 2088 | IRQ_TYPE_EDGE_FALLING, enable); |
| 2089 | } else { |
| 2090 | configure_usb_wakeup_interrupt(mdwc, |
| 2091 | &mdwc->wakeup_irq[DP_HS_PHY_IRQ], |
| 2092 | IRQ_TYPE_EDGE_RISING, true); |
| 2093 | configure_usb_wakeup_interrupt(mdwc, |
| 2094 | &mdwc->wakeup_irq[DM_HS_PHY_IRQ], |
| 2095 | IRQ_TYPE_EDGE_RISING, true); |
| 2096 | } |
| 2097 | |
| 2098 | configure_usb_wakeup_interrupt(mdwc, |
| 2099 | &mdwc->wakeup_irq[SS_PHY_IRQ], |
| 2100 | IRQF_TRIGGER_HIGH | IRQ_TYPE_LEVEL_HIGH, enable); |
| 2101 | return; |
| 2102 | |
| 2103 | disable_usb_irq: |
| 2104 | configure_usb_wakeup_interrupt(mdwc, |
| 2105 | &mdwc->wakeup_irq[DP_HS_PHY_IRQ], 0, enable); |
| 2106 | configure_usb_wakeup_interrupt(mdwc, |
| 2107 | &mdwc->wakeup_irq[DM_HS_PHY_IRQ], 0, enable); |
| 2108 | configure_usb_wakeup_interrupt(mdwc, |
| 2109 | &mdwc->wakeup_irq[SS_PHY_IRQ], 0, enable); |
| 2110 | } |
| 2111 | |
| 2112 | static void configure_nonpdc_usb_interrupt(struct dwc3_msm *mdwc, |
| 2113 | struct usb_irq *uirq, bool enable) |
| 2114 | { |
| 2115 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 2116 | |
| 2117 | if (uirq && enable && !uirq->enable) { |
| 2118 | dbg_event(0xFF, "IRQ_EN", uirq->irq); |
| 2119 | enable_irq_wake(uirq->irq); |
| 2120 | enable_irq(uirq->irq); |
| 2121 | uirq->enable = true; |
| 2122 | } |
| 2123 | |
| 2124 | if (uirq && !enable && uirq->enable) { |
| 2125 | dbg_event(0xFF, "IRQ_DIS", uirq->irq); |
| 2126 | disable_irq_wake(uirq->irq); |
| 2127 | disable_irq_nosync(uirq->irq); |
| 2128 | uirq->enable = true; |
| 2129 | } |
| 2130 | } |
| 2131 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2132 | static int dwc3_msm_suspend(struct dwc3_msm *mdwc) |
| 2133 | { |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 2134 | int ret; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2135 | bool can_suspend_ssphy; |
| 2136 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 2137 | struct dwc3_event_buffer *evt; |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 2138 | struct usb_irq *uirq; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2139 | |
| 2140 | if (atomic_read(&dwc->in_lpm)) { |
| 2141 | dev_dbg(mdwc->dev, "%s: Already suspended\n", __func__); |
| 2142 | return 0; |
| 2143 | } |
| 2144 | |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame] | 2145 | cancel_delayed_work_sync(&mdwc->perf_vote_work); |
| 2146 | msm_dwc3_perf_vote_update(mdwc, false); |
| 2147 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2148 | if (!mdwc->in_host_mode) { |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 2149 | evt = dwc->ev_buf; |
| 2150 | if ((evt->flags & DWC3_EVENT_PENDING)) { |
| 2151 | dev_dbg(mdwc->dev, |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2152 | "%s: %d device events pending, abort suspend\n", |
| 2153 | __func__, evt->count / 4); |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 2154 | return -EBUSY; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2155 | } |
| 2156 | } |
| 2157 | |
| 2158 | if (!mdwc->vbus_active && dwc->is_drd && |
| 2159 | mdwc->otg_state == OTG_STATE_B_PERIPHERAL) { |
| 2160 | /* |
| 2161 | * In some cases, the pm_runtime_suspend may be called by |
| 2162 | * usb_bam when there is pending lpm flag. However, if this is |
| 2163 | * done when cable was disconnected and otg state has not |
| 2164 | * yet changed to IDLE, then it means OTG state machine |
| 2165 | * is running and we race against it. So cancel LPM for now, |
| 2166 | * and OTG state machine will go for LPM later, after completing |
| 2167 | * transition to IDLE state. |
| 2168 | */ |
| 2169 | dev_dbg(mdwc->dev, |
| 2170 | "%s: cable disconnected while not in idle otg state\n", |
| 2171 | __func__); |
| 2172 | return -EBUSY; |
| 2173 | } |
| 2174 | |
| 2175 | /* |
| 2176 | * Check if device is not in CONFIGURED state |
| 2177 | * then check controller state of L2 and break |
| 2178 | * LPM sequence. Check this for device bus suspend case. |
| 2179 | */ |
| 2180 | if ((dwc->is_drd && mdwc->otg_state == OTG_STATE_B_SUSPEND) && |
| 2181 | (dwc->gadget.state != USB_STATE_CONFIGURED)) { |
| 2182 | pr_err("%s(): Trying to go in LPM with state:%d\n", |
| 2183 | __func__, dwc->gadget.state); |
| 2184 | pr_err("%s(): LPM is not performed.\n", __func__); |
| 2185 | return -EBUSY; |
| 2186 | } |
| 2187 | |
| 2188 | ret = dwc3_msm_prepare_suspend(mdwc); |
| 2189 | if (ret) |
| 2190 | return ret; |
| 2191 | |
| 2192 | /* Initialize variables here */ |
| 2193 | can_suspend_ssphy = !(mdwc->in_host_mode && |
| 2194 | dwc3_msm_is_host_superspeed(mdwc)); |
| 2195 | |
| 2196 | /* Disable core irq */ |
| 2197 | if (dwc->irq) |
| 2198 | disable_irq(dwc->irq); |
| 2199 | |
Mayank Rana | f616a7f | 2017-03-20 16:10:39 -0700 | [diff] [blame] | 2200 | if (work_busy(&dwc->bh_work)) |
| 2201 | dbg_event(0xFF, "pend evt", 0); |
| 2202 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2203 | /* disable power event irq, hs and ss phy irq is used as wake up src */ |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 2204 | disable_irq(mdwc->wakeup_irq[PWR_EVNT_IRQ].irq); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2205 | |
| 2206 | dwc3_set_phy_speed_flags(mdwc); |
| 2207 | /* Suspend HS PHY */ |
| 2208 | usb_phy_set_suspend(mdwc->hs_phy, 1); |
| 2209 | |
| 2210 | /* Suspend SS PHY */ |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 2211 | if (dwc->maximum_speed == USB_SPEED_SUPER && can_suspend_ssphy) { |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2212 | /* indicate phy about SS mode */ |
| 2213 | if (dwc3_msm_is_superspeed(mdwc)) |
| 2214 | mdwc->ss_phy->flags |= DEVICE_IN_SS_MODE; |
| 2215 | usb_phy_set_suspend(mdwc->ss_phy, 1); |
| 2216 | mdwc->lpm_flags |= MDWC3_SS_PHY_SUSPEND; |
| 2217 | } |
| 2218 | |
| 2219 | /* make sure above writes are completed before turning off clocks */ |
| 2220 | wmb(); |
| 2221 | |
| 2222 | /* Disable clocks */ |
| 2223 | if (mdwc->bus_aggr_clk) |
| 2224 | clk_disable_unprepare(mdwc->bus_aggr_clk); |
| 2225 | clk_disable_unprepare(mdwc->utmi_clk); |
| 2226 | |
Hemant Kumar | 633dc33 | 2016-08-10 13:41:05 -0700 | [diff] [blame] | 2227 | /* Memory core: OFF, Memory periphery: OFF */ |
| 2228 | if (!mdwc->in_host_mode && !mdwc->vbus_active) { |
| 2229 | clk_set_flags(mdwc->core_clk, CLKFLAG_NORETAIN_MEM); |
| 2230 | clk_set_flags(mdwc->core_clk, CLKFLAG_NORETAIN_PERIPH); |
| 2231 | } |
| 2232 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2233 | clk_set_rate(mdwc->core_clk, 19200000); |
| 2234 | clk_disable_unprepare(mdwc->core_clk); |
Vijayavardhan Vennapusa | 934d9cd | 2016-11-30 13:10:01 +0530 | [diff] [blame] | 2235 | if (mdwc->noc_aggr_clk) |
| 2236 | clk_disable_unprepare(mdwc->noc_aggr_clk); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2237 | /* |
| 2238 | * Disable iface_clk only after core_clk as core_clk has FSM |
| 2239 | * depedency on iface_clk. Hence iface_clk should be turned off |
| 2240 | * after core_clk is turned off. |
| 2241 | */ |
| 2242 | clk_disable_unprepare(mdwc->iface_clk); |
| 2243 | /* USB PHY no more requires TCXO */ |
| 2244 | clk_disable_unprepare(mdwc->xo_clk); |
| 2245 | |
| 2246 | /* Perform controller power collapse */ |
Azhar Shaikh | 69f4c05 | 2016-02-11 11:00:58 -0800 | [diff] [blame] | 2247 | if (!mdwc->in_host_mode && (!mdwc->vbus_active || mdwc->in_restart)) { |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2248 | mdwc->lpm_flags |= MDWC3_POWER_COLLAPSE; |
| 2249 | dev_dbg(mdwc->dev, "%s: power collapse\n", __func__); |
| 2250 | dwc3_msm_config_gdsc(mdwc, 0); |
| 2251 | clk_disable_unprepare(mdwc->sleep_clk); |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 2252 | |
Jack Pham | 9faa51df | 2017-04-03 18:13:40 -0700 | [diff] [blame] | 2253 | if (mdwc->iommu_map) { |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 2254 | arm_iommu_detach_device(mdwc->dev); |
Jack Pham | 9faa51df | 2017-04-03 18:13:40 -0700 | [diff] [blame] | 2255 | dev_dbg(mdwc->dev, "IOMMU detached\n"); |
| 2256 | } |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2257 | } |
| 2258 | |
| 2259 | /* Remove bus voting */ |
| 2260 | if (mdwc->bus_perf_client) { |
Mayank Rana | ca9f318 | 2017-04-13 17:44:14 -0700 | [diff] [blame] | 2261 | dbg_event(0xFF, "bus_devote_start", 0); |
| 2262 | ret = msm_bus_scale_client_update_request( |
| 2263 | mdwc->bus_perf_client, 0); |
| 2264 | dbg_event(0xFF, "bus_devote_finish", 0); |
| 2265 | if (ret) |
| 2266 | dev_err(mdwc->dev, "bus bw unvoting failed %d\n", ret); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2267 | } |
| 2268 | |
| 2269 | /* |
| 2270 | * release wakeup source with timeout to defer system suspend to |
| 2271 | * handle case where on USB cable disconnect, SUSPEND and DISCONNECT |
| 2272 | * event is received. |
| 2273 | */ |
| 2274 | if (mdwc->lpm_to_suspend_delay) { |
| 2275 | dev_dbg(mdwc->dev, "defer suspend with %d(msecs)\n", |
| 2276 | mdwc->lpm_to_suspend_delay); |
| 2277 | pm_wakeup_event(mdwc->dev, mdwc->lpm_to_suspend_delay); |
| 2278 | } else { |
| 2279 | pm_relax(mdwc->dev); |
| 2280 | } |
| 2281 | |
| 2282 | atomic_set(&dwc->in_lpm, 1); |
| 2283 | |
| 2284 | /* |
| 2285 | * with DCP or during cable disconnect, we dont require wakeup |
| 2286 | * using HS_PHY_IRQ or SS_PHY_IRQ. Hence enable wakeup only in |
| 2287 | * case of host bus suspend and device bus suspend. |
| 2288 | */ |
| 2289 | if (mdwc->vbus_active || mdwc->in_host_mode) { |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 2290 | if (mdwc->use_pdc_interrupts) { |
| 2291 | enable_usb_pdc_interrupt(mdwc, true); |
| 2292 | } else { |
| 2293 | uirq = &mdwc->wakeup_irq[HS_PHY_IRQ]; |
| 2294 | configure_nonpdc_usb_interrupt(mdwc, uirq, true); |
| 2295 | uirq = &mdwc->wakeup_irq[SS_PHY_IRQ]; |
| 2296 | configure_nonpdc_usb_interrupt(mdwc, uirq, true); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2297 | } |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2298 | mdwc->lpm_flags |= MDWC3_ASYNC_IRQ_WAKE_CAPABILITY; |
| 2299 | } |
| 2300 | |
| 2301 | dev_info(mdwc->dev, "DWC3 in low power mode\n"); |
| 2302 | return 0; |
| 2303 | } |
| 2304 | |
| 2305 | static int dwc3_msm_resume(struct dwc3_msm *mdwc) |
| 2306 | { |
| 2307 | int ret; |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 2308 | long core_clk_rate; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2309 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 2310 | struct usb_irq *uirq; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2311 | |
| 2312 | dev_dbg(mdwc->dev, "%s: exiting lpm\n", __func__); |
| 2313 | |
| 2314 | if (!atomic_read(&dwc->in_lpm)) { |
| 2315 | dev_dbg(mdwc->dev, "%s: Already resumed\n", __func__); |
| 2316 | return 0; |
| 2317 | } |
| 2318 | |
| 2319 | pm_stay_awake(mdwc->dev); |
| 2320 | |
| 2321 | /* Enable bus voting */ |
| 2322 | if (mdwc->bus_perf_client) { |
Mayank Rana | ca9f318 | 2017-04-13 17:44:14 -0700 | [diff] [blame] | 2323 | dbg_event(0xFF, "bus_vote_start", 1); |
| 2324 | ret = msm_bus_scale_client_update_request( |
| 2325 | mdwc->bus_perf_client, 1); |
| 2326 | dbg_event(0xFF, "bus_vote_finish", 1); |
| 2327 | if (ret) |
| 2328 | dev_err(mdwc->dev, "bus bw voting failed %d\n", ret); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2329 | } |
| 2330 | |
| 2331 | /* Vote for TCXO while waking up USB HSPHY */ |
| 2332 | ret = clk_prepare_enable(mdwc->xo_clk); |
| 2333 | if (ret) |
| 2334 | dev_err(mdwc->dev, "%s failed to vote TCXO buffer%d\n", |
| 2335 | __func__, ret); |
| 2336 | |
| 2337 | /* Restore controller power collapse */ |
| 2338 | if (mdwc->lpm_flags & MDWC3_POWER_COLLAPSE) { |
| 2339 | dev_dbg(mdwc->dev, "%s: exit power collapse\n", __func__); |
| 2340 | dwc3_msm_config_gdsc(mdwc, 1); |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 2341 | ret = reset_control_assert(mdwc->core_reset); |
| 2342 | if (ret) |
| 2343 | dev_err(mdwc->dev, "%s:core_reset assert failed\n", |
| 2344 | __func__); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2345 | /* HW requires a short delay for reset to take place properly */ |
| 2346 | usleep_range(1000, 1200); |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 2347 | ret = reset_control_deassert(mdwc->core_reset); |
| 2348 | if (ret) |
| 2349 | dev_err(mdwc->dev, "%s:core_reset deassert failed\n", |
| 2350 | __func__); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2351 | clk_prepare_enable(mdwc->sleep_clk); |
| 2352 | } |
| 2353 | |
| 2354 | /* |
| 2355 | * Enable clocks |
| 2356 | * Turned ON iface_clk before core_clk due to FSM depedency. |
| 2357 | */ |
| 2358 | clk_prepare_enable(mdwc->iface_clk); |
Vijayavardhan Vennapusa | 934d9cd | 2016-11-30 13:10:01 +0530 | [diff] [blame] | 2359 | if (mdwc->noc_aggr_clk) |
| 2360 | clk_prepare_enable(mdwc->noc_aggr_clk); |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 2361 | |
| 2362 | core_clk_rate = mdwc->core_clk_rate; |
| 2363 | if (mdwc->in_host_mode && mdwc->max_rh_port_speed == USB_SPEED_HIGH) { |
| 2364 | core_clk_rate = mdwc->core_clk_rate_hs; |
| 2365 | dev_dbg(mdwc->dev, "%s: set hs core clk rate %ld\n", __func__, |
| 2366 | core_clk_rate); |
| 2367 | } |
| 2368 | |
| 2369 | clk_set_rate(mdwc->core_clk, core_clk_rate); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2370 | clk_prepare_enable(mdwc->core_clk); |
Hemant Kumar | 5fa3893 | 2016-10-27 11:58:37 -0700 | [diff] [blame] | 2371 | |
| 2372 | /* set Memory core: ON, Memory periphery: ON */ |
| 2373 | clk_set_flags(mdwc->core_clk, CLKFLAG_RETAIN_MEM); |
| 2374 | clk_set_flags(mdwc->core_clk, CLKFLAG_RETAIN_PERIPH); |
| 2375 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2376 | clk_prepare_enable(mdwc->utmi_clk); |
| 2377 | if (mdwc->bus_aggr_clk) |
| 2378 | clk_prepare_enable(mdwc->bus_aggr_clk); |
| 2379 | |
| 2380 | /* Resume SS PHY */ |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 2381 | if (dwc->maximum_speed == USB_SPEED_SUPER && |
| 2382 | mdwc->lpm_flags & MDWC3_SS_PHY_SUSPEND) { |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2383 | mdwc->ss_phy->flags &= ~(PHY_LANE_A | PHY_LANE_B); |
| 2384 | if (mdwc->typec_orientation == ORIENTATION_CC1) |
| 2385 | mdwc->ss_phy->flags |= PHY_LANE_A; |
| 2386 | if (mdwc->typec_orientation == ORIENTATION_CC2) |
| 2387 | mdwc->ss_phy->flags |= PHY_LANE_B; |
| 2388 | usb_phy_set_suspend(mdwc->ss_phy, 0); |
| 2389 | mdwc->ss_phy->flags &= ~DEVICE_IN_SS_MODE; |
| 2390 | mdwc->lpm_flags &= ~MDWC3_SS_PHY_SUSPEND; |
| 2391 | } |
| 2392 | |
| 2393 | mdwc->hs_phy->flags &= ~(PHY_HSFS_MODE | PHY_LS_MODE); |
| 2394 | /* Resume HS PHY */ |
| 2395 | usb_phy_set_suspend(mdwc->hs_phy, 0); |
| 2396 | |
| 2397 | /* Recover from controller power collapse */ |
| 2398 | if (mdwc->lpm_flags & MDWC3_POWER_COLLAPSE) { |
| 2399 | u32 tmp; |
| 2400 | |
Jack Pham | 9faa51df | 2017-04-03 18:13:40 -0700 | [diff] [blame] | 2401 | if (mdwc->iommu_map) { |
| 2402 | ret = arm_iommu_attach_device(mdwc->dev, |
| 2403 | mdwc->iommu_map); |
| 2404 | if (ret) |
| 2405 | dev_err(mdwc->dev, "IOMMU attach failed (%d)\n", |
| 2406 | ret); |
| 2407 | else |
| 2408 | dev_dbg(mdwc->dev, "attached to IOMMU\n"); |
| 2409 | } |
| 2410 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2411 | dev_dbg(mdwc->dev, "%s: exit power collapse\n", __func__); |
| 2412 | |
| 2413 | dwc3_msm_power_collapse_por(mdwc); |
| 2414 | |
| 2415 | /* Get initial P3 status and enable IN_P3 event */ |
| 2416 | tmp = dwc3_msm_read_reg_field(mdwc->base, |
| 2417 | DWC3_GDBGLTSSM, DWC3_GDBGLTSSM_LINKSTATE_MASK); |
| 2418 | atomic_set(&mdwc->in_p3, tmp == DWC3_LINK_STATE_U3); |
| 2419 | dwc3_msm_write_reg_field(mdwc->base, PWR_EVNT_IRQ_MASK_REG, |
| 2420 | PWR_EVNT_POWERDOWN_IN_P3_MASK, 1); |
| 2421 | |
| 2422 | mdwc->lpm_flags &= ~MDWC3_POWER_COLLAPSE; |
| 2423 | } |
| 2424 | |
| 2425 | atomic_set(&dwc->in_lpm, 0); |
| 2426 | |
Vijayavardhan Vennapusa | 6a4c1d9 | 2016-12-08 13:06:26 +0530 | [diff] [blame] | 2427 | /* enable power evt irq for IN P3 detection */ |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 2428 | enable_irq(mdwc->wakeup_irq[PWR_EVNT_IRQ].irq); |
Vijayavardhan Vennapusa | 6a4c1d9 | 2016-12-08 13:06:26 +0530 | [diff] [blame] | 2429 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2430 | /* Disable HSPHY auto suspend */ |
| 2431 | dwc3_msm_write_reg(mdwc->base, DWC3_GUSB2PHYCFG(0), |
| 2432 | dwc3_msm_read_reg(mdwc->base, DWC3_GUSB2PHYCFG(0)) & |
| 2433 | ~(DWC3_GUSB2PHYCFG_ENBLSLPM | |
| 2434 | DWC3_GUSB2PHYCFG_SUSPHY)); |
| 2435 | |
| 2436 | /* Disable wakeup capable for HS_PHY IRQ & SS_PHY_IRQ if enabled */ |
| 2437 | if (mdwc->lpm_flags & MDWC3_ASYNC_IRQ_WAKE_CAPABILITY) { |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 2438 | if (mdwc->use_pdc_interrupts) { |
| 2439 | enable_usb_pdc_interrupt(mdwc, false); |
| 2440 | } else { |
| 2441 | uirq = &mdwc->wakeup_irq[HS_PHY_IRQ]; |
| 2442 | configure_nonpdc_usb_interrupt(mdwc, uirq, false); |
| 2443 | uirq = &mdwc->wakeup_irq[SS_PHY_IRQ]; |
| 2444 | configure_nonpdc_usb_interrupt(mdwc, uirq, false); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2445 | } |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2446 | mdwc->lpm_flags &= ~MDWC3_ASYNC_IRQ_WAKE_CAPABILITY; |
| 2447 | } |
| 2448 | |
| 2449 | dev_info(mdwc->dev, "DWC3 exited from low power mode\n"); |
| 2450 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2451 | /* Enable core irq */ |
| 2452 | if (dwc->irq) |
| 2453 | enable_irq(dwc->irq); |
| 2454 | |
| 2455 | /* |
| 2456 | * Handle other power events that could not have been handled during |
| 2457 | * Low Power Mode |
| 2458 | */ |
| 2459 | dwc3_pwr_event_handler(mdwc); |
| 2460 | |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame] | 2461 | if (pm_qos_request_active(&mdwc->pm_qos_req_dma)) |
| 2462 | schedule_delayed_work(&mdwc->perf_vote_work, |
| 2463 | msecs_to_jiffies(1000 * PM_QOS_SAMPLE_SEC)); |
| 2464 | |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 2465 | dbg_event(0xFF, "Ctl Res", atomic_read(&dwc->in_lpm)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2466 | return 0; |
| 2467 | } |
| 2468 | |
| 2469 | /** |
| 2470 | * dwc3_ext_event_notify - callback to handle events from external transceiver |
| 2471 | * |
| 2472 | * Returns 0 on success |
| 2473 | */ |
| 2474 | static void dwc3_ext_event_notify(struct dwc3_msm *mdwc) |
| 2475 | { |
| 2476 | /* Flush processing any pending events before handling new ones */ |
| 2477 | flush_delayed_work(&mdwc->sm_work); |
| 2478 | |
| 2479 | if (mdwc->id_state == DWC3_ID_FLOAT) { |
| 2480 | dev_dbg(mdwc->dev, "XCVR: ID set\n"); |
| 2481 | set_bit(ID, &mdwc->inputs); |
| 2482 | } else { |
| 2483 | dev_dbg(mdwc->dev, "XCVR: ID clear\n"); |
| 2484 | clear_bit(ID, &mdwc->inputs); |
| 2485 | } |
| 2486 | |
| 2487 | if (mdwc->vbus_active && !mdwc->in_restart) { |
| 2488 | dev_dbg(mdwc->dev, "XCVR: BSV set\n"); |
| 2489 | set_bit(B_SESS_VLD, &mdwc->inputs); |
| 2490 | } else { |
| 2491 | dev_dbg(mdwc->dev, "XCVR: BSV clear\n"); |
| 2492 | clear_bit(B_SESS_VLD, &mdwc->inputs); |
| 2493 | } |
| 2494 | |
| 2495 | if (mdwc->suspend) { |
| 2496 | dev_dbg(mdwc->dev, "XCVR: SUSP set\n"); |
| 2497 | set_bit(B_SUSPEND, &mdwc->inputs); |
| 2498 | } else { |
| 2499 | dev_dbg(mdwc->dev, "XCVR: SUSP clear\n"); |
| 2500 | clear_bit(B_SUSPEND, &mdwc->inputs); |
| 2501 | } |
| 2502 | |
| 2503 | schedule_delayed_work(&mdwc->sm_work, 0); |
| 2504 | } |
| 2505 | |
| 2506 | static void dwc3_resume_work(struct work_struct *w) |
| 2507 | { |
| 2508 | struct dwc3_msm *mdwc = container_of(w, struct dwc3_msm, resume_work); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 2509 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
Jack Pham | 4e9dff7 | 2017-04-04 18:05:53 -0700 | [diff] [blame] | 2510 | union extcon_property_value val; |
| 2511 | unsigned int extcon_id; |
| 2512 | struct extcon_dev *edev = NULL; |
| 2513 | int ret = 0; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2514 | |
| 2515 | dev_dbg(mdwc->dev, "%s: dwc3 resume work\n", __func__); |
| 2516 | |
Jack Pham | 4e9dff7 | 2017-04-04 18:05:53 -0700 | [diff] [blame] | 2517 | if (mdwc->vbus_active) { |
| 2518 | edev = mdwc->extcon_vbus; |
| 2519 | extcon_id = EXTCON_USB; |
| 2520 | } else if (mdwc->id_state == DWC3_ID_GROUND) { |
| 2521 | edev = mdwc->extcon_id; |
| 2522 | extcon_id = EXTCON_USB_HOST; |
| 2523 | } |
| 2524 | |
| 2525 | /* Check speed and Type-C polarity values in order to configure PHY */ |
| 2526 | if (edev && extcon_get_state(edev, extcon_id)) { |
| 2527 | ret = extcon_get_property(edev, extcon_id, |
| 2528 | EXTCON_PROP_USB_SS, &val); |
| 2529 | |
| 2530 | /* Use default dwc->maximum_speed if speed isn't reported */ |
| 2531 | if (!ret) |
| 2532 | dwc->maximum_speed = (val.intval == 0) ? |
| 2533 | USB_SPEED_HIGH : USB_SPEED_SUPER; |
| 2534 | |
| 2535 | if (dwc->maximum_speed > dwc->max_hw_supp_speed) |
| 2536 | dwc->maximum_speed = dwc->max_hw_supp_speed; |
| 2537 | |
Mayank Rana | f70d821 | 2017-06-12 14:02:07 -0700 | [diff] [blame] | 2538 | if (override_usb_speed && |
| 2539 | is_valid_usb_speed(dwc, override_usb_speed)) { |
| 2540 | dwc->maximum_speed = override_usb_speed; |
| 2541 | dbg_event(0xFF, "override_speed", override_usb_speed); |
| 2542 | } |
| 2543 | |
Jack Pham | 4e9dff7 | 2017-04-04 18:05:53 -0700 | [diff] [blame] | 2544 | dbg_event(0xFF, "speed", dwc->maximum_speed); |
| 2545 | |
| 2546 | ret = extcon_get_property(edev, extcon_id, |
| 2547 | EXTCON_PROP_USB_TYPEC_POLARITY, &val); |
| 2548 | if (ret) |
| 2549 | mdwc->typec_orientation = ORIENTATION_NONE; |
| 2550 | else |
| 2551 | mdwc->typec_orientation = val.intval ? |
| 2552 | ORIENTATION_CC2 : ORIENTATION_CC1; |
| 2553 | |
| 2554 | dbg_event(0xFF, "cc_state", mdwc->typec_orientation); |
| 2555 | } |
| 2556 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2557 | /* |
| 2558 | * exit LPM first to meet resume timeline from device side. |
| 2559 | * resume_pending flag would prevent calling |
| 2560 | * dwc3_msm_resume() in case we are here due to system |
| 2561 | * wide resume without usb cable connected. This flag is set |
| 2562 | * only in case of power event irq in lpm. |
| 2563 | */ |
| 2564 | if (mdwc->resume_pending) { |
| 2565 | dwc3_msm_resume(mdwc); |
| 2566 | mdwc->resume_pending = false; |
| 2567 | } |
| 2568 | |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 2569 | if (atomic_read(&mdwc->pm_suspended)) { |
| 2570 | dbg_event(0xFF, "RWrk PMSus", 0); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2571 | /* let pm resume kick in resume work later */ |
| 2572 | return; |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 2573 | } |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2574 | dwc3_ext_event_notify(mdwc); |
| 2575 | } |
| 2576 | |
| 2577 | static void dwc3_pwr_event_handler(struct dwc3_msm *mdwc) |
| 2578 | { |
| 2579 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 2580 | u32 irq_stat, irq_clear = 0; |
| 2581 | |
| 2582 | irq_stat = dwc3_msm_read_reg(mdwc->base, PWR_EVNT_IRQ_STAT_REG); |
| 2583 | dev_dbg(mdwc->dev, "%s irq_stat=%X\n", __func__, irq_stat); |
| 2584 | |
| 2585 | /* Check for P3 events */ |
| 2586 | if ((irq_stat & PWR_EVNT_POWERDOWN_OUT_P3_MASK) && |
| 2587 | (irq_stat & PWR_EVNT_POWERDOWN_IN_P3_MASK)) { |
| 2588 | /* Can't tell if entered or exit P3, so check LINKSTATE */ |
| 2589 | u32 ls = dwc3_msm_read_reg_field(mdwc->base, |
| 2590 | DWC3_GDBGLTSSM, DWC3_GDBGLTSSM_LINKSTATE_MASK); |
| 2591 | dev_dbg(mdwc->dev, "%s link state = 0x%04x\n", __func__, ls); |
| 2592 | atomic_set(&mdwc->in_p3, ls == DWC3_LINK_STATE_U3); |
| 2593 | |
| 2594 | irq_stat &= ~(PWR_EVNT_POWERDOWN_OUT_P3_MASK | |
| 2595 | PWR_EVNT_POWERDOWN_IN_P3_MASK); |
| 2596 | irq_clear |= (PWR_EVNT_POWERDOWN_OUT_P3_MASK | |
| 2597 | PWR_EVNT_POWERDOWN_IN_P3_MASK); |
| 2598 | } else if (irq_stat & PWR_EVNT_POWERDOWN_OUT_P3_MASK) { |
| 2599 | atomic_set(&mdwc->in_p3, 0); |
| 2600 | irq_stat &= ~PWR_EVNT_POWERDOWN_OUT_P3_MASK; |
| 2601 | irq_clear |= PWR_EVNT_POWERDOWN_OUT_P3_MASK; |
| 2602 | } else if (irq_stat & PWR_EVNT_POWERDOWN_IN_P3_MASK) { |
| 2603 | atomic_set(&mdwc->in_p3, 1); |
| 2604 | irq_stat &= ~PWR_EVNT_POWERDOWN_IN_P3_MASK; |
| 2605 | irq_clear |= PWR_EVNT_POWERDOWN_IN_P3_MASK; |
| 2606 | } |
| 2607 | |
| 2608 | /* Clear L2 exit */ |
| 2609 | if (irq_stat & PWR_EVNT_LPM_OUT_L2_MASK) { |
| 2610 | irq_stat &= ~PWR_EVNT_LPM_OUT_L2_MASK; |
| 2611 | irq_stat |= PWR_EVNT_LPM_OUT_L2_MASK; |
| 2612 | } |
| 2613 | |
| 2614 | /* Handle exit from L1 events */ |
| 2615 | if (irq_stat & PWR_EVNT_LPM_OUT_L1_MASK) { |
| 2616 | dev_dbg(mdwc->dev, "%s: handling PWR_EVNT_LPM_OUT_L1_MASK\n", |
| 2617 | __func__); |
| 2618 | if (usb_gadget_wakeup(&dwc->gadget)) |
| 2619 | dev_err(mdwc->dev, "%s failed to take dwc out of L1\n", |
| 2620 | __func__); |
| 2621 | irq_stat &= ~PWR_EVNT_LPM_OUT_L1_MASK; |
| 2622 | irq_clear |= PWR_EVNT_LPM_OUT_L1_MASK; |
| 2623 | } |
| 2624 | |
| 2625 | /* Unhandled events */ |
| 2626 | if (irq_stat) |
| 2627 | dev_dbg(mdwc->dev, "%s: unexpected PWR_EVNT, irq_stat=%X\n", |
| 2628 | __func__, irq_stat); |
| 2629 | |
| 2630 | dwc3_msm_write_reg(mdwc->base, PWR_EVNT_IRQ_STAT_REG, irq_clear); |
| 2631 | } |
| 2632 | |
| 2633 | static irqreturn_t msm_dwc3_pwr_irq_thread(int irq, void *_mdwc) |
| 2634 | { |
| 2635 | struct dwc3_msm *mdwc = _mdwc; |
| 2636 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 2637 | |
| 2638 | dev_dbg(mdwc->dev, "%s\n", __func__); |
| 2639 | |
| 2640 | if (atomic_read(&dwc->in_lpm)) |
| 2641 | dwc3_resume_work(&mdwc->resume_work); |
| 2642 | else |
| 2643 | dwc3_pwr_event_handler(mdwc); |
| 2644 | |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 2645 | dbg_event(0xFF, "PWR IRQ", atomic_read(&dwc->in_lpm)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2646 | return IRQ_HANDLED; |
| 2647 | } |
| 2648 | |
| 2649 | static irqreturn_t msm_dwc3_pwr_irq(int irq, void *data) |
| 2650 | { |
| 2651 | struct dwc3_msm *mdwc = data; |
| 2652 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 2653 | |
| 2654 | dwc->t_pwr_evt_irq = ktime_get(); |
| 2655 | dev_dbg(mdwc->dev, "%s received\n", __func__); |
| 2656 | /* |
| 2657 | * When in Low Power Mode, can't read PWR_EVNT_IRQ_STAT_REG to acertain |
| 2658 | * which interrupts have been triggered, as the clocks are disabled. |
| 2659 | * Resume controller by waking up pwr event irq thread.After re-enabling |
| 2660 | * clocks, dwc3_msm_resume will call dwc3_pwr_event_handler to handle |
| 2661 | * all other power events. |
| 2662 | */ |
| 2663 | if (atomic_read(&dwc->in_lpm)) { |
| 2664 | /* set this to call dwc3_msm_resume() */ |
| 2665 | mdwc->resume_pending = true; |
| 2666 | return IRQ_WAKE_THREAD; |
| 2667 | } |
| 2668 | |
| 2669 | dwc3_pwr_event_handler(mdwc); |
| 2670 | return IRQ_HANDLED; |
| 2671 | } |
| 2672 | |
| 2673 | static int dwc3_cpu_notifier_cb(struct notifier_block *nfb, |
| 2674 | unsigned long action, void *hcpu) |
| 2675 | { |
| 2676 | uint32_t cpu = (uintptr_t)hcpu; |
| 2677 | struct dwc3_msm *mdwc = |
| 2678 | container_of(nfb, struct dwc3_msm, dwc3_cpu_notifier); |
| 2679 | |
| 2680 | if (cpu == cpu_to_affin && action == CPU_ONLINE) { |
| 2681 | pr_debug("%s: cpu online:%u irq:%d\n", __func__, |
| 2682 | cpu_to_affin, mdwc->irq_to_affin); |
| 2683 | irq_set_affinity(mdwc->irq_to_affin, get_cpu_mask(cpu)); |
| 2684 | } |
| 2685 | |
| 2686 | return NOTIFY_OK; |
| 2687 | } |
| 2688 | |
| 2689 | static void dwc3_otg_sm_work(struct work_struct *w); |
| 2690 | |
| 2691 | static int dwc3_msm_get_clk_gdsc(struct dwc3_msm *mdwc) |
| 2692 | { |
| 2693 | int ret; |
| 2694 | |
| 2695 | mdwc->dwc3_gdsc = devm_regulator_get(mdwc->dev, "USB3_GDSC"); |
| 2696 | if (IS_ERR(mdwc->dwc3_gdsc)) |
| 2697 | mdwc->dwc3_gdsc = NULL; |
| 2698 | |
| 2699 | mdwc->xo_clk = devm_clk_get(mdwc->dev, "xo"); |
| 2700 | if (IS_ERR(mdwc->xo_clk)) { |
| 2701 | dev_err(mdwc->dev, "%s unable to get TCXO buffer handle\n", |
| 2702 | __func__); |
| 2703 | ret = PTR_ERR(mdwc->xo_clk); |
| 2704 | return ret; |
| 2705 | } |
| 2706 | clk_set_rate(mdwc->xo_clk, 19200000); |
| 2707 | |
| 2708 | mdwc->iface_clk = devm_clk_get(mdwc->dev, "iface_clk"); |
| 2709 | if (IS_ERR(mdwc->iface_clk)) { |
| 2710 | dev_err(mdwc->dev, "failed to get iface_clk\n"); |
| 2711 | ret = PTR_ERR(mdwc->iface_clk); |
| 2712 | return ret; |
| 2713 | } |
| 2714 | |
| 2715 | /* |
| 2716 | * DWC3 Core requires its CORE CLK (aka master / bus clk) to |
| 2717 | * run at 125Mhz in SSUSB mode and >60MHZ for HSUSB mode. |
| 2718 | * On newer platform it can run at 150MHz as well. |
| 2719 | */ |
| 2720 | mdwc->core_clk = devm_clk_get(mdwc->dev, "core_clk"); |
| 2721 | if (IS_ERR(mdwc->core_clk)) { |
| 2722 | dev_err(mdwc->dev, "failed to get core_clk\n"); |
| 2723 | ret = PTR_ERR(mdwc->core_clk); |
| 2724 | return ret; |
| 2725 | } |
| 2726 | |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 2727 | mdwc->core_reset = devm_reset_control_get(mdwc->dev, "core_reset"); |
| 2728 | if (IS_ERR(mdwc->core_reset)) { |
| 2729 | dev_err(mdwc->dev, "failed to get core_reset\n"); |
| 2730 | return PTR_ERR(mdwc->core_reset); |
| 2731 | } |
| 2732 | |
Vijayavardhan Vennapusa | 8e6a11e | 2016-12-06 12:04:21 +0530 | [diff] [blame] | 2733 | if (of_property_read_u32(mdwc->dev->of_node, "qcom,core-clk-rate", |
Vijayavardhan Vennapusa | 3e668f3 | 2016-01-08 15:58:35 +0530 | [diff] [blame] | 2734 | (u32 *)&mdwc->core_clk_rate)) { |
Vijayavardhan Vennapusa | 8e6a11e | 2016-12-06 12:04:21 +0530 | [diff] [blame] | 2735 | dev_err(mdwc->dev, "USB core-clk-rate is not present\n"); |
| 2736 | return -EINVAL; |
Vijayavardhan Vennapusa | 3e668f3 | 2016-01-08 15:58:35 +0530 | [diff] [blame] | 2737 | } |
| 2738 | |
Vijayavardhan Vennapusa | 8e6a11e | 2016-12-06 12:04:21 +0530 | [diff] [blame] | 2739 | mdwc->core_clk_rate = clk_round_rate(mdwc->core_clk, |
Vijayavardhan Vennapusa | 3e668f3 | 2016-01-08 15:58:35 +0530 | [diff] [blame] | 2740 | mdwc->core_clk_rate); |
Vijayavardhan Vennapusa | 8e6a11e | 2016-12-06 12:04:21 +0530 | [diff] [blame] | 2741 | dev_dbg(mdwc->dev, "USB core frequency = %ld\n", |
| 2742 | mdwc->core_clk_rate); |
| 2743 | ret = clk_set_rate(mdwc->core_clk, mdwc->core_clk_rate); |
| 2744 | if (ret) |
| 2745 | dev_err(mdwc->dev, "fail to set core_clk freq:%d\n", ret); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2746 | |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 2747 | if (of_property_read_u32(mdwc->dev->of_node, "qcom,core-clk-rate-hs", |
| 2748 | (u32 *)&mdwc->core_clk_rate_hs)) { |
| 2749 | dev_dbg(mdwc->dev, "USB core-clk-rate-hs is not present\n"); |
| 2750 | mdwc->core_clk_rate_hs = mdwc->core_clk_rate; |
| 2751 | } |
| 2752 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2753 | mdwc->sleep_clk = devm_clk_get(mdwc->dev, "sleep_clk"); |
| 2754 | if (IS_ERR(mdwc->sleep_clk)) { |
| 2755 | dev_err(mdwc->dev, "failed to get sleep_clk\n"); |
| 2756 | ret = PTR_ERR(mdwc->sleep_clk); |
| 2757 | return ret; |
| 2758 | } |
| 2759 | |
| 2760 | clk_set_rate(mdwc->sleep_clk, 32000); |
| 2761 | mdwc->utmi_clk_rate = 19200000; |
| 2762 | mdwc->utmi_clk = devm_clk_get(mdwc->dev, "utmi_clk"); |
| 2763 | if (IS_ERR(mdwc->utmi_clk)) { |
| 2764 | dev_err(mdwc->dev, "failed to get utmi_clk\n"); |
| 2765 | ret = PTR_ERR(mdwc->utmi_clk); |
| 2766 | return ret; |
| 2767 | } |
| 2768 | |
| 2769 | clk_set_rate(mdwc->utmi_clk, mdwc->utmi_clk_rate); |
| 2770 | mdwc->bus_aggr_clk = devm_clk_get(mdwc->dev, "bus_aggr_clk"); |
| 2771 | if (IS_ERR(mdwc->bus_aggr_clk)) |
| 2772 | mdwc->bus_aggr_clk = NULL; |
| 2773 | |
Vijayavardhan Vennapusa | 934d9cd | 2016-11-30 13:10:01 +0530 | [diff] [blame] | 2774 | mdwc->noc_aggr_clk = devm_clk_get(mdwc->dev, "noc_aggr_clk"); |
| 2775 | if (IS_ERR(mdwc->noc_aggr_clk)) |
| 2776 | mdwc->noc_aggr_clk = NULL; |
| 2777 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2778 | if (of_property_match_string(mdwc->dev->of_node, |
| 2779 | "clock-names", "cfg_ahb_clk") >= 0) { |
| 2780 | mdwc->cfg_ahb_clk = devm_clk_get(mdwc->dev, "cfg_ahb_clk"); |
| 2781 | if (IS_ERR(mdwc->cfg_ahb_clk)) { |
| 2782 | ret = PTR_ERR(mdwc->cfg_ahb_clk); |
| 2783 | mdwc->cfg_ahb_clk = NULL; |
| 2784 | if (ret != -EPROBE_DEFER) |
| 2785 | dev_err(mdwc->dev, |
| 2786 | "failed to get cfg_ahb_clk ret %d\n", |
| 2787 | ret); |
| 2788 | return ret; |
| 2789 | } |
| 2790 | } |
| 2791 | |
| 2792 | return 0; |
| 2793 | } |
| 2794 | |
| 2795 | static int dwc3_msm_id_notifier(struct notifier_block *nb, |
| 2796 | unsigned long event, void *ptr) |
| 2797 | { |
| 2798 | struct dwc3_msm *mdwc = container_of(nb, struct dwc3_msm, id_nb); |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 2799 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2800 | enum dwc3_id_state id; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2801 | |
| 2802 | id = event ? DWC3_ID_GROUND : DWC3_ID_FLOAT; |
| 2803 | |
| 2804 | dev_dbg(mdwc->dev, "host:%ld (id:%d) event received\n", event, id); |
| 2805 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2806 | if (mdwc->id_state != id) { |
| 2807 | mdwc->id_state = id; |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 2808 | dbg_event(0xFF, "id_state", mdwc->id_state); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2809 | queue_work(mdwc->dwc3_wq, &mdwc->resume_work); |
| 2810 | } |
| 2811 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2812 | return NOTIFY_DONE; |
| 2813 | } |
| 2814 | |
| 2815 | static int dwc3_msm_vbus_notifier(struct notifier_block *nb, |
| 2816 | unsigned long event, void *ptr) |
| 2817 | { |
| 2818 | struct dwc3_msm *mdwc = container_of(nb, struct dwc3_msm, vbus_nb); |
| 2819 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2820 | |
| 2821 | dev_dbg(mdwc->dev, "vbus:%ld event received\n", event); |
| 2822 | |
| 2823 | if (mdwc->vbus_active == event) |
| 2824 | return NOTIFY_DONE; |
| 2825 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2826 | mdwc->vbus_active = event; |
Mayank Rana | 83ad582 | 2016-08-09 14:17:22 -0700 | [diff] [blame] | 2827 | if (dwc->is_drd && !mdwc->in_restart) |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2828 | queue_work(mdwc->dwc3_wq, &mdwc->resume_work); |
Jack Pham | 4e9dff7 | 2017-04-04 18:05:53 -0700 | [diff] [blame] | 2829 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2830 | return NOTIFY_DONE; |
| 2831 | } |
Jack Pham | 4e9dff7 | 2017-04-04 18:05:53 -0700 | [diff] [blame] | 2832 | |
Mayank Rana | 5195817 | 2017-02-28 14:49:21 -0800 | [diff] [blame] | 2833 | /* |
| 2834 | * Handle EUD based soft detach/attach event, and force USB high speed mode |
| 2835 | * functionality on receiving soft attach event. |
| 2836 | * |
| 2837 | * @nb - notifier handler |
| 2838 | * @event - event information i.e. soft detach/attach event |
| 2839 | * @ptr - extcon_dev pointer |
| 2840 | * |
| 2841 | * @return int - NOTIFY_DONE always due to EUD |
| 2842 | */ |
| 2843 | static int dwc3_msm_eud_notifier(struct notifier_block *nb, |
| 2844 | unsigned long event, void *ptr) |
| 2845 | { |
| 2846 | struct dwc3_msm *mdwc = container_of(nb, struct dwc3_msm, eud_event_nb); |
| 2847 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
Mayank Rana | 5195817 | 2017-02-28 14:49:21 -0800 | [diff] [blame] | 2848 | |
| 2849 | dbg_event(0xFF, "EUD_NB", event); |
| 2850 | dev_dbg(mdwc->dev, "eud:%ld event received\n", event); |
| 2851 | if (mdwc->vbus_active == event) |
| 2852 | return NOTIFY_DONE; |
| 2853 | |
| 2854 | /* Force USB High-Speed enumeration Only */ |
| 2855 | dwc->maximum_speed = USB_SPEED_HIGH; |
| 2856 | dbg_event(0xFF, "Speed", dwc->maximum_speed); |
| 2857 | mdwc->vbus_active = event; |
| 2858 | if (dwc->is_drd && !mdwc->in_restart) |
| 2859 | queue_work(mdwc->dwc3_wq, &mdwc->resume_work); |
Jack Pham | 4e9dff7 | 2017-04-04 18:05:53 -0700 | [diff] [blame] | 2860 | |
Mayank Rana | 5195817 | 2017-02-28 14:49:21 -0800 | [diff] [blame] | 2861 | return NOTIFY_DONE; |
| 2862 | } |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2863 | |
| 2864 | static int dwc3_msm_extcon_register(struct dwc3_msm *mdwc) |
| 2865 | { |
| 2866 | struct device_node *node = mdwc->dev->of_node; |
| 2867 | struct extcon_dev *edev; |
| 2868 | int ret = 0; |
| 2869 | |
| 2870 | if (!of_property_read_bool(node, "extcon")) |
| 2871 | return 0; |
| 2872 | |
Mayank Rana | 5195817 | 2017-02-28 14:49:21 -0800 | [diff] [blame] | 2873 | /* Use first phandle (mandatory) for USB vbus status notification */ |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2874 | edev = extcon_get_edev_by_phandle(mdwc->dev, 0); |
| 2875 | if (IS_ERR(edev) && PTR_ERR(edev) != -ENODEV) |
| 2876 | return PTR_ERR(edev); |
| 2877 | |
| 2878 | if (!IS_ERR(edev)) { |
| 2879 | mdwc->extcon_vbus = edev; |
| 2880 | mdwc->vbus_nb.notifier_call = dwc3_msm_vbus_notifier; |
| 2881 | ret = extcon_register_notifier(edev, EXTCON_USB, |
| 2882 | &mdwc->vbus_nb); |
| 2883 | if (ret < 0) { |
| 2884 | dev_err(mdwc->dev, "failed to register notifier for USB\n"); |
| 2885 | return ret; |
| 2886 | } |
| 2887 | } |
| 2888 | |
Mayank Rana | 5195817 | 2017-02-28 14:49:21 -0800 | [diff] [blame] | 2889 | /* Use second phandle (optional) for USB ID status notification */ |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2890 | if (of_count_phandle_with_args(node, "extcon", NULL) > 1) { |
| 2891 | edev = extcon_get_edev_by_phandle(mdwc->dev, 1); |
| 2892 | if (IS_ERR(edev) && PTR_ERR(edev) != -ENODEV) { |
| 2893 | ret = PTR_ERR(edev); |
| 2894 | goto err; |
| 2895 | } |
| 2896 | } |
| 2897 | |
| 2898 | if (!IS_ERR(edev)) { |
| 2899 | mdwc->extcon_id = edev; |
| 2900 | mdwc->id_nb.notifier_call = dwc3_msm_id_notifier; |
| 2901 | ret = extcon_register_notifier(edev, EXTCON_USB_HOST, |
| 2902 | &mdwc->id_nb); |
| 2903 | if (ret < 0) { |
| 2904 | dev_err(mdwc->dev, "failed to register notifier for USB-HOST\n"); |
| 2905 | goto err; |
| 2906 | } |
| 2907 | } |
| 2908 | |
Mayank Rana | 5195817 | 2017-02-28 14:49:21 -0800 | [diff] [blame] | 2909 | /* Use third phandle (optional) for EUD based detach/attach events */ |
| 2910 | if (of_count_phandle_with_args(node, "extcon", NULL) > 2) { |
| 2911 | edev = extcon_get_edev_by_phandle(mdwc->dev, 2); |
| 2912 | if (IS_ERR(edev) && PTR_ERR(edev) != -ENODEV) { |
| 2913 | ret = PTR_ERR(edev); |
| 2914 | goto err; |
| 2915 | } |
| 2916 | } |
| 2917 | |
| 2918 | if (!IS_ERR(edev)) { |
| 2919 | mdwc->extcon_eud = edev; |
| 2920 | mdwc->eud_event_nb.notifier_call = dwc3_msm_eud_notifier; |
| 2921 | ret = extcon_register_notifier(edev, EXTCON_USB, |
| 2922 | &mdwc->eud_event_nb); |
| 2923 | if (ret < 0) { |
| 2924 | dev_err(mdwc->dev, "failed to register notifier for EUD-USB\n"); |
| 2925 | goto err1; |
| 2926 | } |
| 2927 | } |
| 2928 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2929 | return 0; |
Mayank Rana | 5195817 | 2017-02-28 14:49:21 -0800 | [diff] [blame] | 2930 | err1: |
| 2931 | if (mdwc->extcon_id) |
| 2932 | extcon_unregister_notifier(mdwc->extcon_id, EXTCON_USB_HOST, |
| 2933 | &mdwc->id_nb); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2934 | err: |
| 2935 | if (mdwc->extcon_vbus) |
| 2936 | extcon_unregister_notifier(mdwc->extcon_vbus, EXTCON_USB, |
| 2937 | &mdwc->vbus_nb); |
| 2938 | return ret; |
| 2939 | } |
| 2940 | |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 2941 | #define SMMU_BASE 0x10000000 /* Device address range base */ |
| 2942 | #define SMMU_SIZE 0x40000000 /* Device address range size */ |
| 2943 | |
| 2944 | static int dwc3_msm_init_iommu(struct dwc3_msm *mdwc) |
| 2945 | { |
| 2946 | struct device_node *node = mdwc->dev->of_node; |
Jack Pham | 283cece | 2017-04-05 09:58:17 -0700 | [diff] [blame] | 2947 | int atomic_ctx = 1, s1_bypass; |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 2948 | int ret; |
| 2949 | |
| 2950 | if (!of_property_read_bool(node, "iommus")) |
| 2951 | return 0; |
| 2952 | |
| 2953 | mdwc->iommu_map = arm_iommu_create_mapping(&platform_bus_type, |
| 2954 | SMMU_BASE, SMMU_SIZE); |
| 2955 | if (IS_ERR_OR_NULL(mdwc->iommu_map)) { |
| 2956 | ret = PTR_ERR(mdwc->iommu_map) ?: -ENODEV; |
| 2957 | dev_err(mdwc->dev, "Failed to create IOMMU mapping (%d)\n", |
| 2958 | ret); |
| 2959 | return ret; |
| 2960 | } |
| 2961 | dev_dbg(mdwc->dev, "IOMMU mapping created: %pK\n", mdwc->iommu_map); |
| 2962 | |
| 2963 | ret = iommu_domain_set_attr(mdwc->iommu_map->domain, DOMAIN_ATTR_ATOMIC, |
| 2964 | &atomic_ctx); |
| 2965 | if (ret) { |
| 2966 | dev_err(mdwc->dev, "IOMMU set atomic attribute failed (%d)\n", |
| 2967 | ret); |
Jack Pham | 9faa51df | 2017-04-03 18:13:40 -0700 | [diff] [blame] | 2968 | goto release_mapping; |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 2969 | } |
| 2970 | |
Jack Pham | 283cece | 2017-04-05 09:58:17 -0700 | [diff] [blame] | 2971 | s1_bypass = of_property_read_bool(node, "qcom,smmu-s1-bypass"); |
| 2972 | ret = iommu_domain_set_attr(mdwc->iommu_map->domain, |
| 2973 | DOMAIN_ATTR_S1_BYPASS, &s1_bypass); |
| 2974 | if (ret) { |
| 2975 | dev_err(mdwc->dev, "IOMMU set s1 bypass (%d) failed (%d)\n", |
| 2976 | s1_bypass, ret); |
| 2977 | goto release_mapping; |
| 2978 | } |
| 2979 | |
Jack Pham | 9faa51df | 2017-04-03 18:13:40 -0700 | [diff] [blame] | 2980 | ret = arm_iommu_attach_device(mdwc->dev, mdwc->iommu_map); |
| 2981 | if (ret) { |
| 2982 | dev_err(mdwc->dev, "IOMMU attach failed (%d)\n", ret); |
| 2983 | goto release_mapping; |
| 2984 | } |
| 2985 | dev_dbg(mdwc->dev, "attached to IOMMU\n"); |
| 2986 | |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 2987 | return 0; |
Jack Pham | 9faa51df | 2017-04-03 18:13:40 -0700 | [diff] [blame] | 2988 | |
| 2989 | release_mapping: |
| 2990 | arm_iommu_release_mapping(mdwc->iommu_map); |
| 2991 | mdwc->iommu_map = NULL; |
| 2992 | return ret; |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 2993 | } |
| 2994 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 2995 | static ssize_t mode_show(struct device *dev, struct device_attribute *attr, |
| 2996 | char *buf) |
| 2997 | { |
| 2998 | struct dwc3_msm *mdwc = dev_get_drvdata(dev); |
| 2999 | |
| 3000 | if (mdwc->vbus_active) |
| 3001 | return snprintf(buf, PAGE_SIZE, "peripheral\n"); |
| 3002 | if (mdwc->id_state == DWC3_ID_GROUND) |
| 3003 | return snprintf(buf, PAGE_SIZE, "host\n"); |
| 3004 | |
| 3005 | return snprintf(buf, PAGE_SIZE, "none\n"); |
| 3006 | } |
| 3007 | |
| 3008 | static ssize_t mode_store(struct device *dev, struct device_attribute *attr, |
| 3009 | const char *buf, size_t count) |
| 3010 | { |
| 3011 | struct dwc3_msm *mdwc = dev_get_drvdata(dev); |
| 3012 | |
| 3013 | if (sysfs_streq(buf, "peripheral")) { |
| 3014 | mdwc->vbus_active = true; |
| 3015 | mdwc->id_state = DWC3_ID_FLOAT; |
| 3016 | } else if (sysfs_streq(buf, "host")) { |
| 3017 | mdwc->vbus_active = false; |
| 3018 | mdwc->id_state = DWC3_ID_GROUND; |
| 3019 | } else { |
| 3020 | mdwc->vbus_active = false; |
| 3021 | mdwc->id_state = DWC3_ID_FLOAT; |
| 3022 | } |
| 3023 | |
| 3024 | dwc3_ext_event_notify(mdwc); |
| 3025 | |
| 3026 | return count; |
| 3027 | } |
| 3028 | |
| 3029 | static DEVICE_ATTR_RW(mode); |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame] | 3030 | static void msm_dwc3_perf_vote_work(struct work_struct *w); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3031 | |
Vamsi Krishna Samavedam | 17f26db | 2017-01-31 17:21:23 -0800 | [diff] [blame] | 3032 | static ssize_t speed_show(struct device *dev, struct device_attribute *attr, |
| 3033 | char *buf) |
| 3034 | { |
| 3035 | struct dwc3_msm *mdwc = dev_get_drvdata(dev); |
| 3036 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 3037 | |
| 3038 | return snprintf(buf, PAGE_SIZE, "%s\n", |
| 3039 | usb_speed_string(dwc->max_hw_supp_speed)); |
| 3040 | } |
| 3041 | |
| 3042 | static ssize_t speed_store(struct device *dev, struct device_attribute *attr, |
| 3043 | const char *buf, size_t count) |
| 3044 | { |
| 3045 | struct dwc3_msm *mdwc = dev_get_drvdata(dev); |
| 3046 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 3047 | enum usb_device_speed req_speed = USB_SPEED_UNKNOWN; |
| 3048 | |
| 3049 | if (sysfs_streq(buf, "high")) |
| 3050 | req_speed = USB_SPEED_HIGH; |
| 3051 | else if (sysfs_streq(buf, "super")) |
| 3052 | req_speed = USB_SPEED_SUPER; |
| 3053 | |
| 3054 | if (req_speed != USB_SPEED_UNKNOWN && |
| 3055 | req_speed != dwc->max_hw_supp_speed) { |
| 3056 | dwc->maximum_speed = dwc->max_hw_supp_speed = req_speed; |
| 3057 | schedule_work(&mdwc->restart_usb_work); |
| 3058 | } |
| 3059 | |
| 3060 | return count; |
| 3061 | } |
| 3062 | static DEVICE_ATTR_RW(speed); |
| 3063 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3064 | static int dwc3_msm_probe(struct platform_device *pdev) |
| 3065 | { |
| 3066 | struct device_node *node = pdev->dev.of_node, *dwc3_node; |
| 3067 | struct device *dev = &pdev->dev; |
Hemant Kumar | 8220a98 | 2017-01-19 18:11:34 -0800 | [diff] [blame] | 3068 | union power_supply_propval pval = {0}; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3069 | struct dwc3_msm *mdwc; |
| 3070 | struct dwc3 *dwc; |
| 3071 | struct resource *res; |
| 3072 | void __iomem *tcsr; |
| 3073 | bool host_mode; |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 3074 | int ret = 0, i; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3075 | int ext_hub_reset_gpio; |
| 3076 | u32 val; |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 3077 | unsigned long irq_type; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3078 | |
| 3079 | mdwc = devm_kzalloc(&pdev->dev, sizeof(*mdwc), GFP_KERNEL); |
| 3080 | if (!mdwc) |
| 3081 | return -ENOMEM; |
| 3082 | |
| 3083 | if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64))) { |
| 3084 | dev_err(&pdev->dev, "setting DMA mask to 64 failed.\n"); |
| 3085 | if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32))) { |
| 3086 | dev_err(&pdev->dev, "setting DMA mask to 32 failed.\n"); |
| 3087 | return -EOPNOTSUPP; |
| 3088 | } |
| 3089 | } |
| 3090 | |
| 3091 | platform_set_drvdata(pdev, mdwc); |
| 3092 | mdwc->dev = &pdev->dev; |
| 3093 | |
| 3094 | INIT_LIST_HEAD(&mdwc->req_complete_list); |
| 3095 | INIT_WORK(&mdwc->resume_work, dwc3_resume_work); |
| 3096 | INIT_WORK(&mdwc->restart_usb_work, dwc3_restart_usb_work); |
Jack Pham | 4b8b4ae | 2016-08-09 11:36:34 -0700 | [diff] [blame] | 3097 | INIT_WORK(&mdwc->vbus_draw_work, dwc3_msm_vbus_draw_work); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3098 | INIT_DELAYED_WORK(&mdwc->sm_work, dwc3_otg_sm_work); |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame] | 3099 | INIT_DELAYED_WORK(&mdwc->perf_vote_work, msm_dwc3_perf_vote_work); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3100 | |
| 3101 | mdwc->dwc3_wq = alloc_ordered_workqueue("dwc3_wq", 0); |
| 3102 | if (!mdwc->dwc3_wq) { |
| 3103 | pr_err("%s: Unable to create workqueue dwc3_wq\n", __func__); |
| 3104 | return -ENOMEM; |
| 3105 | } |
| 3106 | |
| 3107 | /* Get all clks and gdsc reference */ |
| 3108 | ret = dwc3_msm_get_clk_gdsc(mdwc); |
| 3109 | if (ret) { |
| 3110 | dev_err(&pdev->dev, "error getting clock or gdsc.\n"); |
| 3111 | return ret; |
| 3112 | } |
| 3113 | |
| 3114 | mdwc->id_state = DWC3_ID_FLOAT; |
| 3115 | set_bit(ID, &mdwc->inputs); |
| 3116 | |
| 3117 | mdwc->charging_disabled = of_property_read_bool(node, |
| 3118 | "qcom,charging-disabled"); |
| 3119 | |
| 3120 | ret = of_property_read_u32(node, "qcom,lpm-to-suspend-delay-ms", |
| 3121 | &mdwc->lpm_to_suspend_delay); |
| 3122 | if (ret) { |
| 3123 | dev_dbg(&pdev->dev, "setting lpm_to_suspend_delay to zero.\n"); |
| 3124 | mdwc->lpm_to_suspend_delay = 0; |
| 3125 | } |
| 3126 | |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 3127 | memcpy(mdwc->wakeup_irq, usb_irq_info, sizeof(usb_irq_info)); |
| 3128 | for (i = 0; i < USB_MAX_IRQ; i++) { |
| 3129 | irq_type = IRQF_TRIGGER_RISING | IRQF_EARLY_RESUME | |
| 3130 | IRQF_ONESHOT; |
| 3131 | mdwc->wakeup_irq[i].irq = platform_get_irq_byname(pdev, |
| 3132 | mdwc->wakeup_irq[i].name); |
| 3133 | if (mdwc->wakeup_irq[i].irq < 0) { |
| 3134 | /* pwr_evnt_irq is only mandatory irq */ |
| 3135 | if (!strcmp(mdwc->wakeup_irq[i].name, |
| 3136 | "pwr_event_irq")) { |
| 3137 | dev_err(&pdev->dev, "get_irq for %s failed\n\n", |
| 3138 | mdwc->wakeup_irq[i].name); |
| 3139 | ret = -EINVAL; |
| 3140 | goto err; |
| 3141 | } |
| 3142 | mdwc->wakeup_irq[i].irq = 0; |
| 3143 | } else { |
| 3144 | irq_set_status_flags(mdwc->wakeup_irq[i].irq, |
| 3145 | IRQ_NOAUTOEN); |
| 3146 | /* ss_phy_irq is level trigger interrupt */ |
| 3147 | if (!strcmp(mdwc->wakeup_irq[i].name, "ss_phy_irq")) |
| 3148 | irq_type = IRQF_TRIGGER_HIGH | IRQF_ONESHOT | |
| 3149 | IRQ_TYPE_LEVEL_HIGH | IRQF_EARLY_RESUME; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3150 | |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 3151 | ret = devm_request_threaded_irq(&pdev->dev, |
| 3152 | mdwc->wakeup_irq[i].irq, |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3153 | msm_dwc3_pwr_irq, |
| 3154 | msm_dwc3_pwr_irq_thread, |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 3155 | irq_type, |
| 3156 | mdwc->wakeup_irq[i].name, mdwc); |
| 3157 | if (ret) { |
| 3158 | dev_err(&pdev->dev, "irq req %s failed: %d\n\n", |
| 3159 | mdwc->wakeup_irq[i].name, ret); |
| 3160 | goto err; |
| 3161 | } |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3162 | } |
| 3163 | } |
| 3164 | |
| 3165 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tcsr_base"); |
| 3166 | if (!res) { |
| 3167 | dev_dbg(&pdev->dev, "missing TCSR memory resource\n"); |
| 3168 | } else { |
| 3169 | tcsr = devm_ioremap_nocache(&pdev->dev, res->start, |
| 3170 | resource_size(res)); |
| 3171 | if (IS_ERR_OR_NULL(tcsr)) { |
| 3172 | dev_dbg(&pdev->dev, "tcsr ioremap failed\n"); |
| 3173 | } else { |
| 3174 | /* Enable USB3 on the primary USB port. */ |
| 3175 | writel_relaxed(0x1, tcsr); |
| 3176 | /* |
| 3177 | * Ensure that TCSR write is completed before |
| 3178 | * USB registers initialization. |
| 3179 | */ |
| 3180 | mb(); |
| 3181 | } |
| 3182 | } |
| 3183 | |
| 3184 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core_base"); |
| 3185 | if (!res) { |
| 3186 | dev_err(&pdev->dev, "missing memory base resource\n"); |
| 3187 | ret = -ENODEV; |
| 3188 | goto err; |
| 3189 | } |
| 3190 | |
| 3191 | mdwc->base = devm_ioremap_nocache(&pdev->dev, res->start, |
| 3192 | resource_size(res)); |
| 3193 | if (!mdwc->base) { |
| 3194 | dev_err(&pdev->dev, "ioremap failed\n"); |
| 3195 | ret = -ENODEV; |
| 3196 | goto err; |
| 3197 | } |
| 3198 | |
| 3199 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 3200 | "ahb2phy_base"); |
| 3201 | if (res) { |
| 3202 | mdwc->ahb2phy_base = devm_ioremap_nocache(&pdev->dev, |
| 3203 | res->start, resource_size(res)); |
| 3204 | if (IS_ERR_OR_NULL(mdwc->ahb2phy_base)) { |
| 3205 | dev_err(dev, "couldn't find ahb2phy_base addr.\n"); |
| 3206 | mdwc->ahb2phy_base = NULL; |
| 3207 | } else { |
| 3208 | /* |
| 3209 | * On some targets cfg_ahb_clk depends upon usb gdsc |
| 3210 | * regulator. If cfg_ahb_clk is enabled without |
| 3211 | * turning on usb gdsc regulator clk is stuck off. |
| 3212 | */ |
| 3213 | dwc3_msm_config_gdsc(mdwc, 1); |
| 3214 | clk_prepare_enable(mdwc->cfg_ahb_clk); |
| 3215 | /* Configure AHB2PHY for one wait state read/write*/ |
| 3216 | val = readl_relaxed(mdwc->ahb2phy_base + |
| 3217 | PERIPH_SS_AHB2PHY_TOP_CFG); |
| 3218 | if (val != ONE_READ_WRITE_WAIT) { |
| 3219 | writel_relaxed(ONE_READ_WRITE_WAIT, |
| 3220 | mdwc->ahb2phy_base + |
| 3221 | PERIPH_SS_AHB2PHY_TOP_CFG); |
| 3222 | /* complete above write before using USB PHY */ |
| 3223 | mb(); |
| 3224 | } |
| 3225 | clk_disable_unprepare(mdwc->cfg_ahb_clk); |
| 3226 | dwc3_msm_config_gdsc(mdwc, 0); |
| 3227 | } |
| 3228 | } |
| 3229 | |
| 3230 | if (of_get_property(pdev->dev.of_node, "qcom,usb-dbm", NULL)) { |
| 3231 | mdwc->dbm = usb_get_dbm_by_phandle(&pdev->dev, "qcom,usb-dbm"); |
| 3232 | if (IS_ERR(mdwc->dbm)) { |
| 3233 | dev_err(&pdev->dev, "unable to get dbm device\n"); |
| 3234 | ret = -EPROBE_DEFER; |
| 3235 | goto err; |
| 3236 | } |
| 3237 | /* |
| 3238 | * Add power event if the dbm indicates coming out of L1 |
| 3239 | * by interrupt |
| 3240 | */ |
| 3241 | if (dbm_l1_lpm_interrupt(mdwc->dbm)) { |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 3242 | if (!mdwc->wakeup_irq[PWR_EVNT_IRQ].irq) { |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3243 | dev_err(&pdev->dev, |
| 3244 | "need pwr_event_irq exiting L1\n"); |
| 3245 | ret = -EINVAL; |
| 3246 | goto err; |
| 3247 | } |
| 3248 | } |
| 3249 | } |
| 3250 | |
| 3251 | ext_hub_reset_gpio = of_get_named_gpio(node, |
| 3252 | "qcom,ext-hub-reset-gpio", 0); |
| 3253 | |
| 3254 | if (gpio_is_valid(ext_hub_reset_gpio) |
| 3255 | && (!devm_gpio_request(&pdev->dev, ext_hub_reset_gpio, |
| 3256 | "qcom,ext-hub-reset-gpio"))) { |
| 3257 | /* reset external hub */ |
| 3258 | gpio_direction_output(ext_hub_reset_gpio, 1); |
| 3259 | /* |
| 3260 | * Hub reset should be asserted for minimum 5microsec |
| 3261 | * before deasserting. |
| 3262 | */ |
| 3263 | usleep_range(5, 1000); |
| 3264 | gpio_direction_output(ext_hub_reset_gpio, 0); |
| 3265 | } |
| 3266 | |
| 3267 | if (of_property_read_u32(node, "qcom,dwc-usb3-msm-tx-fifo-size", |
| 3268 | &mdwc->tx_fifo_size)) |
| 3269 | dev_err(&pdev->dev, |
| 3270 | "unable to read platform data tx fifo size\n"); |
| 3271 | |
| 3272 | mdwc->disable_host_mode_pm = of_property_read_bool(node, |
| 3273 | "qcom,disable-host-mode-pm"); |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 3274 | mdwc->use_pdc_interrupts = of_property_read_bool(node, |
| 3275 | "qcom,use-pdc-interrupts"); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3276 | dwc3_set_notifier(&dwc3_msm_notify_event); |
| 3277 | |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 3278 | ret = dwc3_msm_init_iommu(mdwc); |
| 3279 | if (ret) |
| 3280 | goto err; |
| 3281 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3282 | /* Assumes dwc3 is the first DT child of dwc3-msm */ |
| 3283 | dwc3_node = of_get_next_available_child(node, NULL); |
| 3284 | if (!dwc3_node) { |
| 3285 | dev_err(&pdev->dev, "failed to find dwc3 child\n"); |
| 3286 | ret = -ENODEV; |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 3287 | goto uninit_iommu; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3288 | } |
| 3289 | |
| 3290 | ret = of_platform_populate(node, NULL, NULL, &pdev->dev); |
| 3291 | if (ret) { |
| 3292 | dev_err(&pdev->dev, |
| 3293 | "failed to add create dwc3 core\n"); |
| 3294 | of_node_put(dwc3_node); |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 3295 | goto uninit_iommu; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3296 | } |
| 3297 | |
| 3298 | mdwc->dwc3 = of_find_device_by_node(dwc3_node); |
| 3299 | of_node_put(dwc3_node); |
| 3300 | if (!mdwc->dwc3) { |
| 3301 | dev_err(&pdev->dev, "failed to get dwc3 platform device\n"); |
| 3302 | goto put_dwc3; |
| 3303 | } |
| 3304 | |
| 3305 | mdwc->hs_phy = devm_usb_get_phy_by_phandle(&mdwc->dwc3->dev, |
| 3306 | "usb-phy", 0); |
| 3307 | if (IS_ERR(mdwc->hs_phy)) { |
| 3308 | dev_err(&pdev->dev, "unable to get hsphy device\n"); |
| 3309 | ret = PTR_ERR(mdwc->hs_phy); |
| 3310 | goto put_dwc3; |
| 3311 | } |
| 3312 | mdwc->ss_phy = devm_usb_get_phy_by_phandle(&mdwc->dwc3->dev, |
| 3313 | "usb-phy", 1); |
| 3314 | if (IS_ERR(mdwc->ss_phy)) { |
| 3315 | dev_err(&pdev->dev, "unable to get ssphy device\n"); |
| 3316 | ret = PTR_ERR(mdwc->ss_phy); |
| 3317 | goto put_dwc3; |
| 3318 | } |
| 3319 | |
| 3320 | mdwc->bus_scale_table = msm_bus_cl_get_pdata(pdev); |
| 3321 | if (mdwc->bus_scale_table) { |
| 3322 | mdwc->bus_perf_client = |
| 3323 | msm_bus_scale_register_client(mdwc->bus_scale_table); |
| 3324 | } |
| 3325 | |
| 3326 | dwc = platform_get_drvdata(mdwc->dwc3); |
| 3327 | if (!dwc) { |
| 3328 | dev_err(&pdev->dev, "Failed to get dwc3 device\n"); |
| 3329 | goto put_dwc3; |
| 3330 | } |
| 3331 | |
| 3332 | mdwc->irq_to_affin = platform_get_irq(mdwc->dwc3, 0); |
| 3333 | mdwc->dwc3_cpu_notifier.notifier_call = dwc3_cpu_notifier_cb; |
| 3334 | |
| 3335 | if (cpu_to_affin) |
| 3336 | register_cpu_notifier(&mdwc->dwc3_cpu_notifier); |
| 3337 | |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 3338 | ret = of_property_read_u32(node, "qcom,num-gsi-evt-buffs", |
| 3339 | &mdwc->num_gsi_event_buffers); |
| 3340 | |
Jack Pham | 9faa51df | 2017-04-03 18:13:40 -0700 | [diff] [blame] | 3341 | /* IOMMU will be reattached upon each resume/connect */ |
| 3342 | if (mdwc->iommu_map) |
| 3343 | arm_iommu_detach_device(mdwc->dev); |
| 3344 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3345 | /* |
| 3346 | * Clocks and regulators will not be turned on until the first time |
| 3347 | * runtime PM resume is called. This is to allow for booting up with |
| 3348 | * charger already connected so as not to disturb PHY line states. |
| 3349 | */ |
| 3350 | mdwc->lpm_flags = MDWC3_POWER_COLLAPSE | MDWC3_SS_PHY_SUSPEND; |
| 3351 | atomic_set(&dwc->in_lpm, 1); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3352 | pm_runtime_set_autosuspend_delay(mdwc->dev, 1000); |
| 3353 | pm_runtime_use_autosuspend(mdwc->dev); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3354 | device_init_wakeup(mdwc->dev, 1); |
| 3355 | |
| 3356 | if (of_property_read_bool(node, "qcom,disable-dev-mode-pm")) |
| 3357 | pm_runtime_get_noresume(mdwc->dev); |
| 3358 | |
| 3359 | ret = dwc3_msm_extcon_register(mdwc); |
| 3360 | if (ret) |
| 3361 | goto put_dwc3; |
| 3362 | |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame] | 3363 | ret = of_property_read_u32(node, "qcom,pm-qos-latency", |
| 3364 | &mdwc->pm_qos_latency); |
| 3365 | if (ret) { |
| 3366 | dev_dbg(&pdev->dev, "setting pm-qos-latency to zero.\n"); |
| 3367 | mdwc->pm_qos_latency = 0; |
| 3368 | } |
| 3369 | |
Hemant Kumar | 8220a98 | 2017-01-19 18:11:34 -0800 | [diff] [blame] | 3370 | mdwc->usb_psy = power_supply_get_by_name("usb"); |
| 3371 | if (!mdwc->usb_psy) { |
| 3372 | dev_warn(mdwc->dev, "Could not get usb power_supply\n"); |
| 3373 | pval.intval = -EINVAL; |
| 3374 | } else { |
| 3375 | power_supply_get_property(mdwc->usb_psy, |
| 3376 | POWER_SUPPLY_PROP_PRESENT, &pval); |
| 3377 | } |
| 3378 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3379 | /* Update initial VBUS/ID state from extcon */ |
Jack Pham | 4e9dff7 | 2017-04-04 18:05:53 -0700 | [diff] [blame] | 3380 | if (mdwc->extcon_vbus && extcon_get_state(mdwc->extcon_vbus, |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3381 | EXTCON_USB)) |
| 3382 | dwc3_msm_vbus_notifier(&mdwc->vbus_nb, true, mdwc->extcon_vbus); |
Jack Pham | 4e9dff7 | 2017-04-04 18:05:53 -0700 | [diff] [blame] | 3383 | else if (mdwc->extcon_id && extcon_get_state(mdwc->extcon_id, |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3384 | EXTCON_USB_HOST)) |
| 3385 | dwc3_msm_id_notifier(&mdwc->id_nb, true, mdwc->extcon_id); |
Hemant Kumar | 8220a98 | 2017-01-19 18:11:34 -0800 | [diff] [blame] | 3386 | else if (!pval.intval) { |
| 3387 | /* USB cable is not connected */ |
| 3388 | schedule_delayed_work(&mdwc->sm_work, 0); |
| 3389 | } else { |
| 3390 | if (pval.intval > 0) |
| 3391 | dev_info(mdwc->dev, "charger detection in progress\n"); |
| 3392 | } |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3393 | |
| 3394 | device_create_file(&pdev->dev, &dev_attr_mode); |
Vamsi Krishna Samavedam | 17f26db | 2017-01-31 17:21:23 -0800 | [diff] [blame] | 3395 | device_create_file(&pdev->dev, &dev_attr_speed); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3396 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3397 | host_mode = usb_get_dr_mode(&mdwc->dwc3->dev) == USB_DR_MODE_HOST; |
| 3398 | if (!dwc->is_drd && host_mode) { |
| 3399 | dev_dbg(&pdev->dev, "DWC3 in host only mode\n"); |
| 3400 | mdwc->id_state = DWC3_ID_GROUND; |
| 3401 | dwc3_ext_event_notify(mdwc); |
| 3402 | } |
| 3403 | |
| 3404 | return 0; |
| 3405 | |
| 3406 | put_dwc3: |
| 3407 | platform_device_put(mdwc->dwc3); |
| 3408 | if (mdwc->bus_perf_client) |
| 3409 | msm_bus_scale_unregister_client(mdwc->bus_perf_client); |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 3410 | uninit_iommu: |
Jack Pham | 9faa51df | 2017-04-03 18:13:40 -0700 | [diff] [blame] | 3411 | if (mdwc->iommu_map) { |
| 3412 | arm_iommu_detach_device(mdwc->dev); |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 3413 | arm_iommu_release_mapping(mdwc->iommu_map); |
Jack Pham | 9faa51df | 2017-04-03 18:13:40 -0700 | [diff] [blame] | 3414 | } |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3415 | err: |
| 3416 | return ret; |
| 3417 | } |
| 3418 | |
| 3419 | static int dwc3_msm_remove_children(struct device *dev, void *data) |
| 3420 | { |
| 3421 | device_unregister(dev); |
| 3422 | return 0; |
| 3423 | } |
| 3424 | |
| 3425 | static int dwc3_msm_remove(struct platform_device *pdev) |
| 3426 | { |
| 3427 | struct dwc3_msm *mdwc = platform_get_drvdata(pdev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 3428 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3429 | int ret_pm; |
| 3430 | |
| 3431 | device_remove_file(&pdev->dev, &dev_attr_mode); |
| 3432 | |
| 3433 | if (cpu_to_affin) |
| 3434 | unregister_cpu_notifier(&mdwc->dwc3_cpu_notifier); |
| 3435 | |
| 3436 | /* |
| 3437 | * In case of system suspend, pm_runtime_get_sync fails. |
| 3438 | * Hence turn ON the clocks manually. |
| 3439 | */ |
| 3440 | ret_pm = pm_runtime_get_sync(mdwc->dev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 3441 | dbg_event(0xFF, "Remov gsyn", ret_pm); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3442 | if (ret_pm < 0) { |
| 3443 | dev_err(mdwc->dev, |
| 3444 | "pm_runtime_get_sync failed with %d\n", ret_pm); |
Vijayavardhan Vennapusa | 934d9cd | 2016-11-30 13:10:01 +0530 | [diff] [blame] | 3445 | if (mdwc->noc_aggr_clk) |
| 3446 | clk_prepare_enable(mdwc->noc_aggr_clk); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3447 | clk_prepare_enable(mdwc->utmi_clk); |
| 3448 | clk_prepare_enable(mdwc->core_clk); |
| 3449 | clk_prepare_enable(mdwc->iface_clk); |
| 3450 | clk_prepare_enable(mdwc->sleep_clk); |
| 3451 | if (mdwc->bus_aggr_clk) |
| 3452 | clk_prepare_enable(mdwc->bus_aggr_clk); |
| 3453 | clk_prepare_enable(mdwc->xo_clk); |
| 3454 | } |
| 3455 | |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame] | 3456 | cancel_delayed_work_sync(&mdwc->perf_vote_work); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3457 | cancel_delayed_work_sync(&mdwc->sm_work); |
| 3458 | |
| 3459 | if (mdwc->hs_phy) |
| 3460 | mdwc->hs_phy->flags &= ~PHY_HOST_MODE; |
| 3461 | platform_device_put(mdwc->dwc3); |
| 3462 | device_for_each_child(&pdev->dev, NULL, dwc3_msm_remove_children); |
| 3463 | |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 3464 | dbg_event(0xFF, "Remov put", 0); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3465 | pm_runtime_disable(mdwc->dev); |
| 3466 | pm_runtime_barrier(mdwc->dev); |
| 3467 | pm_runtime_put_sync(mdwc->dev); |
| 3468 | pm_runtime_set_suspended(mdwc->dev); |
| 3469 | device_wakeup_disable(mdwc->dev); |
| 3470 | |
| 3471 | if (mdwc->bus_perf_client) |
| 3472 | msm_bus_scale_unregister_client(mdwc->bus_perf_client); |
| 3473 | |
| 3474 | if (!IS_ERR_OR_NULL(mdwc->vbus_reg)) |
| 3475 | regulator_disable(mdwc->vbus_reg); |
| 3476 | |
Mayank Rana | d339abe | 2017-05-31 09:19:49 -0700 | [diff] [blame] | 3477 | if (mdwc->wakeup_irq[HS_PHY_IRQ].irq) |
| 3478 | disable_irq(mdwc->wakeup_irq[HS_PHY_IRQ].irq); |
| 3479 | if (mdwc->wakeup_irq[DP_HS_PHY_IRQ].irq) |
| 3480 | disable_irq(mdwc->wakeup_irq[DP_HS_PHY_IRQ].irq); |
| 3481 | if (mdwc->wakeup_irq[DM_HS_PHY_IRQ].irq) |
| 3482 | disable_irq(mdwc->wakeup_irq[DM_HS_PHY_IRQ].irq); |
| 3483 | if (mdwc->wakeup_irq[SS_PHY_IRQ].irq) |
| 3484 | disable_irq(mdwc->wakeup_irq[SS_PHY_IRQ].irq); |
| 3485 | disable_irq(mdwc->wakeup_irq[PWR_EVNT_IRQ].irq); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3486 | |
| 3487 | clk_disable_unprepare(mdwc->utmi_clk); |
| 3488 | clk_set_rate(mdwc->core_clk, 19200000); |
| 3489 | clk_disable_unprepare(mdwc->core_clk); |
| 3490 | clk_disable_unprepare(mdwc->iface_clk); |
| 3491 | clk_disable_unprepare(mdwc->sleep_clk); |
| 3492 | clk_disable_unprepare(mdwc->xo_clk); |
| 3493 | clk_put(mdwc->xo_clk); |
| 3494 | |
| 3495 | dwc3_msm_config_gdsc(mdwc, 0); |
| 3496 | |
Jack Pham | bbe2796 | 2017-03-23 18:42:26 -0700 | [diff] [blame] | 3497 | if (mdwc->iommu_map) { |
| 3498 | if (!atomic_read(&dwc->in_lpm)) |
| 3499 | arm_iommu_detach_device(mdwc->dev); |
| 3500 | arm_iommu_release_mapping(mdwc->iommu_map); |
| 3501 | } |
| 3502 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3503 | return 0; |
| 3504 | } |
| 3505 | |
Jack Pham | 4d4e934 | 2016-12-07 19:25:02 -0800 | [diff] [blame] | 3506 | static int dwc3_msm_host_notifier(struct notifier_block *nb, |
| 3507 | unsigned long event, void *ptr) |
| 3508 | { |
| 3509 | struct dwc3_msm *mdwc = container_of(nb, struct dwc3_msm, host_nb); |
| 3510 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 3511 | struct usb_device *udev = ptr; |
| 3512 | union power_supply_propval pval; |
| 3513 | unsigned int max_power; |
| 3514 | |
| 3515 | if (event != USB_DEVICE_ADD && event != USB_DEVICE_REMOVE) |
| 3516 | return NOTIFY_DONE; |
| 3517 | |
| 3518 | if (!mdwc->usb_psy) { |
| 3519 | mdwc->usb_psy = power_supply_get_by_name("usb"); |
| 3520 | if (!mdwc->usb_psy) |
| 3521 | return NOTIFY_DONE; |
| 3522 | } |
| 3523 | |
| 3524 | /* |
| 3525 | * For direct-attach devices, new udev is direct child of root hub |
| 3526 | * i.e. dwc -> xhci -> root_hub -> udev |
| 3527 | * root_hub's udev->parent==NULL, so traverse struct device hierarchy |
| 3528 | */ |
| 3529 | if (udev->parent && !udev->parent->parent && |
| 3530 | udev->dev.parent->parent == &dwc->xhci->dev) { |
| 3531 | if (event == USB_DEVICE_ADD && udev->actconfig) { |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 3532 | if (!dwc3_msm_is_ss_rhport_connected(mdwc)) { |
| 3533 | /* |
| 3534 | * Core clock rate can be reduced only if root |
| 3535 | * hub SS port is not enabled/connected. |
| 3536 | */ |
| 3537 | clk_set_rate(mdwc->core_clk, |
| 3538 | mdwc->core_clk_rate_hs); |
| 3539 | dev_dbg(mdwc->dev, |
| 3540 | "set hs core clk rate %ld\n", |
| 3541 | mdwc->core_clk_rate_hs); |
| 3542 | mdwc->max_rh_port_speed = USB_SPEED_HIGH; |
| 3543 | } else { |
| 3544 | mdwc->max_rh_port_speed = USB_SPEED_SUPER; |
| 3545 | } |
| 3546 | |
Jack Pham | 4d4e934 | 2016-12-07 19:25:02 -0800 | [diff] [blame] | 3547 | if (udev->speed >= USB_SPEED_SUPER) |
| 3548 | max_power = udev->actconfig->desc.bMaxPower * 8; |
| 3549 | else |
| 3550 | max_power = udev->actconfig->desc.bMaxPower * 2; |
| 3551 | dev_dbg(mdwc->dev, "%s configured bMaxPower:%d (mA)\n", |
| 3552 | dev_name(&udev->dev), max_power); |
| 3553 | |
| 3554 | /* inform PMIC of max power so it can optimize boost */ |
| 3555 | pval.intval = max_power * 1000; |
| 3556 | power_supply_set_property(mdwc->usb_psy, |
| 3557 | POWER_SUPPLY_PROP_BOOST_CURRENT, &pval); |
| 3558 | } else { |
| 3559 | pval.intval = 0; |
| 3560 | power_supply_set_property(mdwc->usb_psy, |
| 3561 | POWER_SUPPLY_PROP_BOOST_CURRENT, &pval); |
Hemant Kumar | 6f504dc | 2017-02-07 14:13:58 -0800 | [diff] [blame] | 3562 | |
| 3563 | /* set rate back to default core clk rate */ |
| 3564 | clk_set_rate(mdwc->core_clk, mdwc->core_clk_rate); |
| 3565 | dev_dbg(mdwc->dev, "set core clk rate %ld\n", |
| 3566 | mdwc->core_clk_rate); |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 3567 | mdwc->max_rh_port_speed = USB_SPEED_UNKNOWN; |
Jack Pham | 4d4e934 | 2016-12-07 19:25:02 -0800 | [diff] [blame] | 3568 | } |
| 3569 | } |
| 3570 | |
| 3571 | return NOTIFY_DONE; |
| 3572 | } |
| 3573 | |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame] | 3574 | static void msm_dwc3_perf_vote_update(struct dwc3_msm *mdwc, bool perf_mode) |
| 3575 | { |
| 3576 | static bool curr_perf_mode; |
| 3577 | int latency = mdwc->pm_qos_latency; |
| 3578 | |
| 3579 | if ((curr_perf_mode == perf_mode) || !latency) |
| 3580 | return; |
| 3581 | |
| 3582 | if (perf_mode) |
| 3583 | pm_qos_update_request(&mdwc->pm_qos_req_dma, latency); |
| 3584 | else |
| 3585 | pm_qos_update_request(&mdwc->pm_qos_req_dma, |
| 3586 | PM_QOS_DEFAULT_VALUE); |
| 3587 | |
| 3588 | curr_perf_mode = perf_mode; |
| 3589 | pr_debug("%s: latency updated to: %d\n", __func__, |
| 3590 | perf_mode ? latency : PM_QOS_DEFAULT_VALUE); |
| 3591 | } |
| 3592 | |
| 3593 | static void msm_dwc3_perf_vote_work(struct work_struct *w) |
| 3594 | { |
| 3595 | struct dwc3_msm *mdwc = container_of(w, struct dwc3_msm, |
| 3596 | perf_vote_work.work); |
| 3597 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 3598 | static unsigned long last_irq_cnt; |
| 3599 | bool in_perf_mode = false; |
| 3600 | |
| 3601 | if (dwc->irq_cnt - last_irq_cnt >= PM_QOS_THRESHOLD) |
| 3602 | in_perf_mode = true; |
| 3603 | |
| 3604 | pr_debug("%s: in_perf_mode:%u, interrupts in last sample:%lu\n", |
| 3605 | __func__, in_perf_mode, (dwc->irq_cnt - last_irq_cnt)); |
| 3606 | |
| 3607 | last_irq_cnt = dwc->irq_cnt; |
| 3608 | msm_dwc3_perf_vote_update(mdwc, in_perf_mode); |
| 3609 | schedule_delayed_work(&mdwc->perf_vote_work, |
| 3610 | msecs_to_jiffies(1000 * PM_QOS_SAMPLE_SEC)); |
| 3611 | } |
| 3612 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3613 | #define VBUS_REG_CHECK_DELAY (msecs_to_jiffies(1000)) |
| 3614 | |
| 3615 | /** |
| 3616 | * dwc3_otg_start_host - helper function for starting/stoping the host |
| 3617 | * controller driver. |
| 3618 | * |
| 3619 | * @mdwc: Pointer to the dwc3_msm structure. |
| 3620 | * @on: start / stop the host controller driver. |
| 3621 | * |
| 3622 | * Returns 0 on success otherwise negative errno. |
| 3623 | */ |
| 3624 | static int dwc3_otg_start_host(struct dwc3_msm *mdwc, int on) |
| 3625 | { |
| 3626 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 3627 | int ret = 0; |
| 3628 | |
| 3629 | if (!dwc->xhci) |
| 3630 | return -EINVAL; |
| 3631 | |
| 3632 | /* |
| 3633 | * The vbus_reg pointer could have multiple values |
| 3634 | * NULL: regulator_get() hasn't been called, or was previously deferred |
| 3635 | * IS_ERR: regulator could not be obtained, so skip using it |
| 3636 | * Valid pointer otherwise |
| 3637 | */ |
| 3638 | if (!mdwc->vbus_reg) { |
| 3639 | mdwc->vbus_reg = devm_regulator_get_optional(mdwc->dev, |
| 3640 | "vbus_dwc3"); |
| 3641 | if (IS_ERR(mdwc->vbus_reg) && |
| 3642 | PTR_ERR(mdwc->vbus_reg) == -EPROBE_DEFER) { |
| 3643 | /* regulators may not be ready, so retry again later */ |
| 3644 | mdwc->vbus_reg = NULL; |
| 3645 | return -EPROBE_DEFER; |
| 3646 | } |
| 3647 | } |
| 3648 | |
| 3649 | if (on) { |
| 3650 | dev_dbg(mdwc->dev, "%s: turn on host\n", __func__); |
| 3651 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3652 | mdwc->hs_phy->flags |= PHY_HOST_MODE; |
Mayank Rana | 0d5efd7 | 2017-06-08 10:06:00 -0700 | [diff] [blame] | 3653 | if (dwc->maximum_speed == USB_SPEED_SUPER) { |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 3654 | mdwc->ss_phy->flags |= PHY_HOST_MODE; |
Mayank Rana | 0d5efd7 | 2017-06-08 10:06:00 -0700 | [diff] [blame] | 3655 | usb_phy_notify_connect(mdwc->ss_phy, |
| 3656 | USB_SPEED_SUPER); |
| 3657 | } |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 3658 | |
Mayank Rana | 0d5efd7 | 2017-06-08 10:06:00 -0700 | [diff] [blame] | 3659 | usb_phy_notify_connect(mdwc->hs_phy, USB_SPEED_HIGH); |
Hemant Kumar | de1df69 | 2016-04-26 19:36:48 -0700 | [diff] [blame] | 3660 | pm_runtime_get_sync(mdwc->dev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 3661 | dbg_event(0xFF, "StrtHost gync", |
| 3662 | atomic_read(&mdwc->dev->power.usage_count)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3663 | if (!IS_ERR(mdwc->vbus_reg)) |
| 3664 | ret = regulator_enable(mdwc->vbus_reg); |
| 3665 | if (ret) { |
| 3666 | dev_err(mdwc->dev, "unable to enable vbus_reg\n"); |
| 3667 | mdwc->hs_phy->flags &= ~PHY_HOST_MODE; |
| 3668 | mdwc->ss_phy->flags &= ~PHY_HOST_MODE; |
| 3669 | pm_runtime_put_sync(mdwc->dev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 3670 | dbg_event(0xFF, "vregerr psync", |
| 3671 | atomic_read(&mdwc->dev->power.usage_count)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3672 | return ret; |
| 3673 | } |
| 3674 | |
| 3675 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); |
| 3676 | |
Jack Pham | 4d4e934 | 2016-12-07 19:25:02 -0800 | [diff] [blame] | 3677 | mdwc->host_nb.notifier_call = dwc3_msm_host_notifier; |
| 3678 | usb_register_notify(&mdwc->host_nb); |
| 3679 | |
Manu Gautam | 976fdfc | 2016-08-18 09:27:35 +0530 | [diff] [blame] | 3680 | mdwc->usbdev_nb.notifier_call = msm_dwc3_usbdev_notify; |
| 3681 | usb_register_atomic_notify(&mdwc->usbdev_nb); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3682 | /* |
| 3683 | * FIXME If micro A cable is disconnected during system suspend, |
| 3684 | * xhci platform device will be removed before runtime pm is |
| 3685 | * enabled for xhci device. Due to this, disable_depth becomes |
| 3686 | * greater than one and runtimepm is not enabled for next microA |
| 3687 | * connect. Fix this by calling pm_runtime_init for xhci device. |
| 3688 | */ |
| 3689 | pm_runtime_init(&dwc->xhci->dev); |
| 3690 | ret = platform_device_add(dwc->xhci); |
| 3691 | if (ret) { |
| 3692 | dev_err(mdwc->dev, |
| 3693 | "%s: failed to add XHCI pdev ret=%d\n", |
| 3694 | __func__, ret); |
| 3695 | if (!IS_ERR(mdwc->vbus_reg)) |
| 3696 | regulator_disable(mdwc->vbus_reg); |
| 3697 | mdwc->hs_phy->flags &= ~PHY_HOST_MODE; |
| 3698 | mdwc->ss_phy->flags &= ~PHY_HOST_MODE; |
| 3699 | pm_runtime_put_sync(mdwc->dev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 3700 | dbg_event(0xFF, "pdeverr psync", |
| 3701 | atomic_read(&mdwc->dev->power.usage_count)); |
Jack Pham | 4d4e934 | 2016-12-07 19:25:02 -0800 | [diff] [blame] | 3702 | usb_unregister_notify(&mdwc->host_nb); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3703 | return ret; |
| 3704 | } |
| 3705 | |
| 3706 | /* |
| 3707 | * In some cases it is observed that USB PHY is not going into |
| 3708 | * suspend with host mode suspend functionality. Hence disable |
| 3709 | * XHCI's runtime PM here if disable_host_mode_pm is set. |
| 3710 | */ |
| 3711 | if (mdwc->disable_host_mode_pm) |
| 3712 | pm_runtime_disable(&dwc->xhci->dev); |
| 3713 | |
| 3714 | mdwc->in_host_mode = true; |
| 3715 | dwc3_usb3_phy_suspend(dwc, true); |
| 3716 | |
| 3717 | /* xHCI should have incremented child count as necessary */ |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 3718 | dbg_event(0xFF, "StrtHost psync", |
| 3719 | atomic_read(&mdwc->dev->power.usage_count)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3720 | pm_runtime_mark_last_busy(mdwc->dev); |
| 3721 | pm_runtime_put_sync_autosuspend(mdwc->dev); |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame] | 3722 | #ifdef CONFIG_SMP |
| 3723 | mdwc->pm_qos_req_dma.type = PM_QOS_REQ_AFFINE_IRQ; |
| 3724 | mdwc->pm_qos_req_dma.irq = dwc->irq; |
| 3725 | #endif |
| 3726 | pm_qos_add_request(&mdwc->pm_qos_req_dma, |
| 3727 | PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
| 3728 | /* start in perf mode for better performance initially */ |
| 3729 | msm_dwc3_perf_vote_update(mdwc, true); |
| 3730 | schedule_delayed_work(&mdwc->perf_vote_work, |
| 3731 | msecs_to_jiffies(1000 * PM_QOS_SAMPLE_SEC)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3732 | } else { |
| 3733 | dev_dbg(mdwc->dev, "%s: turn off host\n", __func__); |
| 3734 | |
Manu Gautam | 976fdfc | 2016-08-18 09:27:35 +0530 | [diff] [blame] | 3735 | usb_unregister_atomic_notify(&mdwc->usbdev_nb); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3736 | if (!IS_ERR(mdwc->vbus_reg)) |
| 3737 | ret = regulator_disable(mdwc->vbus_reg); |
| 3738 | if (ret) { |
| 3739 | dev_err(mdwc->dev, "unable to disable vbus_reg\n"); |
| 3740 | return ret; |
| 3741 | } |
| 3742 | |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame] | 3743 | cancel_delayed_work_sync(&mdwc->perf_vote_work); |
| 3744 | msm_dwc3_perf_vote_update(mdwc, false); |
| 3745 | pm_qos_remove_request(&mdwc->pm_qos_req_dma); |
| 3746 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3747 | pm_runtime_get_sync(mdwc->dev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 3748 | dbg_event(0xFF, "StopHost gsync", |
| 3749 | atomic_read(&mdwc->dev->power.usage_count)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3750 | usb_phy_notify_disconnect(mdwc->hs_phy, USB_SPEED_HIGH); |
Mayank Rana | 0d5efd7 | 2017-06-08 10:06:00 -0700 | [diff] [blame] | 3751 | if (mdwc->ss_phy->flags & PHY_HOST_MODE) { |
| 3752 | usb_phy_notify_disconnect(mdwc->ss_phy, |
| 3753 | USB_SPEED_SUPER); |
| 3754 | mdwc->ss_phy->flags &= ~PHY_HOST_MODE; |
| 3755 | } |
| 3756 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3757 | mdwc->hs_phy->flags &= ~PHY_HOST_MODE; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3758 | platform_device_del(dwc->xhci); |
Jack Pham | 4d4e934 | 2016-12-07 19:25:02 -0800 | [diff] [blame] | 3759 | usb_unregister_notify(&mdwc->host_nb); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3760 | |
| 3761 | /* |
| 3762 | * Perform USB hardware RESET (both core reset and DBM reset) |
| 3763 | * when moving from host to peripheral. This is required for |
| 3764 | * peripheral mode to work. |
| 3765 | */ |
| 3766 | dwc3_msm_block_reset(mdwc, true); |
| 3767 | |
| 3768 | dwc3_usb3_phy_suspend(dwc, false); |
| 3769 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); |
| 3770 | |
| 3771 | mdwc->in_host_mode = false; |
| 3772 | |
| 3773 | /* re-init core and OTG registers as block reset clears these */ |
| 3774 | dwc3_post_host_reset_core_init(dwc); |
| 3775 | pm_runtime_mark_last_busy(mdwc->dev); |
| 3776 | pm_runtime_put_sync_autosuspend(mdwc->dev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 3777 | dbg_event(0xFF, "StopHost psync", |
| 3778 | atomic_read(&mdwc->dev->power.usage_count)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3779 | } |
| 3780 | |
| 3781 | return 0; |
| 3782 | } |
| 3783 | |
| 3784 | static void dwc3_override_vbus_status(struct dwc3_msm *mdwc, bool vbus_present) |
| 3785 | { |
| 3786 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 3787 | |
| 3788 | /* Update OTG VBUS Valid from HSPHY to controller */ |
| 3789 | dwc3_msm_write_readback(mdwc->base, HS_PHY_CTRL_REG, |
| 3790 | vbus_present ? UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL : |
| 3791 | UTMI_OTG_VBUS_VALID, |
| 3792 | vbus_present ? UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL : 0); |
| 3793 | |
| 3794 | /* Update only if Super Speed is supported */ |
| 3795 | if (dwc->maximum_speed == USB_SPEED_SUPER) { |
| 3796 | /* Update VBUS Valid from SSPHY to controller */ |
| 3797 | dwc3_msm_write_readback(mdwc->base, SS_PHY_CTRL_REG, |
| 3798 | LANE0_PWR_PRESENT, |
| 3799 | vbus_present ? LANE0_PWR_PRESENT : 0); |
| 3800 | } |
| 3801 | } |
| 3802 | |
| 3803 | /** |
| 3804 | * dwc3_otg_start_peripheral - bind/unbind the peripheral controller. |
| 3805 | * |
| 3806 | * @mdwc: Pointer to the dwc3_msm structure. |
| 3807 | * @on: Turn ON/OFF the gadget. |
| 3808 | * |
| 3809 | * Returns 0 on success otherwise negative errno. |
| 3810 | */ |
| 3811 | static int dwc3_otg_start_peripheral(struct dwc3_msm *mdwc, int on) |
| 3812 | { |
| 3813 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 3814 | |
| 3815 | pm_runtime_get_sync(mdwc->dev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 3816 | dbg_event(0xFF, "StrtGdgt gsync", |
| 3817 | atomic_read(&mdwc->dev->power.usage_count)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3818 | |
| 3819 | if (on) { |
| 3820 | dev_dbg(mdwc->dev, "%s: turn on gadget %s\n", |
| 3821 | __func__, dwc->gadget.name); |
| 3822 | |
| 3823 | dwc3_override_vbus_status(mdwc, true); |
| 3824 | usb_phy_notify_connect(mdwc->hs_phy, USB_SPEED_HIGH); |
| 3825 | usb_phy_notify_connect(mdwc->ss_phy, USB_SPEED_SUPER); |
| 3826 | |
| 3827 | /* |
| 3828 | * Core reset is not required during start peripheral. Only |
| 3829 | * DBM reset is required, hence perform only DBM reset here. |
| 3830 | */ |
| 3831 | dwc3_msm_block_reset(mdwc, false); |
| 3832 | |
| 3833 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); |
| 3834 | usb_gadget_vbus_connect(&dwc->gadget); |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame] | 3835 | #ifdef CONFIG_SMP |
| 3836 | mdwc->pm_qos_req_dma.type = PM_QOS_REQ_AFFINE_IRQ; |
| 3837 | mdwc->pm_qos_req_dma.irq = dwc->irq; |
| 3838 | #endif |
| 3839 | pm_qos_add_request(&mdwc->pm_qos_req_dma, |
| 3840 | PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
| 3841 | /* start in perf mode for better performance initially */ |
| 3842 | msm_dwc3_perf_vote_update(mdwc, true); |
| 3843 | schedule_delayed_work(&mdwc->perf_vote_work, |
| 3844 | msecs_to_jiffies(1000 * PM_QOS_SAMPLE_SEC)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3845 | } else { |
| 3846 | dev_dbg(mdwc->dev, "%s: turn off gadget %s\n", |
| 3847 | __func__, dwc->gadget.name); |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame] | 3848 | cancel_delayed_work_sync(&mdwc->perf_vote_work); |
| 3849 | msm_dwc3_perf_vote_update(mdwc, false); |
| 3850 | pm_qos_remove_request(&mdwc->pm_qos_req_dma); |
| 3851 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3852 | usb_gadget_vbus_disconnect(&dwc->gadget); |
| 3853 | usb_phy_notify_disconnect(mdwc->hs_phy, USB_SPEED_HIGH); |
| 3854 | usb_phy_notify_disconnect(mdwc->ss_phy, USB_SPEED_SUPER); |
| 3855 | dwc3_override_vbus_status(mdwc, false); |
| 3856 | dwc3_usb3_phy_suspend(dwc, false); |
| 3857 | } |
| 3858 | |
| 3859 | pm_runtime_put_sync(mdwc->dev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 3860 | dbg_event(0xFF, "StopGdgt psync", |
| 3861 | atomic_read(&mdwc->dev->power.usage_count)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3862 | |
| 3863 | return 0; |
| 3864 | } |
| 3865 | |
| 3866 | static int dwc3_msm_gadget_vbus_draw(struct dwc3_msm *mdwc, unsigned int mA) |
| 3867 | { |
Jack Pham | 8caff35 | 2016-08-19 16:33:55 -0700 | [diff] [blame] | 3868 | union power_supply_propval pval = {0}; |
Jack Pham | d72bafe | 2016-08-09 11:07:22 -0700 | [diff] [blame] | 3869 | int ret; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3870 | |
| 3871 | if (mdwc->charging_disabled) |
| 3872 | return 0; |
| 3873 | |
| 3874 | if (mdwc->max_power == mA) |
| 3875 | return 0; |
| 3876 | |
| 3877 | if (!mdwc->usb_psy) { |
| 3878 | mdwc->usb_psy = power_supply_get_by_name("usb"); |
| 3879 | if (!mdwc->usb_psy) { |
| 3880 | dev_warn(mdwc->dev, "Could not get usb power_supply\n"); |
| 3881 | return -ENODEV; |
| 3882 | } |
| 3883 | } |
| 3884 | |
Fenglin Wu | 80826e0 | 2017-04-25 21:45:08 +0800 | [diff] [blame] | 3885 | power_supply_get_property(mdwc->usb_psy, |
| 3886 | POWER_SUPPLY_PROP_REAL_TYPE, &pval); |
Jack Pham | 8caff35 | 2016-08-19 16:33:55 -0700 | [diff] [blame] | 3887 | if (pval.intval != POWER_SUPPLY_TYPE_USB) |
| 3888 | return 0; |
| 3889 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3890 | dev_info(mdwc->dev, "Avail curr from USB = %u\n", mA); |
| 3891 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3892 | /* Set max current limit in uA */ |
Jack Pham | 8caff35 | 2016-08-19 16:33:55 -0700 | [diff] [blame] | 3893 | pval.intval = 1000 * mA; |
Jack Pham | d72bafe | 2016-08-09 11:07:22 -0700 | [diff] [blame] | 3894 | ret = power_supply_set_property(mdwc->usb_psy, |
| 3895 | POWER_SUPPLY_PROP_CURRENT_MAX, &pval); |
| 3896 | if (ret) { |
| 3897 | dev_dbg(mdwc->dev, "power supply error when setting property\n"); |
| 3898 | return ret; |
| 3899 | } |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3900 | |
| 3901 | mdwc->max_power = mA; |
| 3902 | return 0; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3903 | } |
| 3904 | |
| 3905 | |
| 3906 | /** |
| 3907 | * dwc3_otg_sm_work - workqueue function. |
| 3908 | * |
| 3909 | * @w: Pointer to the dwc3 otg workqueue |
| 3910 | * |
| 3911 | * NOTE: After any change in otg_state, we must reschdule the state machine. |
| 3912 | */ |
| 3913 | static void dwc3_otg_sm_work(struct work_struct *w) |
| 3914 | { |
| 3915 | struct dwc3_msm *mdwc = container_of(w, struct dwc3_msm, sm_work.work); |
| 3916 | struct dwc3 *dwc = NULL; |
| 3917 | bool work = 0; |
| 3918 | int ret = 0; |
| 3919 | unsigned long delay = 0; |
| 3920 | const char *state; |
| 3921 | |
| 3922 | if (mdwc->dwc3) |
| 3923 | dwc = platform_get_drvdata(mdwc->dwc3); |
| 3924 | |
| 3925 | if (!dwc) { |
| 3926 | dev_err(mdwc->dev, "dwc is NULL.\n"); |
| 3927 | return; |
| 3928 | } |
| 3929 | |
| 3930 | state = usb_otg_state_string(mdwc->otg_state); |
| 3931 | dev_dbg(mdwc->dev, "%s state\n", state); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 3932 | dbg_event(0xFF, state, 0); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3933 | |
| 3934 | /* Check OTG state */ |
| 3935 | switch (mdwc->otg_state) { |
| 3936 | case OTG_STATE_UNDEFINED: |
Hemant Kumar | 8220a98 | 2017-01-19 18:11:34 -0800 | [diff] [blame] | 3937 | /* put controller and phy in suspend if no cable connected */ |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3938 | if (test_bit(ID, &mdwc->inputs) && |
Hemant Kumar | 8220a98 | 2017-01-19 18:11:34 -0800 | [diff] [blame] | 3939 | !test_bit(B_SESS_VLD, &mdwc->inputs)) { |
| 3940 | dbg_event(0xFF, "undef_id_!bsv", 0); |
| 3941 | pm_runtime_set_active(mdwc->dev); |
| 3942 | pm_runtime_enable(mdwc->dev); |
| 3943 | pm_runtime_get_noresume(mdwc->dev); |
| 3944 | dwc3_msm_resume(mdwc); |
| 3945 | pm_runtime_put_sync(mdwc->dev); |
| 3946 | dbg_event(0xFF, "Undef NoUSB", |
| 3947 | atomic_read(&mdwc->dev->power.usage_count)); |
| 3948 | mdwc->otg_state = OTG_STATE_B_IDLE; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3949 | break; |
Hemant Kumar | 8220a98 | 2017-01-19 18:11:34 -0800 | [diff] [blame] | 3950 | } |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3951 | |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 3952 | dbg_event(0xFF, "Exit UNDEF", 0); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3953 | mdwc->otg_state = OTG_STATE_B_IDLE; |
Hemant Kumar | 8220a98 | 2017-01-19 18:11:34 -0800 | [diff] [blame] | 3954 | pm_runtime_set_suspended(mdwc->dev); |
| 3955 | pm_runtime_enable(mdwc->dev); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3956 | /* fall-through */ |
| 3957 | case OTG_STATE_B_IDLE: |
| 3958 | if (!test_bit(ID, &mdwc->inputs)) { |
| 3959 | dev_dbg(mdwc->dev, "!id\n"); |
| 3960 | mdwc->otg_state = OTG_STATE_A_IDLE; |
| 3961 | work = 1; |
| 3962 | } else if (test_bit(B_SESS_VLD, &mdwc->inputs)) { |
| 3963 | dev_dbg(mdwc->dev, "b_sess_vld\n"); |
| 3964 | /* |
| 3965 | * Increment pm usage count upon cable connect. Count |
| 3966 | * is decremented in OTG_STATE_B_PERIPHERAL state on |
| 3967 | * cable disconnect or in bus suspend. |
| 3968 | */ |
| 3969 | pm_runtime_get_sync(mdwc->dev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 3970 | dbg_event(0xFF, "BIDLE gsync", |
| 3971 | atomic_read(&mdwc->dev->power.usage_count)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3972 | dwc3_otg_start_peripheral(mdwc, 1); |
| 3973 | mdwc->otg_state = OTG_STATE_B_PERIPHERAL; |
| 3974 | work = 1; |
| 3975 | } else { |
| 3976 | dwc3_msm_gadget_vbus_draw(mdwc, 0); |
| 3977 | dev_dbg(mdwc->dev, "Cable disconnected\n"); |
| 3978 | } |
| 3979 | break; |
| 3980 | |
| 3981 | case OTG_STATE_B_PERIPHERAL: |
| 3982 | if (!test_bit(B_SESS_VLD, &mdwc->inputs) || |
| 3983 | !test_bit(ID, &mdwc->inputs)) { |
| 3984 | dev_dbg(mdwc->dev, "!id || !bsv\n"); |
| 3985 | mdwc->otg_state = OTG_STATE_B_IDLE; |
| 3986 | dwc3_otg_start_peripheral(mdwc, 0); |
| 3987 | /* |
| 3988 | * Decrement pm usage count upon cable disconnect |
| 3989 | * which was incremented upon cable connect in |
| 3990 | * OTG_STATE_B_IDLE state |
| 3991 | */ |
| 3992 | pm_runtime_put_sync(mdwc->dev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 3993 | dbg_event(0xFF, "!BSV psync", |
| 3994 | atomic_read(&mdwc->dev->power.usage_count)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 3995 | work = 1; |
| 3996 | } else if (test_bit(B_SUSPEND, &mdwc->inputs) && |
| 3997 | test_bit(B_SESS_VLD, &mdwc->inputs)) { |
| 3998 | dev_dbg(mdwc->dev, "BPER bsv && susp\n"); |
| 3999 | mdwc->otg_state = OTG_STATE_B_SUSPEND; |
| 4000 | /* |
| 4001 | * Decrement pm usage count upon bus suspend. |
| 4002 | * Count was incremented either upon cable |
| 4003 | * connect in OTG_STATE_B_IDLE or host |
| 4004 | * initiated resume after bus suspend in |
| 4005 | * OTG_STATE_B_SUSPEND state |
| 4006 | */ |
| 4007 | pm_runtime_mark_last_busy(mdwc->dev); |
| 4008 | pm_runtime_put_autosuspend(mdwc->dev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 4009 | dbg_event(0xFF, "SUSP put", |
| 4010 | atomic_read(&mdwc->dev->power.usage_count)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 4011 | } |
| 4012 | break; |
| 4013 | |
| 4014 | case OTG_STATE_B_SUSPEND: |
| 4015 | if (!test_bit(B_SESS_VLD, &mdwc->inputs)) { |
| 4016 | dev_dbg(mdwc->dev, "BSUSP: !bsv\n"); |
| 4017 | mdwc->otg_state = OTG_STATE_B_IDLE; |
| 4018 | dwc3_otg_start_peripheral(mdwc, 0); |
| 4019 | } else if (!test_bit(B_SUSPEND, &mdwc->inputs)) { |
| 4020 | dev_dbg(mdwc->dev, "BSUSP !susp\n"); |
| 4021 | mdwc->otg_state = OTG_STATE_B_PERIPHERAL; |
| 4022 | /* |
| 4023 | * Increment pm usage count upon host |
| 4024 | * initiated resume. Count was decremented |
| 4025 | * upon bus suspend in |
| 4026 | * OTG_STATE_B_PERIPHERAL state. |
| 4027 | */ |
| 4028 | pm_runtime_get_sync(mdwc->dev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 4029 | dbg_event(0xFF, "!SUSP gsync", |
| 4030 | atomic_read(&mdwc->dev->power.usage_count)); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 4031 | } |
| 4032 | break; |
| 4033 | |
| 4034 | case OTG_STATE_A_IDLE: |
| 4035 | /* Switch to A-Device*/ |
| 4036 | if (test_bit(ID, &mdwc->inputs)) { |
| 4037 | dev_dbg(mdwc->dev, "id\n"); |
| 4038 | mdwc->otg_state = OTG_STATE_B_IDLE; |
| 4039 | mdwc->vbus_retry_count = 0; |
| 4040 | work = 1; |
| 4041 | } else { |
| 4042 | mdwc->otg_state = OTG_STATE_A_HOST; |
| 4043 | ret = dwc3_otg_start_host(mdwc, 1); |
| 4044 | if ((ret == -EPROBE_DEFER) && |
| 4045 | mdwc->vbus_retry_count < 3) { |
| 4046 | /* |
| 4047 | * Get regulator failed as regulator driver is |
| 4048 | * not up yet. Will try to start host after 1sec |
| 4049 | */ |
| 4050 | mdwc->otg_state = OTG_STATE_A_IDLE; |
| 4051 | dev_dbg(mdwc->dev, "Unable to get vbus regulator. Retrying...\n"); |
| 4052 | delay = VBUS_REG_CHECK_DELAY; |
| 4053 | work = 1; |
| 4054 | mdwc->vbus_retry_count++; |
| 4055 | } else if (ret) { |
| 4056 | dev_err(mdwc->dev, "unable to start host\n"); |
| 4057 | mdwc->otg_state = OTG_STATE_A_IDLE; |
| 4058 | goto ret; |
| 4059 | } |
| 4060 | } |
| 4061 | break; |
| 4062 | |
| 4063 | case OTG_STATE_A_HOST: |
Manu Gautam | 976fdfc | 2016-08-18 09:27:35 +0530 | [diff] [blame] | 4064 | if (test_bit(ID, &mdwc->inputs) || mdwc->hc_died) { |
| 4065 | dev_dbg(mdwc->dev, "id || hc_died\n"); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 4066 | dwc3_otg_start_host(mdwc, 0); |
| 4067 | mdwc->otg_state = OTG_STATE_B_IDLE; |
| 4068 | mdwc->vbus_retry_count = 0; |
Manu Gautam | 976fdfc | 2016-08-18 09:27:35 +0530 | [diff] [blame] | 4069 | mdwc->hc_died = false; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 4070 | work = 1; |
| 4071 | } else { |
| 4072 | dev_dbg(mdwc->dev, "still in a_host state. Resuming root hub.\n"); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 4073 | dbg_event(0xFF, "XHCIResume", 0); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 4074 | if (dwc) |
| 4075 | pm_runtime_resume(&dwc->xhci->dev); |
| 4076 | } |
| 4077 | break; |
| 4078 | |
| 4079 | default: |
| 4080 | dev_err(mdwc->dev, "%s: invalid otg-state\n", __func__); |
| 4081 | |
| 4082 | } |
| 4083 | |
| 4084 | if (work) |
| 4085 | schedule_delayed_work(&mdwc->sm_work, delay); |
| 4086 | |
| 4087 | ret: |
| 4088 | return; |
| 4089 | } |
| 4090 | |
| 4091 | #ifdef CONFIG_PM_SLEEP |
| 4092 | static int dwc3_msm_pm_suspend(struct device *dev) |
| 4093 | { |
| 4094 | int ret = 0; |
| 4095 | struct dwc3_msm *mdwc = dev_get_drvdata(dev); |
| 4096 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 4097 | |
| 4098 | dev_dbg(dev, "dwc3-msm PM suspend\n"); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 4099 | dbg_event(0xFF, "PM Sus", 0); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 4100 | |
| 4101 | flush_workqueue(mdwc->dwc3_wq); |
| 4102 | if (!atomic_read(&dwc->in_lpm)) { |
| 4103 | dev_err(mdwc->dev, "Abort PM suspend!! (USB is outside LPM)\n"); |
| 4104 | return -EBUSY; |
| 4105 | } |
| 4106 | |
| 4107 | ret = dwc3_msm_suspend(mdwc); |
| 4108 | if (!ret) |
| 4109 | atomic_set(&mdwc->pm_suspended, 1); |
| 4110 | |
| 4111 | return ret; |
| 4112 | } |
| 4113 | |
| 4114 | static int dwc3_msm_pm_resume(struct device *dev) |
| 4115 | { |
| 4116 | struct dwc3_msm *mdwc = dev_get_drvdata(dev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 4117 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 4118 | |
| 4119 | dev_dbg(dev, "dwc3-msm PM resume\n"); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 4120 | dbg_event(0xFF, "PM Res", 0); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 4121 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 4122 | /* flush to avoid race in read/write of pm_suspended */ |
| 4123 | flush_workqueue(mdwc->dwc3_wq); |
| 4124 | atomic_set(&mdwc->pm_suspended, 0); |
| 4125 | |
| 4126 | /* kick in otg state machine */ |
| 4127 | queue_work(mdwc->dwc3_wq, &mdwc->resume_work); |
| 4128 | |
| 4129 | return 0; |
| 4130 | } |
| 4131 | #endif |
| 4132 | |
| 4133 | #ifdef CONFIG_PM |
| 4134 | static int dwc3_msm_runtime_idle(struct device *dev) |
| 4135 | { |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 4136 | struct dwc3_msm *mdwc = dev_get_drvdata(dev); |
| 4137 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
| 4138 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 4139 | dev_dbg(dev, "DWC3-msm runtime idle\n"); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 4140 | dbg_event(0xFF, "RT Idle", 0); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 4141 | |
| 4142 | return 0; |
| 4143 | } |
| 4144 | |
| 4145 | static int dwc3_msm_runtime_suspend(struct device *dev) |
| 4146 | { |
| 4147 | struct dwc3_msm *mdwc = dev_get_drvdata(dev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 4148 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 4149 | |
| 4150 | dev_dbg(dev, "DWC3-msm runtime suspend\n"); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 4151 | dbg_event(0xFF, "RT Sus", 0); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 4152 | |
| 4153 | return dwc3_msm_suspend(mdwc); |
| 4154 | } |
| 4155 | |
| 4156 | static int dwc3_msm_runtime_resume(struct device *dev) |
| 4157 | { |
| 4158 | struct dwc3_msm *mdwc = dev_get_drvdata(dev); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 4159 | struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 4160 | |
| 4161 | dev_dbg(dev, "DWC3-msm runtime resume\n"); |
Mayank Rana | 08e4192 | 2017-03-02 15:25:48 -0800 | [diff] [blame] | 4162 | dbg_event(0xFF, "RT Res", 0); |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 4163 | |
| 4164 | return dwc3_msm_resume(mdwc); |
| 4165 | } |
| 4166 | #endif |
| 4167 | |
| 4168 | static const struct dev_pm_ops dwc3_msm_dev_pm_ops = { |
| 4169 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_msm_pm_suspend, dwc3_msm_pm_resume) |
| 4170 | SET_RUNTIME_PM_OPS(dwc3_msm_runtime_suspend, dwc3_msm_runtime_resume, |
| 4171 | dwc3_msm_runtime_idle) |
| 4172 | }; |
| 4173 | |
| 4174 | static const struct of_device_id of_dwc3_matach[] = { |
| 4175 | { |
| 4176 | .compatible = "qcom,dwc-usb3-msm", |
| 4177 | }, |
| 4178 | { }, |
| 4179 | }; |
| 4180 | MODULE_DEVICE_TABLE(of, of_dwc3_matach); |
| 4181 | |
| 4182 | static struct platform_driver dwc3_msm_driver = { |
| 4183 | .probe = dwc3_msm_probe, |
| 4184 | .remove = dwc3_msm_remove, |
| 4185 | .driver = { |
| 4186 | .name = "msm-dwc3", |
| 4187 | .pm = &dwc3_msm_dev_pm_ops, |
| 4188 | .of_match_table = of_dwc3_matach, |
| 4189 | }, |
| 4190 | }; |
| 4191 | |
| 4192 | MODULE_LICENSE("GPL v2"); |
| 4193 | MODULE_DESCRIPTION("DesignWare USB3 MSM Glue Layer"); |
| 4194 | |
| 4195 | static int dwc3_msm_init(void) |
| 4196 | { |
| 4197 | return platform_driver_register(&dwc3_msm_driver); |
| 4198 | } |
| 4199 | module_init(dwc3_msm_init); |
| 4200 | |
| 4201 | static void __exit dwc3_msm_exit(void) |
| 4202 | { |
| 4203 | platform_driver_unregister(&dwc3_msm_driver); |
| 4204 | } |
| 4205 | module_exit(dwc3_msm_exit); |