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Andrew Victor877d7722007-05-11 20:49:56 +01001/*
2 * arch/arm/mach-at91/at91sam9rl.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 */
11
12#include <linux/module.h>
Boris BREZILLON2edb90a2013-10-11 09:37:45 +020013#include <linux/clk/at91_pmc.h>
Andrew Victor877d7722007-05-11 20:49:56 +010014
Nicolas Pitrec9dfafb2011-08-02 10:21:36 -040015#include <asm/proc-fns.h>
Russell King80b02c12009-01-08 10:01:47 +000016#include <asm/irq.h>
Andrew Victor877d7722007-05-11 20:49:56 +010017#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
David Howells9f97da72012-03-28 18:30:01 +010019#include <asm/system_misc.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010020#include <mach/cpu.h>
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +080021#include <mach/at91_dbgu.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010022#include <mach/at91sam9rl.h>
Uwe Kleine-Königac11a1d2013-11-14 10:49:19 +010023#include <mach/hardware.h>
Andrew Victor877d7722007-05-11 20:49:56 +010024
Jean-Christophe PLAGNIOL-VILLARDa510b9b2012-10-30 06:41:28 +080025#include "at91_aic.h"
Jean-Christophe PLAGNIOL-VILLARDf0995d02012-10-30 08:11:24 +080026#include "at91_rstc.h"
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +080027#include "soc.h"
Andrew Victor877d7722007-05-11 20:49:56 +010028#include "generic.h"
29#include "clock.h"
Jean-Christophe PLAGNIOL-VILLARDfaee0cc2011-10-14 01:37:09 +080030#include "sam9_smc.h"
Daniel Lezcano5ad945e2013-09-22 22:29:57 +020031#include "pm.h"
Andrew Victor877d7722007-05-11 20:49:56 +010032
Andrew Victor877d7722007-05-11 20:49:56 +010033/* --------------------------------------------------------------------
34 * Clocks
35 * -------------------------------------------------------------------- */
36
37/*
38 * The peripheral clocks.
39 */
40static struct clk pioA_clk = {
41 .name = "pioA_clk",
42 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
43 .type = CLK_TYPE_PERIPHERAL,
44};
45static struct clk pioB_clk = {
46 .name = "pioB_clk",
47 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
48 .type = CLK_TYPE_PERIPHERAL,
49};
50static struct clk pioC_clk = {
51 .name = "pioC_clk",
52 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
53 .type = CLK_TYPE_PERIPHERAL,
54};
55static struct clk pioD_clk = {
56 .name = "pioD_clk",
57 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
58 .type = CLK_TYPE_PERIPHERAL,
59};
60static struct clk usart0_clk = {
61 .name = "usart0_clk",
62 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
63 .type = CLK_TYPE_PERIPHERAL,
64};
65static struct clk usart1_clk = {
66 .name = "usart1_clk",
67 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
68 .type = CLK_TYPE_PERIPHERAL,
69};
70static struct clk usart2_clk = {
71 .name = "usart2_clk",
72 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
73 .type = CLK_TYPE_PERIPHERAL,
74};
75static struct clk usart3_clk = {
76 .name = "usart3_clk",
77 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
78 .type = CLK_TYPE_PERIPHERAL,
79};
80static struct clk mmc_clk = {
81 .name = "mci_clk",
82 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
83 .type = CLK_TYPE_PERIPHERAL,
84};
85static struct clk twi0_clk = {
86 .name = "twi0_clk",
87 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
88 .type = CLK_TYPE_PERIPHERAL,
89};
90static struct clk twi1_clk = {
91 .name = "twi1_clk",
92 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
93 .type = CLK_TYPE_PERIPHERAL,
94};
95static struct clk spi_clk = {
96 .name = "spi_clk",
97 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
98 .type = CLK_TYPE_PERIPHERAL,
99};
100static struct clk ssc0_clk = {
101 .name = "ssc0_clk",
102 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
103 .type = CLK_TYPE_PERIPHERAL,
104};
105static struct clk ssc1_clk = {
106 .name = "ssc1_clk",
107 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
108 .type = CLK_TYPE_PERIPHERAL,
109};
110static struct clk tc0_clk = {
111 .name = "tc0_clk",
112 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
113 .type = CLK_TYPE_PERIPHERAL,
114};
115static struct clk tc1_clk = {
116 .name = "tc1_clk",
117 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
118 .type = CLK_TYPE_PERIPHERAL,
119};
120static struct clk tc2_clk = {
121 .name = "tc2_clk",
122 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
123 .type = CLK_TYPE_PERIPHERAL,
124};
Andrew Victorbb1ad682008-09-18 19:42:37 +0100125static struct clk pwm_clk = {
126 .name = "pwm_clk",
Andrew Victor877d7722007-05-11 20:49:56 +0100127 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
128 .type = CLK_TYPE_PERIPHERAL,
129};
130static struct clk tsc_clk = {
131 .name = "tsc_clk",
132 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
133 .type = CLK_TYPE_PERIPHERAL,
134};
135static struct clk dma_clk = {
136 .name = "dma_clk",
137 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
138 .type = CLK_TYPE_PERIPHERAL,
139};
140static struct clk udphs_clk = {
141 .name = "udphs_clk",
142 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
143 .type = CLK_TYPE_PERIPHERAL,
144};
145static struct clk lcdc_clk = {
146 .name = "lcdc_clk",
147 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
148 .type = CLK_TYPE_PERIPHERAL,
149};
150static struct clk ac97_clk = {
151 .name = "ac97_clk",
152 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
153 .type = CLK_TYPE_PERIPHERAL,
154};
155
156static struct clk *periph_clocks[] __initdata = {
157 &pioA_clk,
158 &pioB_clk,
159 &pioC_clk,
160 &pioD_clk,
161 &usart0_clk,
162 &usart1_clk,
163 &usart2_clk,
164 &usart3_clk,
165 &mmc_clk,
166 &twi0_clk,
167 &twi1_clk,
168 &spi_clk,
169 &ssc0_clk,
170 &ssc1_clk,
171 &tc0_clk,
172 &tc1_clk,
173 &tc2_clk,
Andrew Victorbb1ad682008-09-18 19:42:37 +0100174 &pwm_clk,
Andrew Victor877d7722007-05-11 20:49:56 +0100175 &tsc_clk,
176 &dma_clk,
177 &udphs_clk,
178 &lcdc_clk,
179 &ac97_clk,
180 // irq0
181};
182
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100183static struct clk_lookup periph_clocks_lookups[] = {
Johan Hovoldbbd44f6b2013-02-07 16:31:58 +0100184 CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
Jean-Christophe PLAGNIOL-VILLARD9d871592011-06-21 14:24:33 +0800185 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
186 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100187 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
188 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
189 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
Bo Shen636036d22012-11-06 13:57:51 +0800190 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
191 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
Bo Shen099343c2012-11-07 11:41:41 +0800192 CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
193 CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
Nikolaus Vossfac368a2011-11-08 11:49:46 +0100194 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
195 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
Jean-Christophe PLAGNIOL-VILLARD619d4a42011-11-13 13:00:58 +0800196 CLKDEV_CON_ID("pioA", &pioA_clk),
197 CLKDEV_CON_ID("pioB", &pioB_clk),
198 CLKDEV_CON_ID("pioC", &pioC_clk),
199 CLKDEV_CON_ID("pioD", &pioD_clk),
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100200};
201
202static struct clk_lookup usart_clocks_lookups[] = {
203 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
204 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
205 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
206 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
207 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
208};
209
Andrew Victor877d7722007-05-11 20:49:56 +0100210/*
211 * The two programmable clocks.
212 * You must configure pin multiplexing to bring these signals out.
213 */
214static struct clk pck0 = {
215 .name = "pck0",
216 .pmc_mask = AT91_PMC_PCK0,
217 .type = CLK_TYPE_PROGRAMMABLE,
218 .id = 0,
219};
220static struct clk pck1 = {
221 .name = "pck1",
222 .pmc_mask = AT91_PMC_PCK1,
223 .type = CLK_TYPE_PROGRAMMABLE,
224 .id = 1,
225};
226
227static void __init at91sam9rl_register_clocks(void)
228{
229 int i;
230
231 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
232 clk_register(periph_clocks[i]);
233
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100234 clkdev_add_table(periph_clocks_lookups,
235 ARRAY_SIZE(periph_clocks_lookups));
236 clkdev_add_table(usart_clocks_lookups,
237 ARRAY_SIZE(usart_clocks_lookups));
238
Andrew Victor877d7722007-05-11 20:49:56 +0100239 clk_register(&pck0);
240 clk_register(&pck1);
241}
242
243/* --------------------------------------------------------------------
244 * GPIO
245 * -------------------------------------------------------------------- */
246
Jean-Christophe PLAGNIOL-VILLARD1a2d9152011-10-17 14:28:38 +0800247static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
Andrew Victor877d7722007-05-11 20:49:56 +0100248 {
249 .id = AT91SAM9RL_ID_PIOA,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800250 .regbase = AT91SAM9RL_BASE_PIOA,
Andrew Victor877d7722007-05-11 20:49:56 +0100251 }, {
252 .id = AT91SAM9RL_ID_PIOB,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800253 .regbase = AT91SAM9RL_BASE_PIOB,
Andrew Victor877d7722007-05-11 20:49:56 +0100254 }, {
255 .id = AT91SAM9RL_ID_PIOC,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800256 .regbase = AT91SAM9RL_BASE_PIOC,
Andrew Victor877d7722007-05-11 20:49:56 +0100257 }, {
258 .id = AT91SAM9RL_ID_PIOD,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800259 .regbase = AT91SAM9RL_BASE_PIOD,
Andrew Victor877d7722007-05-11 20:49:56 +0100260 }
261};
262
Andrew Victor877d7722007-05-11 20:49:56 +0100263/* --------------------------------------------------------------------
264 * AT91SAM9RL processor initialization
265 * -------------------------------------------------------------------- */
266
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800267static void __init at91sam9rl_map_io(void)
Andrew Victor877d7722007-05-11 20:49:56 +0100268{
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +0800269 unsigned long sram_size;
Andrew Victor877d7722007-05-11 20:49:56 +0100270
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +0800271 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
Andrew Victor877d7722007-05-11 20:49:56 +0100272 case AT91_CIDR_SRAMSIZ_32K:
273 sram_size = 2 * SZ_16K;
274 break;
275 case AT91_CIDR_SRAMSIZ_16K:
276 default:
277 sram_size = SZ_16K;
278 }
279
Andrew Victor877d7722007-05-11 20:49:56 +0100280 /* Map SRAM */
Jean-Christophe PLAGNIOL-VILLARDf0051d82011-05-10 03:20:09 +0800281 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800282}
Andrew Victor877d7722007-05-11 20:49:56 +0100283
Jean-Christophe PLAGNIOL-VILLARDcfa5a1f2011-10-14 01:17:18 +0800284static void __init at91sam9rl_ioremap_registers(void)
285{
Jean-Christophe PLAGNIOL-VILLARDf22deee2011-11-01 01:23:20 +0800286 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
Jean-Christophe PLAGNIOL-VILLARDe9f68b52011-11-18 01:25:52 +0800287 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
Jean-Christophe PLAGNIOL-VILLARDf363c402012-02-13 12:58:53 +0800288 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
Jean-Christophe PLAGNIOL-VILLARD4ab0c5992011-09-18 22:29:50 +0800289 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
Jean-Christophe PLAGNIOL-VILLARDfaee0cc2011-10-14 01:37:09 +0800290 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
Jean-Christophe PLAGNIOL-VILLARD4342d642011-11-27 23:15:50 +0800291 at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
Jean-Christophe PLAGNIOL-VILLARD6b625892013-10-16 16:24:57 +0200292 at91_pm_set_standby(at91sam9_sdram_standby);
Jean-Christophe PLAGNIOL-VILLARDcfa5a1f2011-10-14 01:17:18 +0800293}
294
Jean-Christophe PLAGNIOL-VILLARD46539372011-04-24 18:20:28 +0800295static void __init at91sam9rl_initialize(void)
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800296{
Jean-Christophe PLAGNIOL-VILLARD0d781712012-02-05 20:25:32 +0800297 arm_pm_idle = at91sam9_idle;
Russell King1b2073e2011-11-03 09:53:29 +0000298 arm_pm_restart = at91sam9_alt_restart;
Andrew Victor877d7722007-05-11 20:49:56 +0100299
Johan Hovold6de714c2013-10-16 11:56:14 +0200300 at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
Johan Hovold94c4c792013-10-16 11:56:15 +0200301 at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
Johan Hovold6de714c2013-10-16 11:56:14 +0200302
Andrew Victor877d7722007-05-11 20:49:56 +0100303 /* Register GPIO subsystem */
304 at91_gpio_init(at91sam9rl_gpio, 4);
305}
306
307/* --------------------------------------------------------------------
308 * Interrupt initialization
309 * -------------------------------------------------------------------- */
310
311/*
312 * The default interrupt priority levels (0 = lowest, 7 = highest).
313 */
314static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
315 7, /* Advanced Interrupt Controller */
316 7, /* System Peripherals */
317 1, /* Parallel IO Controller A */
318 1, /* Parallel IO Controller B */
319 1, /* Parallel IO Controller C */
320 1, /* Parallel IO Controller D */
321 5, /* USART 0 */
322 5, /* USART 1 */
323 5, /* USART 2 */
324 5, /* USART 3 */
325 0, /* Multimedia Card Interface */
326 6, /* Two-Wire Interface 0 */
327 6, /* Two-Wire Interface 1 */
328 5, /* Serial Peripheral Interface */
329 4, /* Serial Synchronous Controller 0 */
330 4, /* Serial Synchronous Controller 1 */
331 0, /* Timer Counter 0 */
332 0, /* Timer Counter 1 */
333 0, /* Timer Counter 2 */
334 0,
335 0, /* Touch Screen Controller */
336 0, /* DMA Controller */
337 2, /* USB Device High speed port */
338 2, /* LCD Controller */
339 6, /* AC97 Controller */
340 0,
341 0,
342 0,
343 0,
344 0,
345 0,
346 0, /* Advanced Interrupt Controller */
347};
348
Ludovic Desroches84ddb082013-03-22 13:24:09 +0000349AT91_SOC_START(at91sam9rl)
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800350 .map_io = at91sam9rl_map_io,
Jean-Christophe PLAGNIOL-VILLARD92100c12011-04-23 15:28:34 +0800351 .default_irq_priority = at91sam9rl_default_irq_priority,
Jean-Christophe PLAGNIOL-VILLARD546c8302013-06-01 16:40:11 +0200352 .extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
Jean-Christophe PLAGNIOL-VILLARDcfa5a1f2011-10-14 01:17:18 +0800353 .ioremap_registers = at91sam9rl_ioremap_registers,
Jean-Christophe PLAGNIOL-VILLARD51ddec72011-04-24 18:15:34 +0800354 .register_clocks = at91sam9rl_register_clocks,
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800355 .init = at91sam9rl_initialize,
Jean-Christophe PLAGNIOL-VILLARD8d39e0fd02012-08-16 17:36:55 +0800356AT91_SOC_END