Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef MDSS_DSI_H |
| 15 | #define MDSS_DSI_H |
| 16 | |
| 17 | #include <linux/list.h> |
| 18 | #include <linux/mdss_io_util.h> |
| 19 | #include <linux/irqreturn.h> |
| 20 | #include <linux/pinctrl/consumer.h> |
| 21 | #include <linux/gpio.h> |
| 22 | |
| 23 | #include "mdss_panel.h" |
| 24 | #include "mdss_dsi_cmd.h" |
| 25 | #include "mdss_dsi_clk.h" |
| 26 | |
| 27 | #define MMSS_SERDES_BASE_PHY 0x04f01000 /* mmss (De)Serializer CFG */ |
| 28 | |
| 29 | #define MIPI_OUTP(addr, data) writel_relaxed((data), (addr)) |
| 30 | #define MIPI_INP(addr) readl_relaxed(addr) |
| 31 | |
| 32 | #define MIPI_OUTP_SECURE(addr, data) writel_relaxed((data), (addr)) |
| 33 | #define MIPI_INP_SECURE(addr) readl_relaxed(addr) |
| 34 | |
| 35 | #define MIPI_DSI_PRIM 1 |
| 36 | #define MIPI_DSI_SECD 2 |
| 37 | |
| 38 | #define MIPI_DSI_PANEL_VGA 0 |
| 39 | #define MIPI_DSI_PANEL_WVGA 1 |
| 40 | #define MIPI_DSI_PANEL_WVGA_PT 2 |
| 41 | #define MIPI_DSI_PANEL_FWVGA_PT 3 |
| 42 | #define MIPI_DSI_PANEL_WSVGA_PT 4 |
| 43 | #define MIPI_DSI_PANEL_QHD_PT 5 |
| 44 | #define MIPI_DSI_PANEL_WXGA 6 |
| 45 | #define MIPI_DSI_PANEL_WUXGA 7 |
| 46 | #define MIPI_DSI_PANEL_720P_PT 8 |
| 47 | #define DSI_PANEL_MAX 8 |
| 48 | |
| 49 | #define MDSS_DSI_HW_REV_100 0x10000000 /* 8974 */ |
| 50 | #define MDSS_DSI_HW_REV_100_1 0x10000001 /* 8x26 */ |
| 51 | #define MDSS_DSI_HW_REV_100_2 0x10000002 /* 8x26v2 */ |
| 52 | #define MDSS_DSI_HW_REV_101 0x10010000 /* 8974v2 */ |
| 53 | #define MDSS_DSI_HW_REV_101_1 0x10010001 /* 8974Pro */ |
| 54 | #define MDSS_DSI_HW_REV_102 0x10020000 /* 8084 */ |
| 55 | #define MDSS_DSI_HW_REV_103 0x10030000 /* 8994 */ |
| 56 | #define MDSS_DSI_HW_REV_103_1 0x10030001 /* 8916/8936 */ |
| 57 | #define MDSS_DSI_HW_REV_104 0x10040000 /* 8996 */ |
| 58 | #define MDSS_DSI_HW_REV_104_1 0x10040001 /* 8996 */ |
| 59 | #define MDSS_DSI_HW_REV_104_2 0x10040002 /* 8937 */ |
| 60 | |
| 61 | #define MDSS_DSI_HW_REV_STEP_0 0x0 |
| 62 | #define MDSS_DSI_HW_REV_STEP_1 0x1 |
| 63 | #define MDSS_DSI_HW_REV_STEP_2 0x2 |
| 64 | |
| 65 | #define MDSS_STATUS_TE_WAIT_MAX 3 |
| 66 | #define NONE_PANEL "none" |
| 67 | |
| 68 | enum { /* mipi dsi panel */ |
| 69 | DSI_VIDEO_MODE, |
| 70 | DSI_CMD_MODE, |
| 71 | }; |
| 72 | |
| 73 | enum { |
| 74 | ST_DSI_CLK_OFF, |
| 75 | ST_DSI_SUSPEND, |
| 76 | ST_DSI_RESUME, |
| 77 | ST_DSI_PLAYING, |
| 78 | ST_DSI_NUM |
| 79 | }; |
| 80 | |
| 81 | enum { |
| 82 | EV_DSI_UPDATE, |
| 83 | EV_DSI_DONE, |
| 84 | EV_DSI_TOUT, |
| 85 | EV_DSI_NUM |
| 86 | }; |
| 87 | |
| 88 | enum { |
| 89 | LANDSCAPE = 1, |
| 90 | PORTRAIT = 2, |
| 91 | }; |
| 92 | |
| 93 | enum dsi_trigger_type { |
| 94 | DSI_CMD_MODE_DMA, |
| 95 | DSI_CMD_MODE_MDP, |
| 96 | }; |
| 97 | |
| 98 | enum dsi_panel_bl_ctrl { |
| 99 | BL_PWM, |
| 100 | BL_WLED, |
| 101 | BL_DCS_CMD, |
| 102 | UNKNOWN_CTRL, |
| 103 | }; |
| 104 | |
| 105 | enum dsi_panel_status_mode { |
| 106 | ESD_NONE = 0, |
| 107 | ESD_BTA, |
| 108 | ESD_REG, |
| 109 | ESD_REG_NT35596, |
| 110 | ESD_TE, |
| 111 | ESD_MAX, |
| 112 | }; |
| 113 | |
| 114 | enum dsi_ctrl_op_mode { |
| 115 | DSI_LP_MODE, |
| 116 | DSI_HS_MODE, |
| 117 | }; |
| 118 | |
| 119 | enum dsi_lane_map_type { |
| 120 | DSI_LANE_MAP_0123, |
| 121 | DSI_LANE_MAP_3012, |
| 122 | DSI_LANE_MAP_2301, |
| 123 | DSI_LANE_MAP_1230, |
| 124 | DSI_LANE_MAP_0321, |
| 125 | DSI_LANE_MAP_1032, |
| 126 | DSI_LANE_MAP_2103, |
| 127 | DSI_LANE_MAP_3210, |
| 128 | }; |
| 129 | |
| 130 | enum dsi_pm_type { |
| 131 | /* PANEL_PM not used as part of power_data in dsi_shared_data */ |
| 132 | DSI_PANEL_PM, |
| 133 | DSI_CORE_PM, |
| 134 | DSI_CTRL_PM, |
| 135 | DSI_PHY_PM, |
| 136 | DSI_MAX_PM |
| 137 | }; |
| 138 | |
| 139 | /* |
| 140 | * DSI controller states. |
| 141 | * CTRL_STATE_UNKNOWN - Unknown state of DSI controller. |
| 142 | * CTRL_STATE_PANEL_INIT - State specifies that the panel is initialized. |
| 143 | * CTRL_STATE_MDP_ACTIVE - State specifies that MDP is ready to send |
| 144 | * data to DSI. |
| 145 | * CTRL_STATE_DSI_ACTIVE - State specifies that DSI controller/PHY is |
| 146 | * initialized. |
| 147 | */ |
| 148 | #define CTRL_STATE_UNKNOWN 0x00 |
| 149 | #define CTRL_STATE_PANEL_INIT BIT(0) |
| 150 | #define CTRL_STATE_MDP_ACTIVE BIT(1) |
| 151 | #define CTRL_STATE_DSI_ACTIVE BIT(2) |
| 152 | #define CTRL_STATE_PANEL_LP BIT(3) |
| 153 | |
| 154 | #define DSI_NON_BURST_SYNCH_PULSE 0 |
| 155 | #define DSI_NON_BURST_SYNCH_EVENT 1 |
| 156 | #define DSI_BURST_MODE 2 |
| 157 | |
| 158 | #define DSI_RGB_SWAP_RGB 0 |
| 159 | #define DSI_RGB_SWAP_RBG 1 |
| 160 | #define DSI_RGB_SWAP_BGR 2 |
| 161 | #define DSI_RGB_SWAP_BRG 3 |
| 162 | #define DSI_RGB_SWAP_GRB 4 |
| 163 | #define DSI_RGB_SWAP_GBR 5 |
| 164 | |
| 165 | #define DSI_VIDEO_DST_FORMAT_RGB565 0 |
| 166 | #define DSI_VIDEO_DST_FORMAT_RGB666 1 |
| 167 | #define DSI_VIDEO_DST_FORMAT_RGB666_LOOSE 2 |
| 168 | #define DSI_VIDEO_DST_FORMAT_RGB888 3 |
| 169 | |
| 170 | #define DSI_CMD_DST_FORMAT_RGB111 0 |
| 171 | #define DSI_CMD_DST_FORMAT_RGB332 3 |
| 172 | #define DSI_CMD_DST_FORMAT_RGB444 4 |
| 173 | #define DSI_CMD_DST_FORMAT_RGB565 6 |
| 174 | #define DSI_CMD_DST_FORMAT_RGB666 7 |
| 175 | #define DSI_CMD_DST_FORMAT_RGB888 8 |
| 176 | |
| 177 | #define DSI_INTR_DESJEW_MASK BIT(31) |
| 178 | #define DSI_INTR_DYNAMIC_REFRESH_MASK BIT(29) |
| 179 | #define DSI_INTR_DYNAMIC_REFRESH_DONE BIT(28) |
| 180 | #define DSI_INTR_ERROR_MASK BIT(25) |
| 181 | #define DSI_INTR_ERROR BIT(24) |
| 182 | #define DSI_INTR_BTA_DONE_MASK BIT(21) |
| 183 | #define DSI_INTR_BTA_DONE BIT(20) |
| 184 | #define DSI_INTR_VIDEO_DONE_MASK BIT(17) |
| 185 | #define DSI_INTR_VIDEO_DONE BIT(16) |
| 186 | #define DSI_INTR_CMD_MDP_DONE_MASK BIT(9) |
| 187 | #define DSI_INTR_CMD_MDP_DONE BIT(8) |
| 188 | #define DSI_INTR_CMD_DMA_DONE_MASK BIT(1) |
| 189 | #define DSI_INTR_CMD_DMA_DONE BIT(0) |
| 190 | /* Update this if more interrupt masks are added in future chipsets */ |
| 191 | #define DSI_INTR_TOTAL_MASK 0x2222AA02 |
| 192 | |
| 193 | #define DSI_INTR_MASK_ALL \ |
| 194 | (DSI_INTR_DESJEW_MASK | \ |
| 195 | DSI_INTR_DYNAMIC_REFRESH_MASK | \ |
| 196 | DSI_INTR_ERROR_MASK | \ |
| 197 | DSI_INTR_BTA_DONE_MASK | \ |
| 198 | DSI_INTR_VIDEO_DONE_MASK | \ |
| 199 | DSI_INTR_CMD_MDP_DONE_MASK | \ |
| 200 | DSI_INTR_CMD_DMA_DONE_MASK) |
| 201 | |
| 202 | #define DSI_CMD_TRIGGER_NONE 0x0 /* mdp trigger */ |
| 203 | #define DSI_CMD_TRIGGER_TE 0x02 |
| 204 | #define DSI_CMD_TRIGGER_SW 0x04 |
| 205 | #define DSI_CMD_TRIGGER_SW_SEOF 0x05 /* cmd dma only */ |
| 206 | #define DSI_CMD_TRIGGER_SW_TE 0x06 |
| 207 | |
| 208 | #define DSI_VIDEO_TERM BIT(16) |
| 209 | #define DSI_MDP_TERM BIT(8) |
| 210 | #define DSI_DYNAMIC_TERM BIT(4) |
| 211 | #define DSI_BTA_TERM BIT(1) |
| 212 | #define DSI_CMD_TERM BIT(0) |
| 213 | |
| 214 | #define DSI_DATA_LANES_STOP_STATE 0xF |
| 215 | #define DSI_CLK_LANE_STOP_STATE BIT(4) |
| 216 | #define DSI_DATA_LANES_ENABLED 0xF0 |
| 217 | |
| 218 | /* offsets for dynamic refresh */ |
| 219 | #define DSI_DYNAMIC_REFRESH_CTRL 0x200 |
| 220 | #define DSI_DYNAMIC_REFRESH_PIPE_DELAY 0x204 |
| 221 | #define DSI_DYNAMIC_REFRESH_PIPE_DELAY2 0x208 |
| 222 | #define DSI_DYNAMIC_REFRESH_PLL_DELAY 0x20C |
| 223 | |
| 224 | #define MAX_ERR_INDEX 10 |
| 225 | |
| 226 | extern struct device dsi_dev; |
| 227 | extern u32 dsi_irq; |
| 228 | extern struct mdss_dsi_ctrl_pdata *ctrl_list[]; |
| 229 | |
| 230 | enum { |
| 231 | DSI_CTRL_0, |
| 232 | DSI_CTRL_1, |
| 233 | DSI_CTRL_MAX, |
| 234 | }; |
| 235 | |
| 236 | /* |
| 237 | * Common DSI properties for each controller. The DSI root probe will create the |
| 238 | * shared_data struct which should be accessible to each controller. The goal is |
| 239 | * to only access ctrl_pdata and ctrl_pdata->shared_data during the lifetime of |
| 240 | * each controller i.e. mdss_dsi_res should not be used directly. |
| 241 | */ |
| 242 | struct dsi_shared_data { |
| 243 | u32 hw_config; /* DSI setup configuration i.e. single/dual/split */ |
| 244 | u32 pll_src_config; /* PLL source selection for DSI link clocks */ |
| 245 | u32 hw_rev; /* DSI h/w revision */ |
| 246 | u32 phy_rev; /* DSI PHY revision*/ |
| 247 | |
| 248 | /* DSI ULPS clamp register offsets */ |
| 249 | u32 ulps_clamp_ctrl_off; |
| 250 | u32 ulps_phyrst_ctrl_off; |
| 251 | |
| 252 | bool cmd_clk_ln_recovery_en; |
| 253 | bool dsi0_active; |
| 254 | bool dsi1_active; |
| 255 | |
| 256 | /* DSI bus clocks */ |
| 257 | struct clk *mdp_core_clk; |
| 258 | struct clk *ahb_clk; |
| 259 | struct clk *axi_clk; |
| 260 | struct clk *mmss_misc_ahb_clk; |
| 261 | |
| 262 | /* Other shared clocks */ |
| 263 | struct clk *ext_byte0_clk; |
| 264 | struct clk *ext_pixel0_clk; |
| 265 | struct clk *ext_byte1_clk; |
| 266 | struct clk *ext_pixel1_clk; |
| 267 | |
| 268 | /* Clock sources for branch clocks */ |
| 269 | struct clk *byte0_parent; |
| 270 | struct clk *pixel0_parent; |
| 271 | struct clk *byte1_parent; |
| 272 | struct clk *pixel1_parent; |
| 273 | |
| 274 | /* DSI core regulators */ |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 275 | struct mdss_module_power power_data[DSI_MAX_PM]; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 276 | |
| 277 | /* Shared mutex for DSI PHY regulator */ |
| 278 | struct mutex phy_reg_lock; |
| 279 | |
| 280 | /* Data bus(AXI) scale settings */ |
| 281 | struct msm_bus_scale_pdata *bus_scale_table; |
| 282 | u32 bus_handle; |
| 283 | u32 bus_refcount; |
| 284 | |
| 285 | /* Shared mutex for pm_qos ref count */ |
| 286 | struct mutex pm_qos_lock; |
| 287 | u32 pm_qos_req_cnt; |
| 288 | }; |
| 289 | |
| 290 | struct mdss_dsi_data { |
| 291 | bool res_init; |
| 292 | struct platform_device *pdev; |
| 293 | /* List of controller specific struct data */ |
| 294 | struct mdss_dsi_ctrl_pdata *ctrl_pdata[DSI_CTRL_MAX]; |
| 295 | /* |
| 296 | * This structure should hold common data structures like |
| 297 | * mutex, clocks, regulator information, setup information |
| 298 | */ |
| 299 | struct dsi_shared_data *shared_data; |
| 300 | }; |
| 301 | |
| 302 | /* |
| 303 | * enum mdss_dsi_hw_config - Supported DSI h/w configurations |
| 304 | * |
| 305 | * @SINGLE_DSI: Single DSI panel driven by either DSI0 or DSI1. |
| 306 | * @DUAL_DSI: Two DSI panels driven independently by DSI0 & DSI1. |
| 307 | * @SPLIT_DSI: A split DSI panel driven by both the DSI controllers |
| 308 | * with the DSI link clocks sourced by a single DSI PLL. |
| 309 | */ |
| 310 | enum mdss_dsi_hw_config { |
| 311 | SINGLE_DSI, |
| 312 | DUAL_DSI, |
| 313 | SPLIT_DSI, |
| 314 | }; |
| 315 | |
| 316 | /* |
| 317 | * enum mdss_dsi_pll_src_config - The PLL source for DSI link clocks |
| 318 | * |
| 319 | * @PLL_SRC_0: The link clocks are sourced out of PLL0. |
| 320 | * @PLL_SRC_1: The link clocks are sourced out of PLL1. |
| 321 | */ |
| 322 | enum mdss_dsi_pll_src_config { |
| 323 | PLL_SRC_DEFAULT, |
| 324 | PLL_SRC_0, |
| 325 | PLL_SRC_1, |
| 326 | }; |
| 327 | |
| 328 | struct dsi_panel_cmds { |
| 329 | char *buf; |
| 330 | int blen; |
| 331 | struct dsi_cmd_desc *cmds; |
| 332 | int cmd_cnt; |
| 333 | int link_state; |
| 334 | }; |
| 335 | |
| 336 | struct dsi_panel_timing { |
| 337 | struct mdss_panel_timing timing; |
| 338 | uint32_t phy_timing[12]; |
| 339 | uint32_t phy_timing_8996[40]; |
| 340 | /* DSI_CLKOUT_TIMING_CTRL */ |
| 341 | char t_clk_post; |
| 342 | char t_clk_pre; |
| 343 | struct dsi_panel_cmds on_cmds; |
| 344 | struct dsi_panel_cmds post_panel_on_cmds; |
| 345 | struct dsi_panel_cmds switch_cmds; |
| 346 | }; |
| 347 | |
| 348 | struct dsi_kickoff_action { |
| 349 | struct list_head act_entry; |
| 350 | void (*action)(void *); |
| 351 | void *data; |
| 352 | }; |
| 353 | |
| 354 | struct dsi_pinctrl_res { |
| 355 | struct pinctrl *pinctrl; |
| 356 | struct pinctrl_state *gpio_state_active; |
| 357 | struct pinctrl_state *gpio_state_suspend; |
| 358 | }; |
| 359 | |
| 360 | struct panel_horizontal_idle { |
| 361 | int min; |
| 362 | int max; |
| 363 | int idle; |
| 364 | }; |
| 365 | |
| 366 | struct dsi_err_container { |
| 367 | u32 fifo_err_cnt; |
| 368 | u32 phy_err_cnt; |
| 369 | u32 err_cnt; |
| 370 | u32 err_time_delta; |
| 371 | u32 max_err_index; |
| 372 | |
| 373 | u32 index; |
| 374 | s64 err_time[MAX_ERR_INDEX]; |
| 375 | }; |
| 376 | |
| 377 | #define DSI_CTRL_LEFT DSI_CTRL_0 |
| 378 | #define DSI_CTRL_RIGHT DSI_CTRL_1 |
| 379 | #define DSI_CTRL_CLK_SLAVE DSI_CTRL_RIGHT |
| 380 | #define DSI_CTRL_CLK_MASTER DSI_CTRL_LEFT |
| 381 | |
| 382 | #define DSI_EV_PLL_UNLOCKED 0x0001 |
| 383 | #define DSI_EV_DLNx_FIFO_UNDERFLOW 0x0002 |
| 384 | #define DSI_EV_DSI_FIFO_EMPTY 0x0004 |
| 385 | #define DSI_EV_DLNx_FIFO_OVERFLOW 0x0008 |
| 386 | #define DSI_EV_LP_RX_TIMEOUT 0x0010 |
| 387 | #define DSI_EV_STOP_HS_CLK_LANE 0x40000000 |
| 388 | #define DSI_EV_MDP_BUSY_RELEASE 0x80000000 |
| 389 | |
| 390 | #define MDSS_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x02a0 |
| 391 | #define MDSS_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x02a4 |
| 392 | #define MDSS_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x02a8 |
| 393 | #define MDSS_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x02ac |
| 394 | #define MDSS_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x02b0 |
| 395 | #define MSM_DBA_CHIP_NAME_MAX_LEN 20 |
| 396 | |
| 397 | struct mdss_dsi_ctrl_pdata { |
| 398 | int ndx; /* panel_num */ |
| 399 | int (*on)(struct mdss_panel_data *pdata); |
| 400 | int (*post_panel_on)(struct mdss_panel_data *pdata); |
| 401 | int (*off)(struct mdss_panel_data *pdata); |
| 402 | int (*low_power_config)(struct mdss_panel_data *pdata, int enable); |
| 403 | int (*set_col_page_addr)(struct mdss_panel_data *pdata, bool force); |
| 404 | int (*check_status)(struct mdss_dsi_ctrl_pdata *pdata); |
| 405 | int (*check_read_status)(struct mdss_dsi_ctrl_pdata *pdata); |
| 406 | int (*cmdlist_commit)(struct mdss_dsi_ctrl_pdata *ctrl, int from_mdp); |
| 407 | void (*switch_mode)(struct mdss_panel_data *pdata, int mode); |
| 408 | struct mdss_panel_data panel_data; |
| 409 | unsigned char *ctrl_base; |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 410 | struct mdss_io_data ctrl_io; |
| 411 | struct mdss_io_data mmss_misc_io; |
| 412 | struct mdss_io_data phy_io; |
| 413 | struct mdss_io_data phy_regulator_io; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 414 | int reg_size; |
| 415 | u32 flags; |
| 416 | struct clk *byte_clk; |
| 417 | struct clk *esc_clk; |
| 418 | struct clk *pixel_clk; |
| 419 | struct clk *mux_byte_clk; |
| 420 | struct clk *mux_pixel_clk; |
| 421 | struct clk *pll_byte_clk; |
| 422 | struct clk *pll_pixel_clk; |
| 423 | struct clk *shadow_byte_clk; |
| 424 | struct clk *shadow_pixel_clk; |
| 425 | struct clk *byte_clk_rcg; |
| 426 | struct clk *pixel_clk_rcg; |
| 427 | struct clk *vco_dummy_clk; |
| 428 | u8 ctrl_state; |
| 429 | int panel_mode; |
| 430 | int irq_cnt; |
| 431 | int disp_te_gpio; |
| 432 | int rst_gpio; |
| 433 | int disp_en_gpio; |
| 434 | int bklt_en_gpio; |
| 435 | int mode_gpio; |
| 436 | int intf_mux_gpio; |
| 437 | int bklt_ctrl; /* backlight ctrl */ |
| 438 | bool pwm_pmi; |
| 439 | int pwm_period; |
| 440 | int pwm_pmic_gpio; |
| 441 | int pwm_lpg_chan; |
| 442 | int bklt_max; |
| 443 | int new_fps; |
| 444 | int pwm_enabled; |
| 445 | int clk_lane_cnt; |
| 446 | bool dmap_iommu_map; |
| 447 | bool dsi_irq_line; |
| 448 | bool dcs_cmd_insert; |
| 449 | atomic_t te_irq_ready; |
| 450 | bool idle; |
| 451 | |
| 452 | bool cmd_sync_wait_broadcast; |
| 453 | bool cmd_sync_wait_trigger; |
| 454 | |
| 455 | struct mdss_rect roi; |
| 456 | struct pwm_device *pwm_bl; |
| 457 | u32 pclk_rate; |
| 458 | u32 byte_clk_rate; |
| 459 | u32 pclk_rate_bkp; |
| 460 | u32 byte_clk_rate_bkp; |
| 461 | bool refresh_clk_rate; /* flag to recalculate clk_rate */ |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 462 | struct mdss_module_power panel_power_data; |
| 463 | struct mdss_module_power power_data[DSI_MAX_PM]; /* for 8x10 */ |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 464 | u32 dsi_irq_mask; |
| 465 | struct mdss_hw *dsi_hw; |
| 466 | struct mdss_intf_recovery *recovery; |
| 467 | struct mdss_intf_recovery *mdp_callback; |
| 468 | |
| 469 | struct dsi_panel_cmds on_cmds; |
| 470 | struct dsi_panel_cmds post_dms_on_cmds; |
| 471 | struct dsi_panel_cmds post_panel_on_cmds; |
| 472 | struct dsi_panel_cmds off_cmds; |
| 473 | struct dsi_panel_cmds lp_on_cmds; |
| 474 | struct dsi_panel_cmds lp_off_cmds; |
| 475 | struct dsi_panel_cmds status_cmds; |
| 476 | struct dsi_panel_cmds idle_on_cmds; /* for lp mode */ |
| 477 | struct dsi_panel_cmds idle_off_cmds; |
| 478 | u32 *status_valid_params; |
| 479 | u32 *status_cmds_rlen; |
| 480 | u32 *status_value; |
| 481 | unsigned char *return_buf; |
| 482 | u32 groups; /* several alternative values to compare */ |
| 483 | u32 status_error_count; |
| 484 | u32 max_status_error_count; |
| 485 | |
| 486 | struct dsi_panel_cmds video2cmd; |
| 487 | struct dsi_panel_cmds cmd2video; |
| 488 | |
| 489 | char pps_buf[DSC_PPS_LEN]; /* dsc pps */ |
| 490 | |
| 491 | struct dcs_cmd_list cmdlist; |
| 492 | struct completion dma_comp; |
| 493 | struct completion mdp_comp; |
| 494 | struct completion video_comp; |
| 495 | struct completion dynamic_comp; |
| 496 | struct completion bta_comp; |
| 497 | struct completion te_irq_comp; |
| 498 | spinlock_t irq_lock; |
| 499 | spinlock_t mdp_lock; |
| 500 | int mdp_busy; |
| 501 | struct mutex mutex; |
| 502 | struct mutex cmd_mutex; |
| 503 | struct mutex cmdlist_mutex; |
| 504 | struct regulator *lab; /* vreg handle */ |
| 505 | struct regulator *ibb; /* vreg handle */ |
| 506 | struct mutex clk_lane_mutex; |
| 507 | |
| 508 | bool null_insert_enabled; |
| 509 | bool ulps; |
| 510 | bool core_power; |
| 511 | bool mmss_clamp; |
| 512 | char dlane_swap; /* data lane swap */ |
| 513 | bool is_phyreg_enabled; |
| 514 | bool burst_mode_enabled; |
| 515 | |
| 516 | struct dsi_buf tx_buf; |
| 517 | struct dsi_buf rx_buf; |
| 518 | struct dsi_buf status_buf; |
| 519 | int status_mode; |
| 520 | int rx_len; |
| 521 | int cur_max_pkt_size; |
| 522 | |
| 523 | struct dsi_pinctrl_res pin_res; |
| 524 | |
| 525 | unsigned long dma_size; |
| 526 | dma_addr_t dma_addr; |
| 527 | bool cmd_cfg_restore; |
| 528 | bool do_unicast; |
| 529 | |
| 530 | bool idle_enabled; |
| 531 | int horizontal_idle_cnt; |
| 532 | struct panel_horizontal_idle *line_idle; |
| 533 | struct mdss_util_intf *mdss_util; |
| 534 | struct dsi_shared_data *shared_data; |
| 535 | |
| 536 | void *clk_mngr; |
| 537 | void *dsi_clk_handle; |
| 538 | void *mdp_clk_handle; |
| 539 | int m_dsi_vote_cnt; |
| 540 | int m_mdp_vote_cnt; |
| 541 | /* debugfs structure */ |
| 542 | struct mdss_dsi_debugfs_info *debugfs_info; |
| 543 | |
| 544 | struct dsi_err_container err_cont; |
| 545 | |
| 546 | struct kobject *kobj; |
| 547 | int fb_node; |
| 548 | |
| 549 | /* DBA data */ |
| 550 | struct workqueue_struct *workq; |
| 551 | struct delayed_work dba_work; |
| 552 | char bridge_name[MSM_DBA_CHIP_NAME_MAX_LEN]; |
| 553 | uint32_t bridge_index; |
| 554 | bool ds_registered; |
| 555 | |
| 556 | bool timing_db_mode; |
| 557 | bool update_phy_timing; /* flag to recalculate PHY timings */ |
| 558 | |
| 559 | bool phy_power_off; |
| 560 | }; |
| 561 | |
| 562 | struct dsi_status_data { |
| 563 | struct notifier_block fb_notifier; |
| 564 | struct delayed_work check_status; |
| 565 | struct msm_fb_data_type *mfd; |
| 566 | }; |
| 567 | |
| 568 | void mdss_dsi_read_hw_revision(struct mdss_dsi_ctrl_pdata *ctrl); |
| 569 | int dsi_panel_device_register(struct platform_device *ctrl_pdev, |
| 570 | struct device_node *pan_node, struct mdss_dsi_ctrl_pdata *ctrl_pdata); |
| 571 | |
| 572 | int mdss_dsi_cmds_tx(struct mdss_dsi_ctrl_pdata *ctrl, |
| 573 | struct dsi_cmd_desc *cmds, int cnt, int use_dma_tpg); |
| 574 | |
| 575 | int mdss_dsi_cmds_rx(struct mdss_dsi_ctrl_pdata *ctrl, |
| 576 | struct dsi_cmd_desc *cmds, int rlen, int use_dma_tpg); |
| 577 | |
| 578 | void mdss_dsi_host_init(struct mdss_panel_data *pdata); |
| 579 | void mdss_dsi_op_mode_config(int mode, |
| 580 | struct mdss_panel_data *pdata); |
| 581 | void mdss_dsi_restore_intr_mask(struct mdss_dsi_ctrl_pdata *ctrl); |
| 582 | void mdss_dsi_cmd_mode_ctrl(int enable); |
| 583 | void mdp4_dsi_cmd_trigger(void); |
| 584 | void mdss_dsi_cmd_mdp_start(struct mdss_dsi_ctrl_pdata *ctrl); |
| 585 | void mdss_dsi_cmd_bta_sw_trigger(struct mdss_panel_data *pdata); |
| 586 | bool mdss_dsi_ack_err_status(struct mdss_dsi_ctrl_pdata *ctrl); |
| 587 | int mdss_dsi_clk_ctrl(struct mdss_dsi_ctrl_pdata *ctrl, void *clk_handle, |
| 588 | enum mdss_dsi_clk_type clk_type, enum mdss_dsi_clk_state clk_state); |
| 589 | void mdss_dsi_clk_req(struct mdss_dsi_ctrl_pdata *ctrl, |
| 590 | struct dsi_panel_clk_ctrl *clk_ctrl); |
| 591 | void mdss_dsi_controller_cfg(int enable, |
| 592 | struct mdss_panel_data *pdata); |
| 593 | void mdss_dsi_sw_reset(struct mdss_dsi_ctrl_pdata *ctrl_pdata, bool restore); |
| 594 | int mdss_dsi_wait_for_lane_idle(struct mdss_dsi_ctrl_pdata *ctrl); |
| 595 | |
| 596 | irqreturn_t mdss_dsi_isr(int irq, void *ptr); |
| 597 | irqreturn_t hw_vsync_handler(int irq, void *data); |
| 598 | void disable_esd_thread(void); |
| 599 | void mdss_dsi_irq_handler_config(struct mdss_dsi_ctrl_pdata *ctrl_pdata); |
| 600 | |
| 601 | void mdss_dsi_set_tx_power_mode(int mode, struct mdss_panel_data *pdata); |
| 602 | int mdss_dsi_clk_div_config(struct mdss_panel_info *panel_info, |
| 603 | int frame_rate); |
| 604 | int mdss_dsi_clk_refresh(struct mdss_panel_data *pdata, bool update_phy); |
| 605 | int mdss_dsi_link_clk_init(struct platform_device *pdev, |
| 606 | struct mdss_dsi_ctrl_pdata *ctrl_pdata); |
| 607 | void mdss_dsi_link_clk_deinit(struct device *dev, |
| 608 | struct mdss_dsi_ctrl_pdata *ctrl_pdata); |
| 609 | int mdss_dsi_core_clk_init(struct platform_device *pdev, |
| 610 | struct dsi_shared_data *sdata); |
| 611 | void mdss_dsi_core_clk_deinit(struct device *dev, |
| 612 | struct dsi_shared_data *sdata); |
| 613 | int mdss_dsi_shadow_clk_init(struct platform_device *pdev, |
| 614 | struct mdss_dsi_ctrl_pdata *ctrl_pdata); |
| 615 | void mdss_dsi_shadow_clk_deinit(struct device *dev, |
| 616 | struct mdss_dsi_ctrl_pdata *ctrl_pdata); |
| 617 | int mdss_dsi_pre_clkoff_cb(void *priv, |
| 618 | enum mdss_dsi_clk_type clk_type, |
| 619 | enum mdss_dsi_clk_state new_state); |
| 620 | int mdss_dsi_post_clkoff_cb(void *priv, |
| 621 | enum mdss_dsi_clk_type clk_type, |
| 622 | enum mdss_dsi_clk_state curr_state); |
| 623 | int mdss_dsi_post_clkon_cb(void *priv, |
| 624 | enum mdss_dsi_clk_type clk_type, |
| 625 | enum mdss_dsi_clk_state curr_state); |
| 626 | int mdss_dsi_pre_clkon_cb(void *priv, |
| 627 | enum mdss_dsi_clk_type clk_type, |
| 628 | enum mdss_dsi_clk_state new_state); |
| 629 | int mdss_dsi_panel_reset(struct mdss_panel_data *pdata, int enable); |
| 630 | void mdss_dsi_phy_disable(struct mdss_dsi_ctrl_pdata *ctrl); |
| 631 | void mdss_dsi_cmd_test_pattern(struct mdss_dsi_ctrl_pdata *ctrl); |
| 632 | void mdss_dsi_video_test_pattern(struct mdss_dsi_ctrl_pdata *ctrl); |
| 633 | void mdss_dsi_panel_pwm_cfg(struct mdss_dsi_ctrl_pdata *ctrl); |
| 634 | bool mdss_dsi_panel_pwm_enable(struct mdss_dsi_ctrl_pdata *ctrl); |
| 635 | void mdss_dsi_ctrl_phy_restore(struct mdss_dsi_ctrl_pdata *ctrl); |
| 636 | void mdss_dsi_phy_sw_reset(struct mdss_dsi_ctrl_pdata *ctrl); |
| 637 | void mdss_dsi_phy_init(struct mdss_dsi_ctrl_pdata *ctrl); |
| 638 | void mdss_dsi_ctrl_init(struct device *ctrl_dev, |
| 639 | struct mdss_dsi_ctrl_pdata *ctrl); |
| 640 | void mdss_dsi_cmd_mdp_busy(struct mdss_dsi_ctrl_pdata *ctrl); |
| 641 | void mdss_dsi_wait4video_done(struct mdss_dsi_ctrl_pdata *ctrl); |
| 642 | int mdss_dsi_en_wait4dynamic_done(struct mdss_dsi_ctrl_pdata *ctrl); |
| 643 | int mdss_dsi_cmdlist_commit(struct mdss_dsi_ctrl_pdata *ctrl, int from_mdp); |
| 644 | void mdss_dsi_cmdlist_kickoff(int intf); |
| 645 | int mdss_dsi_bta_status_check(struct mdss_dsi_ctrl_pdata *ctrl); |
| 646 | int mdss_dsi_reg_status_check(struct mdss_dsi_ctrl_pdata *ctrl); |
| 647 | bool __mdss_dsi_clk_enabled(struct mdss_dsi_ctrl_pdata *ctrl, u8 clk_type); |
| 648 | void mdss_dsi_ctrl_setup(struct mdss_dsi_ctrl_pdata *ctrl); |
| 649 | bool mdss_dsi_dln0_phy_err(struct mdss_dsi_ctrl_pdata *ctrl, bool print_en); |
| 650 | void mdss_dsi_lp_cd_rx(struct mdss_dsi_ctrl_pdata *ctrl); |
| 651 | void mdss_dsi_read_phy_revision(struct mdss_dsi_ctrl_pdata *ctrl); |
| 652 | int mdss_dsi_panel_cmd_read(struct mdss_dsi_ctrl_pdata *ctrl, char cmd0, |
| 653 | char cmd1, void (*fxn)(int), char *rbuf, int len); |
| 654 | int mdss_dsi_panel_init(struct device_node *node, |
| 655 | struct mdss_dsi_ctrl_pdata *ctrl_pdata, |
| 656 | int ndx); |
| 657 | int mdss_dsi_panel_timing_switch(struct mdss_dsi_ctrl_pdata *ctrl_pdata, |
| 658 | struct mdss_panel_timing *timing); |
| 659 | |
| 660 | int mdss_panel_parse_bl_settings(struct device_node *np, |
| 661 | struct mdss_dsi_ctrl_pdata *ctrl_pdata); |
| 662 | int mdss_panel_get_dst_fmt(u32 bpp, char mipi_mode, u32 pixel_packing, |
| 663 | char *dst_format); |
| 664 | |
| 665 | int mdss_dsi_register_recovery_handler(struct mdss_dsi_ctrl_pdata *ctrl, |
| 666 | struct mdss_intf_recovery *recovery); |
| 667 | void mdss_dsi_unregister_bl_settings(struct mdss_dsi_ctrl_pdata *ctrl_pdata); |
| 668 | void mdss_dsi_panel_dsc_pps_send(struct mdss_dsi_ctrl_pdata *ctrl, |
| 669 | struct mdss_panel_info *pinfo); |
| 670 | void mdss_dsi_dsc_config(struct mdss_dsi_ctrl_pdata *ctrl, |
| 671 | struct dsc_desc *dsc); |
| 672 | void mdss_dsi_dfps_config_8996(struct mdss_dsi_ctrl_pdata *ctrl); |
| 673 | void mdss_dsi_set_burst_mode(struct mdss_dsi_ctrl_pdata *ctrl); |
| 674 | void mdss_dsi_set_reg(struct mdss_dsi_ctrl_pdata *ctrl, int off, |
| 675 | u32 mask, u32 val); |
| 676 | int mdss_dsi_phy_pll_reset_status(struct mdss_dsi_ctrl_pdata *ctrl); |
| 677 | int mdss_dsi_panel_power_ctrl(struct mdss_panel_data *pdata, int power_state); |
| 678 | |
| 679 | static inline const char *__mdss_dsi_pm_name(enum dsi_pm_type module) |
| 680 | { |
| 681 | switch (module) { |
| 682 | case DSI_CORE_PM: return "DSI_CORE_PM"; |
| 683 | case DSI_CTRL_PM: return "DSI_CTRL_PM"; |
| 684 | case DSI_PHY_PM: return "DSI_PHY_PM"; |
| 685 | case DSI_PANEL_PM: return "PANEL_PM"; |
| 686 | default: return "???"; |
| 687 | } |
| 688 | } |
| 689 | |
| 690 | static inline const char *__mdss_dsi_pm_supply_node_name( |
| 691 | enum dsi_pm_type module) |
| 692 | { |
| 693 | switch (module) { |
| 694 | case DSI_CORE_PM: return "qcom,core-supply-entries"; |
| 695 | case DSI_CTRL_PM: return "qcom,ctrl-supply-entries"; |
| 696 | case DSI_PHY_PM: return "qcom,phy-supply-entries"; |
| 697 | case DSI_PANEL_PM: return "qcom,panel-supply-entries"; |
| 698 | default: return "???"; |
| 699 | } |
| 700 | } |
| 701 | |
| 702 | static inline u32 mdss_dsi_get_hw_config(struct dsi_shared_data *sdata) |
| 703 | { |
| 704 | return sdata->hw_config; |
| 705 | } |
| 706 | |
| 707 | static inline bool mdss_dsi_is_hw_config_single(struct dsi_shared_data *sdata) |
| 708 | { |
| 709 | return mdss_dsi_get_hw_config(sdata) == SINGLE_DSI; |
| 710 | } |
| 711 | |
| 712 | static inline bool mdss_dsi_is_hw_config_split(struct dsi_shared_data *sdata) |
| 713 | { |
| 714 | return mdss_dsi_get_hw_config(sdata) == SPLIT_DSI; |
| 715 | } |
| 716 | |
| 717 | static inline bool mdss_dsi_is_hw_config_dual(struct dsi_shared_data *sdata) |
| 718 | { |
| 719 | return mdss_dsi_get_hw_config(sdata) == DUAL_DSI; |
| 720 | } |
| 721 | |
| 722 | static inline bool mdss_dsi_get_pll_src_config(struct dsi_shared_data *sdata) |
| 723 | { |
| 724 | return sdata->pll_src_config; |
| 725 | } |
| 726 | |
| 727 | /* |
| 728 | * mdss_dsi_is_pll_src_default: Check if the DSI device uses default PLL src |
| 729 | * For single-dsi and dual-dsi configuration, PLL source need not be |
| 730 | * explicitly specified. In this case, the default PLL source configuration |
| 731 | * is assumed. |
| 732 | * |
| 733 | * @sdata: pointer to DSI shared data structure |
| 734 | */ |
| 735 | static inline bool mdss_dsi_is_pll_src_default(struct dsi_shared_data *sdata) |
| 736 | { |
| 737 | return sdata->pll_src_config == PLL_SRC_DEFAULT; |
| 738 | } |
| 739 | |
| 740 | /* |
| 741 | * mdss_dsi_is_pll_src_pll0: Check if the PLL source for a DSI device is PLL0 |
| 742 | * The function is only valid if the DSI configuration is single/split DSI. |
| 743 | * Not valid for dual DSI configuration. |
| 744 | * |
| 745 | * @sdata: pointer to DSI shared data structure |
| 746 | */ |
| 747 | static inline bool mdss_dsi_is_pll_src_pll0(struct dsi_shared_data *sdata) |
| 748 | { |
| 749 | return sdata->pll_src_config == PLL_SRC_0; |
| 750 | } |
| 751 | |
| 752 | /* |
| 753 | * mdss_dsi_is_pll_src_pll1: Check if the PLL source for a DSI device is PLL1 |
| 754 | * The function is only valid if the DSI configuration is single/split DSI. |
| 755 | * Not valid for dual DSI configuration. |
| 756 | * |
| 757 | * @sdata: pointer to DSI shared data structure |
| 758 | */ |
| 759 | static inline bool mdss_dsi_is_pll_src_pll1(struct dsi_shared_data *sdata) |
| 760 | { |
| 761 | return sdata->pll_src_config == PLL_SRC_1; |
| 762 | } |
| 763 | |
| 764 | static inline bool mdss_dsi_is_dsi0_active(struct dsi_shared_data *sdata) |
| 765 | { |
| 766 | return sdata->dsi0_active; |
| 767 | } |
| 768 | |
| 769 | static inline bool mdss_dsi_is_dsi1_active(struct dsi_shared_data *sdata) |
| 770 | { |
| 771 | return sdata->dsi1_active; |
| 772 | } |
| 773 | |
| 774 | static inline u32 mdss_dsi_get_phy_revision(struct mdss_dsi_ctrl_pdata *ctrl) |
| 775 | { |
| 776 | return ctrl->shared_data->phy_rev; |
| 777 | } |
| 778 | |
| 779 | static inline const char *mdss_dsi_get_fb_name(struct mdss_dsi_ctrl_pdata *ctrl) |
| 780 | { |
| 781 | struct mdss_panel_info *pinfo = &(ctrl->panel_data.panel_info); |
| 782 | |
| 783 | if (mdss_dsi_is_hw_config_dual(ctrl->shared_data)) { |
| 784 | if (pinfo->is_prim_panel) |
| 785 | return "qcom,mdss-fb-map-prim"; |
| 786 | else |
| 787 | return "qcom,mdss-fb-map-sec"; |
| 788 | } else { |
| 789 | return "qcom,mdss-fb-map-prim"; |
| 790 | } |
| 791 | } |
| 792 | |
| 793 | static inline bool mdss_dsi_sync_wait_enable(struct mdss_dsi_ctrl_pdata *ctrl) |
| 794 | { |
| 795 | return ctrl->cmd_sync_wait_broadcast; |
| 796 | } |
| 797 | |
| 798 | static inline bool mdss_dsi_sync_wait_trigger(struct mdss_dsi_ctrl_pdata *ctrl) |
| 799 | { |
| 800 | return ctrl->cmd_sync_wait_broadcast && |
| 801 | ctrl->cmd_sync_wait_trigger; |
| 802 | } |
| 803 | |
| 804 | static inline bool mdss_dsi_is_left_ctrl(struct mdss_dsi_ctrl_pdata *ctrl) |
| 805 | { |
| 806 | return ctrl->ndx == DSI_CTRL_LEFT; |
| 807 | } |
| 808 | |
| 809 | static inline bool mdss_dsi_is_right_ctrl(struct mdss_dsi_ctrl_pdata *ctrl) |
| 810 | { |
| 811 | return ctrl->ndx == DSI_CTRL_RIGHT; |
| 812 | } |
| 813 | |
| 814 | static inline struct mdss_dsi_ctrl_pdata *mdss_dsi_get_other_ctrl( |
| 815 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 816 | { |
| 817 | if (ctrl->ndx == DSI_CTRL_RIGHT) |
| 818 | return ctrl_list[DSI_CTRL_LEFT]; |
| 819 | |
| 820 | return ctrl_list[DSI_CTRL_RIGHT]; |
| 821 | } |
| 822 | |
| 823 | static inline struct mdss_dsi_ctrl_pdata *mdss_dsi_get_ctrl_by_index(int ndx) |
| 824 | { |
| 825 | if (ndx >= DSI_CTRL_MAX) |
| 826 | return NULL; |
| 827 | |
| 828 | return ctrl_list[ndx]; |
| 829 | } |
| 830 | |
| 831 | static inline bool mdss_dsi_is_ctrl_clk_master(struct mdss_dsi_ctrl_pdata *ctrl) |
| 832 | { |
| 833 | return mdss_dsi_is_hw_config_split(ctrl->shared_data) && |
| 834 | (ctrl->ndx == DSI_CTRL_CLK_MASTER); |
| 835 | } |
| 836 | |
| 837 | static inline bool mdss_dsi_is_ctrl_clk_slave(struct mdss_dsi_ctrl_pdata *ctrl) |
| 838 | { |
| 839 | return mdss_dsi_is_hw_config_split(ctrl->shared_data) && |
| 840 | (ctrl->ndx == DSI_CTRL_CLK_SLAVE); |
| 841 | } |
| 842 | |
| 843 | static inline bool mdss_dsi_is_te_based_esd(struct mdss_dsi_ctrl_pdata *ctrl) |
| 844 | { |
| 845 | return (ctrl->status_mode == ESD_TE) && |
| 846 | gpio_is_valid(ctrl->disp_te_gpio) && |
| 847 | mdss_dsi_is_left_ctrl(ctrl); |
| 848 | } |
| 849 | |
| 850 | static inline struct mdss_dsi_ctrl_pdata *mdss_dsi_get_ctrl_clk_master(void) |
| 851 | { |
| 852 | return ctrl_list[DSI_CTRL_CLK_MASTER]; |
| 853 | } |
| 854 | |
| 855 | static inline struct mdss_dsi_ctrl_pdata *mdss_dsi_get_ctrl_clk_slave(void) |
| 856 | { |
| 857 | return ctrl_list[DSI_CTRL_CLK_SLAVE]; |
| 858 | } |
| 859 | |
| 860 | static inline bool mdss_dsi_is_panel_off(struct mdss_panel_data *pdata) |
| 861 | { |
| 862 | return mdss_panel_is_power_off(pdata->panel_info.panel_power_state); |
| 863 | } |
| 864 | |
| 865 | static inline bool mdss_dsi_is_panel_on(struct mdss_panel_data *pdata) |
| 866 | { |
| 867 | return mdss_panel_is_power_on(pdata->panel_info.panel_power_state); |
| 868 | } |
| 869 | |
| 870 | static inline bool mdss_dsi_is_panel_on_interactive( |
| 871 | struct mdss_panel_data *pdata) |
| 872 | { |
| 873 | return mdss_panel_is_power_on_interactive( |
| 874 | pdata->panel_info.panel_power_state); |
| 875 | } |
| 876 | |
| 877 | static inline bool mdss_dsi_is_panel_on_lp(struct mdss_panel_data *pdata) |
| 878 | { |
| 879 | return mdss_panel_is_power_on_lp(pdata->panel_info.panel_power_state); |
| 880 | } |
| 881 | |
| 882 | static inline bool mdss_dsi_is_panel_on_ulp(struct mdss_panel_data *pdata) |
| 883 | { |
| 884 | return mdss_panel_is_power_on_ulp(pdata->panel_info.panel_power_state); |
| 885 | } |
| 886 | |
| 887 | static inline bool mdss_dsi_ulps_feature_enabled( |
| 888 | struct mdss_panel_data *pdata) |
| 889 | { |
| 890 | return pdata->panel_info.ulps_feature_enabled; |
| 891 | } |
| 892 | |
| 893 | static inline bool mdss_dsi_cmp_panel_reg(struct dsi_buf status_buf, |
| 894 | u32 *status_val, int i) |
| 895 | { |
| 896 | return status_buf.data[i] == status_val[i]; |
| 897 | } |
| 898 | |
| 899 | #endif /* MDSS_DSI_H */ |