blob: 5b86ee5c1eeb7437d4886aef39735fe6e7aab5b2 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2**
3** PCI Lower Bus Adapter (LBA) manager
4**
5** (c) Copyright 1999,2000 Grant Grundler
6** (c) Copyright 1999,2000 Hewlett-Packard Company
7**
8** This program is free software; you can redistribute it and/or modify
9** it under the terms of the GNU General Public License as published by
10** the Free Software Foundation; either version 2 of the License, or
11** (at your option) any later version.
12**
13**
14** This module primarily provides access to PCI bus (config/IOport
15** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
16** with 4 digit model numbers - eg C3000 (and A400...sigh).
17**
18** LBA driver isn't as simple as the Dino driver because:
19** (a) this chip has substantial bug fixes between revisions
20** (Only one Dino bug has a software workaround :^( )
21** (b) has more options which we don't (yet) support (DMA hints, OLARD)
22** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
23** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
24** (dino only deals with "Legacy" PDC)
25**
26** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
27** (I/O SAPIC is integratd in the LBA chip).
28**
29** FIXME: Add support to SBA and LBA drivers for DMA hint sets
30** FIXME: Add support for PCI card hot-plug (OLARD).
31*/
32
33#include <linux/delay.h>
34#include <linux/types.h>
35#include <linux/kernel.h>
36#include <linux/spinlock.h>
37#include <linux/init.h> /* for __init and __devinit */
38#include <linux/pci.h>
39#include <linux/ioport.h>
40#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070041
42#include <asm/byteorder.h>
43#include <asm/pdc.h>
44#include <asm/pdcpat.h>
45#include <asm/page.h>
46#include <asm/system.h>
47
Kyle McMartin1790cf92006-08-24 21:32:49 -040048#include <asm/ropes.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070049#include <asm/hardware.h> /* for register_parisc_driver() stuff */
50#include <asm/parisc-device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070051#include <asm/io.h> /* read/write stuff */
52
53#undef DEBUG_LBA /* general stuff */
54#undef DEBUG_LBA_PORT /* debug I/O Port access */
55#undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */
56#undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */
57
58#undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */
59
60
61#ifdef DEBUG_LBA
62#define DBG(x...) printk(x)
63#else
64#define DBG(x...)
65#endif
66
67#ifdef DEBUG_LBA_PORT
68#define DBG_PORT(x...) printk(x)
69#else
70#define DBG_PORT(x...)
71#endif
72
73#ifdef DEBUG_LBA_CFG
74#define DBG_CFG(x...) printk(x)
75#else
76#define DBG_CFG(x...)
77#endif
78
79#ifdef DEBUG_LBA_PAT
80#define DBG_PAT(x...) printk(x)
81#else
82#define DBG_PAT(x...)
83#endif
84
85
86/*
87** Config accessor functions only pass in the 8-bit bus number and not
88** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
89** number based on what firmware wrote into the scratch register.
90**
91** The "secondary" bus number is set to this before calling
92** pci_register_ops(). If any PPB's are present, the scan will
93** discover them and update the "secondary" and "subordinate"
94** fields in the pci_bus structure.
95**
96** Changes in the configuration *may* result in a different
97** bus number for each LBA depending on what firmware does.
98*/
99
100#define MODULE_NAME "LBA"
101
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102/* non-postable I/O port space, densely packed */
103#define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL)
Helge Deller8039de12006-01-10 20:35:03 -0500104static void __iomem *astro_iop_base __read_mostly;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106static u32 lba_t32;
107
108/* lba flags */
109#define LBA_FLAG_SKIP_PROBE 0x10
110
111#define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
112
113
114/* Looks nice and keeps the compiler happy */
115#define LBA_DEV(d) ((struct lba_device *) (d))
116
117
118/*
119** Only allow 8 subsidiary busses per LBA
120** Problem is the PCI bus numbering is globally shared.
121*/
122#define LBA_MAX_NUM_BUSES 8
123
124/************************************
125 * LBA register read and write support
126 *
127 * BE WARNED: register writes are posted.
128 * (ie follow writes which must reach HW with a read)
129 */
130#define READ_U8(addr) __raw_readb(addr)
131#define READ_U16(addr) __raw_readw(addr)
132#define READ_U32(addr) __raw_readl(addr)
133#define WRITE_U8(value, addr) __raw_writeb(value, addr)
134#define WRITE_U16(value, addr) __raw_writew(value, addr)
135#define WRITE_U32(value, addr) __raw_writel(value, addr)
136
137#define READ_REG8(addr) readb(addr)
138#define READ_REG16(addr) readw(addr)
139#define READ_REG32(addr) readl(addr)
140#define READ_REG64(addr) readq(addr)
141#define WRITE_REG8(value, addr) writeb(value, addr)
142#define WRITE_REG16(value, addr) writew(value, addr)
143#define WRITE_REG32(value, addr) writel(value, addr)
144
145
146#define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
147#define LBA_CFG_BUS(tok) ((u8) ((tok)>>16))
148#define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f)
149#define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
150
151
152/*
153** Extract LBA (Rope) number from HPA
154** REVISIT: 16 ropes for Stretch/Ike?
155*/
156#define ROPES_PER_IOC 8
157#define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1))
158
159
160static void
161lba_dump_res(struct resource *r, int d)
162{
163 int i;
164
165 if (NULL == r)
166 return;
167
168 printk(KERN_DEBUG "(%p)", r->parent);
169 for (i = d; i ; --i) printk(" ");
Matthew Wilcox645d11d2006-12-24 19:28:42 -0700170 printk(KERN_DEBUG "%p [%lx,%lx]/%lx\n", r,
171 (long)r->start, (long)r->end, r->flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172 lba_dump_res(r->child, d+2);
173 lba_dump_res(r->sibling, d);
174}
175
176
177/*
178** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
179** workaround for cfg cycles:
180** -- preserve LBA state
181** -- prevent any DMA from occurring
182** -- turn on smart mode
183** -- probe with config writes before doing config reads
184** -- check ERROR_STATUS
185** -- clear ERROR_STATUS
186** -- restore LBA state
187**
188** The workaround is only used for device discovery.
189*/
190
191static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d)
192{
193 u8 first_bus = d->hba.hba_bus->secondary;
194 u8 last_sub_bus = d->hba.hba_bus->subordinate;
195
196 if ((bus < first_bus) ||
197 (bus > last_sub_bus) ||
198 ((bus - first_bus) >= LBA_MAX_NUM_BUSES)) {
199 return 0;
200 }
201
202 return 1;
203}
204
205
206
207#define LBA_CFG_SETUP(d, tok) { \
208 /* Save contents of error config register. */ \
209 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
210\
211 /* Save contents of status control register. */ \
212 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
213\
214 /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \
215 ** arbitration for full bus walks. \
216 */ \
217 /* Save contents of arb mask register. */ \
218 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
219\
220 /* \
221 * Turn off all device arbitration bits (i.e. everything \
222 * except arbitration enable bit). \
223 */ \
224 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
225\
226 /* \
227 * Set the smart mode bit so that master aborts don't cause \
228 * LBA to go into PCI fatal mode (required). \
229 */ \
230 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
231}
232
233
234#define LBA_CFG_PROBE(d, tok) { \
235 /* \
236 * Setup Vendor ID write and read back the address register \
237 * to make sure that LBA is the bus master. \
238 */ \
239 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
240 /* \
241 * Read address register to ensure that LBA is the bus master, \
242 * which implies that DMA traffic has stopped when DMA arb is off. \
243 */ \
244 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
245 /* \
246 * Generate a cfg write cycle (will have no affect on \
247 * Vendor ID register since read-only). \
248 */ \
249 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
250 /* \
251 * Make sure write has completed before proceeding further, \
252 * i.e. before setting clear enable. \
253 */ \
254 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
255}
256
257
258/*
259 * HPREVISIT:
260 * -- Can't tell if config cycle got the error.
261 *
262 * OV bit is broken until rev 4.0, so can't use OV bit and
263 * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
264 *
265 * As of rev 4.0, no longer need the error check.
266 *
267 * -- Even if we could tell, we still want to return -1
268 * for **ANY** error (not just master abort).
269 *
270 * -- Only clear non-fatal errors (we don't want to bring
271 * LBA out of pci-fatal mode).
272 *
273 * Actually, there is still a race in which
274 * we could be clearing a fatal error. We will
275 * live with this during our initial bus walk
276 * until rev 4.0 (no driver activity during
277 * initial bus walk). The initial bus walk
278 * has race conditions concerning the use of
279 * smart mode as well.
280 */
281
282#define LBA_MASTER_ABORT_ERROR 0xc
283#define LBA_FATAL_ERROR 0x10
284
285#define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \
286 u32 error_status = 0; \
287 /* \
288 * Set clear enable (CE) bit. Unset by HW when new \
289 * errors are logged -- LBA HW ERS section 14.3.3). \
290 */ \
291 WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
292 error_status = READ_REG32(base + LBA_ERROR_STATUS); \
293 if ((error_status & 0x1f) != 0) { \
294 /* \
295 * Fail the config read request. \
296 */ \
297 error = 1; \
298 if ((error_status & LBA_FATAL_ERROR) == 0) { \
299 /* \
300 * Clear error status (if fatal bit not set) by setting \
301 * clear error log bit (CL). \
302 */ \
303 WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
304 } \
305 } \
306}
307
308#define LBA_CFG_TR4_ADDR_SETUP(d, addr) \
309 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
310
311#define LBA_CFG_ADDR_SETUP(d, addr) { \
312 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
313 /* \
314 * Read address register to ensure that LBA is the bus master, \
315 * which implies that DMA traffic has stopped when DMA arb is off. \
316 */ \
317 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
318}
319
320
321#define LBA_CFG_RESTORE(d, base) { \
322 /* \
323 * Restore status control register (turn off clear enable). \
324 */ \
325 WRITE_REG32(status_control, base + LBA_STAT_CTL); \
326 /* \
327 * Restore error config register (turn off smart mode). \
328 */ \
329 WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \
330 /* \
331 * Restore arb mask register (reenables DMA arbitration). \
332 */ \
333 WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \
334}
335
336
337
338static unsigned int
339lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
340{
341 u32 data = ~0U;
342 int error = 0;
343 u32 arb_mask = 0; /* used by LBA_CFG_SETUP/RESTORE */
344 u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */
345 u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */
346
347 LBA_CFG_SETUP(d, tok);
348 LBA_CFG_PROBE(d, tok);
349 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
350 if (!error) {
351 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
352
353 LBA_CFG_ADDR_SETUP(d, tok | reg);
354 switch (size) {
355 case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break;
356 case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break;
357 case 4: data = READ_REG32(data_reg); break;
358 }
359 }
360 LBA_CFG_RESTORE(d, d->hba.base_addr);
361 return(data);
362}
363
364
365static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
366{
367 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
368 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
369 u32 tok = LBA_CFG_TOK(local_bus, devfn);
370 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
371
372 if ((pos > 255) || (devfn > 255))
373 return -EINVAL;
374
375/* FIXME: B2K/C3600 workaround is always use old method... */
376 /* if (!LBA_SKIP_PROBE(d)) */ {
377 /* original - Generate config cycle on broken elroy
378 with risk we will miss PCI bus errors. */
379 *data = lba_rd_cfg(d, tok, pos, size);
380 DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __FUNCTION__, tok, pos, *data);
381 return 0;
382 }
383
384 if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->secondary, devfn, d)) {
385 DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __FUNCTION__, tok, pos);
386 /* either don't want to look or know device isn't present. */
387 *data = ~0U;
388 return(0);
389 }
390
391 /* Basic Algorithm
392 ** Should only get here on fully working LBA rev.
393 ** This is how simple the code should have been.
394 */
395 LBA_CFG_ADDR_SETUP(d, tok | pos);
396 switch(size) {
397 case 1: *data = READ_REG8 (data_reg + (pos & 3)); break;
398 case 2: *data = READ_REG16(data_reg + (pos & 2)); break;
399 case 4: *data = READ_REG32(data_reg); break;
400 }
401 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos, *data);
402 return 0;
403}
404
405
406static void
407lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size)
408{
409 int error = 0;
410 u32 arb_mask = 0;
411 u32 error_config = 0;
412 u32 status_control = 0;
413 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
414
415 LBA_CFG_SETUP(d, tok);
416 LBA_CFG_ADDR_SETUP(d, tok | reg);
417 switch (size) {
418 case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break;
419 case 2: WRITE_REG16(data, data_reg + (reg & 2)); break;
420 case 4: WRITE_REG32(data, data_reg); break;
421 }
422 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
423 LBA_CFG_RESTORE(d, d->hba.base_addr);
424}
425
426
427/*
428 * LBA 4.0 config write code implements non-postable semantics
429 * by doing a read of CONFIG ADDR after the write.
430 */
431
432static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
433{
434 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
435 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
436 u32 tok = LBA_CFG_TOK(local_bus,devfn);
437
438 if ((pos > 255) || (devfn > 255))
439 return -EINVAL;
440
441 if (!LBA_SKIP_PROBE(d)) {
442 /* Original Workaround */
443 lba_wr_cfg(d, tok, pos, (u32) data, size);
444 DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __FUNCTION__, tok, pos,data);
445 return 0;
446 }
447
448 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) {
449 DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __FUNCTION__, tok, pos,data);
450 return 1; /* New Workaround */
451 }
452
453 DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __FUNCTION__, tok, pos, data);
454
455 /* Basic Algorithm */
456 LBA_CFG_ADDR_SETUP(d, tok | pos);
457 switch(size) {
458 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
459 break;
460 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
461 break;
462 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
463 break;
464 }
465 /* flush posted write */
466 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
467 return 0;
468}
469
470
471static struct pci_ops elroy_cfg_ops = {
472 .read = elroy_cfg_read,
473 .write = elroy_cfg_write,
474};
475
476/*
477 * The mercury_cfg_ops are slightly misnamed; they're also used for Elroy
478 * TR4.0 as no additional bugs were found in this areea between Elroy and
479 * Mercury
480 */
481
482static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
483{
484 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
485 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
486 u32 tok = LBA_CFG_TOK(local_bus, devfn);
487 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
488
489 if ((pos > 255) || (devfn > 255))
490 return -EINVAL;
491
492 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
493 switch(size) {
494 case 1:
495 *data = READ_REG8(data_reg + (pos & 3));
496 break;
497 case 2:
498 *data = READ_REG16(data_reg + (pos & 2));
499 break;
500 case 4:
501 *data = READ_REG32(data_reg); break;
502 break;
503 }
504
505 DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data);
506 return 0;
507}
508
509/*
510 * LBA 4.0 config write code implements non-postable semantics
511 * by doing a read of CONFIG ADDR after the write.
512 */
513
514static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
515{
516 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
517 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
518 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
519 u32 tok = LBA_CFG_TOK(local_bus,devfn);
520
521 if ((pos > 255) || (devfn > 255))
522 return -EINVAL;
523
524 DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __FUNCTION__, tok, pos, data);
525
526 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
527 switch(size) {
528 case 1:
529 WRITE_REG8 (data, data_reg + (pos & 3));
530 break;
531 case 2:
532 WRITE_REG16(data, data_reg + (pos & 2));
533 break;
534 case 4:
535 WRITE_REG32(data, data_reg);
536 break;
537 }
538
539 /* flush posted write */
540 lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
541 return 0;
542}
543
544static struct pci_ops mercury_cfg_ops = {
545 .read = mercury_cfg_read,
546 .write = mercury_cfg_write,
547};
548
549
550static void
551lba_bios_init(void)
552{
553 DBG(MODULE_NAME ": lba_bios_init\n");
554}
555
556
557#ifdef CONFIG_64BIT
558
559/*
560** Determine if a device is already configured.
561** If so, reserve it resources.
562**
563** Read PCI cfg command register and see if I/O or MMIO is enabled.
564** PAT has to enable the devices it's using.
565**
566** Note: resources are fixed up before we try to claim them.
567*/
568static void
569lba_claim_dev_resources(struct pci_dev *dev)
570{
571 u16 cmd;
572 int i, srch_flags;
573
574 (void) pci_read_config_word(dev, PCI_COMMAND, &cmd);
575
576 srch_flags = (cmd & PCI_COMMAND_IO) ? IORESOURCE_IO : 0;
577 if (cmd & PCI_COMMAND_MEMORY)
578 srch_flags |= IORESOURCE_MEM;
579
580 if (!srch_flags)
581 return;
582
583 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
584 if (dev->resource[i].flags & srch_flags) {
585 pci_claim_resource(dev, i);
586 DBG(" claimed %s %d [%lx,%lx]/%lx\n",
587 pci_name(dev), i,
588 dev->resource[i].start,
589 dev->resource[i].end,
590 dev->resource[i].flags
591 );
592 }
593 }
594}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700595
596
597/*
Grant Grundler6ca45a22006-01-10 20:47:56 -0500598 * truncate_pat_collision: Deal with overlaps or outright collisions
599 * between PAT PDC reported ranges.
600 *
601 * Broken PA8800 firmware will report lmmio range that
602 * overlaps with CPU HPA. Just truncate the lmmio range.
603 *
604 * BEWARE: conflicts with this lmmio range may be an
605 * elmmio range which is pointing down another rope.
606 *
607 * FIXME: only deals with one collision per range...theoretically we
608 * could have several. Supporting more than one collision will get messy.
609 */
610static unsigned long
611truncate_pat_collision(struct resource *root, struct resource *new)
612{
613 unsigned long start = new->start;
614 unsigned long end = new->end;
615 struct resource *tmp = root->child;
616
617 if (end <= start || start < root->start || !tmp)
618 return 0;
619
620 /* find first overlap */
621 while (tmp && tmp->end < start)
622 tmp = tmp->sibling;
623
624 /* no entries overlap */
625 if (!tmp) return 0;
626
627 /* found one that starts behind the new one
628 ** Don't need to do anything.
629 */
630 if (tmp->start >= end) return 0;
631
632 if (tmp->start <= start) {
633 /* "front" of new one overlaps */
634 new->start = tmp->end + 1;
635
636 if (tmp->end >= end) {
637 /* AACCKK! totally overlaps! drop this range. */
638 return 1;
639 }
640 }
641
642 if (tmp->end < end ) {
643 /* "end" of new one overlaps */
644 new->end = tmp->start - 1;
645 }
646
647 printk(KERN_WARNING "LBA: Truncating lmmio_space [%lx/%lx] "
648 "to [%lx,%lx]\n",
649 start, end,
Matthew Wilcox645d11d2006-12-24 19:28:42 -0700650 (long)new->start, (long)new->end );
Grant Grundler6ca45a22006-01-10 20:47:56 -0500651
652 return 0; /* truncation successful */
653}
654
655#else
656#define lba_claim_dev_resources(dev) do { } while (0)
657#define truncate_pat_collision(r,n) (0)
658#endif
659
660/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661** The algorithm is generic code.
662** But it needs to access local data structures to get the IRQ base.
663** Could make this a "pci_fixup_irq(bus, region)" but not sure
664** it's worth it.
665**
666** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
667** Resources aren't allocated until recursive buswalk below HBA is completed.
668*/
669static void
670lba_fixup_bus(struct pci_bus *bus)
671{
672 struct list_head *ln;
673#ifdef FBB_SUPPORT
674 u16 status;
675#endif
676 struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge));
677 int lba_portbase = HBA_PORT_BASE(ldev->hba.hba_num);
678
679 DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n",
680 bus, bus->secondary, bus->bridge->platform_data);
681
682 /*
683 ** Properly Setup MMIO resources for this bus.
684 ** pci_alloc_primary_bus() mangles this.
685 */
686 if (bus->self) {
687 /* PCI-PCI Bridge */
688 pci_read_bridge_bases(bus);
689 } else {
690 /* Host-PCI Bridge */
691 int err, i;
692
693 DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
694 ldev->hba.io_space.name,
695 ldev->hba.io_space.start, ldev->hba.io_space.end,
696 ldev->hba.io_space.flags);
697 DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
698 ldev->hba.lmmio_space.name,
699 ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end,
700 ldev->hba.lmmio_space.flags);
701
702 err = request_resource(&ioport_resource, &(ldev->hba.io_space));
703 if (err < 0) {
704 lba_dump_res(&ioport_resource, 2);
705 BUG();
706 }
Grant Grundler6ca45a22006-01-10 20:47:56 -0500707 /* advertize Host bridge resources to PCI bus */
708 bus->resource[0] = &(ldev->hba.io_space);
709 i = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710
711 if (ldev->hba.elmmio_space.start) {
712 err = request_resource(&iomem_resource,
713 &(ldev->hba.elmmio_space));
714 if (err < 0) {
715
716 printk("FAILED: lba_fixup_bus() request for "
717 "elmmio_space [%lx/%lx]\n",
Matthew Wilcox645d11d2006-12-24 19:28:42 -0700718 (long)ldev->hba.elmmio_space.start,
719 (long)ldev->hba.elmmio_space.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720
721 /* lba_dump_res(&iomem_resource, 2); */
722 /* BUG(); */
Grant Grundler6ca45a22006-01-10 20:47:56 -0500723 } else
724 bus->resource[i++] = &(ldev->hba.elmmio_space);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700725 }
726
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727
Grant Grundler6ca45a22006-01-10 20:47:56 -0500728 /* Overlaps with elmmio can (and should) fail here.
729 * We will prune (or ignore) the distributed range.
730 *
731 * FIXME: SBA code should register all elmmio ranges first.
732 * that would take care of elmmio ranges routed
733 * to a different rope (already discovered) from
734 * getting registered *after* LBA code has already
735 * registered it's distributed lmmio range.
736 */
737 if (truncate_pat_collision(&iomem_resource,
738 &(ldev->hba.lmmio_space))) {
739
740 printk(KERN_WARNING "LBA: lmmio_space [%lx/%lx] duplicate!\n",
Matthew Wilcox645d11d2006-12-24 19:28:42 -0700741 (long)ldev->hba.lmmio_space.start,
742 (long)ldev->hba.lmmio_space.end);
Grant Grundler6ca45a22006-01-10 20:47:56 -0500743 } else {
744 err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space));
745 if (err < 0) {
746 printk(KERN_ERR "FAILED: lba_fixup_bus() request for "
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747 "lmmio_space [%lx/%lx]\n",
Matthew Wilcox645d11d2006-12-24 19:28:42 -0700748 (long)ldev->hba.lmmio_space.start,
749 (long)ldev->hba.lmmio_space.end);
Grant Grundler6ca45a22006-01-10 20:47:56 -0500750 } else
751 bus->resource[i++] = &(ldev->hba.lmmio_space);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752 }
753
754#ifdef CONFIG_64BIT
755 /* GMMIO is distributed range. Every LBA/Rope gets part it. */
756 if (ldev->hba.gmmio_space.flags) {
757 err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space));
758 if (err < 0) {
759 printk("FAILED: lba_fixup_bus() request for "
760 "gmmio_space [%lx/%lx]\n",
Matthew Wilcox645d11d2006-12-24 19:28:42 -0700761 (long)ldev->hba.gmmio_space.start,
762 (long)ldev->hba.gmmio_space.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700763 lba_dump_res(&iomem_resource, 2);
764 BUG();
765 }
Grant Grundler6ca45a22006-01-10 20:47:56 -0500766 bus->resource[i++] = &(ldev->hba.gmmio_space);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700767 }
768#endif
769
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770 }
771
772 list_for_each(ln, &bus->devices) {
773 int i;
774 struct pci_dev *dev = pci_dev_b(ln);
775
776 DBG("lba_fixup_bus() %s\n", pci_name(dev));
777
778 /* Virtualize Device/Bridge Resources. */
779 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
780 struct resource *res = &dev->resource[i];
781
782 /* If resource not allocated - skip it */
783 if (!res->start)
784 continue;
785
786 if (res->flags & IORESOURCE_IO) {
787 DBG("lba_fixup_bus() I/O Ports [%lx/%lx] -> ",
788 res->start, res->end);
789 res->start |= lba_portbase;
790 res->end |= lba_portbase;
791 DBG("[%lx/%lx]\n", res->start, res->end);
792 } else if (res->flags & IORESOURCE_MEM) {
793 /*
794 ** Convert PCI (IO_VIEW) addresses to
795 ** processor (PA_VIEW) addresses
796 */
797 DBG("lba_fixup_bus() MMIO [%lx/%lx] -> ",
798 res->start, res->end);
799 res->start = PCI_HOST_ADDR(HBA_DATA(ldev), res->start);
800 res->end = PCI_HOST_ADDR(HBA_DATA(ldev), res->end);
801 DBG("[%lx/%lx]\n", res->start, res->end);
802 } else {
803 DBG("lba_fixup_bus() WTF? 0x%lx [%lx/%lx] XXX",
804 res->flags, res->start, res->end);
805 }
806 }
807
808#ifdef FBB_SUPPORT
809 /*
810 ** If one device does not support FBB transfers,
811 ** No one on the bus can be allowed to use them.
812 */
813 (void) pci_read_config_word(dev, PCI_STATUS, &status);
814 bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK);
815#endif
816
817 if (is_pdc_pat()) {
818 /* Claim resources for PDC's devices */
819 lba_claim_dev_resources(dev);
820 }
821
822 /*
823 ** P2PB's have no IRQs. ignore them.
824 */
825 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
826 continue;
827
828 /* Adjust INTERRUPT_LINE for this dev */
829 iosapic_fixup_irq(ldev->iosapic_obj, dev);
830 }
831
832#ifdef FBB_SUPPORT
833/* FIXME/REVISIT - finish figuring out to set FBB on both
834** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL.
835** Can't fixup here anyway....garr...
836*/
837 if (fbb_enable) {
838 if (bus->self) {
839 u8 control;
840 /* enable on PPB */
841 (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control);
842 (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK);
843
844 } else {
845 /* enable on LBA */
846 }
847 fbb_enable = PCI_COMMAND_FAST_BACK;
848 }
849
850 /* Lastly enable FBB/PERR/SERR on all devices too */
851 list_for_each(ln, &bus->devices) {
852 (void) pci_read_config_word(dev, PCI_COMMAND, &status);
853 status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable;
854 (void) pci_write_config_word(dev, PCI_COMMAND, status);
855 }
856#endif
857}
858
859
860struct pci_bios_ops lba_bios_ops = {
861 .init = lba_bios_init,
862 .fixup_bus = lba_fixup_bus,
863};
864
865
866
867
868/*******************************************************
869**
870** LBA Sprockets "I/O Port" Space Accessor Functions
871**
872** This set of accessor functions is intended for use with
873** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
874**
875** Many PCI devices don't require use of I/O port space (eg Tulip,
876** NCR720) since they export the same registers to both MMIO and
877** I/O port space. In general I/O port space is slower than
878** MMIO since drivers are designed so PIO writes can be posted.
879**
880********************************************************/
881
882#define LBA_PORT_IN(size, mask) \
883static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
884{ \
885 u##size t; \
886 t = READ_REG##size(astro_iop_base + addr); \
887 DBG_PORT(" 0x%x\n", t); \
888 return (t); \
889}
890
891LBA_PORT_IN( 8, 3)
892LBA_PORT_IN(16, 2)
893LBA_PORT_IN(32, 0)
894
895
896
897/*
898** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR
899**
900** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
901** guarantee non-postable completion semantics - not avoid X4107.
902** The READ_U32 only guarantees the write data gets to elroy but
903** out to the PCI bus. We can't read stuff from I/O port space
904** since we don't know what has side-effects. Attempting to read
905** from configuration space would be suicidal given the number of
906** bugs in that elroy functionality.
907**
908** Description:
909** DMA read results can improperly pass PIO writes (X4107). The
910** result of this bug is that if a processor modifies a location in
911** memory after having issued PIO writes, the PIO writes are not
912** guaranteed to be completed before a PCI device is allowed to see
913** the modified data in a DMA read.
914**
915** Note that IKE bug X3719 in TR1 IKEs will result in the same
916** symptom.
917**
918** Workaround:
919** The workaround for this bug is to always follow a PIO write with
920** a PIO read to the same bus before starting DMA on that PCI bus.
921**
922*/
923#define LBA_PORT_OUT(size, mask) \
924static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
925{ \
926 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, d, addr, val); \
927 WRITE_REG##size(val, astro_iop_base + addr); \
928 if (LBA_DEV(d)->hw_rev < 3) \
929 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
930}
931
932LBA_PORT_OUT( 8, 3)
933LBA_PORT_OUT(16, 2)
934LBA_PORT_OUT(32, 0)
935
936
937static struct pci_port_ops lba_astro_port_ops = {
938 .inb = lba_astro_in8,
939 .inw = lba_astro_in16,
940 .inl = lba_astro_in32,
941 .outb = lba_astro_out8,
942 .outw = lba_astro_out16,
943 .outl = lba_astro_out32
944};
945
946
947#ifdef CONFIG_64BIT
948#define PIOP_TO_GMMIO(lba, addr) \
949 ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
950
951/*******************************************************
952**
953** LBA PAT "I/O Port" Space Accessor Functions
954**
955** This set of accessor functions is intended for use with
956** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
957**
958** This uses the PIOP space located in the first 64MB of GMMIO.
959** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
960** bits 1:0 stay the same. bits 15:2 become 25:12.
961** Then add the base and we can generate an I/O Port cycle.
962********************************************************/
963#undef LBA_PORT_IN
964#define LBA_PORT_IN(size, mask) \
965static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
966{ \
967 u##size t; \
968 DBG_PORT("%s(0x%p, 0x%x) ->", __FUNCTION__, l, addr); \
969 t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
970 DBG_PORT(" 0x%x\n", t); \
971 return (t); \
972}
973
974LBA_PORT_IN( 8, 3)
975LBA_PORT_IN(16, 2)
976LBA_PORT_IN(32, 0)
977
978
979#undef LBA_PORT_OUT
980#define LBA_PORT_OUT(size, mask) \
981static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
982{ \
Matthew Wilcoxc2c47982006-10-26 10:06:07 -0600983 void __iomem *where = PIOP_TO_GMMIO(LBA_DEV(l), addr); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700984 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, l, addr, val); \
985 WRITE_REG##size(val, where); \
986 /* flush the I/O down to the elroy at least */ \
987 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
988}
989
990LBA_PORT_OUT( 8, 3)
991LBA_PORT_OUT(16, 2)
992LBA_PORT_OUT(32, 0)
993
994
995static struct pci_port_ops lba_pat_port_ops = {
996 .inb = lba_pat_in8,
997 .inw = lba_pat_in16,
998 .inl = lba_pat_in32,
999 .outb = lba_pat_out8,
1000 .outw = lba_pat_out16,
1001 .outl = lba_pat_out32
1002};
1003
1004
1005
1006/*
1007** make range information from PDC available to PCI subsystem.
1008** We make the PDC call here in order to get the PCI bus range
1009** numbers. The rest will get forwarded in pcibios_fixup_bus().
1010** We don't have a struct pci_bus assigned to us yet.
1011*/
1012static void
1013lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1014{
1015 unsigned long bytecnt;
1016 pdc_pat_cell_mod_maddr_block_t pa_pdc_cell; /* PA_VIEW */
1017 pdc_pat_cell_mod_maddr_block_t io_pdc_cell; /* IO_VIEW */
1018 long io_count;
1019 long status; /* PDC return status */
1020 long pa_count;
1021 int i;
1022
1023 /* return cell module (IO view) */
1024 status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1025 PA_VIEW, & pa_pdc_cell);
1026 pa_count = pa_pdc_cell.mod[1];
1027
1028 status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1029 IO_VIEW, &io_pdc_cell);
1030 io_count = io_pdc_cell.mod[1];
1031
1032 /* We've already done this once for device discovery...*/
1033 if (status != PDC_OK) {
1034 panic("pdc_pat_cell_module() call failed for LBA!\n");
1035 }
1036
1037 if (PAT_GET_ENTITY(pa_pdc_cell.mod_info) != PAT_ENTITY_LBA) {
1038 panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
1039 }
1040
1041 /*
1042 ** Inspect the resources PAT tells us about
1043 */
1044 for (i = 0; i < pa_count; i++) {
1045 struct {
1046 unsigned long type;
1047 unsigned long start;
1048 unsigned long end; /* aka finish */
1049 } *p, *io;
1050 struct resource *r;
1051
1052 p = (void *) &(pa_pdc_cell.mod[2+i*3]);
1053 io = (void *) &(io_pdc_cell.mod[2+i*3]);
1054
1055 /* Convert the PAT range data to PCI "struct resource" */
1056 switch(p->type & 0xff) {
1057 case PAT_PBNUM:
1058 lba_dev->hba.bus_num.start = p->start;
1059 lba_dev->hba.bus_num.end = p->end;
1060 break;
1061
1062 case PAT_LMMIO:
1063 /* used to fix up pre-initialized MEM BARs */
1064 if (!lba_dev->hba.lmmio_space.start) {
1065 sprintf(lba_dev->hba.lmmio_name,
Matthew Wilcox645d11d2006-12-24 19:28:42 -07001066 "PCI%02x LMMIO",
1067 (int)lba_dev->hba.bus_num.start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001068 lba_dev->hba.lmmio_space_offset = p->start -
1069 io->start;
1070 r = &lba_dev->hba.lmmio_space;
1071 r->name = lba_dev->hba.lmmio_name;
1072 } else if (!lba_dev->hba.elmmio_space.start) {
1073 sprintf(lba_dev->hba.elmmio_name,
Matthew Wilcox645d11d2006-12-24 19:28:42 -07001074 "PCI%02x ELMMIO",
1075 (int)lba_dev->hba.bus_num.start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001076 r = &lba_dev->hba.elmmio_space;
1077 r->name = lba_dev->hba.elmmio_name;
1078 } else {
1079 printk(KERN_WARNING MODULE_NAME
1080 " only supports 2 LMMIO resources!\n");
1081 break;
1082 }
1083
1084 r->start = p->start;
1085 r->end = p->end;
1086 r->flags = IORESOURCE_MEM;
1087 r->parent = r->sibling = r->child = NULL;
1088 break;
1089
1090 case PAT_GMMIO:
1091 /* MMIO space > 4GB phys addr; for 64-bit BAR */
Matthew Wilcox645d11d2006-12-24 19:28:42 -07001092 sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO",
1093 (int)lba_dev->hba.bus_num.start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001094 r = &lba_dev->hba.gmmio_space;
1095 r->name = lba_dev->hba.gmmio_name;
1096 r->start = p->start;
1097 r->end = p->end;
1098 r->flags = IORESOURCE_MEM;
1099 r->parent = r->sibling = r->child = NULL;
1100 break;
1101
1102 case PAT_NPIOP:
1103 printk(KERN_WARNING MODULE_NAME
1104 " range[%d] : ignoring NPIOP (0x%lx)\n",
1105 i, p->start);
1106 break;
1107
1108 case PAT_PIOP:
1109 /*
1110 ** Postable I/O port space is per PCI host adapter.
1111 ** base of 64MB PIOP region
1112 */
Helge Deller5076c152006-03-27 12:52:15 -07001113 lba_dev->iop_base = ioremap_nocache(p->start, 64 * 1024 * 1024);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001114
Matthew Wilcox645d11d2006-12-24 19:28:42 -07001115 sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1116 (int)lba_dev->hba.bus_num.start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001117 r = &lba_dev->hba.io_space;
1118 r->name = lba_dev->hba.io_name;
1119 r->start = HBA_PORT_BASE(lba_dev->hba.hba_num);
1120 r->end = r->start + HBA_PORT_SPACE_SIZE - 1;
1121 r->flags = IORESOURCE_IO;
1122 r->parent = r->sibling = r->child = NULL;
1123 break;
1124
1125 default:
1126 printk(KERN_WARNING MODULE_NAME
1127 " range[%d] : unknown pat range type (0x%lx)\n",
1128 i, p->type & 0xff);
1129 break;
1130 }
1131 }
1132}
1133#else
1134/* keep compiler from complaining about missing declarations */
1135#define lba_pat_port_ops lba_astro_port_ops
1136#define lba_pat_resources(pa_dev, lba_dev)
1137#endif /* CONFIG_64BIT */
1138
1139
1140extern void sba_distributed_lmmio(struct parisc_device *, struct resource *);
1141extern void sba_directed_lmmio(struct parisc_device *, struct resource *);
1142
1143
1144static void
1145lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1146{
1147 struct resource *r;
1148 int lba_num;
1149
1150 lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
1151
1152 /*
1153 ** With "legacy" firmware, the lowest byte of FW_SCRATCH
1154 ** represents bus->secondary and the second byte represents
1155 ** bus->subsidiary (i.e. highest PPB programmed by firmware).
1156 ** PCI bus walk *should* end up with the same result.
1157 ** FIXME: But we don't have sanity checks in PCI or LBA.
1158 */
1159 lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH);
1160 r = &(lba_dev->hba.bus_num);
1161 r->name = "LBA PCI Busses";
1162 r->start = lba_num & 0xff;
1163 r->end = (lba_num>>8) & 0xff;
1164
1165 /* Set up local PCI Bus resources - we don't need them for
1166 ** Legacy boxes but it's nice to see in /proc/iomem.
1167 */
1168 r = &(lba_dev->hba.lmmio_space);
Matthew Wilcox645d11d2006-12-24 19:28:42 -07001169 sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO",
1170 (int)lba_dev->hba.bus_num.start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171 r->name = lba_dev->hba.lmmio_name;
1172
1173#if 1
1174 /* We want the CPU -> IO routing of addresses.
1175 * The SBA BASE/MASK registers control CPU -> IO routing.
1176 * Ask SBA what is routed to this rope/LBA.
1177 */
1178 sba_distributed_lmmio(pa_dev, r);
1179#else
1180 /*
1181 * The LBA BASE/MASK registers control IO -> System routing.
1182 *
1183 * The following code works but doesn't get us what we want.
1184 * Well, only because firmware (v5.0) on C3000 doesn't program
1185 * the LBA BASE/MASE registers to be the exact inverse of
1186 * the corresponding SBA registers. Other Astro/Pluto
1187 * based platform firmware may do it right.
1188 *
1189 * Should someone want to mess with MSI, they may need to
1190 * reprogram LBA BASE/MASK registers. Thus preserve the code
1191 * below until MSI is known to work on C3000/A500/N4000/RP3440.
1192 *
1193 * Using the code below, /proc/iomem shows:
1194 * ...
1195 * f0000000-f0ffffff : PCI00 LMMIO
1196 * f05d0000-f05d0000 : lcd_data
1197 * f05d0008-f05d0008 : lcd_cmd
1198 * f1000000-f1ffffff : PCI01 LMMIO
1199 * f4000000-f4ffffff : PCI02 LMMIO
1200 * f4000000-f4001fff : sym53c8xx
1201 * f4002000-f4003fff : sym53c8xx
1202 * f4004000-f40043ff : sym53c8xx
1203 * f4005000-f40053ff : sym53c8xx
1204 * f4007000-f4007fff : ohci_hcd
1205 * f4008000-f40083ff : tulip
1206 * f6000000-f6ffffff : PCI03 LMMIO
1207 * f8000000-fbffffff : PCI00 ELMMIO
1208 * fa100000-fa4fffff : stifb mmio
1209 * fb000000-fb1fffff : stifb fb
1210 *
1211 * But everything listed under PCI02 actually lives under PCI00.
1212 * This is clearly wrong.
1213 *
1214 * Asking SBA how things are routed tells the correct story:
1215 * LMMIO_BASE/MASK/ROUTE f4000001 fc000000 00000000
1216 * DIR0_BASE/MASK/ROUTE fa000001 fe000000 00000006
1217 * DIR1_BASE/MASK/ROUTE f9000001 ff000000 00000004
1218 * DIR2_BASE/MASK/ROUTE f0000000 fc000000 00000000
1219 * DIR3_BASE/MASK/ROUTE f0000000 fc000000 00000000
1220 *
1221 * Which looks like this in /proc/iomem:
1222 * f4000000-f47fffff : PCI00 LMMIO
1223 * f4000000-f4001fff : sym53c8xx
1224 * ...[deteled core devices - same as above]...
1225 * f4008000-f40083ff : tulip
1226 * f4800000-f4ffffff : PCI01 LMMIO
1227 * f6000000-f67fffff : PCI02 LMMIO
1228 * f7000000-f77fffff : PCI03 LMMIO
1229 * f9000000-f9ffffff : PCI02 ELMMIO
1230 * fa000000-fbffffff : PCI03 ELMMIO
1231 * fa100000-fa4fffff : stifb mmio
1232 * fb000000-fb1fffff : stifb fb
1233 *
1234 * ie all Built-in core are under now correctly under PCI00.
1235 * The "PCI02 ELMMIO" directed range is for:
1236 * +-[02]---03.0 3Dfx Interactive, Inc. Voodoo 2
1237 *
1238 * All is well now.
1239 */
1240 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE);
1241 if (r->start & 1) {
1242 unsigned long rsize;
1243
1244 r->flags = IORESOURCE_MEM;
1245 /* mmio_mask also clears Enable bit */
1246 r->start &= mmio_mask;
1247 r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start);
1248 rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK);
1249
1250 /*
1251 ** Each rope only gets part of the distributed range.
1252 ** Adjust "window" for this rope.
1253 */
1254 rsize /= ROPES_PER_IOC;
Matthew Wilcox53f01bb2005-10-21 22:36:40 -04001255 r->start += (rsize + 1) * LBA_NUM(pa_dev->hpa.start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001256 r->end = r->start + rsize;
1257 } else {
1258 r->end = r->start = 0; /* Not enabled. */
1259 }
1260#endif
1261
1262 /*
1263 ** "Directed" ranges are used when the "distributed range" isn't
1264 ** sufficient for all devices below a given LBA. Typically devices
1265 ** like graphics cards or X25 may need a directed range when the
1266 ** bus has multiple slots (ie multiple devices) or the device
1267 ** needs more than the typical 4 or 8MB a distributed range offers.
1268 **
1269 ** The main reason for ignoring it now frigging complications.
1270 ** Directed ranges may overlap (and have precedence) over
1271 ** distributed ranges. Or a distributed range assigned to a unused
1272 ** rope may be used by a directed range on a different rope.
1273 ** Support for graphics devices may require fixing this
1274 ** since they may be assigned a directed range which overlaps
1275 ** an existing (but unused portion of) distributed range.
1276 */
1277 r = &(lba_dev->hba.elmmio_space);
Matthew Wilcox645d11d2006-12-24 19:28:42 -07001278 sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO",
1279 (int)lba_dev->hba.bus_num.start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001280 r->name = lba_dev->hba.elmmio_name;
1281
1282#if 1
1283 /* See comment which precedes call to sba_directed_lmmio() */
1284 sba_directed_lmmio(pa_dev, r);
1285#else
1286 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE);
1287
1288 if (r->start & 1) {
1289 unsigned long rsize;
1290 r->flags = IORESOURCE_MEM;
1291 /* mmio_mask also clears Enable bit */
1292 r->start &= mmio_mask;
1293 r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start);
1294 rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK);
1295 r->end = r->start + ~rsize;
1296 }
1297#endif
1298
1299 r = &(lba_dev->hba.io_space);
Matthew Wilcox645d11d2006-12-24 19:28:42 -07001300 sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1301 (int)lba_dev->hba.bus_num.start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001302 r->name = lba_dev->hba.io_name;
1303 r->flags = IORESOURCE_IO;
1304 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L;
1305 r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
1306
1307 /* Virtualize the I/O Port space ranges */
1308 lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num);
1309 r->start |= lba_num;
1310 r->end |= lba_num;
1311}
1312
1313
1314/**************************************************************************
1315**
1316** LBA initialization code (HW and SW)
1317**
1318** o identify LBA chip itself
1319** o initialize LBA chip modes (HardFail)
1320** o FIXME: initialize DMA hints for reasonable defaults
1321** o enable configuration functions
1322** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked)
1323**
1324**************************************************************************/
1325
1326static int __init
1327lba_hw_init(struct lba_device *d)
1328{
1329 u32 stat;
1330 u32 bus_reset; /* PDC_PAT_BUG */
1331
1332#if 0
1333 printk(KERN_DEBUG "LBA %lx STAT_CTL %Lx ERROR_CFG %Lx STATUS %Lx DMA_CTL %Lx\n",
1334 d->hba.base_addr,
1335 READ_REG64(d->hba.base_addr + LBA_STAT_CTL),
1336 READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG),
1337 READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS),
1338 READ_REG64(d->hba.base_addr + LBA_DMA_CTL) );
1339 printk(KERN_DEBUG " ARB mask %Lx pri %Lx mode %Lx mtlt %Lx\n",
1340 READ_REG64(d->hba.base_addr + LBA_ARB_MASK),
1341 READ_REG64(d->hba.base_addr + LBA_ARB_PRI),
1342 READ_REG64(d->hba.base_addr + LBA_ARB_MODE),
1343 READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) );
1344 printk(KERN_DEBUG " HINT cfg 0x%Lx\n",
1345 READ_REG64(d->hba.base_addr + LBA_HINT_CFG));
1346 printk(KERN_DEBUG " HINT reg ");
1347 { int i;
1348 for (i=LBA_HINT_BASE; i< (14*8 + LBA_HINT_BASE); i+=8)
1349 printk(" %Lx", READ_REG64(d->hba.base_addr + i));
1350 }
1351 printk("\n");
1352#endif /* DEBUG_LBA_PAT */
1353
1354#ifdef CONFIG_64BIT
1355/*
1356 * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support
1357 * Only N-Class and up can really make use of Get slot status.
1358 * maybe L-class too but I've never played with it there.
1359 */
1360#endif
1361
1362 /* PDC_PAT_BUG: exhibited in rev 40.48 on L2000 */
1363 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
1364 if (bus_reset) {
1365 printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n");
1366 }
1367
1368 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
1369 if (stat & LBA_SMART_MODE) {
1370 printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n");
1371 stat &= ~LBA_SMART_MODE;
1372 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);
1373 }
1374
1375 /* Set HF mode as the default (vs. -1 mode). */
1376 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
1377 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
1378
1379 /*
1380 ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal
1381 ** if it's not already set. If we just cleared the PCI Bus Reset
1382 ** signal, wait a bit for the PCI devices to recover and setup.
1383 */
1384 if (bus_reset)
1385 mdelay(pci_post_reset_delay);
1386
1387 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
1388 /*
1389 ** PDC_PAT_BUG: PDC rev 40.48 on L2000.
1390 ** B2000/C3600/J6000 also have this problem?
1391 **
1392 ** Elroys with hot pluggable slots don't get configured
1393 ** correctly if the slot is empty. ARB_MASK is set to 0
1394 ** and we can't master transactions on the bus if it's
1395 ** not at least one. 0x3 enables elroy and first slot.
1396 */
1397 printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n");
1398 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);
1399 }
1400
1401 /*
1402 ** FIXME: Hint registers are programmed with default hint
1403 ** values by firmware. Hints should be sane even if we
1404 ** can't reprogram them the way drivers want.
1405 */
1406 return 0;
1407}
1408
Matthew Wilcox353dfe12006-11-18 10:11:03 -07001409/*
1410 * Unfortunately, when firmware numbers busses, it doesn't take into account
1411 * Cardbus bridges. So we have to renumber the busses to suit ourselves.
1412 * Elroy/Mercury don't actually know what bus number they're attached to;
1413 * we use bus 0 to indicate the directly attached bus and any other bus
1414 * number will be taken care of by the PCI-PCI bridge.
1415 */
1416static unsigned int lba_next_bus = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001417
1418/*
Matthew Wilcox353dfe12006-11-18 10:11:03 -07001419 * Determine if lba should claim this chip (return 0) or not (return 1).
1420 * If so, initialize the chip and tell other partners in crime they
1421 * have work to do.
1422 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001423static int __init
1424lba_driver_probe(struct parisc_device *dev)
1425{
1426 struct lba_device *lba_dev;
1427 struct pci_bus *lba_bus;
1428 struct pci_ops *cfg_ops;
1429 u32 func_class;
1430 void *tmp_obj;
1431 char *version;
Helge Deller5076c152006-03-27 12:52:15 -07001432 void __iomem *addr = ioremap_nocache(dev->hpa.start, 4096);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001433
1434 /* Read HW Rev First */
1435 func_class = READ_REG32(addr + LBA_FCLASS);
1436
1437 if (IS_ELROY(dev)) {
1438 func_class &= 0xf;
1439 switch (func_class) {
1440 case 0: version = "TR1.0"; break;
1441 case 1: version = "TR2.0"; break;
1442 case 2: version = "TR2.1"; break;
1443 case 3: version = "TR2.2"; break;
1444 case 4: version = "TR3.0"; break;
1445 case 5: version = "TR4.0"; break;
1446 default: version = "TR4+";
1447 }
1448
Kyle McMartinba9877b2006-08-24 21:28:58 -04001449 printk(KERN_INFO "Elroy version %s (0x%x) found at 0x%lx\n",
Matthew Wilcox645d11d2006-12-24 19:28:42 -07001450 version, func_class & 0xf, (long)dev->hpa.start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001451
1452 if (func_class < 2) {
1453 printk(KERN_WARNING "Can't support LBA older than "
1454 "TR2.1 - continuing under adversity.\n");
1455 }
1456
1457#if 0
1458/* Elroy TR4.0 should work with simple algorithm.
1459 But it doesn't. Still missing something. *sigh*
1460*/
1461 if (func_class > 4) {
1462 cfg_ops = &mercury_cfg_ops;
1463 } else
1464#endif
1465 {
1466 cfg_ops = &elroy_cfg_ops;
1467 }
1468
1469 } else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) {
Kyle McMartinba9877b2006-08-24 21:28:58 -04001470 int major, minor;
1471
Linus Torvalds1da177e2005-04-16 15:20:36 -07001472 func_class &= 0xff;
Kyle McMartinba9877b2006-08-24 21:28:58 -04001473 major = func_class >> 4, minor = func_class & 0xf;
1474
Linus Torvalds1da177e2005-04-16 15:20:36 -07001475 /* We could use one printk for both Elroy and Mercury,
1476 * but for the mask for func_class.
1477 */
Kyle McMartinba9877b2006-08-24 21:28:58 -04001478 printk(KERN_INFO "%s version TR%d.%d (0x%x) found at 0x%lx\n",
1479 IS_MERCURY(dev) ? "Mercury" : "Quicksilver", major,
Matthew Wilcox645d11d2006-12-24 19:28:42 -07001480 minor, func_class, (long)dev->hpa.start);
Kyle McMartinba9877b2006-08-24 21:28:58 -04001481
Linus Torvalds1da177e2005-04-16 15:20:36 -07001482 cfg_ops = &mercury_cfg_ops;
1483 } else {
Matthew Wilcox645d11d2006-12-24 19:28:42 -07001484 printk(KERN_ERR "Unknown LBA found at 0x%lx\n",
1485 (long)dev->hpa.start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001486 return -ENODEV;
1487 }
1488
Matthew Wilcox353dfe12006-11-18 10:11:03 -07001489 /* Tell I/O SAPIC driver we have a IRQ handler/region. */
Matthew Wilcox53f01bb2005-10-21 22:36:40 -04001490 tmp_obj = iosapic_register(dev->hpa.start + LBA_IOSAPIC_BASE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001491
1492 /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't
1493 ** have an IRT entry will get NULL back from iosapic code.
1494 */
1495
Helge Dellercb6fc182006-01-17 12:40:40 -07001496 lba_dev = kzalloc(sizeof(struct lba_device), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001497 if (!lba_dev) {
1498 printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n");
1499 return(1);
1500 }
1501
Linus Torvalds1da177e2005-04-16 15:20:36 -07001502
1503 /* ---------- First : initialize data we already have --------- */
1504
1505 lba_dev->hw_rev = func_class;
1506 lba_dev->hba.base_addr = addr;
1507 lba_dev->hba.dev = dev;
1508 lba_dev->iosapic_obj = tmp_obj; /* save interrupt handle */
1509 lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */
Kyle McMartinb0eecc42006-08-24 21:31:41 -04001510 parisc_set_drvdata(dev, lba_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001511
1512 /* ------------ Second : initialize common stuff ---------- */
1513 pci_bios = &lba_bios_ops;
1514 pcibios_register_hba(HBA_DATA(lba_dev));
1515 spin_lock_init(&lba_dev->lba_lock);
1516
1517 if (lba_hw_init(lba_dev))
1518 return(1);
1519
1520 /* ---------- Third : setup I/O Port and MMIO resources --------- */
1521
1522 if (is_pdc_pat()) {
1523 /* PDC PAT firmware uses PIOP region of GMMIO space. */
1524 pci_port = &lba_pat_port_ops;
1525 /* Go ask PDC PAT what resources this LBA has */
1526 lba_pat_resources(dev, lba_dev);
1527 } else {
1528 if (!astro_iop_base) {
1529 /* Sprockets PDC uses NPIOP region */
Helge Deller5076c152006-03-27 12:52:15 -07001530 astro_iop_base = ioremap_nocache(LBA_PORT_BASE, 64 * 1024);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001531 pci_port = &lba_astro_port_ops;
1532 }
1533
1534 /* Poke the chip a bit for /proc output */
1535 lba_legacy_resources(dev, lba_dev);
1536 }
1537
Matthew Wilcox353dfe12006-11-18 10:11:03 -07001538 if (lba_dev->hba.bus_num.start < lba_next_bus)
1539 lba_dev->hba.bus_num.start = lba_next_bus;
1540
Linus Torvalds1da177e2005-04-16 15:20:36 -07001541 dev->dev.platform_data = lba_dev;
1542 lba_bus = lba_dev->hba.hba_bus =
1543 pci_scan_bus_parented(&dev->dev, lba_dev->hba.bus_num.start,
1544 cfg_ops, NULL);
Matthew Wilcox353dfe12006-11-18 10:11:03 -07001545 if (lba_bus) {
1546 lba_next_bus = lba_bus->subordinate + 1;
Rajesh Shahc431ada2005-04-28 00:25:45 -07001547 pci_bus_add_devices(lba_bus);
Matthew Wilcox353dfe12006-11-18 10:11:03 -07001548 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001549
1550 /* This is in lieu of calling pci_assign_unassigned_resources() */
1551 if (is_pdc_pat()) {
1552 /* assign resources to un-initialized devices */
1553
1554 DBG_PAT("LBA pci_bus_size_bridges()\n");
1555 pci_bus_size_bridges(lba_bus);
1556
1557 DBG_PAT("LBA pci_bus_assign_resources()\n");
1558 pci_bus_assign_resources(lba_bus);
1559
1560#ifdef DEBUG_LBA_PAT
1561 DBG_PAT("\nLBA PIOP resource tree\n");
1562 lba_dump_res(&lba_dev->hba.io_space, 2);
1563 DBG_PAT("\nLBA LMMIO resource tree\n");
1564 lba_dump_res(&lba_dev->hba.lmmio_space, 2);
1565#endif
1566 }
1567 pci_enable_bridges(lba_bus);
1568
1569
1570 /*
1571 ** Once PCI register ops has walked the bus, access to config
1572 ** space is restricted. Avoids master aborts on config cycles.
1573 ** Early LBA revs go fatal on *any* master abort.
1574 */
1575 if (cfg_ops == &elroy_cfg_ops) {
1576 lba_dev->flags |= LBA_FLAG_SKIP_PROBE;
1577 }
1578
1579 /* Whew! Finally done! Tell services we got this one covered. */
1580 return 0;
1581}
1582
1583static struct parisc_device_id lba_tbl[] = {
1584 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa },
1585 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa },
1586 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa },
1587 { 0, }
1588};
1589
1590static struct parisc_driver lba_driver = {
1591 .name = MODULE_NAME,
1592 .id_table = lba_tbl,
1593 .probe = lba_driver_probe,
1594};
1595
1596/*
1597** One time initialization to let the world know the LBA was found.
1598** Must be called exactly once before pci_init().
1599*/
1600void __init lba_init(void)
1601{
1602 register_parisc_driver(&lba_driver);
1603}
1604
1605/*
1606** Initialize the IBASE/IMASK registers for LBA (Elroy).
1607** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA).
1608** sba_iommu is responsible for locking (none needed at init time).
1609*/
1610void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask)
1611{
Helge Deller5076c152006-03-27 12:52:15 -07001612 void __iomem * base_addr = ioremap_nocache(lba->hpa.start, 4096);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001613
1614 imask <<= 2; /* adjust for hints - 2 more bits */
1615
1616 /* Make sure we aren't trying to set bits that aren't writeable. */
1617 WARN_ON((ibase & 0x001fffff) != 0);
1618 WARN_ON((imask & 0x001fffff) != 0);
1619
1620 DBG("%s() ibase 0x%x imask 0x%x\n", __FUNCTION__, ibase, imask);
1621 WRITE_REG32( imask, base_addr + LBA_IMASK);
1622 WRITE_REG32( ibase, base_addr + LBA_IBASE);
1623 iounmap(base_addr);
1624}
1625