Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 1 | /* |
Joerg Roedel | bf3118c | 2009-11-20 13:39:19 +0100 | [diff] [blame] | 2 | * Copyright (C) 2007-2009 Advanced Micro Devices, Inc. |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
| 4 | * Leo Duran <leo.duran@amd.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ |
| 19 | |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 20 | #ifndef _ASM_X86_AMD_IOMMU_TYPES_H |
| 21 | #define _ASM_X86_AMD_IOMMU_TYPES_H |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 22 | |
| 23 | #include <linux/types.h> |
| 24 | #include <linux/list.h> |
| 25 | #include <linux/spinlock.h> |
| 26 | |
| 27 | /* |
Joerg Roedel | bb52777 | 2009-11-20 14:31:51 +0100 | [diff] [blame] | 28 | * Maximum number of IOMMUs supported |
| 29 | */ |
| 30 | #define MAX_IOMMUS 32 |
| 31 | |
| 32 | /* |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 33 | * some size calculation constants |
| 34 | */ |
Joerg Roedel | 83f5aac | 2008-07-11 17:14:34 +0200 | [diff] [blame] | 35 | #define DEV_TABLE_ENTRY_SIZE 32 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 36 | #define ALIAS_TABLE_ENTRY_SIZE 2 |
| 37 | #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) |
| 38 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 39 | /* Length of the MMIO region for the AMD IOMMU */ |
| 40 | #define MMIO_REGION_LENGTH 0x4000 |
| 41 | |
| 42 | /* Capability offsets used by the driver */ |
| 43 | #define MMIO_CAP_HDR_OFFSET 0x00 |
| 44 | #define MMIO_RANGE_OFFSET 0x0c |
Joerg Roedel | a80dc3e | 2008-09-11 16:51:41 +0200 | [diff] [blame] | 45 | #define MMIO_MISC_OFFSET 0x10 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 46 | |
| 47 | /* Masks, shifts and macros to parse the device range capability */ |
| 48 | #define MMIO_RANGE_LD_MASK 0xff000000 |
| 49 | #define MMIO_RANGE_FD_MASK 0x00ff0000 |
| 50 | #define MMIO_RANGE_BUS_MASK 0x0000ff00 |
| 51 | #define MMIO_RANGE_LD_SHIFT 24 |
| 52 | #define MMIO_RANGE_FD_SHIFT 16 |
| 53 | #define MMIO_RANGE_BUS_SHIFT 8 |
| 54 | #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) |
| 55 | #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) |
| 56 | #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) |
Joerg Roedel | a80dc3e | 2008-09-11 16:51:41 +0200 | [diff] [blame] | 57 | #define MMIO_MSI_NUM(x) ((x) & 0x1f) |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 58 | |
| 59 | /* Flag masks for the AMD IOMMU exclusion range */ |
| 60 | #define MMIO_EXCL_ENABLE_MASK 0x01ULL |
| 61 | #define MMIO_EXCL_ALLOW_MASK 0x02ULL |
| 62 | |
| 63 | /* Used offsets into the MMIO space */ |
| 64 | #define MMIO_DEV_TABLE_OFFSET 0x0000 |
| 65 | #define MMIO_CMD_BUF_OFFSET 0x0008 |
| 66 | #define MMIO_EVT_BUF_OFFSET 0x0010 |
| 67 | #define MMIO_CONTROL_OFFSET 0x0018 |
| 68 | #define MMIO_EXCL_BASE_OFFSET 0x0020 |
| 69 | #define MMIO_EXCL_LIMIT_OFFSET 0x0028 |
| 70 | #define MMIO_CMD_HEAD_OFFSET 0x2000 |
| 71 | #define MMIO_CMD_TAIL_OFFSET 0x2008 |
| 72 | #define MMIO_EVT_HEAD_OFFSET 0x2010 |
| 73 | #define MMIO_EVT_TAIL_OFFSET 0x2018 |
| 74 | #define MMIO_STATUS_OFFSET 0x2020 |
| 75 | |
Joerg Roedel | 519c31b | 2008-08-14 19:55:15 +0200 | [diff] [blame] | 76 | /* MMIO status bits */ |
| 77 | #define MMIO_STATUS_COM_WAIT_INT_MASK 0x04 |
| 78 | |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 79 | /* event logging constants */ |
| 80 | #define EVENT_ENTRY_SIZE 0x10 |
| 81 | #define EVENT_TYPE_SHIFT 28 |
| 82 | #define EVENT_TYPE_MASK 0xf |
| 83 | #define EVENT_TYPE_ILL_DEV 0x1 |
| 84 | #define EVENT_TYPE_IO_FAULT 0x2 |
| 85 | #define EVENT_TYPE_DEV_TAB_ERR 0x3 |
| 86 | #define EVENT_TYPE_PAGE_TAB_ERR 0x4 |
| 87 | #define EVENT_TYPE_ILL_CMD 0x5 |
| 88 | #define EVENT_TYPE_CMD_HARD_ERR 0x6 |
| 89 | #define EVENT_TYPE_IOTLB_INV_TO 0x7 |
| 90 | #define EVENT_TYPE_INV_DEV_REQ 0x8 |
| 91 | #define EVENT_DEVID_MASK 0xffff |
| 92 | #define EVENT_DEVID_SHIFT 0 |
| 93 | #define EVENT_DOMID_MASK 0xffff |
| 94 | #define EVENT_DOMID_SHIFT 0 |
| 95 | #define EVENT_FLAGS_MASK 0xfff |
| 96 | #define EVENT_FLAGS_SHIFT 0x10 |
| 97 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 98 | /* feature control bits */ |
| 99 | #define CONTROL_IOMMU_EN 0x00ULL |
| 100 | #define CONTROL_HT_TUN_EN 0x01ULL |
| 101 | #define CONTROL_EVT_LOG_EN 0x02ULL |
| 102 | #define CONTROL_EVT_INT_EN 0x03ULL |
| 103 | #define CONTROL_COMWAIT_EN 0x04ULL |
| 104 | #define CONTROL_PASSPW_EN 0x08ULL |
| 105 | #define CONTROL_RESPASSPW_EN 0x09ULL |
| 106 | #define CONTROL_COHERENT_EN 0x0aULL |
| 107 | #define CONTROL_ISOC_EN 0x0bULL |
| 108 | #define CONTROL_CMDBUF_EN 0x0cULL |
| 109 | #define CONTROL_PPFLOG_EN 0x0dULL |
| 110 | #define CONTROL_PPFINT_EN 0x0eULL |
| 111 | |
| 112 | /* command specific defines */ |
| 113 | #define CMD_COMPL_WAIT 0x01 |
| 114 | #define CMD_INV_DEV_ENTRY 0x02 |
| 115 | #define CMD_INV_IOMMU_PAGES 0x03 |
| 116 | |
| 117 | #define CMD_COMPL_WAIT_STORE_MASK 0x01 |
Joerg Roedel | 519c31b | 2008-08-14 19:55:15 +0200 | [diff] [blame] | 118 | #define CMD_COMPL_WAIT_INT_MASK 0x02 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 119 | #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 |
| 120 | #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 |
| 121 | |
Joerg Roedel | 999ba41 | 2008-07-03 19:35:08 +0200 | [diff] [blame] | 122 | #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL |
| 123 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 124 | /* macros and definitions for device table entries */ |
| 125 | #define DEV_ENTRY_VALID 0x00 |
| 126 | #define DEV_ENTRY_TRANSLATION 0x01 |
| 127 | #define DEV_ENTRY_IR 0x3d |
| 128 | #define DEV_ENTRY_IW 0x3e |
Joerg Roedel | 9f5f5fb | 2008-08-14 19:55:16 +0200 | [diff] [blame] | 129 | #define DEV_ENTRY_NO_PAGE_FAULT 0x62 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 130 | #define DEV_ENTRY_EX 0x67 |
| 131 | #define DEV_ENTRY_SYSMGT1 0x68 |
| 132 | #define DEV_ENTRY_SYSMGT2 0x69 |
| 133 | #define DEV_ENTRY_INIT_PASS 0xb8 |
| 134 | #define DEV_ENTRY_EINT_PASS 0xb9 |
| 135 | #define DEV_ENTRY_NMI_PASS 0xba |
| 136 | #define DEV_ENTRY_LINT0_PASS 0xbe |
| 137 | #define DEV_ENTRY_LINT1_PASS 0xbf |
Joerg Roedel | 38ddf41 | 2008-09-11 10:38:32 +0200 | [diff] [blame] | 138 | #define DEV_ENTRY_MODE_MASK 0x07 |
| 139 | #define DEV_ENTRY_MODE_SHIFT 0x09 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 140 | |
| 141 | /* constants to configure the command buffer */ |
| 142 | #define CMD_BUFFER_SIZE 8192 |
| 143 | #define CMD_BUFFER_ENTRIES 512 |
| 144 | #define MMIO_CMD_SIZE_SHIFT 56 |
| 145 | #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) |
| 146 | |
Joerg Roedel | 335503e | 2008-09-05 14:29:07 +0200 | [diff] [blame] | 147 | /* constants for event buffer handling */ |
| 148 | #define EVT_BUFFER_SIZE 8192 /* 512 entries */ |
| 149 | #define EVT_LEN_MASK (0x9ULL << 56) |
| 150 | |
Joerg Roedel | 0feae53 | 2009-08-26 15:26:30 +0200 | [diff] [blame] | 151 | #define PAGE_MODE_NONE 0x00 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 152 | #define PAGE_MODE_1_LEVEL 0x01 |
| 153 | #define PAGE_MODE_2_LEVEL 0x02 |
| 154 | #define PAGE_MODE_3_LEVEL 0x03 |
Joerg Roedel | 9355a08 | 2009-09-02 14:24:08 +0200 | [diff] [blame] | 155 | #define PAGE_MODE_4_LEVEL 0x04 |
| 156 | #define PAGE_MODE_5_LEVEL 0x05 |
| 157 | #define PAGE_MODE_6_LEVEL 0x06 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 158 | |
Joerg Roedel | 9355a08 | 2009-09-02 14:24:08 +0200 | [diff] [blame] | 159 | #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9)) |
| 160 | #define PM_LEVEL_SIZE(x) (((x) < 6) ? \ |
| 161 | ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \ |
| 162 | (0xffffffffffffffffULL)) |
| 163 | #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL) |
Joerg Roedel | 50020fb | 2009-09-02 15:38:40 +0200 | [diff] [blame] | 164 | #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL) |
| 165 | #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \ |
| 166 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW) |
Joerg Roedel | a6b256b | 2009-09-03 12:21:31 +0200 | [diff] [blame] | 167 | #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL) |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 168 | |
Joerg Roedel | abdc5eb | 2009-09-03 11:33:51 +0200 | [diff] [blame] | 169 | #define PM_MAP_4k 0 |
| 170 | #define PM_ADDR_MASK 0x000ffffffffff000ULL |
| 171 | #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \ |
| 172 | (~((1ULL << (12 + ((lvl) * 9))) - 1))) |
| 173 | #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr)) |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 174 | |
| 175 | #define IOMMU_PTE_P (1ULL << 0) |
Joerg Roedel | 38ddf41 | 2008-09-11 10:38:32 +0200 | [diff] [blame] | 176 | #define IOMMU_PTE_TV (1ULL << 1) |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 177 | #define IOMMU_PTE_U (1ULL << 59) |
| 178 | #define IOMMU_PTE_FC (1ULL << 60) |
| 179 | #define IOMMU_PTE_IR (1ULL << 61) |
| 180 | #define IOMMU_PTE_IW (1ULL << 62) |
| 181 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 182 | #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) |
| 183 | #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P) |
| 184 | #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK)) |
| 185 | #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) |
| 186 | |
| 187 | #define IOMMU_PROT_MASK 0x03 |
| 188 | #define IOMMU_PROT_IR 0x01 |
| 189 | #define IOMMU_PROT_IW 0x02 |
| 190 | |
| 191 | /* IOMMU capabilities */ |
| 192 | #define IOMMU_CAP_IOTLB 24 |
| 193 | #define IOMMU_CAP_NPCACHE 26 |
| 194 | |
| 195 | #define MAX_DOMAIN_ID 65536 |
| 196 | |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 197 | /* FIXME: move this macro to <linux/pci.h> */ |
| 198 | #define PCI_BUS(x) (((x) >> 8) & 0xff) |
| 199 | |
Joerg Roedel | 9fdb19d | 2008-12-02 17:46:25 +0100 | [diff] [blame] | 200 | /* Protection domain flags */ |
| 201 | #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */ |
Joerg Roedel | e2dc14a | 2008-12-10 18:48:59 +0100 | [diff] [blame] | 202 | #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops |
| 203 | domain for an IOMMU */ |
Joerg Roedel | 0feae53 | 2009-08-26 15:26:30 +0200 | [diff] [blame] | 204 | #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page |
| 205 | translation */ |
| 206 | |
Joerg Roedel | fefda11 | 2009-05-20 12:21:42 +0200 | [diff] [blame] | 207 | extern bool amd_iommu_dump; |
| 208 | #define DUMP_printk(format, arg...) \ |
| 209 | do { \ |
| 210 | if (amd_iommu_dump) \ |
Joerg Roedel | 4c6f40d | 2009-09-01 16:43:58 +0200 | [diff] [blame] | 211 | printk(KERN_INFO "AMD-Vi: " format, ## arg); \ |
Joerg Roedel | fefda11 | 2009-05-20 12:21:42 +0200 | [diff] [blame] | 212 | } while(0); |
Joerg Roedel | 9fdb19d | 2008-12-02 17:46:25 +0100 | [diff] [blame] | 213 | |
Joerg Roedel | 318afd4 | 2009-11-23 18:32:38 +0100 | [diff] [blame] | 214 | /* global flag if IOMMUs cache non-present entries */ |
| 215 | extern bool amd_iommu_np_cache; |
| 216 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 217 | /* |
Joerg Roedel | 3bd2217 | 2009-05-04 15:06:20 +0200 | [diff] [blame] | 218 | * Make iterating over all IOMMUs easier |
| 219 | */ |
| 220 | #define for_each_iommu(iommu) \ |
| 221 | list_for_each_entry((iommu), &amd_iommu_list, list) |
| 222 | #define for_each_iommu_safe(iommu, next) \ |
| 223 | list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list) |
| 224 | |
Joerg Roedel | 384de72 | 2009-05-15 12:30:05 +0200 | [diff] [blame] | 225 | #define APERTURE_RANGE_SHIFT 27 /* 128 MB */ |
| 226 | #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT) |
| 227 | #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT) |
| 228 | #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */ |
| 229 | #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT) |
| 230 | #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL) |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 231 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 232 | /* |
| 233 | * This structure contains generic data for IOMMU protection domains |
| 234 | * independent of their use. |
| 235 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 236 | struct protection_domain { |
Joerg Roedel | aeb26f5 | 2009-11-20 16:44:01 +0100 | [diff] [blame] | 237 | struct list_head list; /* for list of all protection domains */ |
Joerg Roedel | 9fdb19d | 2008-12-02 17:46:25 +0100 | [diff] [blame] | 238 | spinlock_t lock; /* mostly used to lock the page table*/ |
| 239 | u16 id; /* the domain id written to the device table */ |
| 240 | int mode; /* paging mode (0-6 levels) */ |
| 241 | u64 *pt_root; /* page table root pointer */ |
| 242 | unsigned long flags; /* flags to find out type of domain */ |
Joerg Roedel | 04bfdd8 | 2009-09-02 16:00:23 +0200 | [diff] [blame] | 243 | bool updated; /* complete domain flush required */ |
Joerg Roedel | 863c74e | 2008-12-02 17:56:36 +0100 | [diff] [blame] | 244 | unsigned dev_cnt; /* devices assigned to this domain */ |
Joerg Roedel | c459611 | 2009-11-20 14:57:32 +0100 | [diff] [blame] | 245 | unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */ |
Joerg Roedel | 9fdb19d | 2008-12-02 17:46:25 +0100 | [diff] [blame] | 246 | void *priv; /* private data */ |
Joerg Roedel | c459611 | 2009-11-20 14:57:32 +0100 | [diff] [blame] | 247 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 248 | }; |
| 249 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 250 | /* |
Joerg Roedel | 657cbb6 | 2009-11-23 15:26:46 +0100 | [diff] [blame^] | 251 | * This struct contains device specific data for the IOMMU |
| 252 | */ |
| 253 | struct iommu_dev_data { |
| 254 | struct device *alias; /* The Alias Device */ |
| 255 | struct protection_domain *domain; /* Domain the device is bound to */ |
| 256 | }; |
| 257 | |
| 258 | /* |
Joerg Roedel | c323956 | 2009-05-12 10:56:44 +0200 | [diff] [blame] | 259 | * For dynamic growth the aperture size is split into ranges of 128MB of |
| 260 | * DMA address space each. This struct represents one such range. |
| 261 | */ |
| 262 | struct aperture_range { |
| 263 | |
| 264 | /* address allocation bitmap */ |
| 265 | unsigned long *bitmap; |
| 266 | |
| 267 | /* |
| 268 | * Array of PTE pages for the aperture. In this array we save all the |
| 269 | * leaf pages of the domain page table used for the aperture. This way |
| 270 | * we don't need to walk the page table to find a specific PTE. We can |
| 271 | * just calculate its address in constant time. |
| 272 | */ |
| 273 | u64 *pte_pages[64]; |
Joerg Roedel | 384de72 | 2009-05-15 12:30:05 +0200 | [diff] [blame] | 274 | |
| 275 | unsigned long offset; |
Joerg Roedel | c323956 | 2009-05-12 10:56:44 +0200 | [diff] [blame] | 276 | }; |
| 277 | |
| 278 | /* |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 279 | * Data container for a dma_ops specific protection domain |
| 280 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 281 | struct dma_ops_domain { |
| 282 | struct list_head list; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 283 | |
| 284 | /* generic protection domain information */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 285 | struct protection_domain domain; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 286 | |
| 287 | /* size of the aperture for the mappings */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 288 | unsigned long aperture_size; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 289 | |
| 290 | /* address we start to search for free addresses */ |
Joerg Roedel | 803b8cb | 2009-05-18 15:32:48 +0200 | [diff] [blame] | 291 | unsigned long next_address; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 292 | |
Joerg Roedel | c323956 | 2009-05-12 10:56:44 +0200 | [diff] [blame] | 293 | /* address space relevant data */ |
Joerg Roedel | 384de72 | 2009-05-15 12:30:05 +0200 | [diff] [blame] | 294 | struct aperture_range *aperture[APERTURE_MAX_RANGES]; |
Joerg Roedel | 1c65577 | 2008-09-04 18:40:05 +0200 | [diff] [blame] | 295 | |
| 296 | /* This will be set to true when TLB needs to be flushed */ |
| 297 | bool need_flush; |
Joerg Roedel | bd60b73 | 2008-09-11 10:24:48 +0200 | [diff] [blame] | 298 | |
| 299 | /* |
| 300 | * if this is a preallocated domain, keep the device for which it was |
| 301 | * preallocated in this variable |
| 302 | */ |
| 303 | u16 target_dev; |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 304 | }; |
| 305 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 306 | /* |
| 307 | * Structure where we save information about one hardware AMD IOMMU in the |
| 308 | * system. |
| 309 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 310 | struct amd_iommu { |
| 311 | struct list_head list; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 312 | |
Joerg Roedel | bb52777 | 2009-11-20 14:31:51 +0100 | [diff] [blame] | 313 | /* Index within the IOMMU array */ |
| 314 | int index; |
| 315 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 316 | /* locks the accesses to the hardware */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 317 | spinlock_t lock; |
| 318 | |
Joerg Roedel | 3eaf28a | 2008-09-08 15:55:10 +0200 | [diff] [blame] | 319 | /* Pointer to PCI device of this IOMMU */ |
| 320 | struct pci_dev *dev; |
| 321 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 322 | /* physical address of MMIO space */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 323 | u64 mmio_phys; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 324 | /* virtual address of MMIO space */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 325 | u8 *mmio_base; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 326 | |
| 327 | /* capabilities of that IOMMU read from ACPI */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 328 | u32 cap; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 329 | |
Richard Kennedy | eac9fbc | 2008-11-24 13:53:24 +0000 | [diff] [blame] | 330 | /* |
| 331 | * Capability pointer. There could be more than one IOMMU per PCI |
| 332 | * device function if there are more than one AMD IOMMU capability |
| 333 | * pointers. |
| 334 | */ |
| 335 | u16 cap_ptr; |
| 336 | |
Joerg Roedel | ee893c2 | 2008-09-08 14:48:04 +0200 | [diff] [blame] | 337 | /* pci domain of this IOMMU */ |
| 338 | u16 pci_seg; |
| 339 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 340 | /* first device this IOMMU handles. read from PCI */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 341 | u16 first_device; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 342 | /* last device this IOMMU handles. read from PCI */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 343 | u16 last_device; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 344 | |
| 345 | /* start of exclusion range of that IOMMU */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 346 | u64 exclusion_start; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 347 | /* length of exclusion range of that IOMMU */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 348 | u64 exclusion_length; |
| 349 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 350 | /* command buffer virtual address */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 351 | u8 *cmd_buf; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 352 | /* size of command buffer */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 353 | u32 cmd_buf_size; |
| 354 | |
Joerg Roedel | 335503e | 2008-09-05 14:29:07 +0200 | [diff] [blame] | 355 | /* size of event buffer */ |
| 356 | u32 evt_buf_size; |
Richard Kennedy | eac9fbc | 2008-11-24 13:53:24 +0000 | [diff] [blame] | 357 | /* event buffer virtual address */ |
| 358 | u8 *evt_buf; |
Joerg Roedel | a80dc3e | 2008-09-11 16:51:41 +0200 | [diff] [blame] | 359 | /* MSI number for event interrupt */ |
| 360 | u16 evt_msi_num; |
Joerg Roedel | 335503e | 2008-09-05 14:29:07 +0200 | [diff] [blame] | 361 | |
Joerg Roedel | a80dc3e | 2008-09-11 16:51:41 +0200 | [diff] [blame] | 362 | /* true if interrupts for this IOMMU are already enabled */ |
| 363 | bool int_enabled; |
| 364 | |
Richard Kennedy | eac9fbc | 2008-11-24 13:53:24 +0000 | [diff] [blame] | 365 | /* if one, we need to send a completion wait command */ |
Joerg Roedel | 0cfd7aa | 2008-12-10 19:58:00 +0100 | [diff] [blame] | 366 | bool need_sync; |
Richard Kennedy | eac9fbc | 2008-11-24 13:53:24 +0000 | [diff] [blame] | 367 | |
Joerg Roedel | b26e81b | 2009-09-03 15:08:09 +0200 | [diff] [blame] | 368 | /* becomes true if a command buffer reset is running */ |
| 369 | bool reset_in_progress; |
| 370 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 371 | /* default dma_ops domain for that IOMMU */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 372 | struct dma_ops_domain *default_dom; |
| 373 | }; |
| 374 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 375 | /* |
| 376 | * List with all IOMMUs in the system. This list is not locked because it is |
| 377 | * only written and read at driver initialization or suspend time |
| 378 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 379 | extern struct list_head amd_iommu_list; |
| 380 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 381 | /* |
Joerg Roedel | bb52777 | 2009-11-20 14:31:51 +0100 | [diff] [blame] | 382 | * Array with pointers to each IOMMU struct |
| 383 | * The indices are referenced in the protection domains |
| 384 | */ |
| 385 | extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; |
| 386 | |
| 387 | /* Number of IOMMUs present in the system */ |
| 388 | extern int amd_iommus_present; |
| 389 | |
| 390 | /* |
Joerg Roedel | aeb26f5 | 2009-11-20 16:44:01 +0100 | [diff] [blame] | 391 | * Declarations for the global list of all protection domains |
| 392 | */ |
| 393 | extern spinlock_t amd_iommu_pd_lock; |
| 394 | extern struct list_head amd_iommu_pd_list; |
| 395 | |
| 396 | /* |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 397 | * Structure defining one entry in the device table |
| 398 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 399 | struct dev_table_entry { |
| 400 | u32 data[8]; |
| 401 | }; |
| 402 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 403 | /* |
| 404 | * One entry for unity mappings parsed out of the ACPI table. |
| 405 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 406 | struct unity_map_entry { |
| 407 | struct list_head list; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 408 | |
| 409 | /* starting device id this entry is used for (including) */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 410 | u16 devid_start; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 411 | /* end device id this entry is used for (including) */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 412 | u16 devid_end; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 413 | |
| 414 | /* start address to unity map (including) */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 415 | u64 address_start; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 416 | /* end address to unity map (including) */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 417 | u64 address_end; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 418 | |
| 419 | /* required protection */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 420 | int prot; |
| 421 | }; |
| 422 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 423 | /* |
| 424 | * List of all unity mappings. It is not locked because as runtime it is only |
| 425 | * read. It is created at ACPI table parsing time. |
| 426 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 427 | extern struct list_head amd_iommu_unity_map; |
| 428 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 429 | /* |
| 430 | * Data structures for device handling |
| 431 | */ |
| 432 | |
| 433 | /* |
| 434 | * Device table used by hardware. Read and write accesses by software are |
| 435 | * locked with the amd_iommu_pd_table lock. |
| 436 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 437 | extern struct dev_table_entry *amd_iommu_dev_table; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 438 | |
| 439 | /* |
| 440 | * Alias table to find requestor ids to device ids. Not locked because only |
| 441 | * read on runtime. |
| 442 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 443 | extern u16 *amd_iommu_alias_table; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 444 | |
| 445 | /* |
| 446 | * Reverse lookup table to find the IOMMU which translates a specific device. |
| 447 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 448 | extern struct amd_iommu **amd_iommu_rlookup_table; |
| 449 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 450 | /* size of the dma_ops aperture as power of 2 */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 451 | extern unsigned amd_iommu_aperture_order; |
| 452 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 453 | /* largest PCI device id we expect translation requests for */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 454 | extern u16 amd_iommu_last_bdf; |
| 455 | |
| 456 | /* data structures for protection domain handling */ |
| 457 | extern struct protection_domain **amd_iommu_pd_table; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 458 | |
| 459 | /* allocation bitmap for domain ids */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 460 | extern unsigned long *amd_iommu_pd_alloc_bitmap; |
| 461 | |
FUJITA Tomonori | afa9fdc | 2008-09-20 01:23:30 +0900 | [diff] [blame] | 462 | /* |
| 463 | * If true, the addresses will be flushed on unmap time, not when |
| 464 | * they are reused |
| 465 | */ |
| 466 | extern bool amd_iommu_unmap_flush; |
| 467 | |
Joerg Roedel | d591b0a | 2008-07-11 17:14:35 +0200 | [diff] [blame] | 468 | /* takes bus and device/function and returns the device id |
| 469 | * FIXME: should that be in generic PCI code? */ |
| 470 | static inline u16 calc_devid(u8 bus, u8 devfn) |
| 471 | { |
| 472 | return (((u16)bus) << 8) | devfn; |
| 473 | } |
| 474 | |
Joerg Roedel | a9dddbe | 2008-12-12 12:33:06 +0100 | [diff] [blame] | 475 | #ifdef CONFIG_AMD_IOMMU_STATS |
| 476 | |
| 477 | struct __iommu_counter { |
| 478 | char *name; |
| 479 | struct dentry *dent; |
| 480 | u64 value; |
| 481 | }; |
| 482 | |
| 483 | #define DECLARE_STATS_COUNTER(nm) \ |
| 484 | static struct __iommu_counter nm = { \ |
| 485 | .name = #nm, \ |
| 486 | } |
| 487 | |
| 488 | #define INC_STATS_COUNTER(name) name.value += 1 |
| 489 | #define ADD_STATS_COUNTER(name, x) name.value += (x) |
| 490 | #define SUB_STATS_COUNTER(name, x) name.value -= (x) |
| 491 | |
| 492 | #else /* CONFIG_AMD_IOMMU_STATS */ |
| 493 | |
| 494 | #define DECLARE_STATS_COUNTER(name) |
| 495 | #define INC_STATS_COUNTER(name) |
| 496 | #define ADD_STATS_COUNTER(name, x) |
| 497 | #define SUB_STATS_COUNTER(name, x) |
| 498 | |
| 499 | #endif /* CONFIG_AMD_IOMMU_STATS */ |
| 500 | |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 501 | #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ |