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gerrit-public.fairphone.software / kernel / msm-4.9 / 65a0707548cce5b054cc8c94bfaa1b0cc9776505 / . / drivers / net / wireless / cnss2 / pci.h
blob: 4a82998c6f1abd7401520425d168f17af84d72ea [file] [log] [blame]
Yue Ma4dac45d2018-02-23 11:49:25 -0800[diff] [blame]1/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
Yue Ma0317e4a2018-01-10 11:48:32 -0800[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef _CNSS_PCI_H
14#define _CNSS_PCI_H
15
16#include <asm/dma-iommu.h>
17#include <linux/iommu.h>
18#include <linux/msm_mhi.h>
19#include <linux/msm_pcie.h>
20#include <linux/pci.h>
21
22#include "main.h"
23
24#define QCA6174_VENDOR_ID 0x168C
25#define QCA6174_DEVICE_ID 0x003E
26#define QCA6174_REV_ID_OFFSET 0x08
27#define QCA6174_REV3_VERSION 0x5020000
28#define QCA6174_REV3_2_VERSION 0x5030000
29#define QCA6290_VENDOR_ID 0x17CB
30#define QCA6290_DEVICE_ID 0x1100
31#define QCA6290_EMULATION_VENDOR_ID 0x168C
32#define QCA6290_EMULATION_DEVICE_ID 0xABCD
33
34enum cnss_mhi_state {
35 CNSS_MHI_INIT,
36 CNSS_MHI_DEINIT,
37 CNSS_MHI_SUSPEND,
38 CNSS_MHI_RESUME,
39 CNSS_MHI_POWER_OFF,
40 CNSS_MHI_POWER_ON,
41 CNSS_MHI_TRIGGER_RDDM,
42 CNSS_MHI_RDDM,
43 CNSS_MHI_RDDM_KERNEL_PANIC,
44 CNSS_MHI_NOTIFY_LINK_ERROR,
45};
46
47struct cnss_msi_user {
48 char *name;
49 int num_vectors;
50 u32 base_vector;
51};
52
53struct cnss_msi_config {
54 int total_vectors;
55 int total_users;
56 struct cnss_msi_user *users;
57};
58
59struct cnss_pci_data {
60 struct pci_dev *pci_dev;
61 struct cnss_plat_data *plat_priv;
62 const struct pci_device_id *pci_device_id;
63 u32 device_id;
64 u16 revision_id;
65 bool pci_link_state;
66 bool pci_link_down_ind;
67 struct pci_saved_state *saved_state;
68 struct pci_saved_state *default_state;
69 struct msm_pcie_register_event msm_pci_event;
70 atomic_t auto_suspended;
71 bool monitor_wake_intr;
72 struct dma_iommu_mapping *smmu_mapping;
Yue Ma4dac45d2018-02-23 11:49:25 -0800[diff] [blame]73 bool smmu_s1_enable;
Yue Ma0317e4a2018-01-10 11:48:32 -0800[diff] [blame]74 dma_addr_t smmu_iova_start;
75 size_t smmu_iova_len;
76 void __iomem *bar;
77 struct cnss_msi_config *msi_config;
78 u32 msi_ep_base_data;
79 struct mhi_device mhi_dev;
80 unsigned long mhi_state;
81};
82
83static inline void cnss_set_pci_priv(struct pci_dev *pci_dev, void *data)
84{
85 pci_set_drvdata(pci_dev, data);
86}
87
88static inline struct cnss_pci_data *cnss_get_pci_priv(struct pci_dev *pci_dev)
89{
90 return pci_get_drvdata(pci_dev);
91}
92
93static inline struct cnss_plat_data *cnss_pci_priv_to_plat_priv(void *bus_priv)
94{
95 struct cnss_pci_data *pci_priv = bus_priv;
96
97 return pci_priv->plat_priv;
98}
99
100static inline void cnss_pci_set_monitor_wake_intr(void *bus_priv, bool val)
101{
102 struct cnss_pci_data *pci_priv = bus_priv;
103
104 pci_priv->monitor_wake_intr = val;
105}
106
107static inline bool cnss_pci_get_monitor_wake_intr(void *bus_priv)
108{
109 struct cnss_pci_data *pci_priv = bus_priv;
110
111 return pci_priv->monitor_wake_intr;
112}
113
114static inline void cnss_pci_set_auto_suspended(void *bus_priv, int val)
115{
116 struct cnss_pci_data *pci_priv = bus_priv;
117
118 atomic_set(&pci_priv->auto_suspended, val);
119}
120
121static inline int cnss_pci_get_auto_suspended(void *bus_priv)
122{
123 struct cnss_pci_data *pci_priv = bus_priv;
124
125 return atomic_read(&pci_priv->auto_suspended);
126}
127
128int cnss_suspend_pci_link(struct cnss_pci_data *pci_priv);
129int cnss_resume_pci_link(struct cnss_pci_data *pci_priv);
130int cnss_pci_init(struct cnss_plat_data *plat_priv);
131void cnss_pci_deinit(struct cnss_plat_data *plat_priv);
132int cnss_pci_alloc_fw_mem(struct cnss_pci_data *pci_priv);
133int cnss_pci_load_m3(struct cnss_pci_data *pci_priv);
134int cnss_pci_get_bar_info(struct cnss_pci_data *pci_priv, void __iomem **va,
135 phys_addr_t *pa);
136int cnss_pci_set_mhi_state(struct cnss_pci_data *pci_priv,
137 enum cnss_mhi_state state);
138int cnss_pci_start_mhi(struct cnss_pci_data *pci_priv);
139void cnss_pci_stop_mhi(struct cnss_pci_data *pci_priv);
140void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv);
141void cnss_pci_clear_dump_info(struct cnss_pci_data *pci_priv);
142int cnss_pm_request_resume(struct cnss_pci_data *pci_priv);
143
144#endif /* _CNSS_PCI_H */