blob: c601622cc98e59664db6102e65650ec5ea1c98a3 [file] [log] [blame]
Stephen M. Cameronedd16362009-12-08 14:09:11 -08001/*
2 * Disk Array driver for HP Smart Array SAS controllers
Scott Teel51c35132014-02-18 13:57:26 -06003 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
Stephen M. Cameronedd16362009-12-08 14:09:11 -08004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21#ifndef HPSA_CMD_H
22#define HPSA_CMD_H
23
24/* general boundary defintions */
25#define SENSEINFOBYTES 32 /* may vary between hbas */
Stephen M. Camerond66ae082012-01-19 14:00:48 -060026#define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */
Stephen M. Cameron33a2ffc2010-02-25 14:03:27 -060027#define HPSA_SG_CHAIN 0x80000000
Matt Gatese1d9cbf2014-02-18 13:55:12 -060028#define HPSA_SG_LAST 0x40000000
Stephen M. Cameronedd16362009-12-08 14:09:11 -080029#define MAXREPLYQS 256
30
31/* Command Status value */
32#define CMD_SUCCESS 0x0000
33#define CMD_TARGET_STATUS 0x0001
34#define CMD_DATA_UNDERRUN 0x0002
35#define CMD_DATA_OVERRUN 0x0003
36#define CMD_INVALID 0x0004
37#define CMD_PROTOCOL_ERR 0x0005
38#define CMD_HARDWARE_ERR 0x0006
39#define CMD_CONNECTION_LOST 0x0007
40#define CMD_ABORTED 0x0008
41#define CMD_ABORT_FAILED 0x0009
42#define CMD_UNSOLICITED_ABORT 0x000A
43#define CMD_TIMEOUT 0x000B
44#define CMD_UNABORTABLE 0x000C
Stephen Cameron9437ac42015-04-23 09:32:16 -050045#define CMD_TMF_STATUS 0x000D
Stephen M. Cameron283b4a92014-02-18 13:55:33 -060046#define CMD_IOACCEL_DISABLED 0x000E
Webb Scales25163bd2015-04-23 09:32:00 -050047#define CMD_CTLR_LOCKUP 0xffff
48/* Note: CMD_CTLR_LOCKUP is not a value defined by the CISS spec
49 * it is a value defined by the driver that commands can be marked
50 * with when a controller lockup has been detected by the driver
51 */
Stephen M. Cameron283b4a92014-02-18 13:55:33 -060052
Stephen Cameron9437ac42015-04-23 09:32:16 -050053/* TMF function status values */
54#define CISS_TMF_COMPLETE 0x00
55#define CISS_TMF_INVALID_FRAME 0x02
56#define CISS_TMF_NOT_SUPPORTED 0x04
57#define CISS_TMF_FAILED 0x05
58#define CISS_TMF_SUCCESS 0x08
59#define CISS_TMF_WRONG_LUN 0x09
60#define CISS_TMF_OVERLAPPED_TAG 0x0a
Stephen M. Cameronedd16362009-12-08 14:09:11 -080061
62/* Unit Attentions ASC's as defined for the MSA2012sa */
63#define POWER_OR_RESET 0x29
64#define STATE_CHANGED 0x2a
65#define UNIT_ATTENTION_CLEARED 0x2f
66#define LUN_FAILED 0x3e
67#define REPORT_LUNS_CHANGED 0x3f
68
69/* Unit Attentions ASCQ's as defined for the MSA2012sa */
70
71 /* These ASCQ's defined for ASC = POWER_OR_RESET */
72#define POWER_ON_RESET 0x00
73#define POWER_ON_REBOOT 0x01
74#define SCSI_BUS_RESET 0x02
75#define MSA_TARGET_RESET 0x03
76#define CONTROLLER_FAILOVER 0x04
77#define TRANSCEIVER_SE 0x05
78#define TRANSCEIVER_LVD 0x06
79
80 /* These ASCQ's defined for ASC = STATE_CHANGED */
81#define RESERVATION_PREEMPTED 0x03
82#define ASYM_ACCESS_CHANGED 0x06
83#define LUN_CAPACITY_CHANGED 0x09
84
85/* transfer direction */
86#define XFER_NONE 0x00
87#define XFER_WRITE 0x01
88#define XFER_READ 0x02
89#define XFER_RSVD 0x03
90
91/* task attribute */
92#define ATTR_UNTAGGED 0x00
93#define ATTR_SIMPLE 0x04
94#define ATTR_HEADOFQUEUE 0x05
95#define ATTR_ORDERED 0x06
96#define ATTR_ACA 0x07
97
98/* cdb type */
Scott Teel54b6e9e2014-02-18 13:56:45 -060099#define TYPE_CMD 0x00
100#define TYPE_MSG 0x01
101#define TYPE_IOACCEL2_CMD 0x81 /* 0x81 is not used by hardware */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800102
Stephen M. Cameron75167d22012-05-01 11:42:51 -0500103/* Message Types */
104#define HPSA_TASK_MANAGEMENT 0x00
105#define HPSA_RESET 0x01
106#define HPSA_SCAN 0x02
107#define HPSA_NOOP 0x03
108
109#define HPSA_CTLR_RESET_TYPE 0x00
110#define HPSA_BUS_RESET_TYPE 0x01
111#define HPSA_TARGET_RESET_TYPE 0x03
112#define HPSA_LUN_RESET_TYPE 0x04
113#define HPSA_NEXUS_RESET_TYPE 0x05
114
115/* Task Management Functions */
116#define HPSA_TMF_ABORT_TASK 0x00
117#define HPSA_TMF_ABORT_TASK_SET 0x01
118#define HPSA_TMF_CLEAR_ACA 0x02
119#define HPSA_TMF_CLEAR_TASK_SET 0x03
120#define HPSA_TMF_QUERY_TASK 0x04
121#define HPSA_TMF_QUERY_TASK_SET 0x05
122#define HPSA_TMF_QUERY_ASYNCEVENT 0x06
123
124
125
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800126/* config space register offsets */
127#define CFG_VENDORID 0x00
128#define CFG_DEVICEID 0x02
129#define CFG_I2OBAR 0x10
130#define CFG_MEM1BAR 0x14
131
132/* i2o space register offsets */
133#define I2O_IBDB_SET 0x20
134#define I2O_IBDB_CLEAR 0x70
135#define I2O_INT_STATUS 0x30
136#define I2O_INT_MASK 0x34
137#define I2O_IBPOST_Q 0x40
138#define I2O_OBPOST_Q 0x44
139#define I2O_DMA1_CFG 0x214
140
141/* Configuration Table */
142#define CFGTBL_ChangeReq 0x00000001l
143#define CFGTBL_AccCmds 0x00000001l
Stephen M. Cameron1df85522010-06-16 13:51:40 -0500144#define DOORBELL_CTLR_RESET 0x00000004l
Stephen M. Cameroncf0b08d2011-05-03 14:59:46 -0500145#define DOORBELL_CTLR_RESET2 0x00000020l
Stephen M. Cameron76438d02014-02-18 13:55:43 -0600146#define DOORBELL_CLEAR_EVENTS 0x00000040l
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800147
148#define CFGTBL_Trans_Simple 0x00000002l
Don Brace303932f2010-02-04 08:42:40 -0600149#define CFGTBL_Trans_Performant 0x00000004l
Matt Gatese1f7de02014-02-18 13:55:17 -0600150#define CFGTBL_Trans_io_accel1 0x00000080l
Stephen M. Cameron1f7cee82014-02-18 13:56:09 -0600151#define CFGTBL_Trans_io_accel2 0x00000100l
Stephen M. Cameron960a30e2011-02-15 15:33:03 -0600152#define CFGTBL_Trans_use_short_tags 0x20000000l
Matt Gates254f7962012-05-01 11:43:06 -0500153#define CFGTBL_Trans_enable_directed_msix (1 << 30)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800154
155#define CFGTBL_BusType_Ultra2 0x00000001l
156#define CFGTBL_BusType_Ultra3 0x00000002l
157#define CFGTBL_BusType_Fibre1G 0x00000100l
158#define CFGTBL_BusType_Fibre2G 0x00000200l
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600159
160/* VPD Inquiry types */
Stephen M. Cameron1b70150a2014-02-18 13:57:16 -0600161#define HPSA_VPD_SUPPORTED_PAGES 0x00
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600162#define HPSA_VPD_LV_DEVICE_GEOMETRY 0xC1
163#define HPSA_VPD_LV_IOACCEL_STATUS 0xC2
Stephen M. Cameron98465902014-02-21 16:25:00 -0600164#define HPSA_VPD_LV_STATUS 0xC3
Stephen M. Cameron1b70150a2014-02-18 13:57:16 -0600165#define HPSA_VPD_HEADER_SZ 4
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600166
Stephen M. Cameron98465902014-02-21 16:25:00 -0600167/* Logical volume states */
Stephen M. Cameron67955ba2014-05-29 10:54:25 -0500168#define HPSA_VPD_LV_STATUS_UNSUPPORTED 0xff
Stephen M. Cameron98465902014-02-21 16:25:00 -0600169#define HPSA_LV_OK 0x0
170#define HPSA_LV_UNDERGOING_ERASE 0x0F
171#define HPSA_LV_UNDERGOING_RPI 0x12
172#define HPSA_LV_PENDING_RPI 0x13
173#define HPSA_LV_ENCRYPTED_NO_KEY 0x14
174#define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15
175#define HPSA_LV_UNDERGOING_ENCRYPTION 0x16
176#define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17
177#define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18
178#define HPSA_LV_PENDING_ENCRYPTION 0x19
179#define HPSA_LV_PENDING_ENCRYPTION_REKEYING 0x1A
180
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800181struct vals32 {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600182 u32 lower;
183 u32 upper;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800184};
185
186union u64bit {
187 struct vals32 val32;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600188 u64 val;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800189};
190
191/* FIXME this is a per controller value (barf!) */
Scott Teelb7ec0212011-10-26 16:21:12 -0500192#define HPSA_MAX_LUN 1024
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800193#define HPSA_MAX_PHYS_LUN 1024
Scott Teelaca4a522012-01-19 14:01:19 -0600194#define MAX_EXT_TARGETS 32
Scott Teelb7ec0212011-10-26 16:21:12 -0500195#define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
Scott Teelaca4a522012-01-19 14:01:19 -0600196 MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800197
198/* SCSI-3 Commands */
199#pragma pack(1)
200
201#define HPSA_INQUIRY 0x12
202struct InquiryData {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600203 u8 data_byte[36];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800204};
205
206#define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */
207#define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
Matt Gatesa93aa1f2014-02-18 13:55:07 -0600208#define HPSA_REPORT_PHYS_EXTENDED 0x02
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600209#define HPSA_CISS_READ 0xc0 /* CISS Read */
210#define HPSA_GET_RAID_MAP 0xc8 /* CISS Get RAID Layout Map */
211
212#define RAID_MAP_MAX_ENTRIES 256
213
214struct raid_map_disk_data {
215 u32 ioaccel_handle; /**< Handle to access this disk via the
216 * I/O accelerator */
217 u8 xor_mult[2]; /**< XOR multipliers for this position,
218 * valid for data disks only */
219 u8 reserved[2];
220};
221
222struct raid_map_data {
Don Brace2b08b3e2015-01-23 16:41:09 -0600223 __le32 structure_size; /* Size of entire structure in bytes */
224 __le32 volume_blk_size; /* bytes / block in the volume */
225 __le64 volume_blk_cnt; /* logical blocks on the volume */
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600226 u8 phys_blk_shift; /* Shift factor to convert between
227 * units of logical blocks and physical
228 * disk blocks */
229 u8 parity_rotation_shift; /* Shift factor to convert between units
230 * of logical stripes and physical
231 * stripes */
Don Brace2b08b3e2015-01-23 16:41:09 -0600232 __le16 strip_size; /* blocks used on each disk / stripe */
233 __le64 disk_starting_blk; /* First disk block used in volume */
234 __le64 disk_blk_cnt; /* disk blocks used by volume / disk */
235 __le16 data_disks_per_row; /* data disk entries / row in the map */
236 __le16 metadata_disks_per_row;/* mirror/parity disk entries / row
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600237 * in the map */
Don Brace2b08b3e2015-01-23 16:41:09 -0600238 __le16 row_cnt; /* rows in each layout map */
239 __le16 layout_map_count; /* layout maps (1 map per mirror/parity
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600240 * group) */
Don Brace2b08b3e2015-01-23 16:41:09 -0600241 __le16 flags; /* Bit 0 set if encryption enabled */
Scott Teeldd0e19f2014-02-18 13:57:31 -0600242#define RAID_MAP_FLAG_ENCRYPT_ON 0x01
Don Brace2b08b3e2015-01-23 16:41:09 -0600243 __le16 dekindex; /* Data encryption key index. */
Scott Teeldd0e19f2014-02-18 13:57:31 -0600244 u8 reserved[16];
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600245 struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES];
246};
247
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800248struct ReportLUNdata {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600249 u8 LUNListLength[4];
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600250 u8 extended_response_flag;
251 u8 reserved[3];
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600252 u8 LUN[HPSA_MAX_LUN][8];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800253};
254
Stephen M. Camerond5b5d962014-05-29 10:53:34 -0500255struct ext_report_lun_entry {
256 u8 lunid[8];
Stephen Cameron41ce4c32015-04-23 09:31:47 -0500257#define MASKED_DEVICE(x) ((x)[3] & 0xC0)
Don Brace03383732015-01-23 16:43:30 -0600258#define GET_BMIC_BUS(lunid) ((lunid)[7] & 0x3F)
259#define GET_BMIC_LEVEL_TWO_TARGET(lunid) ((lunid)[6])
260#define GET_BMIC_DRIVE_NUMBER(lunid) (((GET_BMIC_BUS((lunid)) - 1) << 8) + \
261 GET_BMIC_LEVEL_TWO_TARGET((lunid)))
Stephen M. Camerond5b5d962014-05-29 10:53:34 -0500262 u8 wwid[8];
263 u8 device_type;
264 u8 device_flags;
Stephen Cameron41ce4c32015-04-23 09:31:47 -0500265#define NON_DISK_PHYS_DEV(x) ((x)[17] & 0x01)
266#define PHYS_IOACCEL(x) ((x)[17] & 0x08)
Stephen M. Camerond5b5d962014-05-29 10:53:34 -0500267 u8 lun_count; /* multi-lun device, how many luns */
268 u8 redundant_paths;
269 u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */
270};
271
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800272struct ReportExtendedLUNdata {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600273 u8 LUNListLength[4];
274 u8 extended_response_flag;
275 u8 reserved[3];
Stephen M. Cameron92084712014-11-14 17:26:54 -0600276 struct ext_report_lun_entry LUN[HPSA_MAX_PHYS_LUN];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800277};
278
279struct SenseSubsystem_info {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600280 u8 reserved[36];
281 u8 portname[8];
282 u8 reserved1[1108];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800283};
284
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800285/* BMIC commands */
286#define BMIC_READ 0x26
287#define BMIC_WRITE 0x27
288#define BMIC_CACHE_FLUSH 0xc2
289#define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */
Stephen M. Camerone85c5972012-05-01 11:43:42 -0500290#define BMIC_FLASH_FIRMWARE 0xF7
Stephen M. Cameron316b2212014-02-21 16:25:15 -0600291#define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
Don Brace03383732015-01-23 16:43:30 -0600292#define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800293
294/* Command List Structure */
295union SCSI3Addr {
296 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600297 u8 Dev;
298 u8 Bus:6;
299 u8 Mode:2; /* b00 */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800300 } PeripDev;
301 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600302 u8 DevLSB;
303 u8 DevMSB:6;
304 u8 Mode:2; /* b01 */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800305 } LogDev;
306 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600307 u8 Dev:5;
308 u8 Bus:3;
309 u8 Targ:6;
310 u8 Mode:2; /* b10 */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800311 } LogUnit;
312};
313
314struct PhysDevAddr {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600315 u32 TargetId:24;
316 u32 Bus:6;
317 u32 Mode:2;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800318 /* 2 level target device addr */
319 union SCSI3Addr Target[2];
320};
321
322struct LogDevAddr {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600323 u32 VolId:30;
324 u32 Mode:2;
325 u8 reserved[4];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800326};
327
328union LUNAddr {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600329 u8 LunAddrBytes[8];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800330 union SCSI3Addr SCSI3Lun[4];
331 struct PhysDevAddr PhysDev;
332 struct LogDevAddr LogDev;
333};
334
335struct CommandListHeader {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600336 u8 ReplyQueue;
337 u8 SGList;
Don Brace2b08b3e2015-01-23 16:41:09 -0600338 __le16 SGTotal;
339 __le64 tag;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800340 union LUNAddr LUN;
341};
342
343struct RequestBlock {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600344 u8 CDBLen;
Stephen M. Camerona505b862014-11-14 17:27:04 -0600345 /*
346 * type_attr_dir:
347 * type: low 3 bits
348 * attr: middle 3 bits
349 * dir: high 2 bits
350 */
351 u8 type_attr_dir;
352#define TYPE_ATTR_DIR(t, a, d) ((((d) & 0x03) << 6) |\
353 (((a) & 0x07) << 3) |\
354 ((t) & 0x07))
355#define GET_TYPE(tad) ((tad) & 0x07)
356#define GET_ATTR(tad) (((tad) >> 3) & 0x07)
357#define GET_DIR(tad) (((tad) >> 6) & 0x03)
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600358 u16 Timeout;
359 u8 CDB[16];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800360};
361
362struct ErrDescriptor {
Don Brace2b08b3e2015-01-23 16:41:09 -0600363 __le64 Addr;
364 __le32 Len;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800365};
366
367struct SGDescriptor {
Don Brace2b08b3e2015-01-23 16:41:09 -0600368 __le64 Addr;
369 __le32 Len;
370 __le32 Ext;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800371};
372
373union MoreErrInfo {
374 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600375 u8 Reserved[3];
376 u8 Type;
377 u32 ErrorInfo;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800378 } Common_Info;
379 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600380 u8 Reserved[2];
381 u8 offense_size; /* size of offending entry */
382 u8 offense_num; /* byte # of offense 0-base */
383 u32 offense_value;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800384 } Invalid_Cmd;
385};
386struct ErrorInfo {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600387 u8 ScsiStatus;
388 u8 SenseLen;
389 u16 CommandStatus;
390 u32 ResidualCnt;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800391 union MoreErrInfo MoreErrInfo;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600392 u8 SenseInfo[SENSEINFOBYTES];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800393};
394/* Command types */
395#define CMD_IOCTL_PEND 0x01
396#define CMD_SCSI 0x03
Matt Gatese1f7de02014-02-18 13:55:17 -0600397#define CMD_IOACCEL1 0x04
Mike Millerb66cc252014-02-18 13:56:04 -0600398#define CMD_IOACCEL2 0x05
Stephen Cameron8be986c2015-04-23 09:34:06 -0500399#define IOACCEL2_TMF 0x06
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800400
Don Bracef2405db2015-01-23 16:43:09 -0600401#define DIRECT_LOOKUP_SHIFT 4
Stephen M. Camerond896f3f2011-01-06 14:47:53 -0600402#define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
Don Brace303932f2010-02-04 08:42:40 -0600403
404#define HPSA_ERROR_BIT 0x02
405struct ctlr_info; /* defined in hpsa.h */
Don Bracef2405db2015-01-23 16:43:09 -0600406/* The size of this structure needs to be divisible by 128
407 * on all architectures. The low 4 bits of the addresses
Don Brace303932f2010-02-04 08:42:40 -0600408 * are used as follows:
409 *
410 * bit 0: to device, used to indicate "performant mode" command
411 * from device, indidcates error status.
412 * bit 1-3: to device, indicates block fetch table entry for
413 * reducing DMA in fetching commands from host memory.
Don Brace303932f2010-02-04 08:42:40 -0600414 */
415
Stephen M. Cameron35d697c2014-05-29 10:52:52 -0500416#define COMMANDLIST_ALIGNMENT 128
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800417struct CommandList {
418 struct CommandListHeader Header;
419 struct RequestBlock Request;
420 struct ErrDescriptor ErrDesc;
Stephen M. Camerond66ae082012-01-19 14:00:48 -0600421 struct SGDescriptor SG[SG_ENTRIES_IN_CMD];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800422 /* information associated with the command */
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600423 u32 busaddr; /* physical addr of this record */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800424 struct ErrorInfo *err_info; /* pointer to the allocated mem */
425 struct ctlr_info *h;
426 int cmd_type;
427 long cmdindex;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800428 struct completion *waiting;
Stephen Cameron7fa30302015-01-23 16:44:30 -0600429 struct scsi_cmnd *scsi_cmd;
Don Brace080ef1c2015-01-23 16:43:25 -0600430 struct work_struct work;
Don Brace03383732015-01-23 16:43:30 -0600431
432 /*
433 * For commands using either of the two "ioaccel" paths to
434 * bypass the RAID stack and go directly to the physical disk
435 * phys_disk is a pointer to the hpsa_scsi_dev_t to which the
436 * i/o is destined. We need to store that here because the command
437 * may potentially encounter TASK SET FULL and need to be resubmitted
438 * For "normal" i/o's not using the "ioaccel" paths, phys_disk is
439 * not used.
440 */
441 struct hpsa_scsi_dev_t *phys_disk;
Webb Scalesa58e7e52015-04-23 09:34:16 -0500442
443 int abort_pending;
Webb Scalesd604f532015-04-23 09:35:22 -0500444 struct hpsa_scsi_dev_t *reset_pending;
Stephen Cameron360c73b2015-04-23 09:32:32 -0500445 atomic_t refcount; /* Must be last to avoid memset in hpsa_cmd_init() */
Stephen M. Cameron35d697c2014-05-29 10:52:52 -0500446} __aligned(COMMANDLIST_ALIGNMENT);
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800447
Matt Gatese1f7de02014-02-18 13:55:17 -0600448/* Max S/G elements in I/O accelerator command */
449#define IOACCEL1_MAXSGENTRIES 24
Mike Millerb66cc252014-02-18 13:56:04 -0600450#define IOACCEL2_MAXSGENTRIES 28
Matt Gatese1f7de02014-02-18 13:55:17 -0600451
452/*
453 * Structure for I/O accelerator (mode 1) commands.
454 * Note that this structure must be 128-byte aligned in size.
455 */
Stephen M. Cameron35d697c2014-05-29 10:52:52 -0500456#define IOACCEL1_COMMANDLIST_ALIGNMENT 128
Matt Gatese1f7de02014-02-18 13:55:17 -0600457struct io_accel1_cmd {
Don Brace2b08b3e2015-01-23 16:41:09 -0600458 __le16 dev_handle; /* 0x00 - 0x01 */
Matt Gatese1f7de02014-02-18 13:55:17 -0600459 u8 reserved1; /* 0x02 */
460 u8 function; /* 0x03 */
461 u8 reserved2[8]; /* 0x04 - 0x0B */
462 u32 err_info; /* 0x0C - 0x0F */
463 u8 reserved3[2]; /* 0x10 - 0x11 */
464 u8 err_info_len; /* 0x12 */
465 u8 reserved4; /* 0x13 */
466 u8 sgl_offset; /* 0x14 */
467 u8 reserved5[7]; /* 0x15 - 0x1B */
Don Brace2b08b3e2015-01-23 16:41:09 -0600468 __le32 transfer_len; /* 0x1C - 0x1F */
Matt Gatese1f7de02014-02-18 13:55:17 -0600469 u8 reserved6[4]; /* 0x20 - 0x23 */
Don Brace2b08b3e2015-01-23 16:41:09 -0600470 __le16 io_flags; /* 0x24 - 0x25 */
Matt Gatese1f7de02014-02-18 13:55:17 -0600471 u8 reserved7[14]; /* 0x26 - 0x33 */
472 u8 LUN[8]; /* 0x34 - 0x3B */
Don Brace2b08b3e2015-01-23 16:41:09 -0600473 __le32 control; /* 0x3C - 0x3F */
Matt Gatese1f7de02014-02-18 13:55:17 -0600474 u8 CDB[16]; /* 0x40 - 0x4F */
475 u8 reserved8[16]; /* 0x50 - 0x5F */
Don Brace2b08b3e2015-01-23 16:41:09 -0600476 __le16 host_context_flags; /* 0x60 - 0x61 */
477 __le16 timeout_sec; /* 0x62 - 0x63 */
Matt Gatese1f7de02014-02-18 13:55:17 -0600478 u8 ReplyQueue; /* 0x64 */
479 u8 reserved9[3]; /* 0x65 - 0x67 */
Don Brace2b08b3e2015-01-23 16:41:09 -0600480 __le64 tag; /* 0x68 - 0x6F */
481 __le64 host_addr; /* 0x70 - 0x77 */
Matt Gatese1f7de02014-02-18 13:55:17 -0600482 u8 CISS_LUN[8]; /* 0x78 - 0x7F */
483 struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES];
Stephen M. Cameron35d697c2014-05-29 10:52:52 -0500484} __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT);
Matt Gatese1f7de02014-02-18 13:55:17 -0600485
486#define IOACCEL1_FUNCTION_SCSIIO 0x00
487#define IOACCEL1_SGLOFFSET 32
488
489#define IOACCEL1_IOFLAGS_IO_REQ 0x4000
490#define IOACCEL1_IOFLAGS_CDBLEN_MASK 0x001F
491#define IOACCEL1_IOFLAGS_CDBLEN_MAX 16
492
493#define IOACCEL1_CONTROL_NODATAXFER 0x00000000
494#define IOACCEL1_CONTROL_DATA_OUT 0x01000000
495#define IOACCEL1_CONTROL_DATA_IN 0x02000000
496#define IOACCEL1_CONTROL_TASKPRIO_MASK 0x00007800
497#define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11
498#define IOACCEL1_CONTROL_SIMPLEQUEUE 0x00000000
499#define IOACCEL1_CONTROL_HEADOFQUEUE 0x00000100
500#define IOACCEL1_CONTROL_ORDEREDQUEUE 0x00000200
501#define IOACCEL1_CONTROL_ACA 0x00000400
502
503#define IOACCEL1_HCFLAGS_CISS_FORMAT 0x0013
504
505#define IOACCEL1_BUSADDR_CMDTYPE 0x00000060
506
Mike Millerb66cc252014-02-18 13:56:04 -0600507struct ioaccel2_sg_element {
Don Brace2b08b3e2015-01-23 16:41:09 -0600508 __le64 address;
509 __le32 length;
Mike Millerb66cc252014-02-18 13:56:04 -0600510 u8 reserved[3];
511 u8 chain_indicator;
512#define IOACCEL2_CHAIN 0x80
513};
514
515/*
516 * SCSI Response Format structure for IO Accelerator Mode 2
517 */
518struct io_accel2_scsi_response {
519 u8 IU_type;
520#define IOACCEL2_IU_TYPE_SRF 0x60
521 u8 reserved1[3];
522 u8 req_id[4]; /* request identifier */
523 u8 reserved2[4];
524 u8 serv_response; /* service response */
525#define IOACCEL2_SERV_RESPONSE_COMPLETE 0x000
526#define IOACCEL2_SERV_RESPONSE_FAILURE 0x001
527#define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE 0x002
528#define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS 0x003
529#define IOACCEL2_SERV_RESPONSE_TMF_REJECTED 0x004
530#define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN 0x005
531 u8 status; /* status */
532#define IOACCEL2_STATUS_SR_TASK_COMP_GOOD 0x00
533#define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND 0x02
534#define IOACCEL2_STATUS_SR_TASK_COMP_BUSY 0x08
535#define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON 0x18
536#define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL 0x28
537#define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED 0x40
Scott Teelc3497752014-02-18 13:56:34 -0600538#define IOACCEL2_STATUS_SR_IOACCEL_DISABLED 0x0E
Joe Handzikc40820d2015-04-23 09:33:32 -0500539#define IOACCEL2_STATUS_SR_IO_ERROR 0x01
540#define IOACCEL2_STATUS_SR_IO_ABORTED 0x02
541#define IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE 0x03
542#define IOACCEL2_STATUS_SR_INVALID_DEVICE 0x04
543#define IOACCEL2_STATUS_SR_UNDERRUN 0x51
544#define IOACCEL2_STATUS_SR_OVERRUN 0x75
Mike Millerb66cc252014-02-18 13:56:04 -0600545 u8 data_present; /* low 2 bits */
546#define IOACCEL2_NO_DATAPRESENT 0x000
547#define IOACCEL2_RESPONSE_DATAPRESENT 0x001
548#define IOACCEL2_SENSE_DATA_PRESENT 0x002
549#define IOACCEL2_RESERVED 0x003
550 u8 sense_data_len; /* sense/response data length */
551 u8 resid_cnt[4]; /* residual count */
552 u8 sense_data_buff[32]; /* sense/response data buffer */
553};
554
Mike Millerb66cc252014-02-18 13:56:04 -0600555/*
556 * Structure for I/O accelerator (mode 2 or m2) commands.
557 * Note that this structure must be 128-byte aligned in size.
558 */
Stephen M. Cameron35d697c2014-05-29 10:52:52 -0500559#define IOACCEL2_COMMANDLIST_ALIGNMENT 128
Mike Millerb66cc252014-02-18 13:56:04 -0600560struct io_accel2_cmd {
561 u8 IU_type; /* IU Type */
Scott Teeldd0e19f2014-02-18 13:57:31 -0600562 u8 direction; /* direction, memtype, and encryption */
563#define IOACCEL2_DIRECTION_MASK 0x03 /* bits 0,1: direction */
564#define IOACCEL2_DIRECTION_MEMTYPE_MASK 0x04 /* bit 2: memtype source/dest */
565 /* 0b=PCIe, 1b=DDR */
566#define IOACCEL2_DIRECTION_ENCRYPT_MASK 0x08 /* bit 3: encryption flag */
567 /* 0=off, 1=on */
Mike Millerb66cc252014-02-18 13:56:04 -0600568 u8 reply_queue; /* Reply Queue ID */
569 u8 reserved1; /* Reserved */
Don Brace2b08b3e2015-01-23 16:41:09 -0600570 __le32 scsi_nexus; /* Device Handle */
571 __le32 Tag; /* cciss tag, lower 4 bytes only */
572 __le32 tweak_lower; /* Encryption tweak, lower 4 bytes */
Mike Millerb66cc252014-02-18 13:56:04 -0600573 u8 cdb[16]; /* SCSI Command Descriptor Block */
574 u8 cciss_lun[8]; /* 8 byte SCSI address */
Don Brace2b08b3e2015-01-23 16:41:09 -0600575 __le32 data_len; /* Total bytes to transfer */
Mike Millerb66cc252014-02-18 13:56:04 -0600576 u8 cmd_priority_task_attr; /* priority and task attrs */
577#define IOACCEL2_PRIORITY_MASK 0x78
578#define IOACCEL2_ATTR_MASK 0x07
579 u8 sg_count; /* Number of sg elements */
Don Brace2b08b3e2015-01-23 16:41:09 -0600580 __le16 dekindex; /* Data encryption key index */
581 __le64 err_ptr; /* Error Pointer */
582 __le32 err_len; /* Error Length*/
583 __le32 tweak_upper; /* Encryption tweak, upper 4 bytes */
Mike Millerb66cc252014-02-18 13:56:04 -0600584 struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES];
585 struct io_accel2_scsi_response error_data;
Stephen M. Cameron35d697c2014-05-29 10:52:52 -0500586} __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
Mike Millerb66cc252014-02-18 13:56:04 -0600587
588/*
589 * defines for Mode 2 command struct
590 * FIXME: this can't be all I need mfm
591 */
592#define IOACCEL2_IU_TYPE 0x40
Scott Teel54b6e9e2014-02-18 13:56:45 -0600593#define IOACCEL2_IU_TMF_TYPE 0x41
Mike Millerb66cc252014-02-18 13:56:04 -0600594#define IOACCEL2_DIR_NO_DATA 0x00
595#define IOACCEL2_DIR_DATA_IN 0x01
596#define IOACCEL2_DIR_DATA_OUT 0x02
Stephen Cameron8be986c2015-04-23 09:34:06 -0500597#define IOACCEL2_TMF_ABORT 0x01
Mike Millerb66cc252014-02-18 13:56:04 -0600598/*
599 * SCSI Task Management Request format for Accelerator Mode 2
600 */
601struct hpsa_tmf_struct {
602 u8 iu_type; /* Information Unit Type */
603 u8 reply_queue; /* Reply Queue ID */
604 u8 tmf; /* Task Management Function */
605 u8 reserved1; /* byte 3 Reserved */
Stephen Cameron8be986c2015-04-23 09:34:06 -0500606 __le32 it_nexus; /* SCSI I-T Nexus */
Mike Millerb66cc252014-02-18 13:56:04 -0600607 u8 lun_id[8]; /* LUN ID for TMF request */
Don Brace2b08b3e2015-01-23 16:41:09 -0600608 __le64 tag; /* cciss tag associated w/ request */
609 __le64 abort_tag; /* cciss tag of SCSI cmd or TMF to abort */
610 __le64 error_ptr; /* Error Pointer */
611 __le32 error_len; /* Error Length */
Stephen Cameron8be986c2015-04-23 09:34:06 -0500612} __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
Mike Millerb66cc252014-02-18 13:56:04 -0600613
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800614/* Configuration Table Structure */
615struct HostWrite {
Don Brace2b08b3e2015-01-23 16:41:09 -0600616 __le32 TransportRequest;
617 __le32 command_pool_addr_hi;
618 __le32 CoalIntDelay;
619 __le32 CoalIntCount;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800620};
621
Don Brace303932f2010-02-04 08:42:40 -0600622#define SIMPLE_MODE 0x02
623#define PERFORMANT_MODE 0x04
624#define MEMQ_MODE 0x08
Matt Gatese1f7de02014-02-18 13:55:17 -0600625#define IOACCEL_MODE_1 0x80
Don Brace303932f2010-02-04 08:42:40 -0600626
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600627#define DRIVER_SUPPORT_UA_ENABLE 0x00000001
628
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800629struct CfgTable {
Don Brace2b08b3e2015-01-23 16:41:09 -0600630 u8 Signature[4];
631 __le32 SpecValence;
632 __le32 TransportSupport;
633 __le32 TransportActive;
634 struct HostWrite HostWrite;
635 __le32 CmdsOutMax;
636 __le32 BusTypes;
637 __le32 TransMethodOffset;
638 u8 ServerName[16];
639 __le32 HeartBeat;
640 __le32 driver_support;
641#define ENABLE_SCSI_PREFETCH 0x100
642#define ENABLE_UNIT_ATTN 0x01
643 __le32 MaxScatterGatherElements;
644 __le32 MaxLogicalUnits;
645 __le32 MaxPhysicalDevices;
646 __le32 MaxPhysicalDrivesPerLogicalUnit;
647 __le32 MaxPerformantModeCommands;
648 __le32 MaxBlockFetch;
649 __le32 PowerConservationSupport;
650 __le32 PowerConservationEnable;
651 __le32 TMFSupportFlags;
Stephen M. Cameron75167d22012-05-01 11:42:51 -0500652 u8 TMFTagMask[8];
653 u8 reserved[0x78 - 0x70];
Don Brace2b08b3e2015-01-23 16:41:09 -0600654 __le32 misc_fw_support; /* offset 0x78 */
655#define MISC_FW_DOORBELL_RESET 0x02
656#define MISC_FW_DOORBELL_RESET2 0x010
657#define MISC_FW_RAID_OFFLOAD_BASIC 0x020
658#define MISC_FW_EVENT_NOTIFY 0x080
Stephen M. Cameron580ada32011-05-03 14:59:10 -0500659 u8 driver_version[32];
Don Brace2b08b3e2015-01-23 16:41:09 -0600660 __le32 max_cached_write_size;
661 u8 driver_scratchpad[16];
662 __le32 max_error_info_length;
663 __le32 io_accel_max_embedded_sg_count;
664 __le32 io_accel_request_size_offset;
665 __le32 event_notify;
666#define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30)
667#define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31)
668 __le32 clear_event_notify;
Don Brace303932f2010-02-04 08:42:40 -0600669};
670
671#define NUM_BLOCKFETCH_ENTRIES 8
672struct TransTable_struct {
Don Brace2b08b3e2015-01-23 16:41:09 -0600673 __le32 BlockFetch[NUM_BLOCKFETCH_ENTRIES];
674 __le32 RepQSize;
675 __le32 RepQCount;
676 __le32 RepQCtrAddrLow32;
677 __le32 RepQCtrAddrHigh32;
Stephen M. Cameronf89439b2014-05-29 10:53:02 -0500678#define MAX_REPLY_QUEUES 64
Matt Gates254f7962012-05-01 11:43:06 -0500679 struct vals32 RepQAddr[MAX_REPLY_QUEUES];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800680};
681
682struct hpsa_pci_info {
683 unsigned char bus;
684 unsigned char dev_fn;
685 unsigned short domain;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600686 u32 board_id;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800687};
688
Don Brace03383732015-01-23 16:43:30 -0600689struct bmic_identify_physical_device {
690 u8 scsi_bus; /* SCSI Bus number on controller */
691 u8 scsi_id; /* SCSI ID on this bus */
692 __le16 block_size; /* sector size in bytes */
693 __le32 total_blocks; /* number for sectors on drive */
694 __le32 reserved_blocks; /* controller reserved (RIS) */
695 u8 model[40]; /* Physical Drive Model */
696 u8 serial_number[40]; /* Drive Serial Number */
697 u8 firmware_revision[8]; /* drive firmware revision */
698 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */
699 u8 compaq_drive_stamp; /* 0 means drive not stamped */
700 u8 last_failure_reason;
701#define BMIC_LAST_FAILURE_TOO_SMALL_IN_LOAD_CONFIG 0x01
702#define BMIC_LAST_FAILURE_ERROR_ERASING_RIS 0x02
703#define BMIC_LAST_FAILURE_ERROR_SAVING_RIS 0x03
704#define BMIC_LAST_FAILURE_FAIL_DRIVE_COMMAND 0x04
705#define BMIC_LAST_FAILURE_MARK_BAD_FAILED 0x05
706#define BMIC_LAST_FAILURE_MARK_BAD_FAILED_IN_FINISH_REMAP 0x06
707#define BMIC_LAST_FAILURE_TIMEOUT 0x07
708#define BMIC_LAST_FAILURE_AUTOSENSE_FAILED 0x08
709#define BMIC_LAST_FAILURE_MEDIUM_ERROR_1 0x09
710#define BMIC_LAST_FAILURE_MEDIUM_ERROR_2 0x0a
711#define BMIC_LAST_FAILURE_NOT_READY_BAD_SENSE 0x0b
712#define BMIC_LAST_FAILURE_NOT_READY 0x0c
713#define BMIC_LAST_FAILURE_HARDWARE_ERROR 0x0d
714#define BMIC_LAST_FAILURE_ABORTED_COMMAND 0x0e
715#define BMIC_LAST_FAILURE_WRITE_PROTECTED 0x0f
716#define BMIC_LAST_FAILURE_SPIN_UP_FAILURE_IN_RECOVER 0x10
717#define BMIC_LAST_FAILURE_REBUILD_WRITE_ERROR 0x11
718#define BMIC_LAST_FAILURE_TOO_SMALL_IN_HOT_PLUG 0x12
719#define BMIC_LAST_FAILURE_BUS_RESET_RECOVERY_ABORTED 0x13
720#define BMIC_LAST_FAILURE_REMOVED_IN_HOT_PLUG 0x14
721#define BMIC_LAST_FAILURE_INIT_REQUEST_SENSE_FAILED 0x15
722#define BMIC_LAST_FAILURE_INIT_START_UNIT_FAILED 0x16
723#define BMIC_LAST_FAILURE_INQUIRY_FAILED 0x17
724#define BMIC_LAST_FAILURE_NON_DISK_DEVICE 0x18
725#define BMIC_LAST_FAILURE_READ_CAPACITY_FAILED 0x19
726#define BMIC_LAST_FAILURE_INVALID_BLOCK_SIZE 0x1a
727#define BMIC_LAST_FAILURE_HOT_PLUG_REQUEST_SENSE_FAILED 0x1b
728#define BMIC_LAST_FAILURE_HOT_PLUG_START_UNIT_FAILED 0x1c
729#define BMIC_LAST_FAILURE_WRITE_ERROR_AFTER_REMAP 0x1d
730#define BMIC_LAST_FAILURE_INIT_RESET_RECOVERY_ABORTED 0x1e
731#define BMIC_LAST_FAILURE_DEFERRED_WRITE_ERROR 0x1f
732#define BMIC_LAST_FAILURE_MISSING_IN_SAVE_RIS 0x20
733#define BMIC_LAST_FAILURE_WRONG_REPLACE 0x21
734#define BMIC_LAST_FAILURE_GDP_VPD_INQUIRY_FAILED 0x22
735#define BMIC_LAST_FAILURE_GDP_MODE_SENSE_FAILED 0x23
736#define BMIC_LAST_FAILURE_DRIVE_NOT_IN_48BIT_MODE 0x24
737#define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_HOT_PLUG 0x25
738#define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_LOAD_CFG 0x26
739#define BMIC_LAST_FAILURE_PROTOCOL_ADAPTER_FAILED 0x27
740#define BMIC_LAST_FAILURE_FAULTY_ID_BAY_EMPTY 0x28
741#define BMIC_LAST_FAILURE_FAULTY_ID_BAY_OCCUPIED 0x29
742#define BMIC_LAST_FAILURE_FAULTY_ID_INVALID_BAY 0x2a
743#define BMIC_LAST_FAILURE_WRITE_RETRIES_FAILED 0x2b
744
745#define BMIC_LAST_FAILURE_SMART_ERROR_REPORTED 0x37
746#define BMIC_LAST_FAILURE_PHY_RESET_FAILED 0x38
747#define BMIC_LAST_FAILURE_ONLY_ONE_CTLR_CAN_SEE_DRIVE 0x40
748#define BMIC_LAST_FAILURE_KC_VOLUME_FAILED 0x41
749#define BMIC_LAST_FAILURE_UNEXPECTED_REPLACEMENT 0x42
750#define BMIC_LAST_FAILURE_OFFLINE_ERASE 0x80
751#define BMIC_LAST_FAILURE_OFFLINE_TOO_SMALL 0x81
752#define BMIC_LAST_FAILURE_OFFLINE_DRIVE_TYPE_MIX 0x82
753#define BMIC_LAST_FAILURE_OFFLINE_ERASE_COMPLETE 0x83
754
755 u8 flags;
756 u8 more_flags;
757 u8 scsi_lun; /* SCSI LUN for phys drive */
758 u8 yet_more_flags;
759 u8 even_more_flags;
760 __le32 spi_speed_rules;/* SPI Speed data:Ultra disable diagnose */
761 u8 phys_connector[2]; /* connector number on controller */
762 u8 phys_box_on_bus; /* phys enclosure this drive resides */
763 u8 phys_bay_in_box; /* phys drv bay this drive resides */
764 __le32 rpm; /* Drive rotational speed in rpm */
765 u8 device_type; /* type of drive */
766 u8 sata_version; /* only valid when drive_type is SATA */
767 __le64 big_total_block_count;
768 __le64 ris_starting_lba;
769 __le32 ris_size;
770 u8 wwid[20];
771 u8 controller_phy_map[32];
772 __le16 phy_count;
773 u8 phy_connected_dev_type[256];
774 u8 phy_to_drive_bay_num[256];
775 __le16 phy_to_attached_dev_index[256];
776 u8 box_index;
777 u8 reserved;
778 __le16 extra_physical_drive_flags;
779#define BMIC_PHYS_DRIVE_SUPPORTS_GAS_GAUGE(idphydrv) \
780 (idphydrv->extra_physical_drive_flags & (1 << 10))
781 u8 negotiated_link_rate[256];
782 u8 phy_to_phy_map[256];
783 u8 redundant_path_present_map;
784 u8 redundant_path_failure_map;
785 u8 active_path_number;
786 __le16 alternate_paths_phys_connector[8];
787 u8 alternate_paths_phys_box_on_port[8];
788 u8 multi_lun_device_lun_count;
789 u8 minimum_good_fw_revision[8];
790 u8 unique_inquiry_bytes[20];
791 u8 current_temperature_degreesC;
792 u8 temperature_threshold_degreesC;
793 u8 max_temperature_degreesC;
794 u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512*2^exp */
795 __le16 current_queue_depth_limit;
796 u8 switch_name[10];
797 __le16 switch_port;
798 u8 alternate_paths_switch_name[40];
799 u8 alternate_paths_switch_port[8];
800 __le16 power_on_hours; /* valid only if gas gauge supported */
801 __le16 percent_endurance_used; /* valid only if gas gauge supported. */
802#define BMIC_PHYS_DRIVE_SSD_WEAROUT(idphydrv) \
803 ((idphydrv->percent_endurance_used & 0x80) || \
804 (idphydrv->percent_endurance_used > 10000))
805 u8 drive_authentication;
806#define BMIC_PHYS_DRIVE_AUTHENTICATED(idphydrv) \
807 (idphydrv->drive_authentication == 0x80)
808 u8 smart_carrier_authentication;
809#define BMIC_SMART_CARRIER_AUTHENTICATION_SUPPORTED(idphydrv) \
810 (idphydrv->smart_carrier_authentication != 0x0)
811#define BMIC_SMART_CARRIER_AUTHENTICATED(idphydrv) \
812 (idphydrv->smart_carrier_authentication == 0x01)
813 u8 smart_carrier_app_fw_version;
814 u8 smart_carrier_bootloader_fw_version;
815 u8 encryption_key_name[64];
816 __le32 misc_drive_flags;
817 __le16 dek_index;
818 u8 padding[112];
819};
820
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800821#pragma pack()
822#endif /* HPSA_CMD_H */