| Pavel Machek | 66101de | 2008-10-01 14:36:56 +0200 | [diff] [blame^] | 1 | // 20031229 Turbo add |
| 2 | #define REG_AGC_CTRL1 0x1000 |
| 3 | #define REG_AGC_CTRL2 0x1004 |
| 4 | #define REG_AGC_CTRL3 0x1008 |
| 5 | #define REG_AGC_CTRL4 0x100C |
| 6 | #define REG_AGC_CTRL5 0x1010 |
| 7 | #define REG_AGC_CTRL6 0x1014 |
| 8 | #define REG_AGC_CTRL7 0x1018 |
| 9 | #define REG_AGC_CTRL8 0x101C |
| 10 | #define REG_AGC_CTRL9 0x1020 |
| 11 | #define REG_AGC_CTRL10 0x1024 |
| 12 | #define REG_CCA_CTRL 0x1028 |
| 13 | #define REG_A_ACQ_CTRL 0x102C |
| 14 | #define REG_B_ACQ_CTRL 0x1030 |
| 15 | #define REG_A_TXRX_CTRL 0x1034 |
| 16 | #define REG_B_TXRX_CTRL 0x1038 |
| 17 | #define REG_A_TX_COEF3 0x103C |
| 18 | #define REG_A_TX_COEF2 0x1040 |
| 19 | #define REG_A_TX_COEF1 0x1044 |
| 20 | #define REG_B_TX_COEF2 0x1048 |
| 21 | #define REG_B_TX_COEF1 0x104C |
| 22 | #define REG_MODE_CTRL 0x1050 |
| 23 | #define REG_CALIB_DATA 0x1054 |
| 24 | #define REG_IQ_ALPHA 0x1058 |
| 25 | #define REG_DC_CANCEL 0x105C |
| 26 | #define REG_WTO_READ 0x1060 |
| 27 | #define REG_OFFSET_READ 0x1064 |
| 28 | #define REG_CALIB_READ1 0x1068 |
| 29 | #define REG_CALIB_READ2 0x106C |
| 30 | #define REG_A_FREQ_EST 0x1070 |
| 31 | |
| 32 | |
| 33 | |
| 34 | |
| 35 | // 20031101 Turbo add |
| 36 | #define MASK_AMER_OFF_REG BIT(31) |
| 37 | |
| 38 | #define MASK_BMER_OFF_REG BIT(31) |
| 39 | |
| 40 | #define MASK_LNA_FIX_GAIN (BIT(3)|BIT(4)) |
| 41 | #define MASK_AGC_FIX BIT(1) |
| 42 | |
| 43 | #define MASK_AGC_FIX_GAIN 0xFF00 |
| 44 | |
| 45 | #define MASK_ADC_DC_CAL_STR BIT(10) |
| 46 | #define MASK_CALIB_START BIT(4) |
| 47 | #define MASK_IQCAL_TONE_SEL (BIT(3)|BIT(2)) |
| 48 | #define MASK_IQCAL_MODE (BIT(1)|BIT(0)) |
| 49 | |
| 50 | #define MASK_TX_CAL_0 0xF0000000 |
| 51 | #define TX_CAL_0_SHIFT 28 |
| 52 | #define MASK_TX_CAL_1 0x0F000000 |
| 53 | #define TX_CAL_1_SHIFT 24 |
| 54 | #define MASK_TX_CAL_2 0x00F00000 |
| 55 | #define TX_CAL_2_SHIFT 20 |
| 56 | #define MASK_TX_CAL_3 0x000F0000 |
| 57 | #define TX_CAL_3_SHIFT 16 |
| 58 | #define MASK_RX_CAL_0 0x0000F000 |
| 59 | #define RX_CAL_0_SHIFT 12 |
| 60 | #define MASK_RX_CAL_1 0x00000F00 |
| 61 | #define RX_CAL_1_SHIFT 8 |
| 62 | #define MASK_RX_CAL_2 0x000000F0 |
| 63 | #define RX_CAL_2_SHIFT 4 |
| 64 | #define MASK_RX_CAL_3 0x0000000F |
| 65 | #define RX_CAL_3_SHIFT 0 |
| 66 | |
| 67 | #define MASK_CANCEL_DC_I 0x3E0 |
| 68 | #define CANCEL_DC_I_SHIFT 5 |
| 69 | #define MASK_CANCEL_DC_Q 0x01F |
| 70 | #define CANCEL_DC_Q_SHIFT 0 |
| 71 | |
| 72 | // LA20040210 kevin |
| 73 | //#define MASK_ADC_DC_CAL_I(x) (((x)&0x1FE00)>>9) |
| 74 | //#define MASK_ADC_DC_CAL_Q(x) ((x)&0x1FF) |
| 75 | #define MASK_ADC_DC_CAL_I(x) (((x)&0x0003FE00)>>9) |
| 76 | #define MASK_ADC_DC_CAL_Q(x) ((x)&0x000001FF) |
| 77 | |
| 78 | // LA20040210 kevin (Turbo has wrong definition) |
| 79 | //#define MASK_IQCAL_TONE_I 0x7FFC000 |
| 80 | //#define SHIFT_IQCAL_TONE_I(x) ((x)>>13) |
| 81 | //#define MASK_IQCAL_TONE_Q 0x1FFF |
| 82 | //#define SHIFT_IQCAL_TONE_Q(x) ((x)>>0) |
| 83 | #define MASK_IQCAL_TONE_I 0x00001FFF |
| 84 | #define SHIFT_IQCAL_TONE_I(x) ((x)>>0) |
| 85 | #define MASK_IQCAL_TONE_Q 0x03FFE000 |
| 86 | #define SHIFT_IQCAL_TONE_Q(x) ((x)>>13) |
| 87 | |
| 88 | // LA20040210 kevin (Turbo has wrong definition) |
| 89 | //#define MASK_IQCAL_IMAGE_I 0x7FFC000 |
| 90 | //#define SHIFT_IQCAL_IMAGE_I(x) ((x)>>13) |
| 91 | //#define MASK_IQCAL_IMAGE_Q 0x1FFF |
| 92 | //#define SHIFT_IQCAL_IMAGE_Q(x) ((x)>>0) |
| 93 | |
| 94 | //#define MASK_IQCAL_IMAGE_I 0x00001FFF |
| 95 | //#define SHIFT_IQCAL_IMAGE_I(x) ((x)>>0) |
| 96 | //#define MASK_IQCAL_IMAGE_Q 0x03FFE000 |
| 97 | //#define SHIFT_IQCAL_IMAGE_Q(x) ((x)>>13) |
| 98 | |
| 99 | void phy_set_rf_data( phw_data_t pHwData, u32 index, u32 value ); |
| 100 | #define phy_init_rf( _A ) //RFSynthesizer_initial( _A ) |
| 101 | |