Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1 | MSM USB PHY transceivers |
| 2 | |
Devdutt Patnaik | 9e653b1 | 2017-05-30 22:13:22 -0700 | [diff] [blame] | 3 | HSUSB PHY |
| 4 | |
| 5 | Required properties: |
| 6 | - compatible: Should be "qcom,usb-hsphy-snps-femto" |
| 7 | - reg: Address and length of the register set for the device |
| 8 | Required regs are: |
| 9 | "hsusb_phy_base" : the base register for the PHY |
| 10 | - <supply-name>-supply: phandle to the regulator device tree node |
| 11 | Required "supply-name" examples are: |
| 12 | "vdd" : vdd supply for HSPHY digital circuit operation |
| 13 | "vdda18" : 1.8v supply for HSPHY |
| 14 | "vdda33" : 3.3v supply for HSPHY |
| 15 | - clocks: a list of phandles to the PHY clocks. Use as per |
| 16 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 17 | - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" |
| 18 | property. "ref_clk_src" is a mandatory clock. |
| 19 | - qcom,vdd-voltage-level: This property must be a list of three integer |
| 20 | values (no, min, max) where each value represents either a voltage in |
| 21 | microvolts or a value corresponding to voltage corner |
| 22 | - resets: reset specifier pair consists of phandle for the reset controller |
| 23 | and reset lines used by this controller. |
| 24 | - reset-names: reset signal name strings sorted in the same order as the resets |
| 25 | property. |
| 26 | |
| 27 | Example: |
| 28 | hsphy@f9200000 { |
| 29 | compatible = "qcom,usb-hsphy-snps-femto"; |
| 30 | reg = <0xff1000 0x400>; |
| 31 | vdd-supply = <&pm8841_s2_corner>; |
| 32 | vdda18-supply = <&pm8941_l6>; |
| 33 | vdda33-supply = <&pm8941_l24>; |
| 34 | qcom,vdd-voltage-level = <0 872000 872000>; |
| 35 | }; |
| 36 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 37 | SSUSB-QMP PHY |
| 38 | |
| 39 | Required properties: |
| 40 | - compatible: Should be "qcom,usb-ssphy-qmp", "qcom,usb-ssphy-qmp-v1" or |
Hemant Kumar | bce97a2 | 2017-12-07 16:17:38 -0800 | [diff] [blame] | 41 | "qcom,usb-ssphy-qmp-v2" or "qcom,usb-ssphy-qmp-usb3-or-dp" or |
| 42 | "qcom,usb-ssphy-qmp-dp-combo" |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 43 | - reg: Address and length of the register set for the device |
| 44 | Required regs are: |
| 45 | "qmp_phy_base" : QMP PHY Base register set. |
| 46 | - "vls_clamp_reg" : top-level CSR register to be written to enable phy vls |
Mayank Rana | 4c40cd9 | 2017-03-21 14:40:55 -0700 | [diff] [blame] | 47 | clamp which allows phy to detect autonomous mode. (optional for USB DP PHY) |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 48 | - <supply-name>-supply: phandle to the regulator device tree node |
| 49 | Required "supply-name" examples are: |
| 50 | "vdd" : vdd supply for SSPHY digital circuit operation |
| 51 | "core" : high-voltage analog supply for SSPHY |
| 52 | - clocks: a list of phandles to the PHY clocks. Use as per |
| 53 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 54 | - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" |
| 55 | property. Required clocks are "aux_clk" and "pipe_clk". |
| 56 | - qcom,vdd-voltage-level: This property must be a list of three integer |
| 57 | values (no, min, max) where each value represents either a voltage in |
| 58 | microvolts or a value corresponding to voltage corner |
| 59 | - qcom,qmp-phy-init-seq: QMP PHY initialization sequence with reg offset, its |
| 60 | value, delay after register write. It is not must property to have for emulation. |
| 61 | - qcom,qmp-phy-reg-offset: Provides important phy register offsets in an order |
Mayank Rana | 4c40cd9 | 2017-03-21 14:40:55 -0700 | [diff] [blame] | 62 | defined in the phy driver. |
| 63 | Provide below mentioned register offsets in order for non USB DP combo PHY: |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 64 | USB3_PHY_PCS_STATUS, |
| 65 | USB3_PHY_AUTONOMOUS_MODE_CTRL, |
| 66 | USB3_PHY_LFPS_RXTERM_IRQ_CLEAR, |
| 67 | USB3_PHY_POWER_DOWN_CONTROL, |
| 68 | USB3_PHY_SW_RESET, |
| 69 | USB3_PHY_START |
Mayank Rana | 4c40cd9 | 2017-03-21 14:40:55 -0700 | [diff] [blame] | 70 | |
| 71 | In addion to above following set of registers offset needed for USB DP combo PHY in mentioned order: |
| 72 | USB3_DP_DP_PHY_PD_CTL, |
| 73 | USB3_DP_COM_POWER_DOWN_CTRL, |
| 74 | USB3_DP_COM_SW_RESET, |
| 75 | USB3_DP_COM_RESET_OVRD_CTRL, |
| 76 | USB3_DP_COM_PHY_MODE_CTRL, |
| 77 | USB3_DP_COM_TYPEC_CTRL, |
| 78 | USB3_DP_COM_SWI_CTRL, |
| 79 | USB3_PCS_MISC_CLAMP_ENABLE |
| 80 | |
| 81 | Optional register for configuring USB Type-C port select if available: |
| 82 | USB3_PHY_PCS_MISC_TYPEC_CTRL |
| 83 | |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 84 | - resets: reset specifier pair consists of phandle for the reset controller |
| 85 | and reset lines used by this controller. |
| 86 | - reset-names: reset signal name strings sorted in the same order as the resets |
| 87 | property. |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 88 | |
| 89 | Optional properties: |
| 90 | - reg: Additional register set of address and length to control QMP PHY are: |
| 91 | "tcsr_usb3_dp_phymode" : top-level CSR register to be written to select |
| 92 | super speed usb qmp phy. |
| 93 | - clocks: a list of phandles to the PHY clocks. Use as per |
| 94 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 95 | - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" |
Mayank Rana | 561d044 | 2017-03-16 18:19:14 -0700 | [diff] [blame] | 96 | property. "cfg_ahb_clk" and "com_aux_clk" are an optional clocks. |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 97 | - qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to |
| 98 | the USB PHY and the controller must rely on external VBUS notification in |
| 99 | order to manually relay the notification to the SSPHY. |
| 100 | - qcom,emulation: Indicates that we are running on emulation platform. |
| 101 | - qcom,core-voltage-level: This property must be a list of three integer |
| 102 | values (no, min, max) where each value represents either a voltage in |
| 103 | microvolts or a value corresponding to voltage corner. |
| 104 | |
| 105 | Example: |
| 106 | ssphy0: ssphy@f9b38000 { |
| 107 | compatible = "qcom,usb-ssphy-qmp"; |
| 108 | reg = <0xf9b38000 0x16c>, |
| 109 | <0x01947244 0x4>; |
| 110 | reg-names = "qmp_phy_base", |
| 111 | "vls_clamp_reg"; |
| 112 | vdd-supply = <&pmd9635_l4>; |
| 113 | vdda18-supply = <&pmd9635_l8>; |
| 114 | qcom,vdd-voltage-level = <0 900000 1050000>; |
| 115 | qcom,vbus-valid-override; |
| 116 | |
| 117 | clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>, |
| 118 | <&clock_gcc clk_gcc_usb3_phy_pipe_clk>, |
| 119 | <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 120 | <&clock_gcc clk_ln_bb_clk1>, |
| 121 | <&clock_gcc clk_gcc_usb3_clkref_clk>; |
| 122 | |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 123 | clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", |
| 124 | "ref_clk_src", "ref_clk"; |
| 125 | |
| 126 | resets = <&clock_gcc GCC_USB3_PHY_BCR>, |
| 127 | <&clock_gcc GCC_USB3PHY_PHY_BCR>; |
| 128 | reset-names = "phy_reset", |
| 129 | "phy_phy_reset"; |
| 130 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 131 | }; |
| 132 | |
| 133 | QUSB2 High-Speed PHY |
| 134 | |
| 135 | Required properties: |
| 136 | - compatible: Should be "qcom,qusb2phy" or "qcom,qusb2phy-v2" |
| 137 | - reg: Address and length of the QUSB2 PHY register set |
| 138 | - reg-names: Should be "qusb_phy_base". |
| 139 | - <supply-name>-supply: phandle to the regulator device tree node |
| 140 | Required supplies are: |
| 141 | "vdd" : vdd supply for digital circuit operation |
| 142 | "vdda18" : 1.8v high-voltage analog supply |
| 143 | "vdda33" : 3.3v high-voltage analog supply |
Devdutt Patnaik | 1c03dfd | 2017-03-19 23:38:43 -0700 | [diff] [blame] | 144 | - clocks: a list of phandles to the PHY clocks. Use as per |
| 145 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 146 | - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" |
| 147 | property. "ref_clk_src" is a mandatory clock. |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 148 | - qcom,vdd-voltage-level: This property must be a list of three integer |
| 149 | values (no, min, max) where each value represents either a voltage in |
| 150 | microvolts or a value corresponding to voltage corner |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 151 | - phy_type: Should be one of "ulpi" or "utmi". ChipIdea core uses "ulpi" mode. |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 152 | - resets: reset specifier pair consists of phandle for the reset controller |
| 153 | and reset lines used by this controller. |
| 154 | - reset-names: reset signal name strings sorted in the same order as the resets |
| 155 | property. |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 156 | - qcom,qusb-phy-reg-offset: Provides important phy register offsets in an order defined in phy driver. |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 157 | |
| 158 | Optional properties: |
| 159 | - reg-names: Additional registers corresponding with the following: |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 160 | "efuse_addr": EFUSE address to read and update analog tune parameter. |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 161 | "emu_phy_base" : phy base address used for programming emulation target phy. |
| 162 | "ref_clk_addr" : ref_clk bcr address used for on/off ref_clk before reset. |
Chandana Kishori Chiluveru | 94bd075 | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 163 | "tcsr_clamp_dig_n" : To enable/disable digital clamp to the phy. When |
| 164 | de-asserted, it will prevent random leakage from qusb2 phy resulting from |
| 165 | out of sequence turn on/off of 1p8, 3p3 and DVDD regulators. |
Mayank Rana | 547e24c | 2017-11-01 15:47:04 -0700 | [diff] [blame] | 166 | "refgen_north_bg_reg" : address used to read REFGEN status for overriding QUSB PHY register. |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 167 | - clocks: a list of phandles to the PHY clocks. Use as per |
| 168 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 169 | - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" |
Devdutt Patnaik | 1c03dfd | 2017-03-19 23:38:43 -0700 | [diff] [blame] | 170 | property. "cfg_ahb_clk" and "ref_clk" are optional clocks. |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 171 | - qcom,qusb-phy-init-seq: QUSB PHY initialization sequence with value,reg pair. |
| 172 | - qcom,qusb-phy-host-init-seq: QUSB PHY initialization sequence for host mode |
| 173 | with value,reg pair. |
| 174 | - qcom,emu-init-seq : emulation initialization sequence with value,reg pair. |
| 175 | - qcom,phy-pll-reset-seq : emulation PLL reset sequence with value,reg pair. |
| 176 | - qcom,emu-dcm-reset-seq : emulation DCM reset sequence with value,reg pair. |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 177 | - qcom,efuse-bit-pos: start bit position within EFUSE register |
| 178 | - qcom,efuse-num-bits: Number of bits to read from EFUSE register |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 179 | - qcom,emulation: Indicates that we are running on emulation platform. |
| 180 | - qcom,hold-reset: Indicates that hold QUSB PHY into reset state. |
| 181 | - qcom,phy-clk-scheme: Should be one of "cml" or "cmos" if ref_clk_addr is provided. |
| 182 | - qcom,major-rev: provide major revision number to differentiate power up sequence. default is 2.0 |
Hemant Kumar | 2bb3bdf | 2017-11-22 13:53:08 -0800 | [diff] [blame] | 183 | - pinctrl-names/pinctrl-0/1: The GPIOs configured as output function. Names represents "active" |
| 184 | state when attached in host mode and "suspend" state when detached. |
Vijayavardhan Vennapusa | d5954b9 | 2017-08-18 11:59:02 +0530 | [diff] [blame] | 185 | - qcom,tune2-efuse-correction: The value to be adjusted from fused value for |
| 186 | improved rise/fall times. |
Pratham Pratap | 945af2a | 2018-01-24 18:29:33 +0530 | [diff] [blame] | 187 | - nvmem-cells: specifies the handle to represent the SoC revision. |
| 188 | usually it is defined by qfprom device node. |
| 189 | - nvmem-cell-names: specifies the given nvmem cell name as defined in |
| 190 | qfprom node. |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 191 | |
| 192 | Example: |
| 193 | qusb_phy: qusb@f9b39000 { |
| 194 | compatible = "qcom,qusb2phy"; |
| 195 | reg = <0x00079000 0x7000>; |
| 196 | reg-names = "qusb_phy_base"; |
| 197 | vdd-supply = <&pm8994_s2_corner>; |
| 198 | vdda18-supply = <&pm8994_l6>; |
| 199 | vdda33-supply = <&pm8994_l24>; |
| 200 | qcom,vdd-voltage-level = <1 5 7>; |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 201 | qcom,qusb-phy-reg-offset = |
| 202 | <0x240 /* QUSB2PHY_PORT_TUNE1 */ |
| 203 | 0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */ |
| 204 | 0x210 /* QUSB2PHY_PWR_CTRL1 */ |
| 205 | 0x230 /* QUSB2PHY_INTR_CTRL */ |
| 206 | 0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */ |
Mayank Rana | 129111e | 2017-11-01 15:31:22 -0700 | [diff] [blame] | 207 | 0x254 /* QUSB2PHY_TEST1 */ |
| 208 | 0x198>; /* QUSB2PHY_PLL_BIAS_CONTROL_2 */ |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 209 | qcom,efuse-bit-pos = <21>; |
| 210 | qcom,efuse-num-bits = <3>; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 211 | |
| 212 | clocks = <&clock_rpm clk_ln_bb_clk>, |
| 213 | <&clock_gcc clk_gcc_rx2_usb1_clkref_clk>, |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 214 | <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>; |
| 215 | clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk"; |
| 216 | resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; |
| 217 | reset-names = "phy_reset"; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 218 | }; |