Magnus Damm | eccf060 | 2013-03-26 10:34:24 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Source for the r8a73a4 SoC |
| 3 | * |
| 4 | * Copyright (C) 2013 Renesas Solutions Corp. |
| 5 | * Copyright (C) 2013 Magnus Damm |
| 6 | * |
| 7 | * This file is licensed under the terms of the GNU General Public License |
| 8 | * version 2. This program is licensed "as is" without any warranty of any |
| 9 | * kind, whether express or implied. |
| 10 | */ |
| 11 | |
Ulrich Hecht | a76809a | 2015-01-20 13:51:39 +0100 | [diff] [blame] | 12 | #include <dt-bindings/clock/r8a73a4-clock.h> |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 14 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | |
Magnus Damm | eccf060 | 2013-03-26 10:34:24 +0900 | [diff] [blame] | 16 | / { |
| 17 | compatible = "renesas,r8a73a4"; |
| 18 | interrupt-parent = <&gic>; |
Takashi Yoshii | 26a0d2d | 2013-03-29 16:45:56 +0900 | [diff] [blame] | 19 | #address-cells = <2>; |
| 20 | #size-cells = <2>; |
Magnus Damm | eccf060 | 2013-03-26 10:34:24 +0900 | [diff] [blame] | 21 | |
| 22 | cpus { |
| 23 | #address-cells = <1>; |
| 24 | #size-cells = <0>; |
| 25 | |
| 26 | cpu0: cpu@0 { |
| 27 | device_type = "cpu"; |
| 28 | compatible = "arm,cortex-a15"; |
| 29 | reg = <0>; |
| 30 | clock-frequency = <1500000000>; |
| 31 | }; |
| 32 | }; |
| 33 | |
Magnus Damm | eccf060 | 2013-03-26 10:34:24 +0900 | [diff] [blame] | 34 | timer { |
| 35 | compatible = "arm,armv7-timer"; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 36 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 37 | <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 38 | <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 39 | <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
Magnus Damm | eccf060 | 2013-03-26 10:34:24 +0900 | [diff] [blame] | 40 | }; |
Magnus Damm | 984ca29 | 2013-03-26 10:34:42 +0900 | [diff] [blame] | 41 | |
Geert Uytterhoeven | 35dd549 | 2015-01-14 12:13:00 +0100 | [diff] [blame] | 42 | dbsc1: memory-controller@e6790000 { |
| 43 | compatible = "renesas,dbsc-r8a73a4"; |
| 44 | reg = <0 0xe6790000 0 0x10000>; |
| 45 | }; |
| 46 | |
| 47 | dbsc2: memory-controller@e67a0000 { |
| 48 | compatible = "renesas,dbsc-r8a73a4"; |
| 49 | reg = <0 0xe67a0000 0 0x10000>; |
| 50 | }; |
| 51 | |
Ulrich Hecht | 7300505 | 2014-09-25 10:32:14 +0900 | [diff] [blame] | 52 | dmac: dma-multiplexer { |
| 53 | compatible = "renesas,shdma-mux"; |
| 54 | #dma-cells = <1>; |
| 55 | dma-channels = <20>; |
| 56 | dma-requests = <256>; |
| 57 | #address-cells = <2>; |
| 58 | #size-cells = <2>; |
| 59 | ranges; |
| 60 | |
| 61 | dma0: dma-controller@e6700020 { |
| 62 | compatible = "renesas,shdma-r8a73a4"; |
| 63 | reg = <0 0xe6700020 0 0x89e0>; |
| 64 | interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH |
| 65 | 0 200 IRQ_TYPE_LEVEL_HIGH |
| 66 | 0 201 IRQ_TYPE_LEVEL_HIGH |
| 67 | 0 202 IRQ_TYPE_LEVEL_HIGH |
| 68 | 0 203 IRQ_TYPE_LEVEL_HIGH |
| 69 | 0 204 IRQ_TYPE_LEVEL_HIGH |
| 70 | 0 205 IRQ_TYPE_LEVEL_HIGH |
| 71 | 0 206 IRQ_TYPE_LEVEL_HIGH |
| 72 | 0 207 IRQ_TYPE_LEVEL_HIGH |
| 73 | 0 208 IRQ_TYPE_LEVEL_HIGH |
| 74 | 0 209 IRQ_TYPE_LEVEL_HIGH |
| 75 | 0 210 IRQ_TYPE_LEVEL_HIGH |
| 76 | 0 211 IRQ_TYPE_LEVEL_HIGH |
| 77 | 0 212 IRQ_TYPE_LEVEL_HIGH |
| 78 | 0 213 IRQ_TYPE_LEVEL_HIGH |
| 79 | 0 214 IRQ_TYPE_LEVEL_HIGH |
| 80 | 0 215 IRQ_TYPE_LEVEL_HIGH |
| 81 | 0 216 IRQ_TYPE_LEVEL_HIGH |
| 82 | 0 217 IRQ_TYPE_LEVEL_HIGH |
| 83 | 0 218 IRQ_TYPE_LEVEL_HIGH |
| 84 | 0 219 IRQ_TYPE_LEVEL_HIGH>; |
| 85 | interrupt-names = "error", |
| 86 | "ch0", "ch1", "ch2", "ch3", |
| 87 | "ch4", "ch5", "ch6", "ch7", |
| 88 | "ch8", "ch9", "ch10", "ch11", |
| 89 | "ch12", "ch13", "ch14", "ch15", |
| 90 | "ch16", "ch17", "ch18", "ch19"; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 91 | clocks = <&mstp2_clks R8A73A4_CLK_DMAC>; |
Ulrich Hecht | 7300505 | 2014-09-25 10:32:14 +0900 | [diff] [blame] | 92 | }; |
| 93 | }; |
| 94 | |
| 95 | pfc: pfc@e6050000 { |
| 96 | compatible = "renesas,pfc-r8a73a4"; |
| 97 | reg = <0 0xe6050000 0 0x9000>; |
| 98 | gpio-controller; |
| 99 | #gpio-cells = <2>; |
| 100 | interrupts-extended = |
| 101 | <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, |
| 102 | <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, |
| 103 | <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, |
| 104 | <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, |
| 105 | <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, |
| 106 | <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, |
| 107 | <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, |
| 108 | <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, |
| 109 | <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, |
| 110 | <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, |
| 111 | <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, |
| 112 | <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, |
| 113 | <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, |
| 114 | <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, |
| 115 | <&irqc1 24 0>, <&irqc1 25 0>; |
| 116 | }; |
| 117 | |
| 118 | i2c5: i2c@e60b0000 { |
| 119 | #address-cells = <1>; |
| 120 | #size-cells = <0>; |
Geert Uytterhoeven | 7e9ad4d | 2014-11-06 12:52:10 +0100 | [diff] [blame] | 121 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
Ulrich Hecht | 7300505 | 2014-09-25 10:32:14 +0900 | [diff] [blame] | 122 | reg = <0 0xe60b0000 0 0x428>; |
| 123 | interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 124 | clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; |
Simon Horman | f7b6523 | 2014-07-07 09:54:36 +0200 | [diff] [blame] | 125 | |
| 126 | status = "disabled"; |
| 127 | }; |
| 128 | |
| 129 | cmt1: timer@e6130000 { |
Geert Uytterhoeven | 2cd823f | 2014-10-24 13:36:02 +0200 | [diff] [blame] | 130 | compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; |
Simon Horman | f7b6523 | 2014-07-07 09:54:36 +0200 | [diff] [blame] | 131 | reg = <0 0xe6130000 0 0x1004>; |
| 132 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 133 | clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; |
| 134 | clock-names = "fck"; |
Simon Horman | f7b6523 | 2014-07-07 09:54:36 +0200 | [diff] [blame] | 135 | |
| 136 | renesas,channels-mask = <0xff>; |
| 137 | |
Ulrich Hecht | 7300505 | 2014-09-25 10:32:14 +0900 | [diff] [blame] | 138 | status = "disabled"; |
| 139 | }; |
| 140 | |
Magnus Damm | 984ca29 | 2013-03-26 10:34:42 +0900 | [diff] [blame] | 141 | irqc0: interrupt-controller@e61c0000 { |
Geert Uytterhoeven | 34abee3 | 2014-09-15 12:21:17 +0200 | [diff] [blame] | 142 | compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; |
Magnus Damm | 984ca29 | 2013-03-26 10:34:42 +0900 | [diff] [blame] | 143 | #interrupt-cells = <2>; |
| 144 | interrupt-controller; |
Takashi Yoshii | 26a0d2d | 2013-03-29 16:45:56 +0900 | [diff] [blame] | 145 | reg = <0 0xe61c0000 0 0x200>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 146 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
| 147 | <0 1 IRQ_TYPE_LEVEL_HIGH>, |
| 148 | <0 2 IRQ_TYPE_LEVEL_HIGH>, |
| 149 | <0 3 IRQ_TYPE_LEVEL_HIGH>, |
| 150 | <0 4 IRQ_TYPE_LEVEL_HIGH>, |
| 151 | <0 5 IRQ_TYPE_LEVEL_HIGH>, |
| 152 | <0 6 IRQ_TYPE_LEVEL_HIGH>, |
| 153 | <0 7 IRQ_TYPE_LEVEL_HIGH>, |
| 154 | <0 8 IRQ_TYPE_LEVEL_HIGH>, |
| 155 | <0 9 IRQ_TYPE_LEVEL_HIGH>, |
| 156 | <0 10 IRQ_TYPE_LEVEL_HIGH>, |
| 157 | <0 11 IRQ_TYPE_LEVEL_HIGH>, |
| 158 | <0 12 IRQ_TYPE_LEVEL_HIGH>, |
| 159 | <0 13 IRQ_TYPE_LEVEL_HIGH>, |
| 160 | <0 14 IRQ_TYPE_LEVEL_HIGH>, |
| 161 | <0 15 IRQ_TYPE_LEVEL_HIGH>, |
| 162 | <0 16 IRQ_TYPE_LEVEL_HIGH>, |
| 163 | <0 17 IRQ_TYPE_LEVEL_HIGH>, |
| 164 | <0 18 IRQ_TYPE_LEVEL_HIGH>, |
| 165 | <0 19 IRQ_TYPE_LEVEL_HIGH>, |
| 166 | <0 20 IRQ_TYPE_LEVEL_HIGH>, |
| 167 | <0 21 IRQ_TYPE_LEVEL_HIGH>, |
| 168 | <0 22 IRQ_TYPE_LEVEL_HIGH>, |
| 169 | <0 23 IRQ_TYPE_LEVEL_HIGH>, |
| 170 | <0 24 IRQ_TYPE_LEVEL_HIGH>, |
| 171 | <0 25 IRQ_TYPE_LEVEL_HIGH>, |
| 172 | <0 26 IRQ_TYPE_LEVEL_HIGH>, |
| 173 | <0 27 IRQ_TYPE_LEVEL_HIGH>, |
| 174 | <0 28 IRQ_TYPE_LEVEL_HIGH>, |
| 175 | <0 29 IRQ_TYPE_LEVEL_HIGH>, |
| 176 | <0 30 IRQ_TYPE_LEVEL_HIGH>, |
| 177 | <0 31 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | 984ca29 | 2013-03-26 10:34:42 +0900 | [diff] [blame] | 178 | }; |
| 179 | |
| 180 | irqc1: interrupt-controller@e61c0200 { |
Geert Uytterhoeven | 34abee3 | 2014-09-15 12:21:17 +0200 | [diff] [blame] | 181 | compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; |
Magnus Damm | 984ca29 | 2013-03-26 10:34:42 +0900 | [diff] [blame] | 182 | #interrupt-cells = <2>; |
| 183 | interrupt-controller; |
Takashi Yoshii | 26a0d2d | 2013-03-29 16:45:56 +0900 | [diff] [blame] | 184 | reg = <0 0xe61c0200 0 0x200>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 185 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, |
| 186 | <0 33 IRQ_TYPE_LEVEL_HIGH>, |
| 187 | <0 34 IRQ_TYPE_LEVEL_HIGH>, |
| 188 | <0 35 IRQ_TYPE_LEVEL_HIGH>, |
| 189 | <0 36 IRQ_TYPE_LEVEL_HIGH>, |
| 190 | <0 37 IRQ_TYPE_LEVEL_HIGH>, |
| 191 | <0 38 IRQ_TYPE_LEVEL_HIGH>, |
| 192 | <0 39 IRQ_TYPE_LEVEL_HIGH>, |
| 193 | <0 40 IRQ_TYPE_LEVEL_HIGH>, |
| 194 | <0 41 IRQ_TYPE_LEVEL_HIGH>, |
| 195 | <0 42 IRQ_TYPE_LEVEL_HIGH>, |
| 196 | <0 43 IRQ_TYPE_LEVEL_HIGH>, |
| 197 | <0 44 IRQ_TYPE_LEVEL_HIGH>, |
| 198 | <0 45 IRQ_TYPE_LEVEL_HIGH>, |
| 199 | <0 46 IRQ_TYPE_LEVEL_HIGH>, |
| 200 | <0 47 IRQ_TYPE_LEVEL_HIGH>, |
| 201 | <0 48 IRQ_TYPE_LEVEL_HIGH>, |
| 202 | <0 49 IRQ_TYPE_LEVEL_HIGH>, |
| 203 | <0 50 IRQ_TYPE_LEVEL_HIGH>, |
| 204 | <0 51 IRQ_TYPE_LEVEL_HIGH>, |
| 205 | <0 52 IRQ_TYPE_LEVEL_HIGH>, |
| 206 | <0 53 IRQ_TYPE_LEVEL_HIGH>, |
| 207 | <0 54 IRQ_TYPE_LEVEL_HIGH>, |
| 208 | <0 55 IRQ_TYPE_LEVEL_HIGH>, |
| 209 | <0 56 IRQ_TYPE_LEVEL_HIGH>, |
| 210 | <0 57 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | 984ca29 | 2013-03-26 10:34:42 +0900 | [diff] [blame] | 211 | }; |
| 212 | |
Kuninori Morimoto | c91cf2f | 2013-03-25 23:18:15 -0700 | [diff] [blame] | 213 | thermal@e61f0000 { |
Geert Uytterhoeven | a2cfaa7 | 2014-08-28 10:20:39 +0200 | [diff] [blame] | 214 | compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; |
Takashi Yoshii | 26a0d2d | 2013-03-29 16:45:56 +0900 | [diff] [blame] | 215 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, |
| 216 | <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 217 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 218 | clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; |
Kuninori Morimoto | c91cf2f | 2013-03-25 23:18:15 -0700 | [diff] [blame] | 219 | }; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 220 | |
| 221 | i2c0: i2c@e6500000 { |
| 222 | #address-cells = <1>; |
| 223 | #size-cells = <0>; |
Geert Uytterhoeven | 7e9ad4d | 2014-11-06 12:52:10 +0100 | [diff] [blame] | 224 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 225 | reg = <0 0xe6500000 0 0x428>; |
Laurent Pinchart | d6dd131 | 2013-11-28 17:22:13 +0100 | [diff] [blame] | 226 | interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 227 | clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; |
Guennadi Liakhovetski | eda3a4f | 2013-09-26 13:06:01 +0200 | [diff] [blame] | 228 | status = "disabled"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 229 | }; |
| 230 | |
| 231 | i2c1: i2c@e6510000 { |
| 232 | #address-cells = <1>; |
| 233 | #size-cells = <0>; |
Geert Uytterhoeven | 7e9ad4d | 2014-11-06 12:52:10 +0100 | [diff] [blame] | 234 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 235 | reg = <0 0xe6510000 0 0x428>; |
Laurent Pinchart | d6dd131 | 2013-11-28 17:22:13 +0100 | [diff] [blame] | 236 | interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 237 | clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; |
Guennadi Liakhovetski | eda3a4f | 2013-09-26 13:06:01 +0200 | [diff] [blame] | 238 | status = "disabled"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 239 | }; |
| 240 | |
| 241 | i2c2: i2c@e6520000 { |
| 242 | #address-cells = <1>; |
| 243 | #size-cells = <0>; |
Geert Uytterhoeven | 7e9ad4d | 2014-11-06 12:52:10 +0100 | [diff] [blame] | 244 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 245 | reg = <0 0xe6520000 0 0x428>; |
Laurent Pinchart | d6dd131 | 2013-11-28 17:22:13 +0100 | [diff] [blame] | 246 | interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 247 | clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; |
Guennadi Liakhovetski | eda3a4f | 2013-09-26 13:06:01 +0200 | [diff] [blame] | 248 | status = "disabled"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 249 | }; |
| 250 | |
| 251 | i2c3: i2c@e6530000 { |
| 252 | #address-cells = <1>; |
| 253 | #size-cells = <0>; |
Geert Uytterhoeven | 7e9ad4d | 2014-11-06 12:52:10 +0100 | [diff] [blame] | 254 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 255 | reg = <0 0xe6530000 0 0x428>; |
Laurent Pinchart | d6dd131 | 2013-11-28 17:22:13 +0100 | [diff] [blame] | 256 | interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 257 | clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; |
Guennadi Liakhovetski | eda3a4f | 2013-09-26 13:06:01 +0200 | [diff] [blame] | 258 | status = "disabled"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 259 | }; |
| 260 | |
| 261 | i2c4: i2c@e6540000 { |
| 262 | #address-cells = <1>; |
| 263 | #size-cells = <0>; |
Geert Uytterhoeven | 7e9ad4d | 2014-11-06 12:52:10 +0100 | [diff] [blame] | 264 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 265 | reg = <0 0xe6540000 0 0x428>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 266 | interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 267 | clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; |
Guennadi Liakhovetski | eda3a4f | 2013-09-26 13:06:01 +0200 | [diff] [blame] | 268 | status = "disabled"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 269 | }; |
| 270 | |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 271 | i2c6: i2c@e6550000 { |
| 272 | #address-cells = <1>; |
| 273 | #size-cells = <0>; |
Geert Uytterhoeven | 7e9ad4d | 2014-11-06 12:52:10 +0100 | [diff] [blame] | 274 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 275 | reg = <0 0xe6550000 0 0x428>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 276 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 277 | clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; |
Guennadi Liakhovetski | eda3a4f | 2013-09-26 13:06:01 +0200 | [diff] [blame] | 278 | status = "disabled"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 279 | }; |
| 280 | |
| 281 | i2c7: i2c@e6560000 { |
| 282 | #address-cells = <1>; |
| 283 | #size-cells = <0>; |
Geert Uytterhoeven | 7e9ad4d | 2014-11-06 12:52:10 +0100 | [diff] [blame] | 284 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 285 | reg = <0 0xe6560000 0 0x428>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 286 | interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 287 | clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; |
Guennadi Liakhovetski | eda3a4f | 2013-09-26 13:06:01 +0200 | [diff] [blame] | 288 | status = "disabled"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 289 | }; |
| 290 | |
| 291 | i2c8: i2c@e6570000 { |
| 292 | #address-cells = <1>; |
| 293 | #size-cells = <0>; |
Geert Uytterhoeven | 7e9ad4d | 2014-11-06 12:52:10 +0100 | [diff] [blame] | 294 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 295 | reg = <0 0xe6570000 0 0x428>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 296 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 297 | clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; |
Guennadi Liakhovetski | eda3a4f | 2013-09-26 13:06:01 +0200 | [diff] [blame] | 298 | status = "disabled"; |
Guennadi Liakhovetski | f98c106 | 2013-06-27 11:47:57 +0200 | [diff] [blame] | 299 | }; |
Guennadi Liakhovetski | 369ee2d | 2013-07-08 17:54:45 +0200 | [diff] [blame] | 300 | |
Ulrich Hecht | 0b3a0ef | 2014-11-04 17:21:24 +0100 | [diff] [blame] | 301 | scifb0: serial@e6c20000 { |
Simon Horman | 94f1a03 | 2014-07-07 09:54:33 +0200 | [diff] [blame] | 302 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
| 303 | reg = <0 0xe6c20000 0 0x100>; |
| 304 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 305 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; |
| 306 | clock-names = "sci_ick"; |
Simon Horman | 94f1a03 | 2014-07-07 09:54:33 +0200 | [diff] [blame] | 307 | status = "disabled"; |
| 308 | }; |
| 309 | |
Ulrich Hecht | 0b3a0ef | 2014-11-04 17:21:24 +0100 | [diff] [blame] | 310 | scifb1: serial@e6c30000 { |
Simon Horman | 94f1a03 | 2014-07-07 09:54:33 +0200 | [diff] [blame] | 311 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
| 312 | reg = <0 0xe6c30000 0 0x100>; |
| 313 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 314 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; |
| 315 | clock-names = "sci_ick"; |
Simon Horman | 94f1a03 | 2014-07-07 09:54:33 +0200 | [diff] [blame] | 316 | status = "disabled"; |
| 317 | }; |
| 318 | |
Ulrich Hecht | 7300505 | 2014-09-25 10:32:14 +0900 | [diff] [blame] | 319 | scifa0: serial@e6c40000 { |
| 320 | compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; |
| 321 | reg = <0 0xe6c40000 0 0x100>; |
| 322 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 323 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; |
| 324 | clock-names = "sci_ick"; |
Ulrich Hecht | 7300505 | 2014-09-25 10:32:14 +0900 | [diff] [blame] | 325 | status = "disabled"; |
| 326 | }; |
| 327 | |
| 328 | scifa1: serial@e6c50000 { |
| 329 | compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; |
| 330 | reg = <0 0xe6c50000 0 0x100>; |
| 331 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 332 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; |
| 333 | clock-names = "sci_ick"; |
Ulrich Hecht | 7300505 | 2014-09-25 10:32:14 +0900 | [diff] [blame] | 334 | status = "disabled"; |
| 335 | }; |
| 336 | |
Ulrich Hecht | 0b3a0ef | 2014-11-04 17:21:24 +0100 | [diff] [blame] | 337 | scifb2: serial@e6ce0000 { |
Simon Horman | 94f1a03 | 2014-07-07 09:54:33 +0200 | [diff] [blame] | 338 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
| 339 | reg = <0 0xe6ce0000 0 0x100>; |
| 340 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 341 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; |
| 342 | clock-names = "sci_ick"; |
Simon Horman | 94f1a03 | 2014-07-07 09:54:33 +0200 | [diff] [blame] | 343 | status = "disabled"; |
| 344 | }; |
| 345 | |
Ulrich Hecht | 0b3a0ef | 2014-11-04 17:21:24 +0100 | [diff] [blame] | 346 | scifb3: serial@e6cf0000 { |
Simon Horman | 94f1a03 | 2014-07-07 09:54:33 +0200 | [diff] [blame] | 347 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
| 348 | reg = <0 0xe6cf0000 0 0x100>; |
| 349 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 350 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; |
| 351 | clock-names = "sci_ick"; |
Simon Horman | 94f1a03 | 2014-07-07 09:54:33 +0200 | [diff] [blame] | 352 | status = "disabled"; |
| 353 | }; |
| 354 | |
Kuninori Morimoto | 43304a5 | 2013-10-21 19:35:31 -0700 | [diff] [blame] | 355 | sdhi0: sd@ee100000 { |
Guennadi Liakhovetski | df1d058 | 2013-08-29 17:14:49 +0200 | [diff] [blame] | 356 | compatible = "renesas,sdhi-r8a73a4"; |
Guennadi Liakhovetski | 369ee2d | 2013-07-08 17:54:45 +0200 | [diff] [blame] | 357 | reg = <0 0xee100000 0 0x100>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 358 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 359 | clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; |
Guennadi Liakhovetski | 369ee2d | 2013-07-08 17:54:45 +0200 | [diff] [blame] | 360 | cap-sd-highspeed; |
| 361 | status = "disabled"; |
| 362 | }; |
| 363 | |
Kuninori Morimoto | 43304a5 | 2013-10-21 19:35:31 -0700 | [diff] [blame] | 364 | sdhi1: sd@ee120000 { |
Guennadi Liakhovetski | df1d058 | 2013-08-29 17:14:49 +0200 | [diff] [blame] | 365 | compatible = "renesas,sdhi-r8a73a4"; |
Guennadi Liakhovetski | 369ee2d | 2013-07-08 17:54:45 +0200 | [diff] [blame] | 366 | reg = <0 0xee120000 0 0x100>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 367 | interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 368 | clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; |
Guennadi Liakhovetski | 369ee2d | 2013-07-08 17:54:45 +0200 | [diff] [blame] | 369 | cap-sd-highspeed; |
| 370 | status = "disabled"; |
| 371 | }; |
| 372 | |
Kuninori Morimoto | 43304a5 | 2013-10-21 19:35:31 -0700 | [diff] [blame] | 373 | sdhi2: sd@ee140000 { |
Guennadi Liakhovetski | df1d058 | 2013-08-29 17:14:49 +0200 | [diff] [blame] | 374 | compatible = "renesas,sdhi-r8a73a4"; |
Guennadi Liakhovetski | 369ee2d | 2013-07-08 17:54:45 +0200 | [diff] [blame] | 375 | reg = <0 0xee140000 0 0x100>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 376 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 377 | clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; |
Guennadi Liakhovetski | 369ee2d | 2013-07-08 17:54:45 +0200 | [diff] [blame] | 378 | cap-sd-highspeed; |
| 379 | status = "disabled"; |
| 380 | }; |
Ulrich Hecht | 7300505 | 2014-09-25 10:32:14 +0900 | [diff] [blame] | 381 | |
| 382 | mmcif0: mmc@ee200000 { |
| 383 | compatible = "renesas,sh-mmcif"; |
| 384 | reg = <0 0xee200000 0 0x80>; |
| 385 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 386 | clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; |
Ulrich Hecht | 7300505 | 2014-09-25 10:32:14 +0900 | [diff] [blame] | 387 | reg-io-width = <4>; |
| 388 | status = "disabled"; |
| 389 | }; |
| 390 | |
| 391 | mmcif1: mmc@ee220000 { |
| 392 | compatible = "renesas,sh-mmcif"; |
| 393 | reg = <0 0xee220000 0 0x80>; |
| 394 | interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 662dd64 | 2015-01-20 13:51:41 +0100 | [diff] [blame^] | 395 | clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; |
Ulrich Hecht | 7300505 | 2014-09-25 10:32:14 +0900 | [diff] [blame] | 396 | reg-io-width = <4>; |
| 397 | status = "disabled"; |
| 398 | }; |
| 399 | |
| 400 | gic: interrupt-controller@f1001000 { |
| 401 | compatible = "arm,cortex-a15-gic"; |
| 402 | #interrupt-cells = <3>; |
| 403 | #address-cells = <0>; |
| 404 | interrupt-controller; |
| 405 | reg = <0 0xf1001000 0 0x1000>, |
| 406 | <0 0xf1002000 0 0x1000>, |
| 407 | <0 0xf1004000 0 0x2000>, |
| 408 | <0 0xf1006000 0 0x2000>; |
| 409 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| 410 | }; |
Ulrich Hecht | a76809a | 2015-01-20 13:51:39 +0100 | [diff] [blame] | 411 | |
| 412 | clocks { |
| 413 | #address-cells = <2>; |
| 414 | #size-cells = <2>; |
| 415 | ranges; |
| 416 | |
| 417 | /* External root clocks */ |
| 418 | extalr_clk: extalr_clk { |
| 419 | compatible = "fixed-clock"; |
| 420 | #clock-cells = <0>; |
| 421 | clock-frequency = <32768>; |
| 422 | clock-output-names = "extalr"; |
| 423 | }; |
| 424 | extal1_clk: extal1_clk { |
| 425 | compatible = "fixed-clock"; |
| 426 | #clock-cells = <0>; |
| 427 | clock-frequency = <25000000>; |
| 428 | clock-output-names = "extal1"; |
| 429 | }; |
| 430 | extal2_clk: extal2_clk { |
| 431 | compatible = "fixed-clock"; |
| 432 | #clock-cells = <0>; |
| 433 | clock-frequency = <48000000>; |
| 434 | clock-output-names = "extal2"; |
| 435 | }; |
| 436 | fsiack_clk: fsiack_clk { |
| 437 | compatible = "fixed-clock"; |
| 438 | #clock-cells = <0>; |
| 439 | /* This value must be overridden by the board. */ |
| 440 | clock-frequency = <0>; |
| 441 | clock-output-names = "fsiack"; |
| 442 | }; |
| 443 | fsibck_clk: fsibck_clk { |
| 444 | compatible = "fixed-clock"; |
| 445 | #clock-cells = <0>; |
| 446 | /* This value must be overridden by the board. */ |
| 447 | clock-frequency = <0>; |
| 448 | clock-output-names = "fsibck"; |
| 449 | }; |
| 450 | |
| 451 | /* Special CPG clocks */ |
| 452 | cpg_clocks: cpg_clocks@e6150000 { |
| 453 | compatible = "renesas,r8a73a4-cpg-clocks"; |
| 454 | reg = <0 0xe6150000 0 0x10000>; |
| 455 | clocks = <&extal1_clk>, <&extal2_clk>; |
| 456 | #clock-cells = <1>; |
| 457 | clock-output-names = "main", "pll0", "pll1", "pll2", |
| 458 | "pll2s", "pll2h", "z", "z2", |
| 459 | "i", "m3", "b", "m1", "m2", |
| 460 | "zx", "zs", "hp"; |
| 461 | }; |
| 462 | |
| 463 | /* Variable factor clocks (DIV6) */ |
| 464 | zb_clk: zb_clk@e6150010 { |
| 465 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 466 | reg = <0 0xe6150010 0 4>; |
| 467 | clocks = <&pll1_div2_clk>, <0>, |
| 468 | <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; |
| 469 | #clock-cells = <0>; |
| 470 | clock-output-names = "zb"; |
| 471 | }; |
| 472 | sdhi0_clk: sdhi0_clk@e6150074 { |
| 473 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 474 | reg = <0 0xe6150074 0 4>; |
| 475 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 476 | <0>, <&extal2_clk>; |
| 477 | #clock-cells = <0>; |
| 478 | clock-output-names = "sdhi0ck"; |
| 479 | }; |
| 480 | sdhi1_clk: sdhi1_clk@e6150078 { |
| 481 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 482 | reg = <0 0xe6150078 0 4>; |
| 483 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 484 | <0>, <&extal2_clk>; |
| 485 | #clock-cells = <0>; |
| 486 | clock-output-names = "sdhi1ck"; |
| 487 | }; |
| 488 | sdhi2_clk: sdhi2_clk@e615007c { |
| 489 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 490 | reg = <0 0xe615007c 0 4>; |
| 491 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 492 | <0>, <&extal2_clk>; |
| 493 | #clock-cells = <0>; |
| 494 | clock-output-names = "sdhi2ck"; |
| 495 | }; |
| 496 | mmc0_clk: mmc0_clk@e6150240 { |
| 497 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 498 | reg = <0 0xe6150240 0 4>; |
| 499 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 500 | <0>, <&extal2_clk>; |
| 501 | #clock-cells = <0>; |
| 502 | clock-output-names = "mmc0"; |
| 503 | }; |
| 504 | mmc1_clk: mmc1_clk@e6150244 { |
| 505 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 506 | reg = <0 0xe6150244 0 4>; |
| 507 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 508 | <0>, <&extal2_clk>; |
| 509 | #clock-cells = <0>; |
| 510 | clock-output-names = "mmc1"; |
| 511 | }; |
| 512 | vclk1_clk: vclk1_clk@e6150008 { |
| 513 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 514 | reg = <0 0xe6150008 0 4>; |
| 515 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 516 | <0>, <&extal2_clk>, <&main_div2_clk>, |
| 517 | <&extalr_clk>, <0>, <0>; |
| 518 | #clock-cells = <0>; |
| 519 | clock-output-names = "vclk1"; |
| 520 | }; |
| 521 | vclk2_clk: vclk2_clk@e615000c { |
| 522 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 523 | reg = <0 0xe615000c 0 4>; |
| 524 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 525 | <0>, <&extal2_clk>, <&main_div2_clk>, |
| 526 | <&extalr_clk>, <0>, <0>; |
| 527 | #clock-cells = <0>; |
| 528 | clock-output-names = "vclk2"; |
| 529 | }; |
| 530 | vclk3_clk: vclk3_clk@e615001c { |
| 531 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 532 | reg = <0 0xe615001c 0 4>; |
| 533 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 534 | <0>, <&extal2_clk>, <&main_div2_clk>, |
| 535 | <&extalr_clk>, <0>, <0>; |
| 536 | #clock-cells = <0>; |
| 537 | clock-output-names = "vclk3"; |
| 538 | }; |
| 539 | vclk4_clk: vclk4_clk@e6150014 { |
| 540 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 541 | reg = <0 0xe6150014 0 4>; |
| 542 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 543 | <0>, <&extal2_clk>, <&main_div2_clk>, |
| 544 | <&extalr_clk>, <0>, <0>; |
| 545 | #clock-cells = <0>; |
| 546 | clock-output-names = "vclk4"; |
| 547 | }; |
| 548 | vclk5_clk: vclk5_clk@e6150034 { |
| 549 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 550 | reg = <0 0xe6150034 0 4>; |
| 551 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 552 | <0>, <&extal2_clk>, <&main_div2_clk>, |
| 553 | <&extalr_clk>, <0>, <0>; |
| 554 | #clock-cells = <0>; |
| 555 | clock-output-names = "vclk5"; |
| 556 | }; |
| 557 | fsia_clk: fsia_clk@e6150018 { |
| 558 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 559 | reg = <0 0xe6150018 0 4>; |
| 560 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 561 | <&fsiack_clk>, <0>; |
| 562 | #clock-cells = <0>; |
| 563 | clock-output-names = "fsia"; |
| 564 | }; |
| 565 | fsib_clk: fsib_clk@e6150090 { |
| 566 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 567 | reg = <0 0xe6150090 0 4>; |
| 568 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 569 | <&fsibck_clk>, <0>; |
| 570 | #clock-cells = <0>; |
| 571 | clock-output-names = "fsib"; |
| 572 | }; |
| 573 | mp_clk: mp_clk@e6150080 { |
| 574 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 575 | reg = <0 0xe6150080 0 4>; |
| 576 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 577 | <&extal2_clk>, <&extal2_clk>; |
| 578 | #clock-cells = <0>; |
| 579 | clock-output-names = "mp"; |
| 580 | }; |
| 581 | m4_clk: m4_clk@e6150098 { |
| 582 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 583 | reg = <0 0xe6150098 0 4>; |
| 584 | clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; |
| 585 | #clock-cells = <0>; |
| 586 | clock-output-names = "m4"; |
| 587 | }; |
| 588 | hsi_clk: hsi_clk@e615026c { |
| 589 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 590 | reg = <0 0xe615026c 0 4>; |
| 591 | clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, |
| 592 | <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; |
| 593 | #clock-cells = <0>; |
| 594 | clock-output-names = "hsi"; |
| 595 | }; |
| 596 | spuv_clk: spuv_clk@e6150094 { |
| 597 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 598 | reg = <0 0xe6150094 0 4>; |
| 599 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 600 | <&extal2_clk>, <&extal2_clk>; |
| 601 | #clock-cells = <0>; |
| 602 | clock-output-names = "spuv"; |
| 603 | }; |
| 604 | |
| 605 | /* Fixed factor clocks */ |
| 606 | main_div2_clk: main_div2_clk { |
| 607 | compatible = "fixed-factor-clock"; |
| 608 | clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; |
| 609 | #clock-cells = <0>; |
| 610 | clock-div = <2>; |
| 611 | clock-mult = <1>; |
| 612 | clock-output-names = "main_div2"; |
| 613 | }; |
| 614 | pll0_div2_clk: pll0_div2_clk { |
| 615 | compatible = "fixed-factor-clock"; |
| 616 | clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; |
| 617 | #clock-cells = <0>; |
| 618 | clock-div = <2>; |
| 619 | clock-mult = <1>; |
| 620 | clock-output-names = "pll0_div2"; |
| 621 | }; |
| 622 | pll1_div2_clk: pll1_div2_clk { |
| 623 | compatible = "fixed-factor-clock"; |
| 624 | clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; |
| 625 | #clock-cells = <0>; |
| 626 | clock-div = <2>; |
| 627 | clock-mult = <1>; |
| 628 | clock-output-names = "pll1_div2"; |
| 629 | }; |
| 630 | extal1_div2_clk: extal1_div2_clk { |
| 631 | compatible = "fixed-factor-clock"; |
| 632 | clocks = <&extal1_clk>; |
| 633 | #clock-cells = <0>; |
| 634 | clock-div = <2>; |
| 635 | clock-mult = <1>; |
| 636 | clock-output-names = "extal1_div2"; |
| 637 | }; |
| 638 | |
| 639 | /* Gate clocks */ |
| 640 | mstp2_clks: mstp2_clks@e6150138 { |
| 641 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 642 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; |
| 643 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, |
| 644 | <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; |
| 645 | #clock-cells = <1>; |
| 646 | clock-indices = < |
| 647 | R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 |
| 648 | R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 |
| 649 | R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 |
| 650 | R8A73A4_CLK_DMAC |
| 651 | >; |
| 652 | clock-output-names = |
| 653 | "scifa0", "scifa1", "scifb0", "scifb1", |
| 654 | "scifb2", "scifb3", "dmac"; |
| 655 | }; |
| 656 | mstp3_clks: mstp3_clks@e615013c { |
| 657 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 658 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; |
| 659 | clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, |
| 660 | <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, |
| 661 | <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, |
| 662 | <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks |
| 663 | R8A73A4_CLK_HP>, <&cpg_clocks |
| 664 | R8A73A4_CLK_HP>, <&extalr_clk>; |
| 665 | #clock-cells = <1>; |
| 666 | clock-indices = < |
| 667 | R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 |
| 668 | R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 |
| 669 | R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 |
| 670 | R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 |
| 671 | R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 |
| 672 | R8A73A4_CLK_CMT1 |
| 673 | >; |
| 674 | clock-output-names = |
| 675 | "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", |
| 676 | "mmcif0", "iic6", "iic7", "iic0", "iic1", |
| 677 | "cmt1"; |
| 678 | }; |
| 679 | mstp4_clks: mstp4_clks@e6150140 { |
| 680 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 681 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; |
| 682 | clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>, |
| 683 | <&cpg_clocks R8A73A4_CLK_HP>; |
| 684 | #clock-cells = <1>; |
| 685 | clock-indices = < |
| 686 | R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 |
| 687 | R8A73A4_CLK_IIC3 |
| 688 | >; |
| 689 | clock-output-names = |
| 690 | "iic5", "iic4", "iic3"; |
| 691 | }; |
| 692 | mstp5_clks: mstp5_clks@e6150144 { |
| 693 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 694 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; |
| 695 | clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; |
| 696 | #clock-cells = <1>; |
| 697 | clock-indices = < |
| 698 | R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 |
| 699 | >; |
| 700 | clock-output-names = |
| 701 | "thermal", "iic8"; |
| 702 | }; |
| 703 | }; |
Magnus Damm | eccf060 | 2013-03-26 10:34:24 +0900 | [diff] [blame] | 704 | }; |