Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/iopoll.h> |
| 14 | #include <linux/slab.h> |
| 15 | #include <uapi/media/cam_isp.h> |
| 16 | #include <uapi/media/cam_defs.h> |
| 17 | |
| 18 | #include "cam_ife_csid_core.h" |
| 19 | #include "cam_isp_hw.h" |
| 20 | #include "cam_soc_util.h" |
| 21 | #include "cam_io_util.h" |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 22 | #include "cam_debug_util.h" |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 23 | |
| 24 | /* Timeout value in msec */ |
| 25 | #define IFE_CSID_TIMEOUT 1000 |
| 26 | |
| 27 | /* TPG VC/DT values */ |
| 28 | #define CAM_IFE_CSID_TPG_VC_VAL 0xA |
| 29 | #define CAM_IFE_CSID_TPG_DT_VAL 0x2B |
| 30 | |
| 31 | /* Timeout values in usec */ |
| 32 | #define CAM_IFE_CSID_TIMEOUT_SLEEP_US 1000 |
| 33 | #define CAM_IFE_CSID_TIMEOUT_ALL_US 1000000 |
| 34 | |
| 35 | static int cam_ife_csid_is_ipp_format_supported( |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 36 | uint32_t in_format) |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 37 | { |
| 38 | int rc = -EINVAL; |
| 39 | |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 40 | switch (in_format) { |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 41 | case CAM_FORMAT_MIPI_RAW_6: |
| 42 | case CAM_FORMAT_MIPI_RAW_8: |
| 43 | case CAM_FORMAT_MIPI_RAW_10: |
| 44 | case CAM_FORMAT_MIPI_RAW_12: |
| 45 | case CAM_FORMAT_MIPI_RAW_14: |
| 46 | case CAM_FORMAT_MIPI_RAW_16: |
| 47 | case CAM_FORMAT_MIPI_RAW_20: |
| 48 | case CAM_FORMAT_DPCM_10_6_10: |
| 49 | case CAM_FORMAT_DPCM_10_8_10: |
| 50 | case CAM_FORMAT_DPCM_12_6_12: |
| 51 | case CAM_FORMAT_DPCM_12_8_12: |
| 52 | case CAM_FORMAT_DPCM_14_8_14: |
| 53 | case CAM_FORMAT_DPCM_14_10_14: |
| 54 | rc = 0; |
| 55 | break; |
| 56 | default: |
| 57 | break; |
| 58 | } |
| 59 | return rc; |
| 60 | } |
| 61 | |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 62 | static int cam_ife_csid_get_format_rdi( |
| 63 | uint32_t in_format, uint32_t out_format, |
| 64 | uint32_t *decode_fmt, uint32_t *plain_fmt) |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 65 | { |
| 66 | int rc = 0; |
| 67 | |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 68 | switch (in_format) { |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 69 | case CAM_FORMAT_MIPI_RAW_6: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 70 | switch (out_format) { |
| 71 | case CAM_FORMAT_MIPI_RAW_6: |
| 72 | *decode_fmt = 0xf; |
| 73 | break; |
| 74 | case CAM_FORMAT_PLAIN8: |
| 75 | *decode_fmt = 0x0; |
| 76 | *plain_fmt = 0x0; |
| 77 | break; |
| 78 | default: |
| 79 | rc = -EINVAL; |
| 80 | break; |
| 81 | } |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 82 | break; |
| 83 | case CAM_FORMAT_MIPI_RAW_8: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 84 | switch (out_format) { |
| 85 | case CAM_FORMAT_MIPI_RAW_8: |
Harsh Shah | ea34b60 | 2017-09-29 11:42:45 -0700 | [diff] [blame] | 86 | case CAM_FORMAT_PLAIN128: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 87 | *decode_fmt = 0xf; |
| 88 | break; |
| 89 | case CAM_FORMAT_PLAIN8: |
| 90 | *decode_fmt = 0x1; |
| 91 | *plain_fmt = 0x0; |
| 92 | break; |
| 93 | default: |
| 94 | rc = -EINVAL; |
| 95 | break; |
| 96 | } |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 97 | break; |
| 98 | case CAM_FORMAT_MIPI_RAW_10: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 99 | switch (out_format) { |
| 100 | case CAM_FORMAT_MIPI_RAW_10: |
Harsh Shah | ea34b60 | 2017-09-29 11:42:45 -0700 | [diff] [blame] | 101 | case CAM_FORMAT_PLAIN128: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 102 | *decode_fmt = 0xf; |
| 103 | break; |
| 104 | case CAM_FORMAT_PLAIN16_10: |
| 105 | *decode_fmt = 0x2; |
| 106 | *plain_fmt = 0x1; |
| 107 | break; |
| 108 | default: |
| 109 | rc = -EINVAL; |
| 110 | break; |
| 111 | } |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 112 | break; |
| 113 | case CAM_FORMAT_MIPI_RAW_12: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 114 | switch (out_format) { |
| 115 | case CAM_FORMAT_MIPI_RAW_12: |
| 116 | *decode_fmt = 0xf; |
| 117 | break; |
| 118 | case CAM_FORMAT_PLAIN16_12: |
| 119 | *decode_fmt = 0x3; |
| 120 | *plain_fmt = 0x1; |
| 121 | break; |
| 122 | default: |
| 123 | rc = -EINVAL; |
| 124 | break; |
| 125 | } |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 126 | break; |
| 127 | case CAM_FORMAT_MIPI_RAW_14: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 128 | switch (out_format) { |
| 129 | case CAM_FORMAT_MIPI_RAW_14: |
| 130 | *decode_fmt = 0xf; |
| 131 | break; |
| 132 | case CAM_FORMAT_PLAIN16_14: |
| 133 | *decode_fmt = 0x4; |
| 134 | *plain_fmt = 0x1; |
| 135 | break; |
| 136 | default: |
| 137 | rc = -EINVAL; |
| 138 | break; |
| 139 | } |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 140 | break; |
| 141 | case CAM_FORMAT_MIPI_RAW_16: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 142 | switch (out_format) { |
| 143 | case CAM_FORMAT_MIPI_RAW_16: |
| 144 | *decode_fmt = 0xf; |
| 145 | break; |
| 146 | case CAM_FORMAT_PLAIN16_16: |
| 147 | *decode_fmt = 0x5; |
| 148 | *plain_fmt = 0x1; |
| 149 | break; |
| 150 | default: |
| 151 | rc = -EINVAL; |
| 152 | break; |
| 153 | } |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 154 | break; |
| 155 | case CAM_FORMAT_MIPI_RAW_20: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 156 | switch (out_format) { |
| 157 | case CAM_FORMAT_MIPI_RAW_20: |
| 158 | *decode_fmt = 0xf; |
| 159 | break; |
| 160 | case CAM_FORMAT_PLAIN32_20: |
| 161 | *decode_fmt = 0x6; |
| 162 | *plain_fmt = 0x2; |
| 163 | break; |
| 164 | default: |
| 165 | rc = -EINVAL; |
| 166 | break; |
| 167 | } |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 168 | break; |
| 169 | case CAM_FORMAT_DPCM_10_6_10: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 170 | *decode_fmt = 0x7; |
| 171 | *plain_fmt = 0x1; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 172 | break; |
| 173 | case CAM_FORMAT_DPCM_10_8_10: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 174 | *decode_fmt = 0x8; |
| 175 | *plain_fmt = 0x1; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 176 | break; |
| 177 | case CAM_FORMAT_DPCM_12_6_12: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 178 | *decode_fmt = 0x9; |
| 179 | *plain_fmt = 0x1; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 180 | break; |
| 181 | case CAM_FORMAT_DPCM_12_8_12: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 182 | *decode_fmt = 0xA; |
| 183 | *plain_fmt = 0x1; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 184 | break; |
| 185 | case CAM_FORMAT_DPCM_14_8_14: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 186 | *decode_fmt = 0xB; |
| 187 | *plain_fmt = 0x1; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 188 | break; |
| 189 | case CAM_FORMAT_DPCM_14_10_14: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 190 | *decode_fmt = 0xC; |
| 191 | *plain_fmt = 0x1; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 192 | break; |
| 193 | default: |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 194 | rc = -EINVAL; |
| 195 | break; |
| 196 | } |
| 197 | |
| 198 | if (rc) |
Ravikishore Pampana | c19ba62 | 2017-09-21 17:20:48 +0530 | [diff] [blame] | 199 | CAM_ERR(CAM_ISP, "Unsupported format pair in %d out %d", |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 200 | in_format, out_format); |
| 201 | |
| 202 | return rc; |
| 203 | } |
| 204 | |
| 205 | static int cam_ife_csid_get_format_ipp( |
| 206 | uint32_t in_format, |
| 207 | uint32_t *decode_fmt, uint32_t *plain_fmt) |
| 208 | { |
| 209 | int rc = 0; |
| 210 | |
| 211 | CAM_DBG(CAM_ISP, "input format:%d", |
| 212 | in_format); |
| 213 | |
| 214 | switch (in_format) { |
| 215 | case CAM_FORMAT_MIPI_RAW_6: |
| 216 | *decode_fmt = 0; |
| 217 | *plain_fmt = 0; |
| 218 | break; |
| 219 | case CAM_FORMAT_MIPI_RAW_8: |
| 220 | *decode_fmt = 0x1; |
| 221 | *plain_fmt = 0; |
| 222 | break; |
| 223 | case CAM_FORMAT_MIPI_RAW_10: |
| 224 | *decode_fmt = 0x2; |
| 225 | *plain_fmt = 0x1; |
| 226 | break; |
| 227 | case CAM_FORMAT_MIPI_RAW_12: |
| 228 | *decode_fmt = 0x3; |
| 229 | *plain_fmt = 0x1; |
| 230 | break; |
| 231 | case CAM_FORMAT_MIPI_RAW_14: |
| 232 | *decode_fmt = 0x4; |
| 233 | *plain_fmt = 0x1; |
| 234 | break; |
| 235 | case CAM_FORMAT_MIPI_RAW_16: |
| 236 | *decode_fmt = 0x5; |
| 237 | *plain_fmt = 0x1; |
| 238 | break; |
| 239 | case CAM_FORMAT_MIPI_RAW_20: |
| 240 | *decode_fmt = 0x6; |
| 241 | *plain_fmt = 0x2; |
| 242 | break; |
| 243 | case CAM_FORMAT_DPCM_10_6_10: |
| 244 | *decode_fmt = 0x7; |
| 245 | *plain_fmt = 0x1; |
| 246 | break; |
| 247 | case CAM_FORMAT_DPCM_10_8_10: |
| 248 | *decode_fmt = 0x8; |
| 249 | *plain_fmt = 0x1; |
| 250 | break; |
| 251 | case CAM_FORMAT_DPCM_12_6_12: |
| 252 | *decode_fmt = 0x9; |
| 253 | *plain_fmt = 0x1; |
| 254 | break; |
| 255 | case CAM_FORMAT_DPCM_12_8_12: |
| 256 | *decode_fmt = 0xA; |
| 257 | *plain_fmt = 0x1; |
| 258 | break; |
| 259 | case CAM_FORMAT_DPCM_14_8_14: |
| 260 | *decode_fmt = 0xB; |
| 261 | *plain_fmt = 0x1; |
| 262 | break; |
| 263 | case CAM_FORMAT_DPCM_14_10_14: |
| 264 | *decode_fmt = 0xC; |
| 265 | *plain_fmt = 0x1; |
| 266 | break; |
| 267 | default: |
| 268 | CAM_ERR(CAM_ISP, "Unsupported format %d", |
| 269 | in_format); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 270 | rc = -EINVAL; |
| 271 | } |
| 272 | |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 273 | CAM_DBG(CAM_ISP, "decode_fmt:%d plain_fmt:%d", |
| 274 | *decode_fmt, *plain_fmt); |
| 275 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 276 | return rc; |
| 277 | } |
| 278 | |
| 279 | static int cam_ife_csid_cid_get(struct cam_ife_csid_hw *csid_hw, |
| 280 | struct cam_isp_resource_node **res, int32_t vc, uint32_t dt, |
| 281 | uint32_t res_type) |
| 282 | { |
| 283 | int rc = 0; |
| 284 | struct cam_ife_csid_cid_data *cid_data; |
| 285 | uint32_t i = 0, j = 0; |
| 286 | |
| 287 | for (i = 0; i < CAM_IFE_CSID_CID_RES_MAX; i++) { |
| 288 | if (csid_hw->cid_res[i].res_state >= |
| 289 | CAM_ISP_RESOURCE_STATE_RESERVED) { |
| 290 | cid_data = (struct cam_ife_csid_cid_data *) |
| 291 | csid_hw->cid_res[i].res_priv; |
| 292 | if (res_type == CAM_ISP_IFE_IN_RES_TPG) { |
| 293 | if (cid_data->tpg_set) { |
| 294 | cid_data->cnt++; |
| 295 | *res = &csid_hw->cid_res[i]; |
| 296 | break; |
| 297 | } |
| 298 | } else { |
| 299 | if (cid_data->vc == vc && cid_data->dt == dt) { |
| 300 | cid_data->cnt++; |
| 301 | *res = &csid_hw->cid_res[i]; |
| 302 | break; |
| 303 | } |
| 304 | } |
| 305 | } |
| 306 | } |
| 307 | |
| 308 | if (i == CAM_IFE_CSID_CID_RES_MAX) { |
| 309 | if (res_type == CAM_ISP_IFE_IN_RES_TPG) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 310 | CAM_ERR(CAM_ISP, "CSID:%d TPG CID not available", |
| 311 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 312 | rc = -EINVAL; |
| 313 | } |
| 314 | |
| 315 | for (j = 0; j < CAM_IFE_CSID_CID_RES_MAX; j++) { |
| 316 | if (csid_hw->cid_res[j].res_state == |
| 317 | CAM_ISP_RESOURCE_STATE_AVAILABLE) { |
| 318 | cid_data = (struct cam_ife_csid_cid_data *) |
| 319 | csid_hw->cid_res[j].res_priv; |
| 320 | cid_data->vc = vc; |
| 321 | cid_data->dt = dt; |
| 322 | cid_data->cnt = 1; |
| 323 | csid_hw->cid_res[j].res_state = |
| 324 | CAM_ISP_RESOURCE_STATE_RESERVED; |
| 325 | *res = &csid_hw->cid_res[j]; |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 326 | CAM_DBG(CAM_ISP, "CSID:%d CID %d allocated", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 327 | csid_hw->hw_intf->hw_idx, |
| 328 | csid_hw->cid_res[j].res_id); |
| 329 | break; |
| 330 | } |
| 331 | } |
| 332 | |
| 333 | if (j == CAM_IFE_CSID_CID_RES_MAX) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 334 | CAM_ERR(CAM_ISP, "CSID:%d Free cid is not available", |
| 335 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 336 | rc = -EINVAL; |
| 337 | } |
| 338 | } |
| 339 | |
| 340 | return rc; |
| 341 | } |
| 342 | |
| 343 | |
| 344 | static int cam_ife_csid_global_reset(struct cam_ife_csid_hw *csid_hw) |
| 345 | { |
| 346 | struct cam_hw_soc_info *soc_info; |
| 347 | struct cam_ife_csid_reg_offset *csid_reg; |
| 348 | int rc = 0; |
| 349 | uint32_t i, irq_mask_rx, irq_mask_ipp = 0, |
| 350 | irq_mask_rdi[CAM_IFE_CSID_RDI_MAX]; |
| 351 | |
| 352 | soc_info = &csid_hw->hw_info->soc_info; |
| 353 | csid_reg = csid_hw->csid_info->csid_reg; |
| 354 | |
| 355 | if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 356 | CAM_ERR(CAM_ISP, "CSID:%d Invalid HW State:%d", |
| 357 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 358 | csid_hw->hw_info->hw_state); |
| 359 | return -EINVAL; |
| 360 | } |
| 361 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 362 | CAM_DBG(CAM_ISP, "CSID:%d Csid reset", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 363 | csid_hw->hw_intf->hw_idx); |
| 364 | |
| 365 | init_completion(&csid_hw->csid_top_complete); |
| 366 | |
| 367 | /* Save interrupt mask registers values*/ |
| 368 | irq_mask_rx = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 369 | csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); |
| 370 | |
| 371 | if (csid_reg->cmn_reg->no_pix) |
| 372 | irq_mask_ipp = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 373 | csid_reg->ipp_reg->csid_ipp_irq_mask_addr); |
| 374 | |
| 375 | for (i = 0; i < csid_reg->cmn_reg->no_rdis; i++) { |
| 376 | irq_mask_rdi[i] = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 377 | csid_reg->rdi_reg[i]->csid_rdi_irq_mask_addr); |
| 378 | } |
| 379 | |
| 380 | /* Mask all interrupts */ |
| 381 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 382 | csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); |
| 383 | |
| 384 | if (csid_reg->cmn_reg->no_pix) |
| 385 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 386 | csid_reg->ipp_reg->csid_ipp_irq_mask_addr); |
| 387 | |
| 388 | for (i = 0; i < csid_reg->cmn_reg->no_rdis; i++) |
| 389 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 390 | csid_reg->rdi_reg[i]->csid_rdi_irq_mask_addr); |
| 391 | |
| 392 | /* clear all interrupts */ |
| 393 | cam_io_w_mb(1, soc_info->reg_map[0].mem_base + |
| 394 | csid_reg->cmn_reg->csid_top_irq_clear_addr); |
| 395 | |
| 396 | cam_io_w_mb(csid_reg->csi2_reg->csi2_irq_mask_all, |
| 397 | soc_info->reg_map[0].mem_base + |
| 398 | csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr); |
| 399 | |
| 400 | if (csid_reg->cmn_reg->no_pix) |
| 401 | cam_io_w_mb(csid_reg->cmn_reg->ipp_irq_mask_all, |
| 402 | soc_info->reg_map[0].mem_base + |
| 403 | csid_reg->ipp_reg->csid_ipp_irq_clear_addr); |
| 404 | |
| 405 | for (i = 0 ; i < csid_reg->cmn_reg->no_rdis; i++) |
| 406 | cam_io_w_mb(csid_reg->cmn_reg->rdi_irq_mask_all, |
| 407 | soc_info->reg_map[0].mem_base + |
| 408 | csid_reg->rdi_reg[i]->csid_rdi_irq_clear_addr); |
| 409 | |
| 410 | cam_io_w_mb(1, soc_info->reg_map[0].mem_base + |
| 411 | csid_reg->cmn_reg->csid_irq_cmd_addr); |
| 412 | |
| 413 | cam_io_w_mb(0x80, soc_info->reg_map[0].mem_base + |
| 414 | csid_hw->csid_info->csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); |
| 415 | |
| 416 | /* enable the IPP and RDI format measure */ |
| 417 | if (csid_reg->cmn_reg->no_pix) |
| 418 | cam_io_w_mb(0x1, soc_info->reg_map[0].mem_base + |
| 419 | csid_reg->ipp_reg->csid_ipp_cfg0_addr); |
| 420 | |
| 421 | for (i = 0; i < csid_reg->cmn_reg->no_rdis; i++) |
| 422 | cam_io_w_mb(0x2, soc_info->reg_map[0].mem_base + |
| 423 | csid_reg->rdi_reg[i]->csid_rdi_cfg0_addr); |
| 424 | |
| 425 | /* perform the top CSID HW reset */ |
| 426 | cam_io_w_mb(csid_reg->cmn_reg->csid_rst_stb, |
| 427 | soc_info->reg_map[0].mem_base + |
| 428 | csid_reg->cmn_reg->csid_rst_strobes_addr); |
| 429 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 430 | CAM_DBG(CAM_ISP, " Waiting for reset complete from irq handler"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 431 | rc = wait_for_completion_timeout(&csid_hw->csid_top_complete, |
| 432 | msecs_to_jiffies(IFE_CSID_TIMEOUT)); |
| 433 | if (rc <= 0) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 434 | CAM_ERR(CAM_ISP, "CSID:%d reset completion in fail rc = %d", |
| 435 | csid_hw->hw_intf->hw_idx, rc); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 436 | if (rc == 0) |
| 437 | rc = -ETIMEDOUT; |
| 438 | } else { |
| 439 | rc = 0; |
| 440 | } |
| 441 | |
| 442 | /*restore all interrupt masks */ |
| 443 | cam_io_w_mb(irq_mask_rx, soc_info->reg_map[0].mem_base + |
| 444 | csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); |
| 445 | |
| 446 | if (csid_reg->cmn_reg->no_pix) |
| 447 | cam_io_w_mb(irq_mask_ipp, soc_info->reg_map[0].mem_base + |
| 448 | csid_reg->ipp_reg->csid_ipp_irq_mask_addr); |
| 449 | |
| 450 | for (i = 0; i < csid_reg->cmn_reg->no_rdis; i++) |
| 451 | cam_io_w_mb(irq_mask_rdi[i], soc_info->reg_map[0].mem_base + |
| 452 | csid_reg->rdi_reg[i]->csid_rdi_irq_mask_addr); |
| 453 | |
| 454 | return rc; |
| 455 | } |
| 456 | |
| 457 | static int cam_ife_csid_path_reset(struct cam_ife_csid_hw *csid_hw, |
| 458 | struct cam_csid_reset_cfg_args *reset) |
| 459 | { |
| 460 | int rc = 0; |
| 461 | struct cam_hw_soc_info *soc_info; |
| 462 | struct cam_isp_resource_node *res; |
| 463 | struct cam_ife_csid_reg_offset *csid_reg; |
| 464 | uint32_t reset_strb_addr, reset_strb_val, val, id; |
| 465 | struct completion *complete; |
| 466 | |
| 467 | csid_reg = csid_hw->csid_info->csid_reg; |
| 468 | soc_info = &csid_hw->hw_info->soc_info; |
| 469 | res = reset->node_res; |
| 470 | |
| 471 | if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 472 | CAM_ERR(CAM_ISP, "CSID:%d Invalid hw state :%d", |
| 473 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 474 | csid_hw->hw_info->hw_state); |
| 475 | return -EINVAL; |
| 476 | } |
| 477 | |
| 478 | if (res->res_id >= CAM_IFE_PIX_PATH_RES_MAX) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 479 | CAM_DBG(CAM_ISP, "CSID:%d Invalid res id%d", |
| 480 | csid_hw->hw_intf->hw_idx, res->res_id); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 481 | rc = -EINVAL; |
| 482 | goto end; |
| 483 | } |
| 484 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 485 | CAM_DBG(CAM_ISP, "CSID:%d resource:%d", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 486 | csid_hw->hw_intf->hw_idx, res->res_id); |
| 487 | |
| 488 | if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) { |
| 489 | if (!csid_reg->ipp_reg) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 490 | CAM_ERR(CAM_ISP, "CSID:%d IPP not supported :%d", |
| 491 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 492 | res->res_id); |
| 493 | return -EINVAL; |
| 494 | } |
| 495 | |
| 496 | reset_strb_addr = csid_reg->ipp_reg->csid_ipp_rst_strobes_addr; |
| 497 | complete = &csid_hw->csid_ipp_complete; |
| 498 | |
| 499 | /* Enable path reset done interrupt */ |
| 500 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 501 | csid_reg->ipp_reg->csid_ipp_irq_mask_addr); |
| 502 | val |= CSID_PATH_INFO_RST_DONE; |
| 503 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 504 | csid_reg->ipp_reg->csid_ipp_irq_mask_addr); |
| 505 | |
| 506 | } else { |
| 507 | id = res->res_id; |
| 508 | if (!csid_reg->rdi_reg[id]) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 509 | CAM_ERR(CAM_ISP, "CSID:%d RDI res not supported :%d", |
| 510 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 511 | res->res_id); |
| 512 | return -EINVAL; |
| 513 | } |
| 514 | |
| 515 | reset_strb_addr = |
| 516 | csid_reg->rdi_reg[id]->csid_rdi_rst_strobes_addr; |
| 517 | complete = |
| 518 | &csid_hw->csid_rdin_complete[id]; |
| 519 | |
| 520 | /* Enable path reset done interrupt */ |
| 521 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 522 | csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); |
| 523 | val |= CSID_PATH_INFO_RST_DONE; |
| 524 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 525 | csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); |
| 526 | } |
| 527 | |
| 528 | init_completion(complete); |
| 529 | reset_strb_val = csid_reg->cmn_reg->path_rst_stb_all; |
| 530 | |
| 531 | /* Enable the Test gen before reset */ |
| 532 | cam_io_w_mb(1, csid_hw->hw_info->soc_info.reg_map[0].mem_base + |
| 533 | csid_reg->tpg_reg->csid_tpg_ctrl_addr); |
| 534 | |
| 535 | /* Reset the corresponding ife csid path */ |
| 536 | cam_io_w_mb(reset_strb_val, soc_info->reg_map[0].mem_base + |
| 537 | reset_strb_addr); |
| 538 | |
| 539 | rc = wait_for_completion_timeout(complete, |
| 540 | msecs_to_jiffies(IFE_CSID_TIMEOUT)); |
| 541 | if (rc <= 0) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 542 | CAM_ERR(CAM_ISP, "CSID:%d Res id %d fail rc = %d", |
| 543 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 544 | res->res_id, rc); |
| 545 | if (rc == 0) |
| 546 | rc = -ETIMEDOUT; |
| 547 | } |
| 548 | |
| 549 | /* Disable Test Gen after reset*/ |
| 550 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 551 | csid_reg->tpg_reg->csid_tpg_ctrl_addr); |
| 552 | |
| 553 | end: |
| 554 | return rc; |
| 555 | |
| 556 | } |
| 557 | |
| 558 | static int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw, |
| 559 | struct cam_csid_hw_reserve_resource_args *cid_reserv) |
| 560 | { |
| 561 | int rc = 0; |
| 562 | struct cam_ife_csid_cid_data *cid_data; |
| 563 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 564 | CAM_DBG(CAM_ISP, |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 565 | "CSID:%d res_sel:0x%x Lane type:%d lane_num:%d dt:%d vc:%d", |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 566 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 567 | cid_reserv->in_port->res_type, |
| 568 | cid_reserv->in_port->lane_type, |
| 569 | cid_reserv->in_port->lane_num, |
| 570 | cid_reserv->in_port->dt, |
| 571 | cid_reserv->in_port->vc); |
| 572 | |
| 573 | if (cid_reserv->in_port->res_type >= CAM_ISP_IFE_IN_RES_MAX) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 574 | CAM_ERR(CAM_ISP, "CSID:%d Invalid phy sel %d", |
| 575 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 576 | cid_reserv->in_port->res_type); |
| 577 | rc = -EINVAL; |
| 578 | goto end; |
| 579 | } |
| 580 | |
| 581 | if (cid_reserv->in_port->lane_type >= CAM_ISP_LANE_TYPE_MAX && |
| 582 | cid_reserv->in_port->res_type != CAM_ISP_IFE_IN_RES_TPG) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 583 | CAM_ERR(CAM_ISP, "CSID:%d Invalid lane type %d", |
| 584 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 585 | cid_reserv->in_port->lane_type); |
| 586 | rc = -EINVAL; |
| 587 | goto end; |
| 588 | } |
| 589 | |
| 590 | if ((cid_reserv->in_port->lane_type == CAM_ISP_LANE_TYPE_DPHY && |
| 591 | cid_reserv->in_port->lane_num > 4) && |
| 592 | cid_reserv->in_port->res_type != CAM_ISP_IFE_IN_RES_TPG) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 593 | CAM_ERR(CAM_ISP, "CSID:%d Invalid lane num %d", |
| 594 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 595 | cid_reserv->in_port->lane_num); |
| 596 | rc = -EINVAL; |
| 597 | goto end; |
| 598 | } |
| 599 | if ((cid_reserv->in_port->lane_type == CAM_ISP_LANE_TYPE_CPHY && |
| 600 | cid_reserv->in_port->lane_num > 3) && |
| 601 | cid_reserv->in_port->res_type != CAM_ISP_IFE_IN_RES_TPG) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 602 | CAM_ERR(CAM_ISP, " CSID:%d Invalid lane type %d & num %d", |
| 603 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 604 | cid_reserv->in_port->lane_type, |
| 605 | cid_reserv->in_port->lane_num); |
| 606 | rc = -EINVAL; |
| 607 | goto end; |
| 608 | } |
| 609 | |
| 610 | /* CSID CSI2 v2.0 supports 31 vc */ |
| 611 | if (cid_reserv->in_port->dt > 0x3f || |
| 612 | cid_reserv->in_port->vc > 0x1f) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 613 | CAM_ERR(CAM_ISP, "CSID:%d Invalid vc:%d dt %d", |
| 614 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 615 | cid_reserv->in_port->vc, cid_reserv->in_port->dt); |
| 616 | rc = -EINVAL; |
| 617 | goto end; |
| 618 | } |
| 619 | |
| 620 | if (cid_reserv->in_port->res_type == CAM_ISP_IFE_IN_RES_TPG && ( |
| 621 | (cid_reserv->in_port->format < CAM_FORMAT_MIPI_RAW_8 && |
| 622 | cid_reserv->in_port->format > CAM_FORMAT_MIPI_RAW_16))) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 623 | CAM_ERR(CAM_ISP, " CSID:%d Invalid tpg decode fmt %d", |
| 624 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 625 | cid_reserv->in_port->format); |
| 626 | rc = -EINVAL; |
| 627 | goto end; |
| 628 | } |
| 629 | |
Harsh Shah | 398b012 | 2017-09-28 15:36:39 -0700 | [diff] [blame] | 630 | if (cid_reserv->in_port->res_type == CAM_ISP_IFE_IN_RES_PHY_3 && |
| 631 | csid_hw->hw_intf->hw_idx != 2) { |
| 632 | rc = -EINVAL; |
| 633 | goto end; |
| 634 | } |
| 635 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 636 | if (csid_hw->csi2_reserve_cnt) { |
| 637 | /* current configure res type should match requested res type */ |
| 638 | if (csid_hw->res_type != cid_reserv->in_port->res_type) { |
| 639 | rc = -EINVAL; |
| 640 | goto end; |
| 641 | } |
| 642 | |
| 643 | if (cid_reserv->in_port->res_type != CAM_ISP_IFE_IN_RES_TPG) { |
| 644 | if (csid_hw->csi2_rx_cfg.lane_cfg != |
| 645 | cid_reserv->in_port->lane_cfg || |
| 646 | csid_hw->csi2_rx_cfg.lane_type != |
| 647 | cid_reserv->in_port->lane_type || |
| 648 | csid_hw->csi2_rx_cfg.lane_num != |
| 649 | cid_reserv->in_port->lane_num) { |
| 650 | rc = -EINVAL; |
| 651 | goto end; |
| 652 | } |
| 653 | } else { |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 654 | if (csid_hw->tpg_cfg.in_format != |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 655 | cid_reserv->in_port->format || |
| 656 | csid_hw->tpg_cfg.width != |
| 657 | cid_reserv->in_port->left_width || |
| 658 | csid_hw->tpg_cfg.height != |
| 659 | cid_reserv->in_port->height || |
| 660 | csid_hw->tpg_cfg.test_pattern != |
| 661 | cid_reserv->in_port->test_pattern) { |
| 662 | rc = -EINVAL; |
| 663 | goto end; |
| 664 | } |
| 665 | } |
| 666 | } |
| 667 | |
| 668 | if (!csid_hw->csi2_reserve_cnt) { |
| 669 | csid_hw->res_type = cid_reserv->in_port->res_type; |
| 670 | /* Take the first CID resource*/ |
| 671 | csid_hw->cid_res[0].res_state = CAM_ISP_RESOURCE_STATE_RESERVED; |
| 672 | cid_data = (struct cam_ife_csid_cid_data *) |
| 673 | csid_hw->cid_res[0].res_priv; |
| 674 | |
| 675 | csid_hw->csi2_rx_cfg.lane_cfg = |
| 676 | cid_reserv->in_port->lane_cfg; |
| 677 | csid_hw->csi2_rx_cfg.lane_type = |
| 678 | cid_reserv->in_port->lane_type; |
| 679 | csid_hw->csi2_rx_cfg.lane_num = |
| 680 | cid_reserv->in_port->lane_num; |
| 681 | |
| 682 | if (cid_reserv->in_port->res_type == CAM_ISP_IFE_IN_RES_TPG) { |
| 683 | csid_hw->csi2_rx_cfg.phy_sel = 0; |
| 684 | if (cid_reserv->in_port->format > |
| 685 | CAM_FORMAT_MIPI_RAW_16) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 686 | CAM_ERR(CAM_ISP, " Wrong TPG format"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 687 | rc = -EINVAL; |
| 688 | goto end; |
| 689 | } |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 690 | csid_hw->tpg_cfg.in_format = |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 691 | cid_reserv->in_port->format; |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 692 | csid_hw->tpg_cfg.usage_type = |
| 693 | cid_reserv->in_port->usage_type; |
| 694 | if (cid_reserv->in_port->usage_type) |
| 695 | csid_hw->tpg_cfg.width = |
| 696 | (cid_reserv->in_port->right_stop + 1); |
| 697 | else |
| 698 | csid_hw->tpg_cfg.width = |
| 699 | cid_reserv->in_port->left_width; |
| 700 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 701 | csid_hw->tpg_cfg.height = cid_reserv->in_port->height; |
| 702 | csid_hw->tpg_cfg.test_pattern = |
| 703 | cid_reserv->in_port->test_pattern; |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 704 | |
| 705 | CAM_DBG(CAM_ISP, "CSID:%d TPG width:%d height:%d", |
| 706 | csid_hw->hw_intf->hw_idx, |
| 707 | csid_hw->tpg_cfg.width, |
| 708 | csid_hw->tpg_cfg.height); |
| 709 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 710 | cid_data->tpg_set = 1; |
| 711 | } else { |
| 712 | csid_hw->csi2_rx_cfg.phy_sel = |
| 713 | (cid_reserv->in_port->res_type & 0xFF) - 1; |
| 714 | } |
| 715 | |
| 716 | cid_data->vc = cid_reserv->in_port->vc; |
| 717 | cid_data->dt = cid_reserv->in_port->dt; |
| 718 | cid_data->cnt = 1; |
| 719 | cid_reserv->node_res = &csid_hw->cid_res[0]; |
| 720 | csid_hw->csi2_reserve_cnt++; |
| 721 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 722 | CAM_DBG(CAM_ISP, |
| 723 | "CSID:%d CID :%d resource acquired successfully", |
| 724 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 725 | cid_reserv->node_res->res_id); |
| 726 | } else { |
| 727 | rc = cam_ife_csid_cid_get(csid_hw, &cid_reserv->node_res, |
| 728 | cid_reserv->in_port->vc, cid_reserv->in_port->dt, |
| 729 | cid_reserv->in_port->res_type); |
| 730 | /* if success then increment the reserve count */ |
| 731 | if (!rc) { |
| 732 | if (csid_hw->csi2_reserve_cnt == UINT_MAX) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 733 | CAM_ERR(CAM_ISP, |
| 734 | "CSID%d reserve cnt reached max", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 735 | csid_hw->hw_intf->hw_idx); |
| 736 | rc = -EINVAL; |
| 737 | } else { |
| 738 | csid_hw->csi2_reserve_cnt++; |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 739 | CAM_DBG(CAM_ISP, "CSID:%d CID:%d acquired", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 740 | csid_hw->hw_intf->hw_idx, |
| 741 | cid_reserv->node_res->res_id); |
| 742 | } |
| 743 | } |
| 744 | } |
| 745 | |
| 746 | end: |
| 747 | return rc; |
| 748 | } |
| 749 | |
| 750 | |
| 751 | static int cam_ife_csid_path_reserve(struct cam_ife_csid_hw *csid_hw, |
| 752 | struct cam_csid_hw_reserve_resource_args *reserve) |
| 753 | { |
| 754 | int rc = 0; |
| 755 | struct cam_ife_csid_path_cfg *path_data; |
| 756 | struct cam_isp_resource_node *res; |
| 757 | |
| 758 | /* CSID CSI2 v2.0 supports 31 vc */ |
| 759 | if (reserve->in_port->dt > 0x3f || reserve->in_port->vc > 0x1f || |
| 760 | (reserve->sync_mode >= CAM_ISP_HW_SYNC_MAX)) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 761 | CAM_ERR(CAM_ISP, "CSID:%d Invalid vc:%d dt %d mode:%d", |
| 762 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 763 | reserve->in_port->vc, reserve->in_port->dt, |
| 764 | reserve->sync_mode); |
| 765 | rc = -EINVAL; |
| 766 | goto end; |
| 767 | } |
| 768 | |
| 769 | switch (reserve->res_id) { |
| 770 | case CAM_IFE_PIX_PATH_RES_IPP: |
| 771 | if (csid_hw->ipp_res.res_state != |
| 772 | CAM_ISP_RESOURCE_STATE_AVAILABLE) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 773 | CAM_DBG(CAM_ISP, |
| 774 | "CSID:%d IPP resource not available %d", |
| 775 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 776 | csid_hw->ipp_res.res_state); |
| 777 | rc = -EINVAL; |
| 778 | goto end; |
| 779 | } |
| 780 | |
| 781 | if (cam_ife_csid_is_ipp_format_supported( |
| 782 | reserve->in_port->format)) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 783 | CAM_ERR(CAM_ISP, |
| 784 | "CSID:%d res id:%d un support format %d", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 785 | csid_hw->hw_intf->hw_idx, reserve->res_id, |
| 786 | reserve->in_port->format); |
| 787 | rc = -EINVAL; |
| 788 | goto end; |
| 789 | } |
| 790 | |
| 791 | /* assign the IPP resource */ |
| 792 | res = &csid_hw->ipp_res; |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 793 | CAM_DBG(CAM_ISP, |
| 794 | "CSID:%d IPP resource:%d acquired successfully", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 795 | csid_hw->hw_intf->hw_idx, res->res_id); |
| 796 | |
| 797 | break; |
| 798 | case CAM_IFE_PIX_PATH_RES_RDI_0: |
| 799 | case CAM_IFE_PIX_PATH_RES_RDI_1: |
| 800 | case CAM_IFE_PIX_PATH_RES_RDI_2: |
| 801 | case CAM_IFE_PIX_PATH_RES_RDI_3: |
| 802 | if (csid_hw->rdi_res[reserve->res_id].res_state != |
| 803 | CAM_ISP_RESOURCE_STATE_AVAILABLE) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 804 | CAM_DBG(CAM_ISP, |
| 805 | "CSID:%d RDI:%d resource not available %d", |
| 806 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 807 | reserve->res_id, |
| 808 | csid_hw->rdi_res[reserve->res_id].res_state); |
| 809 | rc = -EINVAL; |
| 810 | goto end; |
| 811 | } else { |
| 812 | res = &csid_hw->rdi_res[reserve->res_id]; |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 813 | CAM_DBG(CAM_ISP, |
| 814 | "CSID:%d RDI resource:%d acquire success", |
| 815 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 816 | res->res_id); |
| 817 | } |
| 818 | |
| 819 | break; |
| 820 | default: |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 821 | CAM_ERR(CAM_ISP, "CSID:%d Invalid res id:%d", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 822 | csid_hw->hw_intf->hw_idx, reserve->res_id); |
| 823 | rc = -EINVAL; |
| 824 | goto end; |
| 825 | } |
| 826 | |
| 827 | res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; |
| 828 | path_data = (struct cam_ife_csid_path_cfg *)res->res_priv; |
| 829 | |
| 830 | path_data->cid = reserve->cid; |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 831 | path_data->in_format = reserve->in_port->format; |
| 832 | path_data->out_format = reserve->out_port->format; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 833 | path_data->master_idx = reserve->master_idx; |
| 834 | path_data->sync_mode = reserve->sync_mode; |
| 835 | path_data->height = reserve->in_port->height; |
| 836 | path_data->start_line = reserve->in_port->line_start; |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 837 | path_data->end_line = reserve->in_port->line_stop; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 838 | if (reserve->in_port->res_type == CAM_ISP_IFE_IN_RES_TPG) { |
| 839 | path_data->dt = CAM_IFE_CSID_TPG_DT_VAL; |
| 840 | path_data->vc = CAM_IFE_CSID_TPG_VC_VAL; |
| 841 | } else { |
| 842 | path_data->dt = reserve->in_port->dt; |
| 843 | path_data->vc = reserve->in_port->vc; |
| 844 | } |
| 845 | |
| 846 | if (reserve->sync_mode == CAM_ISP_HW_SYNC_MASTER) { |
| 847 | path_data->crop_enable = 1; |
| 848 | path_data->start_pixel = reserve->in_port->left_start; |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 849 | path_data->end_pixel = reserve->in_port->left_stop; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 850 | path_data->width = reserve->in_port->left_width; |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 851 | CAM_DBG(CAM_ISP, "CSID:%dmaster:startpixel 0x%x endpixel:0x%x", |
| 852 | csid_hw->hw_intf->hw_idx, path_data->start_pixel, |
| 853 | path_data->end_pixel); |
| 854 | CAM_DBG(CAM_ISP, "CSID:%dmaster:line start:0x%x line end:0x%x", |
| 855 | csid_hw->hw_intf->hw_idx, path_data->start_line, |
| 856 | path_data->end_line); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 857 | } else if (reserve->sync_mode == CAM_ISP_HW_SYNC_SLAVE) { |
| 858 | path_data->crop_enable = 1; |
| 859 | path_data->start_pixel = reserve->in_port->right_start; |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 860 | path_data->end_pixel = reserve->in_port->right_stop; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 861 | path_data->width = reserve->in_port->right_width; |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 862 | CAM_DBG(CAM_ISP, "CSID:%d slave:start:0x%x end:0x%x width 0x%x", |
| 863 | csid_hw->hw_intf->hw_idx, path_data->start_pixel, |
| 864 | path_data->end_pixel, path_data->width); |
| 865 | CAM_DBG(CAM_ISP, "CSID:%dmaster:line start:0x%x line end:0x%x", |
| 866 | csid_hw->hw_intf->hw_idx, path_data->start_line, |
| 867 | path_data->end_line); |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 868 | } else { |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 869 | path_data->crop_enable = 0; |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 870 | path_data->width = reserve->in_port->left_width; |
| 871 | path_data->start_pixel = reserve->in_port->left_start; |
| 872 | } |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 873 | |
Ravikishore Pampana | c19ba62 | 2017-09-21 17:20:48 +0530 | [diff] [blame] | 874 | CAM_DBG(CAM_ISP, "Res %d width %d height %d", reserve->res_id, |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 875 | path_data->width, path_data->height); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 876 | reserve->node_res = res; |
| 877 | |
| 878 | end: |
| 879 | return rc; |
| 880 | } |
| 881 | |
| 882 | static int cam_ife_csid_enable_hw(struct cam_ife_csid_hw *csid_hw) |
| 883 | { |
| 884 | int rc = 0; |
| 885 | struct cam_ife_csid_reg_offset *csid_reg; |
| 886 | struct cam_hw_soc_info *soc_info; |
| 887 | uint32_t i, status, val; |
| 888 | |
| 889 | csid_reg = csid_hw->csid_info->csid_reg; |
| 890 | soc_info = &csid_hw->hw_info->soc_info; |
| 891 | |
| 892 | /* overflow check before increment */ |
| 893 | if (csid_hw->hw_info->open_count == UINT_MAX) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 894 | CAM_ERR(CAM_ISP, "CSID:%d Open count reached max", |
| 895 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 896 | return -EINVAL; |
| 897 | } |
| 898 | |
| 899 | /* Increment ref Count */ |
| 900 | csid_hw->hw_info->open_count++; |
| 901 | if (csid_hw->hw_info->open_count > 1) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 902 | CAM_DBG(CAM_ISP, "CSID hw has already been enabled"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 903 | return rc; |
| 904 | } |
| 905 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 906 | CAM_DBG(CAM_ISP, "CSID:%d init CSID HW", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 907 | csid_hw->hw_intf->hw_idx); |
| 908 | |
| 909 | rc = cam_ife_csid_enable_soc_resources(soc_info); |
| 910 | if (rc) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 911 | CAM_ERR(CAM_ISP, "CSID:%d Enable SOC failed", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 912 | csid_hw->hw_intf->hw_idx); |
| 913 | goto err; |
| 914 | } |
| 915 | |
| 916 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 917 | CAM_DBG(CAM_ISP, "CSID:%d enable top irq interrupt", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 918 | csid_hw->hw_intf->hw_idx); |
| 919 | |
| 920 | csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_UP; |
| 921 | /* Enable the top IRQ interrupt */ |
| 922 | cam_io_w_mb(1, soc_info->reg_map[0].mem_base + |
| 923 | csid_reg->cmn_reg->csid_top_irq_mask_addr); |
| 924 | |
| 925 | rc = cam_ife_csid_global_reset(csid_hw); |
| 926 | if (rc) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 927 | CAM_ERR(CAM_ISP, "CSID:%d csid_reset fail rc = %d", |
| 928 | csid_hw->hw_intf->hw_idx, rc); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 929 | rc = -ETIMEDOUT; |
| 930 | goto disable_soc; |
| 931 | } |
| 932 | |
| 933 | /* |
| 934 | * Reset the SW registers |
| 935 | * SW register reset also reset the mask irq, so poll the irq status |
| 936 | * to check the reset complete. |
| 937 | */ |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 938 | CAM_DBG(CAM_ISP, "CSID:%d Reset Software registers", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 939 | csid_hw->hw_intf->hw_idx); |
| 940 | |
| 941 | cam_io_w_mb(csid_reg->cmn_reg->csid_rst_stb_sw_all, |
| 942 | soc_info->reg_map[0].mem_base + |
| 943 | csid_reg->cmn_reg->csid_rst_strobes_addr); |
| 944 | |
| 945 | rc = readl_poll_timeout(soc_info->reg_map[0].mem_base + |
| 946 | csid_reg->cmn_reg->csid_top_irq_status_addr, |
| 947 | status, (status & 0x1) == 0x1, |
| 948 | CAM_IFE_CSID_TIMEOUT_SLEEP_US, CAM_IFE_CSID_TIMEOUT_ALL_US); |
| 949 | if (rc < 0) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 950 | CAM_ERR(CAM_ISP, "software register reset timeout....."); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 951 | rc = -ETIMEDOUT; |
| 952 | goto disable_soc; |
| 953 | } |
| 954 | |
| 955 | /* clear all interrupts */ |
| 956 | cam_io_w_mb(1, soc_info->reg_map[0].mem_base + |
| 957 | csid_reg->cmn_reg->csid_top_irq_clear_addr); |
| 958 | |
| 959 | cam_io_w_mb(csid_reg->csi2_reg->csi2_irq_mask_all, |
| 960 | soc_info->reg_map[0].mem_base + |
| 961 | csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr); |
| 962 | |
| 963 | if (csid_reg->cmn_reg->no_pix) |
| 964 | cam_io_w_mb(csid_reg->cmn_reg->ipp_irq_mask_all, |
| 965 | soc_info->reg_map[0].mem_base + |
| 966 | csid_reg->ipp_reg->csid_ipp_irq_clear_addr); |
| 967 | |
| 968 | for (i = 0; i < csid_reg->cmn_reg->no_rdis; i++) |
| 969 | cam_io_w_mb(csid_reg->cmn_reg->rdi_irq_mask_all, |
| 970 | soc_info->reg_map[0].mem_base + |
| 971 | csid_reg->rdi_reg[i]->csid_rdi_irq_clear_addr); |
| 972 | |
| 973 | cam_io_w_mb(1, soc_info->reg_map[0].mem_base + |
| 974 | csid_reg->cmn_reg->csid_irq_cmd_addr); |
| 975 | |
| 976 | /* Enable the top IRQ interrupt */ |
| 977 | cam_io_w_mb(1, soc_info->reg_map[0].mem_base + |
| 978 | csid_reg->cmn_reg->csid_top_irq_mask_addr); |
| 979 | |
| 980 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 981 | csid_reg->cmn_reg->csid_hw_version_addr); |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 982 | CAM_DBG(CAM_ISP, "CSID:%d CSID HW version: 0x%x", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 983 | csid_hw->hw_intf->hw_idx, val); |
| 984 | |
| 985 | return 0; |
| 986 | |
| 987 | disable_soc: |
| 988 | cam_ife_csid_disable_soc_resources(soc_info); |
| 989 | csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; |
| 990 | err: |
| 991 | csid_hw->hw_info->open_count--; |
| 992 | return rc; |
| 993 | } |
| 994 | |
| 995 | static int cam_ife_csid_disable_hw(struct cam_ife_csid_hw *csid_hw) |
| 996 | { |
| 997 | int rc = 0; |
| 998 | struct cam_hw_soc_info *soc_info; |
| 999 | struct cam_ife_csid_reg_offset *csid_reg; |
| 1000 | |
| 1001 | |
| 1002 | /* Decrement ref Count */ |
| 1003 | if (csid_hw->hw_info->open_count) |
| 1004 | csid_hw->hw_info->open_count--; |
| 1005 | if (csid_hw->hw_info->open_count) |
| 1006 | return rc; |
| 1007 | |
| 1008 | soc_info = &csid_hw->hw_info->soc_info; |
| 1009 | csid_reg = csid_hw->csid_info->csid_reg; |
| 1010 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1011 | CAM_DBG(CAM_ISP, "CSID:%d De-init CSID HW", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1012 | csid_hw->hw_intf->hw_idx); |
| 1013 | |
| 1014 | /*disable the top IRQ interrupt */ |
| 1015 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 1016 | csid_reg->cmn_reg->csid_top_irq_mask_addr); |
| 1017 | |
| 1018 | rc = cam_ife_csid_disable_soc_resources(soc_info); |
| 1019 | if (rc) |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1020 | CAM_ERR(CAM_ISP, "CSID:%d Disable CSID SOC failed", |
| 1021 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1022 | |
| 1023 | csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; |
| 1024 | return rc; |
| 1025 | } |
| 1026 | |
| 1027 | |
| 1028 | static int cam_ife_csid_tpg_start(struct cam_ife_csid_hw *csid_hw, |
| 1029 | struct cam_isp_resource_node *res) |
| 1030 | { |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1031 | int rc = 0; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1032 | uint32_t val = 0; |
| 1033 | struct cam_hw_soc_info *soc_info; |
| 1034 | |
| 1035 | csid_hw->tpg_start_cnt++; |
| 1036 | if (csid_hw->tpg_start_cnt == 1) { |
| 1037 | /*Enable the TPG */ |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1038 | CAM_DBG(CAM_ISP, "CSID:%d start CSID TPG", |
| 1039 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1040 | |
| 1041 | soc_info = &csid_hw->hw_info->soc_info; |
| 1042 | { |
| 1043 | uint32_t val; |
| 1044 | uint32_t i; |
| 1045 | uint32_t base = 0x600; |
| 1046 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1047 | CAM_DBG(CAM_ISP, "================ TPG ============"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1048 | for (i = 0; i < 16; i++) { |
| 1049 | val = cam_io_r_mb( |
| 1050 | soc_info->reg_map[0].mem_base + |
| 1051 | base + i * 4); |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1052 | CAM_DBG(CAM_ISP, "reg 0x%x = 0x%x", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1053 | (base + i*4), val); |
| 1054 | } |
| 1055 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1056 | CAM_DBG(CAM_ISP, "================ IPP ============="); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1057 | base = 0x200; |
| 1058 | for (i = 0; i < 10; i++) { |
| 1059 | val = cam_io_r_mb( |
| 1060 | soc_info->reg_map[0].mem_base + |
| 1061 | base + i * 4); |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1062 | CAM_DBG(CAM_ISP, "reg 0x%x = 0x%x", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1063 | (base + i*4), val); |
| 1064 | } |
| 1065 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1066 | CAM_DBG(CAM_ISP, "================ RX ============="); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1067 | base = 0x100; |
| 1068 | for (i = 0; i < 5; i++) { |
| 1069 | val = cam_io_r_mb( |
| 1070 | soc_info->reg_map[0].mem_base + |
| 1071 | base + i * 4); |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1072 | CAM_DBG(CAM_ISP, "reg 0x%x = 0x%x", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1073 | (base + i*4), val); |
| 1074 | } |
| 1075 | } |
| 1076 | |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1077 | /* Enable the IFE force clock on for dual isp case */ |
| 1078 | if (csid_hw->tpg_cfg.usage_type) { |
| 1079 | rc = cam_ife_csid_enable_ife_force_clock_on(soc_info, |
| 1080 | csid_hw->csid_info->csid_reg->tpg_reg-> |
| 1081 | tpg_cpas_ife_reg_offset); |
| 1082 | if (rc) |
| 1083 | return rc; |
| 1084 | } |
| 1085 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1086 | CAM_DBG(CAM_ISP, "============ TPG control ============"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1087 | val = (4 << 20); |
| 1088 | val |= (0x80 << 8); |
| 1089 | val |= (((csid_hw->csi2_rx_cfg.lane_num - 1) & 0x3) << 4); |
| 1090 | val |= 7; |
| 1091 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1092 | csid_hw->csid_info->csid_reg->tpg_reg-> |
| 1093 | csid_tpg_ctrl_addr); |
| 1094 | |
| 1095 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + 0x600); |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1096 | CAM_DBG(CAM_ISP, "reg 0x%x = 0x%x", 0x600, val); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1097 | } |
| 1098 | |
| 1099 | return 0; |
| 1100 | } |
| 1101 | |
| 1102 | static int cam_ife_csid_tpg_stop(struct cam_ife_csid_hw *csid_hw, |
| 1103 | struct cam_isp_resource_node *res) |
| 1104 | { |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1105 | int rc = 0; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1106 | struct cam_hw_soc_info *soc_info; |
| 1107 | |
| 1108 | if (csid_hw->tpg_start_cnt) |
| 1109 | csid_hw->tpg_start_cnt--; |
| 1110 | |
| 1111 | if (csid_hw->tpg_start_cnt) |
| 1112 | return 0; |
| 1113 | |
| 1114 | soc_info = &csid_hw->hw_info->soc_info; |
| 1115 | |
| 1116 | /* disable the TPG */ |
| 1117 | if (!csid_hw->tpg_start_cnt) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1118 | CAM_DBG(CAM_ISP, "CSID:%d stop CSID TPG", |
| 1119 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1120 | |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1121 | /* Disable the IFE force clock on for dual isp case */ |
| 1122 | if (csid_hw->tpg_cfg.usage_type) |
| 1123 | rc = cam_ife_csid_disable_ife_force_clock_on(soc_info, |
| 1124 | csid_hw->csid_info->csid_reg->tpg_reg-> |
| 1125 | tpg_cpas_ife_reg_offset); |
| 1126 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1127 | /*stop the TPG */ |
| 1128 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 1129 | csid_hw->csid_info->csid_reg->tpg_reg->csid_tpg_ctrl_addr); |
| 1130 | } |
| 1131 | |
| 1132 | return 0; |
| 1133 | } |
| 1134 | |
| 1135 | |
| 1136 | static int cam_ife_csid_config_tpg(struct cam_ife_csid_hw *csid_hw, |
| 1137 | struct cam_isp_resource_node *res) |
| 1138 | { |
| 1139 | struct cam_ife_csid_reg_offset *csid_reg; |
| 1140 | struct cam_hw_soc_info *soc_info; |
| 1141 | uint32_t val = 0; |
| 1142 | |
| 1143 | csid_reg = csid_hw->csid_info->csid_reg; |
| 1144 | soc_info = &csid_hw->hw_info->soc_info; |
| 1145 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1146 | CAM_DBG(CAM_ISP, "CSID:%d TPG config", |
| 1147 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1148 | |
| 1149 | /* configure one DT, infinite frames */ |
| 1150 | val = (0 << 16) | (1 << 10) | CAM_IFE_CSID_TPG_VC_VAL; |
| 1151 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1152 | csid_reg->tpg_reg->csid_tpg_vc_cfg0_addr); |
| 1153 | |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1154 | /* vertical blanking count = 0x3FF, horzontal blanking count = 0x740*/ |
| 1155 | val = (0x3FF << 12) | 0x740; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1156 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1157 | csid_reg->tpg_reg->csid_tpg_vc_cfg1_addr); |
| 1158 | |
| 1159 | cam_io_w_mb(0x12345678, soc_info->reg_map[0].mem_base + |
| 1160 | csid_hw->csid_info->csid_reg->tpg_reg->csid_tpg_lfsr_seed_addr); |
| 1161 | |
| 1162 | val = csid_hw->tpg_cfg.width << 16 | |
| 1163 | csid_hw->tpg_cfg.height; |
| 1164 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1165 | csid_reg->tpg_reg->csid_tpg_dt_n_cfg_0_addr); |
| 1166 | |
| 1167 | cam_io_w_mb(CAM_IFE_CSID_TPG_DT_VAL, soc_info->reg_map[0].mem_base + |
| 1168 | csid_reg->tpg_reg->csid_tpg_dt_n_cfg_1_addr); |
| 1169 | |
| 1170 | /* |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 1171 | * in_format is the same as the input resource format. |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1172 | * it is one larger than the register spec format. |
| 1173 | */ |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 1174 | val = ((csid_hw->tpg_cfg.in_format - 1) << 16) | 0x8; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1175 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1176 | csid_reg->tpg_reg->csid_tpg_dt_n_cfg_2_addr); |
| 1177 | |
Jing Zhou | a4e9fbe | 2017-05-15 14:37:21 -0700 | [diff] [blame] | 1178 | /* static frame with split color bar */ |
| 1179 | val = 1 << 5; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1180 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1181 | csid_reg->tpg_reg->csid_tpg_color_bars_cfg_addr); |
| 1182 | /* config pix pattern */ |
| 1183 | cam_io_w_mb(csid_hw->tpg_cfg.test_pattern, |
| 1184 | soc_info->reg_map[0].mem_base + |
| 1185 | csid_reg->tpg_reg->csid_tpg_common_gen_cfg_addr); |
| 1186 | |
| 1187 | return 0; |
| 1188 | } |
| 1189 | |
| 1190 | static int cam_ife_csid_enable_csi2( |
| 1191 | struct cam_ife_csid_hw *csid_hw, |
| 1192 | struct cam_isp_resource_node *res) |
| 1193 | { |
| 1194 | int rc = 0; |
| 1195 | struct cam_ife_csid_reg_offset *csid_reg; |
| 1196 | struct cam_hw_soc_info *soc_info; |
| 1197 | struct cam_ife_csid_cid_data *cid_data; |
| 1198 | uint32_t val = 0; |
| 1199 | |
| 1200 | csid_reg = csid_hw->csid_info->csid_reg; |
| 1201 | soc_info = &csid_hw->hw_info->soc_info; |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1202 | CAM_DBG(CAM_ISP, "CSID:%d count:%d config csi2 rx", |
| 1203 | csid_hw->hw_intf->hw_idx, csid_hw->csi2_cfg_cnt); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1204 | |
| 1205 | /* overflow check before increment */ |
| 1206 | if (csid_hw->csi2_cfg_cnt == UINT_MAX) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1207 | CAM_ERR(CAM_ISP, "CSID:%d Open count reached max", |
| 1208 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1209 | return -EINVAL; |
| 1210 | } |
| 1211 | |
| 1212 | cid_data = (struct cam_ife_csid_cid_data *)res->res_priv; |
| 1213 | |
| 1214 | res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; |
| 1215 | csid_hw->csi2_cfg_cnt++; |
| 1216 | if (csid_hw->csi2_cfg_cnt > 1) |
| 1217 | return rc; |
| 1218 | |
| 1219 | /* rx cfg0 */ |
| 1220 | val = (csid_hw->csi2_rx_cfg.lane_num - 1) | |
| 1221 | (csid_hw->csi2_rx_cfg.lane_cfg << 4) | |
| 1222 | (csid_hw->csi2_rx_cfg.lane_type << 24); |
Alex Wong | 7857860 | 2017-07-07 19:51:43 -0700 | [diff] [blame] | 1223 | val |= (csid_hw->csi2_rx_cfg.phy_sel & 0x3) << 20; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1224 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1225 | csid_reg->csi2_reg->csid_csi2_rx_cfg0_addr); |
| 1226 | |
| 1227 | /* rx cfg1*/ |
| 1228 | val = (1 << csid_reg->csi2_reg->csi2_misr_enable_shift_val); |
| 1229 | /* if VC value is more than 3 than set full width of VC */ |
| 1230 | if (cid_data->vc > 3) |
| 1231 | val |= (1 << csid_reg->csi2_reg->csi2_vc_mode_shift_val); |
| 1232 | |
| 1233 | /* enable packet ecc correction */ |
| 1234 | val |= 1; |
| 1235 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1236 | csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); |
| 1237 | |
| 1238 | if (csid_hw->res_type == CAM_ISP_IFE_IN_RES_TPG) { |
| 1239 | /* Config the TPG */ |
| 1240 | rc = cam_ife_csid_config_tpg(csid_hw, res); |
| 1241 | if (rc) { |
| 1242 | res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; |
| 1243 | return rc; |
| 1244 | } |
| 1245 | } |
| 1246 | |
| 1247 | /*Enable the CSI2 rx inerrupts */ |
| 1248 | val = CSID_CSI2_RX_INFO_RST_DONE | |
| 1249 | CSID_CSI2_RX_ERROR_TG_FIFO_OVERFLOW | |
| 1250 | CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW | |
| 1251 | CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW | |
| 1252 | CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW | |
| 1253 | CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW | |
| 1254 | CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION | |
| 1255 | CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION | |
Harsh Shah | 1b8eb23 | 2017-10-09 19:20:52 -0700 | [diff] [blame] | 1256 | CSID_CSI2_RX_ERROR_CRC | |
| 1257 | CSID_CSI2_RX_ERROR_ECC | |
| 1258 | CSID_CSI2_RX_ERROR_MMAPPED_VC_DT | |
| 1259 | CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW | |
| 1260 | CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1261 | CSID_CSI2_RX_ERROR_CPHY_PH_CRC; |
Ravikishore Pampana | c19ba62 | 2017-09-21 17:20:48 +0530 | [diff] [blame] | 1262 | |
| 1263 | /* Enable the interrupt based on csid debug info set */ |
| 1264 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOT_IRQ) |
| 1265 | val |= CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED | |
| 1266 | CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED | |
| 1267 | CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED | |
| 1268 | CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED; |
| 1269 | |
| 1270 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOT_IRQ) |
| 1271 | val |= CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED | |
| 1272 | CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED | |
| 1273 | CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED | |
| 1274 | CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED; |
| 1275 | |
| 1276 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) |
| 1277 | val |= CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED; |
| 1278 | |
| 1279 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) |
| 1280 | val |= CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED; |
| 1281 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) |
| 1282 | val |= CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED; |
| 1283 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1284 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1285 | csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); |
| 1286 | |
| 1287 | return 0; |
| 1288 | } |
| 1289 | |
| 1290 | static int cam_ife_csid_disable_csi2( |
| 1291 | struct cam_ife_csid_hw *csid_hw, |
| 1292 | struct cam_isp_resource_node *res) |
| 1293 | { |
| 1294 | struct cam_ife_csid_reg_offset *csid_reg; |
| 1295 | struct cam_hw_soc_info *soc_info; |
| 1296 | |
| 1297 | if (res->res_id >= CAM_IFE_CSID_CID_MAX) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1298 | CAM_ERR(CAM_ISP, "CSID:%d Invalid res id :%d", |
| 1299 | csid_hw->hw_intf->hw_idx, res->res_id); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1300 | return -EINVAL; |
| 1301 | } |
| 1302 | |
| 1303 | csid_reg = csid_hw->csid_info->csid_reg; |
| 1304 | soc_info = &csid_hw->hw_info->soc_info; |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1305 | CAM_DBG(CAM_ISP, "CSID:%d cnt : %d Disable csi2 rx", |
| 1306 | csid_hw->hw_intf->hw_idx, csid_hw->csi2_cfg_cnt); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1307 | |
| 1308 | if (csid_hw->csi2_cfg_cnt) |
| 1309 | csid_hw->csi2_cfg_cnt--; |
| 1310 | |
| 1311 | if (csid_hw->csi2_cfg_cnt) |
| 1312 | return 0; |
| 1313 | |
| 1314 | /*Disable the CSI2 rx inerrupts */ |
| 1315 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 1316 | csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); |
| 1317 | |
| 1318 | res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; |
| 1319 | |
| 1320 | return 0; |
| 1321 | } |
| 1322 | |
| 1323 | static int cam_ife_csid_init_config_ipp_path( |
| 1324 | struct cam_ife_csid_hw *csid_hw, |
| 1325 | struct cam_isp_resource_node *res) |
| 1326 | { |
| 1327 | int rc = 0; |
| 1328 | struct cam_ife_csid_path_cfg *path_data; |
| 1329 | struct cam_ife_csid_reg_offset *csid_reg; |
| 1330 | struct cam_hw_soc_info *soc_info; |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 1331 | uint32_t decode_format = 0, plain_format = 0, val = 0; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1332 | |
| 1333 | path_data = (struct cam_ife_csid_path_cfg *) res->res_priv; |
| 1334 | csid_reg = csid_hw->csid_info->csid_reg; |
| 1335 | soc_info = &csid_hw->hw_info->soc_info; |
| 1336 | |
| 1337 | if (!csid_reg->ipp_reg) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1338 | CAM_ERR(CAM_ISP, "CSID:%d IPP:%d is not supported on HW", |
| 1339 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1340 | res->res_id); |
| 1341 | return -EINVAL; |
| 1342 | } |
| 1343 | |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 1344 | CAM_DBG(CAM_ISP, "Config IPP Path"); |
| 1345 | rc = cam_ife_csid_get_format_ipp(path_data->in_format, |
| 1346 | &decode_format, &plain_format); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1347 | if (rc) |
| 1348 | return rc; |
| 1349 | |
Jing Zhou | bb536a8 | 2017-05-18 15:20:38 -0700 | [diff] [blame] | 1350 | /* |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1351 | * configure the IPP and enable the time stamp capture. |
| 1352 | * enable the HW measrurement blocks |
| 1353 | */ |
| 1354 | val = (path_data->vc << csid_reg->cmn_reg->vc_shift_val) | |
| 1355 | (path_data->dt << csid_reg->cmn_reg->dt_shift_val) | |
| 1356 | (path_data->cid << csid_reg->cmn_reg->dt_id_shift_val) | |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 1357 | (decode_format << csid_reg->cmn_reg->fmt_shift_val) | |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1358 | (path_data->crop_enable << |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1359 | csid_reg->cmn_reg->crop_h_en_shift_val) | |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1360 | (path_data->crop_enable << |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1361 | csid_reg->cmn_reg->crop_v_en_shift_val) | |
| 1362 | (1 << 1) | 1; |
| 1363 | val |= (1 << csid_reg->ipp_reg->pix_store_en_shift_val); |
| 1364 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1365 | csid_reg->ipp_reg->csid_ipp_cfg0_addr); |
| 1366 | |
Jing Zhou | dedc476 | 2017-06-19 17:45:36 +0530 | [diff] [blame] | 1367 | /* select the post irq sub sample strobe for time stamp capture */ |
| 1368 | cam_io_w_mb(CSID_TIMESTAMP_STB_POST_IRQ, soc_info->reg_map[0].mem_base + |
| 1369 | csid_reg->ipp_reg->csid_ipp_cfg1_addr); |
| 1370 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1371 | if (path_data->crop_enable) { |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1372 | val = (((path_data->end_pixel & 0xFFFF) << |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1373 | csid_reg->cmn_reg->crop_shift) | |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1374 | (path_data->start_pixel & 0xFFFF)); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1375 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1376 | csid_reg->ipp_reg->csid_ipp_hcrop_addr); |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1377 | CAM_DBG(CAM_ISP, "CSID:%d Horizontal crop config val: 0x%x", |
| 1378 | csid_hw->hw_intf->hw_idx, val); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1379 | |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1380 | val = (((path_data->end_line & 0xFFFF) << |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1381 | csid_reg->cmn_reg->crop_shift) | |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1382 | (path_data->start_line & 0xFFFF)); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1383 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1384 | csid_reg->ipp_reg->csid_ipp_vcrop_addr); |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1385 | CAM_DBG(CAM_ISP, "CSID:%d Vertical Crop config val: 0x%x", |
| 1386 | csid_hw->hw_intf->hw_idx, val); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1387 | } |
| 1388 | |
| 1389 | /* set frame drop pattern to 0 and period to 1 */ |
| 1390 | cam_io_w_mb(1, soc_info->reg_map[0].mem_base + |
| 1391 | csid_reg->ipp_reg->csid_ipp_frm_drop_period_addr); |
| 1392 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 1393 | csid_reg->ipp_reg->csid_ipp_frm_drop_pattern_addr); |
| 1394 | /* set irq sub sample pattern to 0 and period to 1 */ |
| 1395 | cam_io_w_mb(1, soc_info->reg_map[0].mem_base + |
| 1396 | csid_reg->ipp_reg->csid_ipp_irq_subsample_period_addr); |
| 1397 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 1398 | csid_reg->ipp_reg->csid_ipp_irq_subsample_pattern_addr); |
| 1399 | /* set pixel drop pattern to 0 and period to 1 */ |
| 1400 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 1401 | csid_reg->ipp_reg->csid_ipp_pix_drop_pattern_addr); |
| 1402 | cam_io_w_mb(1, soc_info->reg_map[0].mem_base + |
| 1403 | csid_reg->ipp_reg->csid_ipp_pix_drop_period_addr); |
| 1404 | /* set line drop pattern to 0 and period to 1 */ |
| 1405 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 1406 | csid_reg->ipp_reg->csid_ipp_line_drop_pattern_addr); |
| 1407 | cam_io_w_mb(1, soc_info->reg_map[0].mem_base + |
| 1408 | csid_reg->ipp_reg->csid_ipp_line_drop_period_addr); |
| 1409 | |
| 1410 | /*Set master or slave IPP */ |
| 1411 | if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER) |
| 1412 | /*Set halt mode as master */ |
| 1413 | val = CSID_HALT_MODE_MASTER << 2; |
| 1414 | else if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) |
| 1415 | /*Set halt mode as slave and set master idx */ |
| 1416 | val = path_data->master_idx << 4 | CSID_HALT_MODE_SLAVE << 2; |
| 1417 | else |
| 1418 | /* Default is internal halt mode */ |
| 1419 | val = 0; |
| 1420 | |
| 1421 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1422 | csid_reg->ipp_reg->csid_ipp_ctrl_addr); |
| 1423 | |
| 1424 | /* Enable the IPP path */ |
| 1425 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 1426 | csid_reg->ipp_reg->csid_ipp_cfg0_addr); |
| 1427 | val |= (1 << csid_reg->cmn_reg->path_en_shift_val); |
| 1428 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1429 | csid_reg->ipp_reg->csid_ipp_cfg0_addr); |
| 1430 | |
Ravikishore Pampana | c19ba62 | 2017-09-21 17:20:48 +0530 | [diff] [blame] | 1431 | /* configure the rx packet capture based on csid debug set */ |
| 1432 | val = 0; |
| 1433 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) |
| 1434 | val = ((1 << |
| 1435 | csid_reg->csi2_reg->csi2_capture_short_pkt_en_shift) | |
| 1436 | (path_data->vc << |
| 1437 | csid_reg->csi2_reg->csi2_capture_short_pkt_vc_shift)); |
| 1438 | |
| 1439 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) |
| 1440 | val |= ((1 << |
| 1441 | csid_reg->csi2_reg->csi2_capture_long_pkt_en_shift) | |
| 1442 | (path_data->dt << |
| 1443 | csid_reg->csi2_reg->csi2_capture_long_pkt_dt_shift) | |
| 1444 | (path_data->vc << |
| 1445 | csid_reg->csi2_reg->csi2_capture_long_pkt_vc_shift)); |
| 1446 | |
| 1447 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) |
| 1448 | val |= ((1 << |
| 1449 | csid_reg->csi2_reg->csi2_capture_cphy_pkt_en_shift) | |
| 1450 | (path_data->dt << |
| 1451 | csid_reg->csi2_reg->csi2_capture_cphy_pkt_dt_shift) | |
| 1452 | (path_data->vc << |
| 1453 | csid_reg->csi2_reg->csi2_capture_cphy_pkt_vc_shift)); |
| 1454 | |
| 1455 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1456 | csid_reg->csi2_reg->csid_csi2_rx_capture_ctrl_addr); |
| 1457 | CAM_DBG(CAM_ISP, "rx capture control value 0x%x", val); |
| 1458 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1459 | res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; |
| 1460 | |
| 1461 | return rc; |
| 1462 | } |
| 1463 | |
| 1464 | static int cam_ife_csid_deinit_ipp_path( |
| 1465 | struct cam_ife_csid_hw *csid_hw, |
| 1466 | struct cam_isp_resource_node *res) |
| 1467 | { |
| 1468 | int rc = 0; |
| 1469 | struct cam_ife_csid_reg_offset *csid_reg; |
| 1470 | struct cam_hw_soc_info *soc_info; |
| 1471 | uint32_t val = 0; |
| 1472 | |
| 1473 | csid_reg = csid_hw->csid_info->csid_reg; |
| 1474 | soc_info = &csid_hw->hw_info->soc_info; |
| 1475 | |
| 1476 | if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1477 | CAM_ERR(CAM_ISP, |
| 1478 | "CSID:%d Res type %d res_id:%d in wrong state %d", |
| 1479 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1480 | res->res_type, res->res_id, res->res_state); |
| 1481 | rc = -EINVAL; |
| 1482 | } |
| 1483 | |
| 1484 | if (!csid_reg->ipp_reg) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1485 | CAM_ERR(CAM_ISP, "CSID:%d IPP %d is not supported on HW", |
| 1486 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1487 | res->res_id); |
| 1488 | rc = -EINVAL; |
| 1489 | } |
| 1490 | |
| 1491 | /* Disable the IPP path */ |
| 1492 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 1493 | csid_reg->ipp_reg->csid_ipp_cfg0_addr); |
| 1494 | val &= ~(1 << csid_reg->cmn_reg->path_en_shift_val); |
| 1495 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1496 | csid_reg->ipp_reg->csid_ipp_cfg0_addr); |
| 1497 | |
| 1498 | res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; |
| 1499 | return rc; |
| 1500 | } |
| 1501 | |
| 1502 | static int cam_ife_csid_enable_ipp_path( |
| 1503 | struct cam_ife_csid_hw *csid_hw, |
| 1504 | struct cam_isp_resource_node *res) |
| 1505 | { |
| 1506 | struct cam_ife_csid_reg_offset *csid_reg; |
| 1507 | struct cam_hw_soc_info *soc_info; |
| 1508 | struct cam_ife_csid_path_cfg *path_data; |
| 1509 | uint32_t val = 0; |
| 1510 | |
| 1511 | path_data = (struct cam_ife_csid_path_cfg *) res->res_priv; |
| 1512 | csid_reg = csid_hw->csid_info->csid_reg; |
| 1513 | soc_info = &csid_hw->hw_info->soc_info; |
| 1514 | |
| 1515 | if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1516 | CAM_ERR(CAM_ISP, |
| 1517 | "CSID:%d res type:%d res_id:%d Invalid state%d", |
| 1518 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1519 | res->res_type, res->res_id, res->res_state); |
| 1520 | return -EINVAL; |
| 1521 | } |
| 1522 | |
| 1523 | if (!csid_reg->ipp_reg) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1524 | CAM_ERR(CAM_ISP, "CSID:%d IPP %d not supported on HW", |
| 1525 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1526 | res->res_id); |
| 1527 | return -EINVAL; |
| 1528 | } |
| 1529 | |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 1530 | CAM_DBG(CAM_ISP, "Enable IPP path"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1531 | |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 1532 | /* Resume at frame boundary */ |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1533 | if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER) { |
| 1534 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 1535 | csid_reg->ipp_reg->csid_ipp_ctrl_addr); |
| 1536 | val |= CAM_CSID_RESUME_AT_FRAME_BOUNDARY; |
| 1537 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1538 | csid_reg->ipp_reg->csid_ipp_ctrl_addr); |
| 1539 | } else if (path_data->sync_mode == CAM_ISP_HW_SYNC_NONE) { |
| 1540 | cam_io_w_mb(CAM_CSID_RESUME_AT_FRAME_BOUNDARY, |
| 1541 | soc_info->reg_map[0].mem_base + |
| 1542 | csid_reg->ipp_reg->csid_ipp_ctrl_addr); |
| 1543 | } |
| 1544 | /* for slave mode, not need to resume for slave device */ |
| 1545 | |
| 1546 | /* Enable the required ipp interrupts */ |
Ravikishore Pampana | ad6bc90 | 2017-07-12 19:37:06 +0530 | [diff] [blame] | 1547 | val = CSID_PATH_INFO_RST_DONE | CSID_PATH_ERROR_FIFO_OVERFLOW; |
Ravikishore Pampana | c19ba62 | 2017-09-21 17:20:48 +0530 | [diff] [blame] | 1548 | |
| 1549 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ) |
| 1550 | val |= CSID_PATH_INFO_INPUT_SOF; |
| 1551 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ) |
| 1552 | val |= CSID_PATH_INFO_INPUT_EOF; |
| 1553 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1554 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1555 | csid_reg->ipp_reg->csid_ipp_irq_mask_addr); |
| 1556 | |
| 1557 | res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; |
| 1558 | |
| 1559 | return 0; |
| 1560 | } |
| 1561 | |
| 1562 | static int cam_ife_csid_disable_ipp_path( |
| 1563 | struct cam_ife_csid_hw *csid_hw, |
| 1564 | struct cam_isp_resource_node *res, |
| 1565 | enum cam_ife_csid_halt_cmd stop_cmd) |
| 1566 | { |
| 1567 | int rc = 0; |
| 1568 | struct cam_ife_csid_reg_offset *csid_reg; |
| 1569 | struct cam_hw_soc_info *soc_info; |
| 1570 | struct cam_ife_csid_path_cfg *path_data; |
| 1571 | uint32_t val = 0; |
| 1572 | |
| 1573 | path_data = (struct cam_ife_csid_path_cfg *) res->res_priv; |
| 1574 | csid_reg = csid_hw->csid_info->csid_reg; |
| 1575 | soc_info = &csid_hw->hw_info->soc_info; |
| 1576 | |
| 1577 | if (res->res_id >= CAM_IFE_PIX_PATH_RES_MAX) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1578 | CAM_DBG(CAM_ISP, "CSID:%d Invalid res id%d", |
| 1579 | csid_hw->hw_intf->hw_idx, res->res_id); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1580 | return -EINVAL; |
| 1581 | } |
| 1582 | |
| 1583 | if (res->res_state == CAM_ISP_RESOURCE_STATE_INIT_HW || |
| 1584 | res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1585 | CAM_DBG(CAM_ISP, "CSID:%d Res:%d already in stopped state:%d", |
| 1586 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1587 | res->res_id, res->res_state); |
| 1588 | return rc; |
| 1589 | } |
| 1590 | |
| 1591 | if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1592 | CAM_DBG(CAM_ISP, "CSID:%d Res:%d Invalid state%d", |
| 1593 | csid_hw->hw_intf->hw_idx, res->res_id, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1594 | res->res_state); |
| 1595 | return -EINVAL; |
| 1596 | } |
| 1597 | |
| 1598 | if (!csid_reg->ipp_reg) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1599 | CAM_ERR(CAM_ISP, "CSID:%d IPP%d is not supported on HW", |
| 1600 | csid_hw->hw_intf->hw_idx, res->res_id); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1601 | return -EINVAL; |
| 1602 | } |
| 1603 | |
| 1604 | if (stop_cmd != CAM_CSID_HALT_AT_FRAME_BOUNDARY && |
| 1605 | stop_cmd != CAM_CSID_HALT_IMMEDIATELY) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1606 | CAM_ERR(CAM_ISP, "CSID:%d un supported stop command:%d", |
| 1607 | csid_hw->hw_intf->hw_idx, stop_cmd); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1608 | return -EINVAL; |
| 1609 | } |
| 1610 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1611 | CAM_DBG(CAM_ISP, "CSID:%d res_id:%d", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1612 | csid_hw->hw_intf->hw_idx, res->res_id); |
| 1613 | |
| 1614 | if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER) { |
| 1615 | /* configure Halt */ |
| 1616 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 1617 | csid_reg->ipp_reg->csid_ipp_ctrl_addr); |
| 1618 | val &= ~0x3; |
| 1619 | val |= stop_cmd; |
| 1620 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1621 | csid_reg->ipp_reg->csid_ipp_ctrl_addr); |
| 1622 | } else if (path_data->sync_mode == CAM_ISP_HW_SYNC_NONE) |
| 1623 | cam_io_w_mb(stop_cmd, soc_info->reg_map[0].mem_base + |
| 1624 | csid_reg->ipp_reg->csid_ipp_ctrl_addr); |
| 1625 | |
| 1626 | /* For slave mode, halt command should take it from master */ |
| 1627 | |
| 1628 | /* Enable the EOF interrupt for resume at boundary case */ |
| 1629 | if (stop_cmd != CAM_CSID_HALT_IMMEDIATELY) { |
| 1630 | init_completion(&csid_hw->csid_ipp_complete); |
| 1631 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 1632 | csid_reg->ipp_reg->csid_ipp_irq_mask_addr); |
| 1633 | val |= CSID_PATH_INFO_INPUT_EOF; |
| 1634 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1635 | csid_reg->ipp_reg->csid_ipp_irq_mask_addr); |
| 1636 | } else { |
| 1637 | val &= ~(CSID_PATH_INFO_RST_DONE | |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 1638 | CSID_PATH_ERROR_FIFO_OVERFLOW); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1639 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1640 | csid_reg->ipp_reg->csid_ipp_irq_mask_addr); |
| 1641 | } |
| 1642 | |
| 1643 | return rc; |
| 1644 | } |
| 1645 | |
| 1646 | |
| 1647 | static int cam_ife_csid_init_config_rdi_path( |
| 1648 | struct cam_ife_csid_hw *csid_hw, |
| 1649 | struct cam_isp_resource_node *res) |
| 1650 | { |
| 1651 | int rc = 0; |
| 1652 | struct cam_ife_csid_path_cfg *path_data; |
| 1653 | struct cam_ife_csid_reg_offset *csid_reg; |
| 1654 | struct cam_hw_soc_info *soc_info; |
| 1655 | uint32_t path_format = 0, plain_fmt = 0, val = 0, id; |
| 1656 | |
| 1657 | path_data = (struct cam_ife_csid_path_cfg *) res->res_priv; |
| 1658 | csid_reg = csid_hw->csid_info->csid_reg; |
| 1659 | soc_info = &csid_hw->hw_info->soc_info; |
| 1660 | |
| 1661 | id = res->res_id; |
| 1662 | if (!csid_reg->rdi_reg[id]) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1663 | CAM_ERR(CAM_ISP, "CSID:%d RDI:%d is not supported on HW", |
| 1664 | csid_hw->hw_intf->hw_idx, id); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1665 | return -EINVAL; |
| 1666 | } |
| 1667 | |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 1668 | rc = cam_ife_csid_get_format_rdi(path_data->in_format, |
| 1669 | path_data->out_format, &path_format, &plain_fmt); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1670 | if (rc) |
| 1671 | return rc; |
| 1672 | |
Jing Zhou | bb536a8 | 2017-05-18 15:20:38 -0700 | [diff] [blame] | 1673 | /* |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1674 | * RDI path config and enable the time stamp capture |
| 1675 | * Enable the measurement blocks |
| 1676 | */ |
| 1677 | val = (path_data->vc << csid_reg->cmn_reg->vc_shift_val) | |
| 1678 | (path_data->dt << csid_reg->cmn_reg->dt_shift_val) | |
| 1679 | (path_data->cid << csid_reg->cmn_reg->dt_id_shift_val) | |
| 1680 | (path_format << csid_reg->cmn_reg->fmt_shift_val) | |
| 1681 | (plain_fmt << csid_reg->cmn_reg->plain_fmt_shit_val) | |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1682 | (path_data->crop_enable << |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1683 | csid_reg->cmn_reg->crop_h_en_shift_val) | |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1684 | (path_data->crop_enable << |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1685 | csid_reg->cmn_reg->crop_v_en_shift_val) | |
| 1686 | (1 << 2) | 3; |
| 1687 | |
| 1688 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1689 | csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); |
| 1690 | |
Jing Zhou | dedc476 | 2017-06-19 17:45:36 +0530 | [diff] [blame] | 1691 | /* select the post irq sub sample strobe for time stamp capture */ |
| 1692 | cam_io_w_mb(CSID_TIMESTAMP_STB_POST_IRQ, soc_info->reg_map[0].mem_base + |
| 1693 | csid_reg->rdi_reg[id]->csid_rdi_cfg1_addr); |
| 1694 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1695 | if (path_data->crop_enable) { |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1696 | val = (((path_data->end_pixel & 0xFFFF) << |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1697 | csid_reg->cmn_reg->crop_shift) | |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1698 | (path_data->start_pixel & 0xFFFF)); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1699 | |
| 1700 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1701 | csid_reg->rdi_reg[id]->csid_rdi_rpp_hcrop_addr); |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1702 | CAM_DBG(CAM_ISP, "CSID:%d Horizontal crop config val: 0x%x", |
| 1703 | csid_hw->hw_intf->hw_idx, val); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1704 | |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1705 | val = (((path_data->end_line & 0xFFFF) << |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1706 | csid_reg->cmn_reg->crop_shift) | |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1707 | (path_data->start_line & 0xFFFF)); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1708 | |
| 1709 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1710 | csid_reg->rdi_reg[id]->csid_rdi_rpp_vcrop_addr); |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 1711 | CAM_DBG(CAM_ISP, "CSID:%d Vertical Crop config val: 0x%x", |
| 1712 | csid_hw->hw_intf->hw_idx, val); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1713 | } |
| 1714 | /* set frame drop pattern to 0 and period to 1 */ |
| 1715 | cam_io_w_mb(1, soc_info->reg_map[0].mem_base + |
| 1716 | csid_reg->rdi_reg[id]->csid_rdi_frm_drop_period_addr); |
| 1717 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 1718 | csid_reg->rdi_reg[id]->csid_rdi_frm_drop_pattern_addr); |
| 1719 | /* set IRQ sum sabmple */ |
| 1720 | cam_io_w_mb(1, soc_info->reg_map[0].mem_base + |
| 1721 | csid_reg->rdi_reg[id]->csid_rdi_irq_subsample_period_addr); |
| 1722 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 1723 | csid_reg->rdi_reg[id]->csid_rdi_irq_subsample_pattern_addr); |
| 1724 | |
| 1725 | /* set pixel drop pattern to 0 and period to 1 */ |
| 1726 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 1727 | csid_reg->rdi_reg[id]->csid_rdi_rpp_pix_drop_pattern_addr); |
| 1728 | cam_io_w_mb(1, soc_info->reg_map[0].mem_base + |
| 1729 | csid_reg->rdi_reg[id]->csid_rdi_rpp_pix_drop_period_addr); |
| 1730 | /* set line drop pattern to 0 and period to 1 */ |
| 1731 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 1732 | csid_reg->rdi_reg[id]->csid_rdi_rpp_line_drop_pattern_addr); |
| 1733 | cam_io_w_mb(1, soc_info->reg_map[0].mem_base + |
| 1734 | csid_reg->rdi_reg[id]->csid_rdi_rpp_line_drop_period_addr); |
| 1735 | |
| 1736 | /* Configure the halt mode */ |
| 1737 | cam_io_w_mb(0, soc_info->reg_map[0].mem_base + |
| 1738 | csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); |
| 1739 | |
| 1740 | /* Enable the RPP path */ |
| 1741 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 1742 | csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); |
| 1743 | val |= (1 << csid_reg->cmn_reg->path_en_shift_val); |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 1744 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1745 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1746 | csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); |
| 1747 | |
Ravikishore Pampana | c19ba62 | 2017-09-21 17:20:48 +0530 | [diff] [blame] | 1748 | /* configure the rx packet capture based on csid debug set */ |
| 1749 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) |
| 1750 | val = ((1 << |
| 1751 | csid_reg->csi2_reg->csi2_capture_short_pkt_en_shift) | |
| 1752 | (path_data->vc << |
| 1753 | csid_reg->csi2_reg->csi2_capture_short_pkt_vc_shift)); |
| 1754 | |
| 1755 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) |
| 1756 | val |= ((1 << |
| 1757 | csid_reg->csi2_reg->csi2_capture_long_pkt_en_shift) | |
| 1758 | (path_data->dt << |
| 1759 | csid_reg->csi2_reg->csi2_capture_long_pkt_dt_shift) | |
| 1760 | (path_data->vc << |
| 1761 | csid_reg->csi2_reg->csi2_capture_long_pkt_vc_shift)); |
| 1762 | |
| 1763 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) |
| 1764 | val |= ((1 << |
| 1765 | csid_reg->csi2_reg->csi2_capture_cphy_pkt_en_shift) | |
| 1766 | (path_data->dt << |
| 1767 | csid_reg->csi2_reg->csi2_capture_cphy_pkt_dt_shift) | |
| 1768 | (path_data->vc << |
| 1769 | csid_reg->csi2_reg->csi2_capture_cphy_pkt_vc_shift)); |
| 1770 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1771 | csid_reg->csi2_reg->csid_csi2_rx_capture_ctrl_addr); |
| 1772 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1773 | res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; |
| 1774 | |
| 1775 | return rc; |
| 1776 | } |
| 1777 | |
| 1778 | static int cam_ife_csid_deinit_rdi_path( |
| 1779 | struct cam_ife_csid_hw *csid_hw, |
| 1780 | struct cam_isp_resource_node *res) |
| 1781 | { |
| 1782 | int rc = 0; |
| 1783 | struct cam_ife_csid_reg_offset *csid_reg; |
| 1784 | struct cam_hw_soc_info *soc_info; |
| 1785 | uint32_t val = 0, id; |
| 1786 | |
| 1787 | csid_reg = csid_hw->csid_info->csid_reg; |
| 1788 | soc_info = &csid_hw->hw_info->soc_info; |
| 1789 | id = res->res_id; |
| 1790 | |
| 1791 | if (res->res_id > CAM_IFE_PIX_PATH_RES_RDI_3 || |
| 1792 | res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW || |
| 1793 | !csid_reg->rdi_reg[id]) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1794 | CAM_ERR(CAM_ISP, "CSID:%d Invalid res id%d state:%d", |
| 1795 | csid_hw->hw_intf->hw_idx, res->res_id, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1796 | res->res_state); |
| 1797 | return -EINVAL; |
| 1798 | } |
| 1799 | |
| 1800 | /* Disable the RDI path */ |
| 1801 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 1802 | csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); |
| 1803 | val &= ~(1 << csid_reg->cmn_reg->path_en_shift_val); |
| 1804 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1805 | csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); |
| 1806 | |
| 1807 | res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; |
| 1808 | return rc; |
| 1809 | } |
| 1810 | |
| 1811 | static int cam_ife_csid_enable_rdi_path( |
| 1812 | struct cam_ife_csid_hw *csid_hw, |
| 1813 | struct cam_isp_resource_node *res) |
| 1814 | { |
| 1815 | struct cam_ife_csid_reg_offset *csid_reg; |
| 1816 | struct cam_hw_soc_info *soc_info; |
| 1817 | uint32_t id, val; |
| 1818 | |
| 1819 | csid_reg = csid_hw->csid_info->csid_reg; |
| 1820 | soc_info = &csid_hw->hw_info->soc_info; |
| 1821 | id = res->res_id; |
| 1822 | |
| 1823 | if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW || |
| 1824 | res->res_id > CAM_IFE_PIX_PATH_RES_RDI_3 || |
| 1825 | !csid_reg->rdi_reg[id]) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1826 | CAM_ERR(CAM_ISP, |
| 1827 | "CSID:%d invalid res type:%d res_id:%d state%d", |
| 1828 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1829 | res->res_type, res->res_id, res->res_state); |
| 1830 | return -EINVAL; |
| 1831 | } |
| 1832 | |
| 1833 | /*resume at frame boundary */ |
| 1834 | cam_io_w_mb(CAM_CSID_RESUME_AT_FRAME_BOUNDARY, |
| 1835 | soc_info->reg_map[0].mem_base + |
| 1836 | csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); |
| 1837 | |
| 1838 | /* Enable the required RDI interrupts */ |
Ravikishore Pampana | c19ba62 | 2017-09-21 17:20:48 +0530 | [diff] [blame] | 1839 | val = CSID_PATH_INFO_RST_DONE | CSID_PATH_ERROR_FIFO_OVERFLOW; |
| 1840 | |
| 1841 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ) |
| 1842 | val |= CSID_PATH_INFO_INPUT_SOF; |
| 1843 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ) |
| 1844 | val |= CSID_PATH_INFO_INPUT_EOF; |
| 1845 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1846 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1847 | csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); |
| 1848 | |
| 1849 | res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; |
| 1850 | |
| 1851 | return 0; |
| 1852 | } |
| 1853 | |
| 1854 | |
| 1855 | static int cam_ife_csid_disable_rdi_path( |
| 1856 | struct cam_ife_csid_hw *csid_hw, |
| 1857 | struct cam_isp_resource_node *res, |
| 1858 | enum cam_ife_csid_halt_cmd stop_cmd) |
| 1859 | { |
| 1860 | int rc = 0; |
| 1861 | struct cam_ife_csid_reg_offset *csid_reg; |
| 1862 | struct cam_hw_soc_info *soc_info; |
| 1863 | uint32_t val = 0, id; |
| 1864 | |
| 1865 | csid_reg = csid_hw->csid_info->csid_reg; |
| 1866 | soc_info = &csid_hw->hw_info->soc_info; |
| 1867 | id = res->res_id; |
| 1868 | |
| 1869 | if (res->res_id >= CAM_IFE_PIX_PATH_RES_MAX || |
| 1870 | !csid_reg->rdi_reg[res->res_id]) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1871 | CAM_DBG(CAM_ISP, "CSID:%d Invalid res id%d", |
| 1872 | csid_hw->hw_intf->hw_idx, res->res_id); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1873 | return -EINVAL; |
| 1874 | } |
| 1875 | |
| 1876 | if (res->res_state == CAM_ISP_RESOURCE_STATE_INIT_HW || |
| 1877 | res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1878 | CAM_DBG(CAM_ISP, "CSID:%d Res:%d already in stopped state:%d", |
| 1879 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1880 | res->res_id, res->res_state); |
| 1881 | return rc; |
| 1882 | } |
| 1883 | |
| 1884 | if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1885 | CAM_DBG(CAM_ISP, "CSID:%d Res:%d Invalid res_state%d", |
| 1886 | csid_hw->hw_intf->hw_idx, res->res_id, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1887 | res->res_state); |
| 1888 | return -EINVAL; |
| 1889 | } |
| 1890 | |
| 1891 | if (stop_cmd != CAM_CSID_HALT_AT_FRAME_BOUNDARY && |
| 1892 | stop_cmd != CAM_CSID_HALT_IMMEDIATELY) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1893 | CAM_ERR(CAM_ISP, "CSID:%d un supported stop command:%d", |
| 1894 | csid_hw->hw_intf->hw_idx, stop_cmd); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1895 | return -EINVAL; |
| 1896 | } |
| 1897 | |
| 1898 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1899 | CAM_DBG(CAM_ISP, "CSID:%d res_id:%d", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1900 | csid_hw->hw_intf->hw_idx, res->res_id); |
| 1901 | |
| 1902 | init_completion(&csid_hw->csid_rdin_complete[id]); |
| 1903 | |
| 1904 | if (stop_cmd != CAM_CSID_HALT_IMMEDIATELY) { |
| 1905 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 1906 | csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); |
| 1907 | val |= CSID_PATH_INFO_INPUT_EOF; |
| 1908 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1909 | csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); |
| 1910 | } else { |
| 1911 | val &= ~(CSID_PATH_INFO_RST_DONE | |
| 1912 | CSID_PATH_ERROR_FIFO_OVERFLOW); |
| 1913 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 1914 | csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); |
| 1915 | } |
| 1916 | |
| 1917 | /*Halt the RDI path */ |
| 1918 | cam_io_w_mb(stop_cmd, soc_info->reg_map[0].mem_base + |
| 1919 | csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); |
| 1920 | |
| 1921 | return rc; |
| 1922 | } |
| 1923 | |
| 1924 | static int cam_ife_csid_get_time_stamp( |
| 1925 | struct cam_ife_csid_hw *csid_hw, void *cmd_args) |
| 1926 | { |
| 1927 | struct cam_csid_get_time_stamp_args *time_stamp; |
| 1928 | struct cam_isp_resource_node *res; |
| 1929 | struct cam_ife_csid_reg_offset *csid_reg; |
| 1930 | struct cam_hw_soc_info *soc_info; |
| 1931 | uint32_t time_32, id; |
| 1932 | |
| 1933 | time_stamp = (struct cam_csid_get_time_stamp_args *)cmd_args; |
| 1934 | res = time_stamp->node_res; |
| 1935 | csid_reg = csid_hw->csid_info->csid_reg; |
| 1936 | soc_info = &csid_hw->hw_info->soc_info; |
| 1937 | |
| 1938 | if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH || |
| 1939 | res->res_id >= CAM_IFE_PIX_PATH_RES_MAX) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1940 | CAM_DBG(CAM_ISP, "CSID:%d Invalid res_type:%d res id%d", |
| 1941 | csid_hw->hw_intf->hw_idx, res->res_type, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1942 | res->res_id); |
| 1943 | return -EINVAL; |
| 1944 | } |
| 1945 | |
| 1946 | if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 1947 | CAM_ERR(CAM_ISP, "CSID:%d Invalid dev state :%d", |
| 1948 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1949 | csid_hw->hw_info->hw_state); |
| 1950 | return -EINVAL; |
| 1951 | } |
| 1952 | |
| 1953 | if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) { |
| 1954 | time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 1955 | csid_reg->ipp_reg->csid_ipp_timestamp_curr1_sof_addr); |
| 1956 | time_stamp->time_stamp_val = time_32; |
| 1957 | time_stamp->time_stamp_val = time_stamp->time_stamp_val << 32; |
| 1958 | time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 1959 | csid_reg->ipp_reg->csid_ipp_timestamp_curr0_sof_addr); |
| 1960 | time_stamp->time_stamp_val |= time_32; |
| 1961 | } else { |
| 1962 | id = res->res_id; |
| 1963 | time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 1964 | csid_reg->rdi_reg[id]-> |
| 1965 | csid_rdi_timestamp_curr1_sof_addr); |
| 1966 | time_stamp->time_stamp_val = time_32; |
| 1967 | time_stamp->time_stamp_val = time_stamp->time_stamp_val << 32; |
| 1968 | |
| 1969 | time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 1970 | csid_reg->rdi_reg[id]-> |
| 1971 | csid_rdi_timestamp_curr0_sof_addr); |
| 1972 | time_stamp->time_stamp_val |= time_32; |
| 1973 | } |
| 1974 | |
| 1975 | return 0; |
| 1976 | } |
Ravikishore Pampana | c19ba62 | 2017-09-21 17:20:48 +0530 | [diff] [blame] | 1977 | |
| 1978 | static int cam_ife_csid_set_csid_debug(struct cam_ife_csid_hw *csid_hw, |
| 1979 | void *cmd_args) |
| 1980 | { |
| 1981 | uint32_t *csid_debug; |
| 1982 | |
| 1983 | csid_debug = (uint32_t *) cmd_args; |
| 1984 | csid_hw->csid_debug = *csid_debug; |
| 1985 | CAM_DBG(CAM_ISP, "CSID:%d set csid debug value:%d", |
| 1986 | csid_hw->hw_intf->hw_idx, csid_hw->csid_debug); |
| 1987 | |
| 1988 | return 0; |
| 1989 | } |
| 1990 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 1991 | static int cam_ife_csid_res_wait_for_halt( |
| 1992 | struct cam_ife_csid_hw *csid_hw, |
| 1993 | struct cam_isp_resource_node *res) |
| 1994 | { |
| 1995 | int rc = 0; |
| 1996 | struct cam_ife_csid_reg_offset *csid_reg; |
| 1997 | struct cam_hw_soc_info *soc_info; |
| 1998 | |
| 1999 | struct completion *complete; |
| 2000 | uint32_t val = 0, id; |
| 2001 | |
| 2002 | csid_reg = csid_hw->csid_info->csid_reg; |
| 2003 | soc_info = &csid_hw->hw_info->soc_info; |
| 2004 | |
| 2005 | if (res->res_id >= CAM_IFE_PIX_PATH_RES_MAX) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2006 | CAM_DBG(CAM_ISP, "CSID:%d Invalid res id%d", |
| 2007 | csid_hw->hw_intf->hw_idx, res->res_id); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2008 | return -EINVAL; |
| 2009 | } |
| 2010 | |
| 2011 | if (res->res_state == CAM_ISP_RESOURCE_STATE_INIT_HW || |
| 2012 | res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2013 | CAM_DBG(CAM_ISP, "CSID:%d Res:%d already in stopped state:%d", |
| 2014 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2015 | res->res_id, res->res_state); |
| 2016 | return rc; |
| 2017 | } |
| 2018 | |
| 2019 | if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2020 | CAM_DBG(CAM_ISP, "CSID:%d Res:%d Invalid state%d", |
| 2021 | csid_hw->hw_intf->hw_idx, res->res_id, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2022 | res->res_state); |
| 2023 | return -EINVAL; |
| 2024 | } |
| 2025 | |
| 2026 | if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) |
| 2027 | complete = &csid_hw->csid_ipp_complete; |
| 2028 | else |
| 2029 | complete = &csid_hw->csid_rdin_complete[res->res_id]; |
| 2030 | |
| 2031 | rc = wait_for_completion_timeout(complete, |
| 2032 | msecs_to_jiffies(IFE_CSID_TIMEOUT)); |
| 2033 | if (rc <= 0) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2034 | CAM_ERR(CAM_ISP, "CSID%d stop at frame boundary failid:%drc:%d", |
| 2035 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2036 | res->res_id, rc); |
| 2037 | if (rc == 0) |
| 2038 | /* continue even have timeout */ |
| 2039 | rc = -ETIMEDOUT; |
| 2040 | } |
| 2041 | |
| 2042 | /* Disable the interrupt */ |
| 2043 | if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) { |
| 2044 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 2045 | csid_reg->ipp_reg->csid_ipp_irq_mask_addr); |
| 2046 | val &= ~(CSID_PATH_INFO_INPUT_EOF | CSID_PATH_INFO_RST_DONE | |
| 2047 | CSID_PATH_ERROR_FIFO_OVERFLOW); |
| 2048 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 2049 | csid_reg->ipp_reg->csid_ipp_irq_mask_addr); |
| 2050 | } else { |
| 2051 | id = res->res_id; |
| 2052 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 2053 | csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); |
| 2054 | val &= ~(CSID_PATH_INFO_INPUT_EOF | CSID_PATH_INFO_RST_DONE | |
| 2055 | CSID_PATH_ERROR_FIFO_OVERFLOW); |
| 2056 | cam_io_w_mb(val, soc_info->reg_map[0].mem_base + |
| 2057 | csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); |
| 2058 | } |
| 2059 | /* set state to init HW */ |
| 2060 | res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; |
| 2061 | return rc; |
| 2062 | } |
| 2063 | |
| 2064 | static int cam_ife_csid_get_hw_caps(void *hw_priv, |
| 2065 | void *get_hw_cap_args, uint32_t arg_size) |
| 2066 | { |
| 2067 | int rc = 0; |
| 2068 | struct cam_ife_csid_hw_caps *hw_caps; |
| 2069 | struct cam_ife_csid_hw *csid_hw; |
| 2070 | struct cam_hw_info *csid_hw_info; |
| 2071 | struct cam_ife_csid_reg_offset *csid_reg; |
| 2072 | |
| 2073 | if (!hw_priv || !get_hw_cap_args) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2074 | CAM_ERR(CAM_ISP, "CSID: Invalid args"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2075 | return -EINVAL; |
| 2076 | } |
| 2077 | |
| 2078 | csid_hw_info = (struct cam_hw_info *)hw_priv; |
| 2079 | csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; |
| 2080 | csid_reg = csid_hw->csid_info->csid_reg; |
| 2081 | hw_caps = (struct cam_ife_csid_hw_caps *) get_hw_cap_args; |
| 2082 | |
| 2083 | hw_caps->no_rdis = csid_reg->cmn_reg->no_rdis; |
| 2084 | hw_caps->no_pix = csid_reg->cmn_reg->no_pix; |
| 2085 | hw_caps->major_version = csid_reg->cmn_reg->major_version; |
| 2086 | hw_caps->minor_version = csid_reg->cmn_reg->minor_version; |
| 2087 | hw_caps->version_incr = csid_reg->cmn_reg->version_incr; |
| 2088 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2089 | CAM_DBG(CAM_ISP, |
| 2090 | "CSID:%d No rdis:%d, no pix:%d, major:%d minor:%d ver :%d", |
| 2091 | csid_hw->hw_intf->hw_idx, hw_caps->no_rdis, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2092 | hw_caps->no_pix, hw_caps->major_version, hw_caps->minor_version, |
| 2093 | hw_caps->version_incr); |
| 2094 | |
| 2095 | return rc; |
| 2096 | } |
| 2097 | |
| 2098 | static int cam_ife_csid_reset(void *hw_priv, |
| 2099 | void *reset_args, uint32_t arg_size) |
| 2100 | { |
| 2101 | struct cam_ife_csid_hw *csid_hw; |
| 2102 | struct cam_hw_info *csid_hw_info; |
| 2103 | struct cam_csid_reset_cfg_args *reset; |
| 2104 | int rc = 0; |
| 2105 | |
| 2106 | if (!hw_priv || !reset_args || (arg_size != |
| 2107 | sizeof(struct cam_csid_reset_cfg_args))) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2108 | CAM_ERR(CAM_ISP, "CSID:Invalid args"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2109 | return -EINVAL; |
| 2110 | } |
| 2111 | |
| 2112 | csid_hw_info = (struct cam_hw_info *)hw_priv; |
| 2113 | csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; |
| 2114 | reset = (struct cam_csid_reset_cfg_args *)reset_args; |
| 2115 | |
| 2116 | switch (reset->reset_type) { |
| 2117 | case CAM_IFE_CSID_RESET_GLOBAL: |
| 2118 | rc = cam_ife_csid_global_reset(csid_hw); |
| 2119 | break; |
| 2120 | case CAM_IFE_CSID_RESET_PATH: |
| 2121 | rc = cam_ife_csid_path_reset(csid_hw, reset); |
| 2122 | break; |
| 2123 | default: |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2124 | CAM_ERR(CAM_ISP, "CSID:Invalid reset type :%d", |
| 2125 | reset->reset_type); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2126 | rc = -EINVAL; |
| 2127 | break; |
| 2128 | } |
| 2129 | |
| 2130 | return rc; |
| 2131 | } |
| 2132 | |
| 2133 | static int cam_ife_csid_reserve(void *hw_priv, |
| 2134 | void *reserve_args, uint32_t arg_size) |
| 2135 | { |
| 2136 | int rc = 0; |
| 2137 | struct cam_ife_csid_hw *csid_hw; |
| 2138 | struct cam_hw_info *csid_hw_info; |
| 2139 | struct cam_csid_hw_reserve_resource_args *reserv; |
| 2140 | |
| 2141 | if (!hw_priv || !reserve_args || (arg_size != |
| 2142 | sizeof(struct cam_csid_hw_reserve_resource_args))) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2143 | CAM_ERR(CAM_ISP, "CSID: Invalid args"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2144 | return -EINVAL; |
| 2145 | } |
| 2146 | |
| 2147 | csid_hw_info = (struct cam_hw_info *)hw_priv; |
| 2148 | csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; |
| 2149 | reserv = (struct cam_csid_hw_reserve_resource_args *)reserve_args; |
| 2150 | |
| 2151 | mutex_lock(&csid_hw->hw_info->hw_mutex); |
| 2152 | switch (reserv->res_type) { |
| 2153 | case CAM_ISP_RESOURCE_CID: |
| 2154 | rc = cam_ife_csid_cid_reserve(csid_hw, reserv); |
| 2155 | break; |
| 2156 | case CAM_ISP_RESOURCE_PIX_PATH: |
| 2157 | rc = cam_ife_csid_path_reserve(csid_hw, reserv); |
| 2158 | break; |
| 2159 | default: |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2160 | CAM_ERR(CAM_ISP, "CSID:%d Invalid res type :%d", |
| 2161 | csid_hw->hw_intf->hw_idx, reserv->res_type); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2162 | rc = -EINVAL; |
| 2163 | break; |
| 2164 | } |
| 2165 | mutex_unlock(&csid_hw->hw_info->hw_mutex); |
| 2166 | return rc; |
| 2167 | } |
| 2168 | |
| 2169 | static int cam_ife_csid_release(void *hw_priv, |
| 2170 | void *release_args, uint32_t arg_size) |
| 2171 | { |
| 2172 | int rc = 0; |
| 2173 | struct cam_ife_csid_hw *csid_hw; |
| 2174 | struct cam_hw_info *csid_hw_info; |
| 2175 | struct cam_isp_resource_node *res; |
| 2176 | struct cam_ife_csid_cid_data *cid_data; |
| 2177 | |
| 2178 | if (!hw_priv || !release_args || |
| 2179 | (arg_size != sizeof(struct cam_isp_resource_node))) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2180 | CAM_ERR(CAM_ISP, "CSID: Invalid args"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2181 | return -EINVAL; |
| 2182 | } |
| 2183 | |
| 2184 | csid_hw_info = (struct cam_hw_info *)hw_priv; |
| 2185 | csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; |
| 2186 | res = (struct cam_isp_resource_node *)release_args; |
| 2187 | |
| 2188 | mutex_lock(&csid_hw->hw_info->hw_mutex); |
| 2189 | if ((res->res_type == CAM_ISP_RESOURCE_CID && |
| 2190 | res->res_id >= CAM_IFE_CSID_CID_MAX) || |
| 2191 | (res->res_type == CAM_ISP_RESOURCE_PIX_PATH && |
| 2192 | res->res_id >= CAM_IFE_PIX_PATH_RES_MAX)) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2193 | CAM_ERR(CAM_ISP, "CSID:%d Invalid res type:%d res id%d", |
| 2194 | csid_hw->hw_intf->hw_idx, res->res_type, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2195 | res->res_id); |
| 2196 | rc = -EINVAL; |
| 2197 | goto end; |
| 2198 | } |
| 2199 | |
| 2200 | if (res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2201 | CAM_DBG(CAM_ISP, |
| 2202 | "CSID:%d res type:%d Res %d in released state", |
| 2203 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2204 | res->res_type, res->res_id); |
| 2205 | goto end; |
| 2206 | } |
| 2207 | |
| 2208 | if (res->res_type == CAM_ISP_RESOURCE_PIX_PATH && |
| 2209 | res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2210 | CAM_DBG(CAM_ISP, |
| 2211 | "CSID:%d res type:%d Res id:%d invalid state:%d", |
| 2212 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2213 | res->res_type, res->res_id, res->res_state); |
| 2214 | rc = -EINVAL; |
| 2215 | goto end; |
| 2216 | } |
| 2217 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2218 | CAM_DBG(CAM_ISP, "CSID:%d res type :%d Resource id:%d", |
| 2219 | csid_hw->hw_intf->hw_idx, res->res_type, res->res_id); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2220 | |
| 2221 | switch (res->res_type) { |
| 2222 | case CAM_ISP_RESOURCE_CID: |
| 2223 | cid_data = (struct cam_ife_csid_cid_data *) res->res_priv; |
| 2224 | if (cid_data->cnt) |
| 2225 | cid_data->cnt--; |
| 2226 | |
| 2227 | if (!cid_data->cnt) |
| 2228 | res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; |
| 2229 | |
| 2230 | if (csid_hw->csi2_reserve_cnt) |
| 2231 | csid_hw->csi2_reserve_cnt--; |
| 2232 | |
| 2233 | if (!csid_hw->csi2_reserve_cnt) |
| 2234 | memset(&csid_hw->csi2_rx_cfg, 0, |
| 2235 | sizeof(struct cam_ife_csid_csi2_rx_cfg)); |
| 2236 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2237 | CAM_DBG(CAM_ISP, "CSID:%d res id :%d cnt:%d reserv cnt:%d", |
| 2238 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2239 | res->res_id, cid_data->cnt, csid_hw->csi2_reserve_cnt); |
| 2240 | |
| 2241 | break; |
| 2242 | case CAM_ISP_RESOURCE_PIX_PATH: |
| 2243 | res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; |
| 2244 | break; |
| 2245 | default: |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2246 | CAM_ERR(CAM_ISP, "CSID:%d Invalid res type:%d res id%d", |
| 2247 | csid_hw->hw_intf->hw_idx, res->res_type, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2248 | res->res_id); |
| 2249 | rc = -EINVAL; |
| 2250 | break; |
| 2251 | } |
| 2252 | |
| 2253 | end: |
| 2254 | mutex_unlock(&csid_hw->hw_info->hw_mutex); |
| 2255 | return rc; |
| 2256 | } |
| 2257 | |
| 2258 | static int cam_ife_csid_init_hw(void *hw_priv, |
| 2259 | void *init_args, uint32_t arg_size) |
| 2260 | { |
| 2261 | int rc = 0; |
| 2262 | struct cam_ife_csid_hw *csid_hw; |
| 2263 | struct cam_hw_info *csid_hw_info; |
| 2264 | struct cam_isp_resource_node *res; |
| 2265 | struct cam_ife_csid_reg_offset *csid_reg; |
| 2266 | |
| 2267 | if (!hw_priv || !init_args || |
| 2268 | (arg_size != sizeof(struct cam_isp_resource_node))) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2269 | CAM_ERR(CAM_ISP, "CSID: Invalid args"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2270 | return -EINVAL; |
| 2271 | } |
| 2272 | |
| 2273 | csid_hw_info = (struct cam_hw_info *)hw_priv; |
| 2274 | csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; |
| 2275 | res = (struct cam_isp_resource_node *)init_args; |
| 2276 | csid_reg = csid_hw->csid_info->csid_reg; |
| 2277 | |
| 2278 | mutex_lock(&csid_hw->hw_info->hw_mutex); |
| 2279 | if ((res->res_type == CAM_ISP_RESOURCE_CID && |
| 2280 | res->res_id >= CAM_IFE_CSID_CID_MAX) || |
| 2281 | (res->res_type == CAM_ISP_RESOURCE_PIX_PATH && |
| 2282 | res->res_id >= CAM_IFE_PIX_PATH_RES_MAX)) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2283 | CAM_ERR(CAM_ISP, "CSID:%d Invalid res tpe:%d res id%d", |
| 2284 | csid_hw->hw_intf->hw_idx, res->res_type, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2285 | res->res_id); |
| 2286 | rc = -EINVAL; |
| 2287 | goto end; |
| 2288 | } |
| 2289 | |
| 2290 | |
| 2291 | if ((res->res_type == CAM_ISP_RESOURCE_PIX_PATH) && |
| 2292 | (res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED)) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2293 | CAM_ERR(CAM_ISP, |
| 2294 | "CSID:%d res type:%d res_id:%dInvalid state %d", |
| 2295 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2296 | res->res_type, res->res_id, res->res_state); |
| 2297 | rc = -EINVAL; |
| 2298 | goto end; |
| 2299 | } |
| 2300 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2301 | CAM_DBG(CAM_ISP, "CSID:%d res type :%d res_id:%d", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2302 | csid_hw->hw_intf->hw_idx, res->res_type, res->res_id); |
| 2303 | |
| 2304 | |
| 2305 | /* Initialize the csid hardware */ |
| 2306 | rc = cam_ife_csid_enable_hw(csid_hw); |
| 2307 | if (rc) |
| 2308 | goto end; |
| 2309 | |
| 2310 | switch (res->res_type) { |
| 2311 | case CAM_ISP_RESOURCE_CID: |
| 2312 | rc = cam_ife_csid_enable_csi2(csid_hw, res); |
| 2313 | break; |
| 2314 | case CAM_ISP_RESOURCE_PIX_PATH: |
| 2315 | if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) |
| 2316 | rc = cam_ife_csid_init_config_ipp_path(csid_hw, res); |
| 2317 | else |
| 2318 | rc = cam_ife_csid_init_config_rdi_path(csid_hw, res); |
| 2319 | |
| 2320 | break; |
| 2321 | default: |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2322 | CAM_ERR(CAM_ISP, "CSID:%d Invalid res type state %d", |
| 2323 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2324 | res->res_type); |
| 2325 | break; |
| 2326 | } |
| 2327 | |
| 2328 | if (rc) |
| 2329 | cam_ife_csid_disable_hw(csid_hw); |
| 2330 | end: |
| 2331 | mutex_unlock(&csid_hw->hw_info->hw_mutex); |
| 2332 | return rc; |
| 2333 | } |
| 2334 | |
| 2335 | static int cam_ife_csid_deinit_hw(void *hw_priv, |
| 2336 | void *deinit_args, uint32_t arg_size) |
| 2337 | { |
| 2338 | int rc = 0; |
| 2339 | struct cam_ife_csid_hw *csid_hw; |
| 2340 | struct cam_hw_info *csid_hw_info; |
| 2341 | struct cam_isp_resource_node *res; |
| 2342 | |
| 2343 | if (!hw_priv || !deinit_args || |
| 2344 | (arg_size != sizeof(struct cam_isp_resource_node))) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2345 | CAM_ERR(CAM_ISP, "CSID:Invalid arguments"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2346 | return -EINVAL; |
| 2347 | } |
| 2348 | |
| 2349 | res = (struct cam_isp_resource_node *)deinit_args; |
| 2350 | csid_hw_info = (struct cam_hw_info *)hw_priv; |
| 2351 | csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; |
| 2352 | |
| 2353 | mutex_lock(&csid_hw->hw_info->hw_mutex); |
| 2354 | if (res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2355 | CAM_DBG(CAM_ISP, "CSID:%d Res:%d already in De-init state", |
| 2356 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2357 | res->res_id); |
| 2358 | goto end; |
| 2359 | } |
| 2360 | |
| 2361 | switch (res->res_type) { |
| 2362 | case CAM_ISP_RESOURCE_CID: |
| 2363 | rc = cam_ife_csid_disable_csi2(csid_hw, res); |
| 2364 | break; |
| 2365 | case CAM_ISP_RESOURCE_PIX_PATH: |
| 2366 | if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) |
| 2367 | rc = cam_ife_csid_deinit_ipp_path(csid_hw, res); |
| 2368 | else |
| 2369 | rc = cam_ife_csid_deinit_rdi_path(csid_hw, res); |
| 2370 | |
| 2371 | break; |
| 2372 | default: |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2373 | CAM_ERR(CAM_ISP, "CSID:%d Invalid Res type %d", |
| 2374 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2375 | res->res_type); |
| 2376 | goto end; |
| 2377 | } |
| 2378 | |
| 2379 | /* Disable CSID HW */ |
| 2380 | cam_ife_csid_disable_hw(csid_hw); |
| 2381 | |
| 2382 | end: |
| 2383 | mutex_unlock(&csid_hw->hw_info->hw_mutex); |
| 2384 | return rc; |
| 2385 | } |
| 2386 | |
| 2387 | static int cam_ife_csid_start(void *hw_priv, void *start_args, |
| 2388 | uint32_t arg_size) |
| 2389 | { |
| 2390 | int rc = 0; |
| 2391 | struct cam_ife_csid_hw *csid_hw; |
| 2392 | struct cam_hw_info *csid_hw_info; |
| 2393 | struct cam_isp_resource_node *res; |
| 2394 | struct cam_ife_csid_reg_offset *csid_reg; |
| 2395 | |
| 2396 | if (!hw_priv || !start_args || |
| 2397 | (arg_size != sizeof(struct cam_isp_resource_node))) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2398 | CAM_ERR(CAM_ISP, "CSID: Invalid args"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2399 | return -EINVAL; |
| 2400 | } |
| 2401 | |
| 2402 | csid_hw_info = (struct cam_hw_info *)hw_priv; |
| 2403 | csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; |
| 2404 | res = (struct cam_isp_resource_node *)start_args; |
| 2405 | csid_reg = csid_hw->csid_info->csid_reg; |
| 2406 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2407 | if ((res->res_type == CAM_ISP_RESOURCE_CID && |
| 2408 | res->res_id >= CAM_IFE_CSID_CID_MAX) || |
| 2409 | (res->res_type == CAM_ISP_RESOURCE_PIX_PATH && |
| 2410 | res->res_id >= CAM_IFE_PIX_PATH_RES_MAX)) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2411 | CAM_DBG(CAM_ISP, "CSID:%d Invalid res tpe:%d res id:%d", |
| 2412 | csid_hw->hw_intf->hw_idx, res->res_type, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2413 | res->res_id); |
| 2414 | rc = -EINVAL; |
| 2415 | goto end; |
| 2416 | } |
| 2417 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2418 | CAM_DBG(CAM_ISP, "CSID:%d res_type :%d res_id:%d", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2419 | csid_hw->hw_intf->hw_idx, res->res_type, res->res_id); |
| 2420 | |
| 2421 | switch (res->res_type) { |
| 2422 | case CAM_ISP_RESOURCE_CID: |
| 2423 | if (csid_hw->res_type == CAM_ISP_IFE_IN_RES_TPG) |
| 2424 | rc = cam_ife_csid_tpg_start(csid_hw, res); |
| 2425 | break; |
| 2426 | case CAM_ISP_RESOURCE_PIX_PATH: |
| 2427 | if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) |
| 2428 | rc = cam_ife_csid_enable_ipp_path(csid_hw, res); |
| 2429 | else |
| 2430 | rc = cam_ife_csid_enable_rdi_path(csid_hw, res); |
| 2431 | break; |
| 2432 | default: |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2433 | CAM_ERR(CAM_ISP, "CSID:%d Invalid res type%d", |
| 2434 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2435 | res->res_type); |
| 2436 | break; |
| 2437 | } |
| 2438 | end: |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2439 | return rc; |
| 2440 | } |
| 2441 | |
| 2442 | static int cam_ife_csid_stop(void *hw_priv, |
| 2443 | void *stop_args, uint32_t arg_size) |
| 2444 | { |
| 2445 | int rc = 0; |
| 2446 | struct cam_ife_csid_hw *csid_hw; |
| 2447 | struct cam_hw_info *csid_hw_info; |
| 2448 | struct cam_isp_resource_node *res; |
| 2449 | struct cam_csid_hw_stop_args *csid_stop; |
| 2450 | uint32_t i; |
| 2451 | |
| 2452 | if (!hw_priv || !stop_args || |
| 2453 | (arg_size != sizeof(struct cam_csid_hw_stop_args))) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2454 | CAM_ERR(CAM_ISP, "CSID: Invalid args"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2455 | return -EINVAL; |
| 2456 | } |
| 2457 | csid_stop = (struct cam_csid_hw_stop_args *) stop_args; |
| 2458 | csid_hw_info = (struct cam_hw_info *)hw_priv; |
| 2459 | csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; |
| 2460 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2461 | /* Stop the resource first */ |
| 2462 | for (i = 0; i < csid_stop->num_res; i++) { |
| 2463 | res = csid_stop->node_res[i]; |
| 2464 | switch (res->res_type) { |
| 2465 | case CAM_ISP_RESOURCE_CID: |
| 2466 | if (csid_hw->res_type == CAM_ISP_IFE_IN_RES_TPG) |
| 2467 | rc = cam_ife_csid_tpg_stop(csid_hw, res); |
| 2468 | break; |
| 2469 | case CAM_ISP_RESOURCE_PIX_PATH: |
| 2470 | if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) |
| 2471 | rc = cam_ife_csid_disable_ipp_path(csid_hw, |
| 2472 | res, csid_stop->stop_cmd); |
| 2473 | else |
| 2474 | rc = cam_ife_csid_disable_rdi_path(csid_hw, |
| 2475 | res, csid_stop->stop_cmd); |
| 2476 | |
| 2477 | break; |
| 2478 | default: |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2479 | CAM_ERR(CAM_ISP, "CSID:%d Invalid res type%d", |
| 2480 | csid_hw->hw_intf->hw_idx, |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2481 | res->res_type); |
| 2482 | break; |
| 2483 | } |
| 2484 | } |
| 2485 | |
| 2486 | /*wait for the path to halt */ |
| 2487 | for (i = 0; i < csid_stop->num_res; i++) { |
| 2488 | res = csid_stop->node_res[i]; |
| 2489 | if (res->res_type == CAM_ISP_RESOURCE_PIX_PATH && |
| 2490 | csid_stop->stop_cmd == CAM_CSID_HALT_AT_FRAME_BOUNDARY) |
| 2491 | rc = cam_ife_csid_res_wait_for_halt(csid_hw, res); |
Ravikishore Pampana | ad6bc90 | 2017-07-12 19:37:06 +0530 | [diff] [blame] | 2492 | else |
| 2493 | res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2494 | } |
| 2495 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2496 | return rc; |
| 2497 | |
| 2498 | } |
| 2499 | |
| 2500 | static int cam_ife_csid_read(void *hw_priv, |
| 2501 | void *read_args, uint32_t arg_size) |
| 2502 | { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2503 | CAM_ERR(CAM_ISP, "CSID: un supported"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2504 | |
| 2505 | return -EINVAL; |
| 2506 | } |
| 2507 | |
| 2508 | static int cam_ife_csid_write(void *hw_priv, |
| 2509 | void *write_args, uint32_t arg_size) |
| 2510 | { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2511 | CAM_ERR(CAM_ISP, "CSID: un supported"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2512 | return -EINVAL; |
| 2513 | } |
| 2514 | |
| 2515 | static int cam_ife_csid_process_cmd(void *hw_priv, |
| 2516 | uint32_t cmd_type, void *cmd_args, uint32_t arg_size) |
| 2517 | { |
| 2518 | int rc = 0; |
| 2519 | struct cam_ife_csid_hw *csid_hw; |
| 2520 | struct cam_hw_info *csid_hw_info; |
| 2521 | |
| 2522 | if (!hw_priv || !cmd_args) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2523 | CAM_ERR(CAM_ISP, "CSID: Invalid arguments"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2524 | return -EINVAL; |
| 2525 | } |
| 2526 | |
| 2527 | csid_hw_info = (struct cam_hw_info *)hw_priv; |
| 2528 | csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; |
| 2529 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2530 | switch (cmd_type) { |
| 2531 | case CAM_IFE_CSID_CMD_GET_TIME_STAMP: |
| 2532 | rc = cam_ife_csid_get_time_stamp(csid_hw, cmd_args); |
| 2533 | break; |
Ravikishore Pampana | c19ba62 | 2017-09-21 17:20:48 +0530 | [diff] [blame] | 2534 | case CAM_IFE_CSID_SET_CSID_DEBUG: |
| 2535 | rc = cam_ife_csid_set_csid_debug(csid_hw, cmd_args); |
| 2536 | break; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2537 | default: |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2538 | CAM_ERR(CAM_ISP, "CSID:%d un supported cmd:%d", |
| 2539 | csid_hw->hw_intf->hw_idx, cmd_type); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2540 | rc = -EINVAL; |
| 2541 | break; |
| 2542 | } |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2543 | |
| 2544 | return rc; |
| 2545 | |
| 2546 | } |
| 2547 | |
| 2548 | irqreturn_t cam_ife_csid_irq(int irq_num, void *data) |
| 2549 | { |
| 2550 | struct cam_ife_csid_hw *csid_hw; |
| 2551 | struct cam_hw_soc_info *soc_info; |
| 2552 | struct cam_ife_csid_reg_offset *csid_reg; |
Harsh Shah | 1b8eb23 | 2017-10-09 19:20:52 -0700 | [diff] [blame] | 2553 | uint32_t i, irq_status_top, irq_status_rx, irq_status_ipp = 0; |
| 2554 | uint32_t irq_status_rdi[4] = {0, 0, 0, 0}; |
Harsh Shah | f713639 | 2017-08-29 12:42:52 -0700 | [diff] [blame] | 2555 | uint32_t val; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2556 | |
| 2557 | csid_hw = (struct cam_ife_csid_hw *)data; |
| 2558 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2559 | CAM_DBG(CAM_ISP, "CSID %d IRQ Handling", csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2560 | |
| 2561 | if (!data) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2562 | CAM_ERR(CAM_ISP, "CSID: Invalid arguments"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2563 | return IRQ_HANDLED; |
| 2564 | } |
| 2565 | |
| 2566 | csid_reg = csid_hw->csid_info->csid_reg; |
| 2567 | soc_info = &csid_hw->hw_info->soc_info; |
| 2568 | |
| 2569 | /* read */ |
| 2570 | irq_status_top = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 2571 | csid_reg->cmn_reg->csid_top_irq_status_addr); |
| 2572 | |
| 2573 | irq_status_rx = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 2574 | csid_reg->csi2_reg->csid_csi2_rx_irq_status_addr); |
| 2575 | |
| 2576 | if (csid_reg->cmn_reg->no_pix) |
| 2577 | irq_status_ipp = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 2578 | csid_reg->ipp_reg->csid_ipp_irq_status_addr); |
| 2579 | |
| 2580 | |
| 2581 | for (i = 0; i < csid_reg->cmn_reg->no_rdis; i++) |
| 2582 | irq_status_rdi[i] = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 2583 | csid_reg->rdi_reg[i]->csid_rdi_irq_status_addr); |
| 2584 | |
| 2585 | /* clear */ |
| 2586 | cam_io_w_mb(irq_status_top, soc_info->reg_map[0].mem_base + |
| 2587 | csid_reg->cmn_reg->csid_top_irq_clear_addr); |
| 2588 | cam_io_w_mb(irq_status_rx, soc_info->reg_map[0].mem_base + |
| 2589 | csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr); |
| 2590 | if (csid_reg->cmn_reg->no_pix) |
| 2591 | cam_io_w_mb(irq_status_ipp, soc_info->reg_map[0].mem_base + |
| 2592 | csid_reg->ipp_reg->csid_ipp_irq_clear_addr); |
| 2593 | |
| 2594 | for (i = 0; i < csid_reg->cmn_reg->no_rdis; i++) { |
| 2595 | cam_io_w_mb(irq_status_rdi[i], soc_info->reg_map[0].mem_base + |
| 2596 | csid_reg->rdi_reg[i]->csid_rdi_irq_clear_addr); |
| 2597 | } |
| 2598 | cam_io_w_mb(1, soc_info->reg_map[0].mem_base + |
| 2599 | csid_reg->cmn_reg->csid_irq_cmd_addr); |
| 2600 | |
Harsh Shah | 1b8eb23 | 2017-10-09 19:20:52 -0700 | [diff] [blame] | 2601 | CAM_DBG(CAM_ISP, "irq_status_top = 0x%x", irq_status_top); |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2602 | CAM_DBG(CAM_ISP, "irq_status_rx = 0x%x", irq_status_rx); |
| 2603 | CAM_DBG(CAM_ISP, "irq_status_ipp = 0x%x", irq_status_ipp); |
Harsh Shah | 1b8eb23 | 2017-10-09 19:20:52 -0700 | [diff] [blame] | 2604 | CAM_DBG(CAM_ISP, "irq_status_rdi0= 0x%x", irq_status_rdi[0]); |
| 2605 | CAM_DBG(CAM_ISP, "irq_status_rdi1= 0x%x", irq_status_rdi[1]); |
| 2606 | CAM_DBG(CAM_ISP, "irq_status_rdi2= 0x%x", irq_status_rdi[2]); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2607 | |
| 2608 | if (irq_status_top) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2609 | CAM_DBG(CAM_ISP, "CSID global reset complete......Exit"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2610 | complete(&csid_hw->csid_top_complete); |
| 2611 | return IRQ_HANDLED; |
| 2612 | } |
| 2613 | |
| 2614 | |
| 2615 | if (irq_status_rx & BIT(csid_reg->csi2_reg->csi2_rst_done_shift_val)) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2616 | CAM_DBG(CAM_ISP, "csi rx reset complete"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2617 | complete(&csid_hw->csid_csi2_complete); |
| 2618 | } |
| 2619 | |
| 2620 | if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW) { |
Harsh Shah | 1b8eb23 | 2017-10-09 19:20:52 -0700 | [diff] [blame] | 2621 | CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 0 over flow", |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2622 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2623 | } |
| 2624 | if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW) { |
Harsh Shah | 1b8eb23 | 2017-10-09 19:20:52 -0700 | [diff] [blame] | 2625 | CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 1 over flow", |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2626 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2627 | } |
| 2628 | if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW) { |
Harsh Shah | 1b8eb23 | 2017-10-09 19:20:52 -0700 | [diff] [blame] | 2629 | CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 2 over flow", |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2630 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2631 | } |
| 2632 | if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW) { |
Harsh Shah | 1b8eb23 | 2017-10-09 19:20:52 -0700 | [diff] [blame] | 2633 | CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 3 over flow", |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2634 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2635 | } |
| 2636 | if (irq_status_rx & CSID_CSI2_RX_ERROR_TG_FIFO_OVERFLOW) { |
Harsh Shah | 1b8eb23 | 2017-10-09 19:20:52 -0700 | [diff] [blame] | 2637 | CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d TG OVER FLOW", |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2638 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2639 | } |
| 2640 | if (irq_status_rx & CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION) { |
Harsh Shah | 1b8eb23 | 2017-10-09 19:20:52 -0700 | [diff] [blame] | 2641 | CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_EOT_RECEPTION", |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2642 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2643 | } |
| 2644 | if (irq_status_rx & CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION) { |
Harsh Shah | 1b8eb23 | 2017-10-09 19:20:52 -0700 | [diff] [blame] | 2645 | CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_SOT_RECEPTION", |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2646 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2647 | } |
| 2648 | if (irq_status_rx & CSID_CSI2_RX_ERROR_CPHY_PH_CRC) { |
Harsh Shah | 1b8eb23 | 2017-10-09 19:20:52 -0700 | [diff] [blame] | 2649 | CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_PH_CRC", |
| 2650 | csid_hw->hw_intf->hw_idx); |
| 2651 | } |
| 2652 | if (irq_status_rx & CSID_CSI2_RX_ERROR_CRC) { |
| 2653 | CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d ERROR_CRC", |
| 2654 | csid_hw->hw_intf->hw_idx); |
| 2655 | } |
| 2656 | if (irq_status_rx & CSID_CSI2_RX_ERROR_ECC) { |
| 2657 | CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d ERROR_ECC", |
| 2658 | csid_hw->hw_intf->hw_idx); |
| 2659 | } |
| 2660 | if (irq_status_rx & CSID_CSI2_RX_ERROR_MMAPPED_VC_DT) { |
| 2661 | CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d MMAPPED_VC_DT", |
| 2662 | csid_hw->hw_intf->hw_idx); |
| 2663 | } |
| 2664 | if (irq_status_rx & CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW) { |
| 2665 | CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d ERROR_STREAM_UNDERFLOW", |
| 2666 | csid_hw->hw_intf->hw_idx); |
| 2667 | } |
| 2668 | if (irq_status_rx & CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME) { |
| 2669 | CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d UNBOUNDED_FRAME", |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2670 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2671 | } |
| 2672 | |
Ravikishore Pampana | c19ba62 | 2017-09-21 17:20:48 +0530 | [diff] [blame] | 2673 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOT_IRQ) { |
| 2674 | if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED) { |
| 2675 | CAM_ERR(CAM_ISP, "CSID:%d PHY_DL0_EOT_CAPTURED", |
| 2676 | csid_hw->hw_intf->hw_idx); |
| 2677 | } |
| 2678 | if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED) { |
| 2679 | CAM_ERR(CAM_ISP, "CSID:%d PHY_DL1_EOT_CAPTURED", |
| 2680 | csid_hw->hw_intf->hw_idx); |
| 2681 | } |
| 2682 | if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED) { |
| 2683 | CAM_ERR(CAM_ISP, "CSID:%d PHY_DL2_EOT_CAPTURED", |
| 2684 | csid_hw->hw_intf->hw_idx); |
| 2685 | } |
| 2686 | if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED) { |
| 2687 | CAM_ERR(CAM_ISP, "CSID:%d PHY_DL3_EOT_CAPTURED", |
| 2688 | csid_hw->hw_intf->hw_idx); |
| 2689 | } |
| 2690 | } |
| 2691 | |
| 2692 | if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOT_IRQ) { |
| 2693 | if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED) { |
| 2694 | CAM_ERR(CAM_ISP, "CSID:%d PHY_DL0_SOT_CAPTURED", |
| 2695 | csid_hw->hw_intf->hw_idx); |
| 2696 | } |
| 2697 | if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED) { |
| 2698 | CAM_ERR(CAM_ISP, "CSID:%d PHY_DL1_SOT_CAPTURED", |
| 2699 | csid_hw->hw_intf->hw_idx); |
| 2700 | } |
| 2701 | if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED) { |
| 2702 | CAM_ERR(CAM_ISP, "CSID:%d PHY_DL2_SOT_CAPTURED", |
| 2703 | csid_hw->hw_intf->hw_idx); |
| 2704 | } |
| 2705 | if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED) { |
| 2706 | CAM_ERR(CAM_ISP, "CSID:%d PHY_DL3_SOT_CAPTURED", |
| 2707 | csid_hw->hw_intf->hw_idx); |
| 2708 | } |
| 2709 | } |
| 2710 | |
| 2711 | if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) && |
| 2712 | (irq_status_rx & CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED)) { |
| 2713 | CAM_ERR(CAM_ISP, "CSID:%d LONG_PKT_CAPTURED", |
| 2714 | csid_hw->hw_intf->hw_idx); |
| 2715 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 2716 | csid_reg->csi2_reg-> |
| 2717 | csid_csi2_rx_captured_long_pkt_0_addr); |
| 2718 | CAM_ERR(CAM_ISP, "CSID:%d long packet VC :%d DT:%d WC:%d", |
| 2719 | csid_hw->hw_intf->hw_idx, |
| 2720 | (val >> 22), ((val >> 16) & 0x3F), (val & 0xFFFF)); |
| 2721 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 2722 | csid_reg->csi2_reg-> |
| 2723 | csid_csi2_rx_captured_long_pkt_1_addr); |
| 2724 | CAM_ERR(CAM_ISP, "CSID:%d long packet ECC :%d", |
| 2725 | csid_hw->hw_intf->hw_idx, val); |
| 2726 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 2727 | csid_reg->csi2_reg-> |
| 2728 | csid_csi2_rx_captured_long_pkt_ftr_addr); |
| 2729 | CAM_ERR(CAM_ISP, "CSID:%d long pkt cal CRC:%d expected CRC:%d", |
| 2730 | csid_hw->hw_intf->hw_idx, (val >> 16), (val & 0xFFFF)); |
| 2731 | } |
| 2732 | if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) && |
| 2733 | (irq_status_rx & CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED)) { |
| 2734 | CAM_ERR(CAM_ISP, "CSID:%d SHORT_PKT_CAPTURED", |
| 2735 | csid_hw->hw_intf->hw_idx); |
| 2736 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 2737 | csid_reg->csi2_reg-> |
| 2738 | csid_csi2_rx_captured_short_pkt_0_addr); |
| 2739 | CAM_ERR(CAM_ISP, "CSID:%d short pkt VC :%d DT:%d LC:%d", |
| 2740 | csid_hw->hw_intf->hw_idx, |
| 2741 | (val >> 22), ((val >> 16) & 0x1F), (val & 0xFFFF)); |
| 2742 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 2743 | csid_reg->csi2_reg-> |
| 2744 | csid_csi2_rx_captured_short_pkt_1_addr); |
| 2745 | CAM_ERR(CAM_ISP, "CSID:%d short packet ECC :%d", val); |
| 2746 | } |
| 2747 | |
| 2748 | if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) && |
| 2749 | (irq_status_rx & CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED)) { |
| 2750 | CAM_ERR(CAM_ISP, "CSID:%d CPHY_PKT_HDR_CAPTURED", |
| 2751 | csid_hw->hw_intf->hw_idx); |
| 2752 | val = cam_io_r_mb(soc_info->reg_map[0].mem_base + |
| 2753 | csid_reg->csi2_reg-> |
| 2754 | csid_csi2_rx_captured_cphy_pkt_hdr_addr); |
| 2755 | CAM_ERR(CAM_ISP, "CSID:%d cphy packet VC :%d DT:%d WC:%d", |
| 2756 | csid_hw->hw_intf->hw_idx, |
| 2757 | (val >> 22), ((val >> 16) & 0x1F), (val & 0xFFFF)); |
| 2758 | } |
| 2759 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2760 | /*read the IPP errors */ |
| 2761 | if (csid_reg->cmn_reg->no_pix) { |
| 2762 | /* IPP reset done bit */ |
| 2763 | if (irq_status_ipp & |
| 2764 | BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2765 | CAM_DBG(CAM_ISP, "CSID IPP reset complete"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2766 | complete(&csid_hw->csid_ipp_complete); |
| 2767 | } |
Ravikishore Pampana | ff6132e | 2017-07-27 15:32:31 +0530 | [diff] [blame] | 2768 | |
Ravikishore Pampana | c19ba62 | 2017-09-21 17:20:48 +0530 | [diff] [blame] | 2769 | if ((irq_status_ipp & CSID_PATH_INFO_INPUT_SOF) && |
| 2770 | (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) |
| 2771 | CAM_ERR(CAM_ISP, "CSID:%d IPP SOF received", |
| 2772 | csid_hw->hw_intf->hw_idx); |
| 2773 | |
| 2774 | if ((irq_status_ipp & CSID_PATH_INFO_INPUT_EOF) && |
| 2775 | (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)) |
| 2776 | CAM_ERR(CAM_ISP, "CSID:%d IPP EOF received", |
| 2777 | csid_hw->hw_intf->hw_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2778 | |
| 2779 | if (irq_status_ipp & CSID_PATH_INFO_INPUT_EOF) |
| 2780 | complete(&csid_hw->csid_ipp_complete); |
| 2781 | |
| 2782 | if (irq_status_ipp & CSID_PATH_ERROR_FIFO_OVERFLOW) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2783 | CAM_ERR(CAM_ISP, "CSID:%d IPP fifo over flow", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2784 | csid_hw->hw_intf->hw_idx); |
| 2785 | /*Stop IPP path immediately */ |
| 2786 | cam_io_w_mb(CAM_CSID_HALT_IMMEDIATELY, |
| 2787 | soc_info->reg_map[0].mem_base + |
| 2788 | csid_reg->ipp_reg->csid_ipp_ctrl_addr); |
| 2789 | } |
| 2790 | } |
| 2791 | |
| 2792 | for (i = 0; i < csid_reg->cmn_reg->no_rdis; i++) { |
| 2793 | if (irq_status_rdi[i] & |
| 2794 | BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { |
Ravikishore Pampana | c19ba62 | 2017-09-21 17:20:48 +0530 | [diff] [blame] | 2795 | CAM_DBG(CAM_ISP, "CSID RDI%d reset complete", i); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2796 | complete(&csid_hw->csid_rdin_complete[i]); |
| 2797 | } |
| 2798 | |
Ravikishore Pampana | c19ba62 | 2017-09-21 17:20:48 +0530 | [diff] [blame] | 2799 | if ((irq_status_rdi[i] & CSID_PATH_INFO_INPUT_SOF) && |
| 2800 | (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) |
| 2801 | CAM_ERR(CAM_ISP, "CSID RDI:%d SOF received", i); |
| 2802 | |
| 2803 | if ((irq_status_rdi[i] & CSID_PATH_INFO_INPUT_EOF) && |
| 2804 | (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)) |
| 2805 | CAM_ERR(CAM_ISP, "CSID RDI:%d EOF received", i); |
Ravikishore Pampana | ad6bc90 | 2017-07-12 19:37:06 +0530 | [diff] [blame] | 2806 | |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2807 | if (irq_status_rdi[i] & CSID_PATH_INFO_INPUT_EOF) |
| 2808 | complete(&csid_hw->csid_rdin_complete[i]); |
| 2809 | |
| 2810 | if (irq_status_rdi[i] & CSID_PATH_ERROR_FIFO_OVERFLOW) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2811 | CAM_ERR(CAM_ISP, "CSID:%d RDI fifo over flow", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2812 | csid_hw->hw_intf->hw_idx); |
| 2813 | /*Stop RDI path immediately */ |
| 2814 | cam_io_w_mb(CAM_CSID_HALT_IMMEDIATELY, |
| 2815 | soc_info->reg_map[0].mem_base + |
| 2816 | csid_reg->rdi_reg[i]->csid_rdi_ctrl_addr); |
| 2817 | } |
| 2818 | } |
| 2819 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2820 | CAM_DBG(CAM_ISP, "IRQ Handling exit"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2821 | return IRQ_HANDLED; |
| 2822 | } |
| 2823 | |
| 2824 | int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, |
| 2825 | uint32_t csid_idx) |
| 2826 | { |
| 2827 | int rc = -EINVAL; |
| 2828 | uint32_t i; |
| 2829 | struct cam_ife_csid_path_cfg *path_data; |
| 2830 | struct cam_ife_csid_cid_data *cid_data; |
| 2831 | struct cam_hw_info *csid_hw_info; |
| 2832 | struct cam_ife_csid_hw *ife_csid_hw = NULL; |
| 2833 | |
| 2834 | if (csid_idx >= CAM_IFE_CSID_HW_RES_MAX) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2835 | CAM_ERR(CAM_ISP, "Invalid csid index:%d", csid_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2836 | return rc; |
| 2837 | } |
| 2838 | |
| 2839 | csid_hw_info = (struct cam_hw_info *) csid_hw_intf->hw_priv; |
| 2840 | ife_csid_hw = (struct cam_ife_csid_hw *) csid_hw_info->core_info; |
| 2841 | |
| 2842 | ife_csid_hw->hw_intf = csid_hw_intf; |
| 2843 | ife_csid_hw->hw_info = csid_hw_info; |
| 2844 | |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2845 | CAM_DBG(CAM_ISP, "type %d index %d", |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2846 | ife_csid_hw->hw_intf->hw_type, csid_idx); |
| 2847 | |
| 2848 | |
| 2849 | ife_csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; |
| 2850 | mutex_init(&ife_csid_hw->hw_info->hw_mutex); |
| 2851 | spin_lock_init(&ife_csid_hw->hw_info->hw_lock); |
| 2852 | init_completion(&ife_csid_hw->hw_info->hw_complete); |
| 2853 | |
| 2854 | init_completion(&ife_csid_hw->csid_top_complete); |
| 2855 | init_completion(&ife_csid_hw->csid_csi2_complete); |
| 2856 | init_completion(&ife_csid_hw->csid_ipp_complete); |
| 2857 | for (i = 0; i < CAM_IFE_CSID_RDI_MAX; i++) |
| 2858 | init_completion(&ife_csid_hw->csid_rdin_complete[i]); |
| 2859 | |
| 2860 | |
| 2861 | rc = cam_ife_csid_init_soc_resources(&ife_csid_hw->hw_info->soc_info, |
| 2862 | cam_ife_csid_irq, ife_csid_hw); |
| 2863 | if (rc < 0) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2864 | CAM_ERR(CAM_ISP, "CSID:%d Failed to init_soc", csid_idx); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2865 | goto err; |
| 2866 | } |
| 2867 | |
| 2868 | ife_csid_hw->hw_intf->hw_ops.get_hw_caps = cam_ife_csid_get_hw_caps; |
| 2869 | ife_csid_hw->hw_intf->hw_ops.init = cam_ife_csid_init_hw; |
| 2870 | ife_csid_hw->hw_intf->hw_ops.deinit = cam_ife_csid_deinit_hw; |
| 2871 | ife_csid_hw->hw_intf->hw_ops.reset = cam_ife_csid_reset; |
| 2872 | ife_csid_hw->hw_intf->hw_ops.reserve = cam_ife_csid_reserve; |
| 2873 | ife_csid_hw->hw_intf->hw_ops.release = cam_ife_csid_release; |
| 2874 | ife_csid_hw->hw_intf->hw_ops.start = cam_ife_csid_start; |
| 2875 | ife_csid_hw->hw_intf->hw_ops.stop = cam_ife_csid_stop; |
| 2876 | ife_csid_hw->hw_intf->hw_ops.read = cam_ife_csid_read; |
| 2877 | ife_csid_hw->hw_intf->hw_ops.write = cam_ife_csid_write; |
| 2878 | ife_csid_hw->hw_intf->hw_ops.process_cmd = cam_ife_csid_process_cmd; |
| 2879 | |
| 2880 | /*Initialize the CID resoure */ |
| 2881 | for (i = 0; i < CAM_IFE_CSID_CID_RES_MAX; i++) { |
| 2882 | ife_csid_hw->cid_res[i].res_type = CAM_ISP_RESOURCE_CID; |
| 2883 | ife_csid_hw->cid_res[i].res_id = i; |
| 2884 | ife_csid_hw->cid_res[i].res_state = |
| 2885 | CAM_ISP_RESOURCE_STATE_AVAILABLE; |
| 2886 | ife_csid_hw->cid_res[i].hw_intf = ife_csid_hw->hw_intf; |
| 2887 | |
| 2888 | cid_data = kzalloc(sizeof(struct cam_ife_csid_cid_data), |
| 2889 | GFP_KERNEL); |
| 2890 | if (!cid_data) { |
| 2891 | rc = -ENOMEM; |
| 2892 | goto err; |
| 2893 | } |
| 2894 | ife_csid_hw->cid_res[i].res_priv = cid_data; |
| 2895 | } |
| 2896 | |
| 2897 | /* Initialize the IPP resources */ |
| 2898 | if (ife_csid_hw->csid_info->csid_reg->cmn_reg->no_pix) { |
| 2899 | ife_csid_hw->ipp_res.res_type = CAM_ISP_RESOURCE_PIX_PATH; |
| 2900 | ife_csid_hw->ipp_res.res_id = CAM_IFE_PIX_PATH_RES_IPP; |
| 2901 | ife_csid_hw->ipp_res.res_state = |
| 2902 | CAM_ISP_RESOURCE_STATE_AVAILABLE; |
| 2903 | ife_csid_hw->ipp_res.hw_intf = ife_csid_hw->hw_intf; |
| 2904 | path_data = kzalloc(sizeof(struct cam_ife_csid_path_cfg), |
| 2905 | GFP_KERNEL); |
| 2906 | if (!path_data) { |
| 2907 | rc = -ENOMEM; |
| 2908 | goto err; |
| 2909 | } |
| 2910 | ife_csid_hw->ipp_res.res_priv = path_data; |
| 2911 | } |
| 2912 | |
| 2913 | /* Initialize the RDI resource */ |
| 2914 | for (i = 0; i < ife_csid_hw->csid_info->csid_reg->cmn_reg->no_rdis; |
| 2915 | i++) { |
| 2916 | /* res type is from RDI 0 to RDI3 */ |
| 2917 | ife_csid_hw->rdi_res[i].res_type = |
| 2918 | CAM_ISP_RESOURCE_PIX_PATH; |
| 2919 | ife_csid_hw->rdi_res[i].res_id = i; |
| 2920 | ife_csid_hw->rdi_res[i].res_state = |
| 2921 | CAM_ISP_RESOURCE_STATE_AVAILABLE; |
| 2922 | ife_csid_hw->rdi_res[i].hw_intf = ife_csid_hw->hw_intf; |
| 2923 | |
| 2924 | path_data = kzalloc(sizeof(struct cam_ife_csid_path_cfg), |
| 2925 | GFP_KERNEL); |
| 2926 | if (!path_data) { |
| 2927 | rc = -ENOMEM; |
| 2928 | goto err; |
| 2929 | } |
| 2930 | ife_csid_hw->rdi_res[i].res_priv = path_data; |
| 2931 | } |
| 2932 | |
Ravikishore Pampana | c19ba62 | 2017-09-21 17:20:48 +0530 | [diff] [blame] | 2933 | ife_csid_hw->csid_debug = 0; |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2934 | return 0; |
| 2935 | err: |
| 2936 | if (rc) { |
| 2937 | kfree(ife_csid_hw->ipp_res.res_priv); |
| 2938 | for (i = 0; i < |
| 2939 | ife_csid_hw->csid_info->csid_reg->cmn_reg->no_rdis; i++) |
| 2940 | kfree(ife_csid_hw->rdi_res[i].res_priv); |
| 2941 | |
| 2942 | for (i = 0; i < CAM_IFE_CSID_CID_RES_MAX; i++) |
| 2943 | kfree(ife_csid_hw->cid_res[i].res_priv); |
| 2944 | |
| 2945 | } |
| 2946 | |
| 2947 | return rc; |
| 2948 | } |
| 2949 | |
| 2950 | |
| 2951 | int cam_ife_csid_hw_deinit(struct cam_ife_csid_hw *ife_csid_hw) |
| 2952 | { |
| 2953 | int rc = -EINVAL; |
| 2954 | uint32_t i; |
| 2955 | |
| 2956 | if (!ife_csid_hw) { |
Jigarkumar Zala | 7c4fd37 | 2017-07-24 18:43:04 -0700 | [diff] [blame] | 2957 | CAM_ERR(CAM_ISP, "Invalid param"); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2958 | return rc; |
| 2959 | } |
| 2960 | |
| 2961 | /* release the privdate data memory from resources */ |
| 2962 | kfree(ife_csid_hw->ipp_res.res_priv); |
| 2963 | for (i = 0; i < |
| 2964 | ife_csid_hw->csid_info->csid_reg->cmn_reg->no_rdis; |
| 2965 | i++) { |
| 2966 | kfree(ife_csid_hw->rdi_res[i].res_priv); |
| 2967 | } |
| 2968 | for (i = 0; i < CAM_IFE_CSID_CID_RES_MAX; i++) |
| 2969 | kfree(ife_csid_hw->cid_res[i].res_priv); |
| 2970 | |
Ravikishore Pampana | ad6bc90 | 2017-07-12 19:37:06 +0530 | [diff] [blame] | 2971 | cam_ife_csid_deinit_soc_resources(&ife_csid_hw->hw_info->soc_info); |
Jing Zhou | ff57d86 | 2017-03-21 00:54:25 -0700 | [diff] [blame] | 2972 | |
| 2973 | return 0; |
| 2974 | } |