David Howells | 527dcdc | 2012-03-28 18:30:02 +0100 | [diff] [blame] | 1 | #ifndef __PARISC_BARRIER_H |
| 2 | #define __PARISC_BARRIER_H |
| 3 | |
| 4 | /* |
| 5 | ** This is simply the barrier() macro from linux/kernel.h but when serial.c |
| 6 | ** uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h |
| 7 | ** hasn't yet been included yet so it fails, thus repeating the macro here. |
| 8 | ** |
| 9 | ** PA-RISC architecture allows for weakly ordered memory accesses although |
| 10 | ** none of the processors use it. There is a strong ordered bit that is |
| 11 | ** set in the O-bit of the page directory entry. Operating systems that |
| 12 | ** can not tolerate out of order accesses should set this bit when mapping |
| 13 | ** pages. The O-bit of the PSW should also be set to 1 (I don't believe any |
| 14 | ** of the processor implemented the PSW O-bit). The PCX-W ERS states that |
| 15 | ** the TLB O-bit is not implemented so the page directory does not need to |
| 16 | ** have the O-bit set when mapping pages (section 3.1). This section also |
| 17 | ** states that the PSW Y, Z, G, and O bits are not implemented. |
| 18 | ** So it looks like nothing needs to be done for parisc-linux (yet). |
| 19 | ** (thanks to chada for the above comment -ggg) |
| 20 | ** |
| 21 | ** The __asm__ op below simple prevents gcc/ld from reordering |
| 22 | ** instructions across the mb() "call". |
| 23 | */ |
| 24 | #define mb() __asm__ __volatile__("":::"memory") /* barrier() */ |
| 25 | #define rmb() mb() |
| 26 | #define wmb() mb() |
| 27 | #define smp_mb() mb() |
| 28 | #define smp_rmb() mb() |
| 29 | #define smp_wmb() mb() |
| 30 | #define smp_read_barrier_depends() do { } while(0) |
| 31 | #define read_barrier_depends() do { } while(0) |
| 32 | |
| 33 | #define set_mb(var, value) do { var = value; mb(); } while (0) |
| 34 | |
| 35 | #endif /* __PARISC_BARRIER_H */ |