Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 1 | /* |
Santosh Shilimkar | 705814b | 2012-04-12 16:51:47 +0530 | [diff] [blame] | 2 | * OMAP4+ Power Management Routines |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 3 | * |
Santosh Shilimkar | 705814b | 2012-04-12 16:51:47 +0530 | [diff] [blame] | 4 | * Copyright (C) 2010-2013 Texas Instruments, Inc. |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 5 | * Rajendra Nayak <rnayak@ti.com> |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 6 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/pm.h> |
| 14 | #include <linux/suspend.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/list.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/slab.h> |
David Howells | 9f97da7 | 2012-03-28 18:30:01 +0100 | [diff] [blame] | 19 | #include <asm/system_misc.h> |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 20 | |
Tony Lindgren | e4c060d | 2012-10-05 13:25:59 -0700 | [diff] [blame] | 21 | #include "soc.h" |
Tony Lindgren | 4e65331 | 2011-11-10 22:45:17 +0100 | [diff] [blame] | 22 | #include "common.h" |
Santosh Shilimkar | 3c50729 | 2011-01-05 22:03:17 +0530 | [diff] [blame] | 23 | #include "clockdomain.h" |
Paul Walmsley | 72e06d0 | 2010-12-21 21:05:16 -0700 | [diff] [blame] | 24 | #include "powerdomain.h" |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 25 | #include "pm.h" |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 26 | |
Nishanth Menon | de70af4 | 2014-01-20 14:06:37 -0600 | [diff] [blame] | 27 | u16 pm44xx_errata; |
| 28 | |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 29 | struct power_state { |
| 30 | struct powerdomain *pwrdm; |
| 31 | u32 next_state; |
| 32 | #ifdef CONFIG_SUSPEND |
| 33 | u32 saved_state; |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 34 | u32 saved_logic_state; |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 35 | #endif |
| 36 | struct list_head node; |
| 37 | }; |
| 38 | |
| 39 | static LIST_HEAD(pwrst_list); |
| 40 | |
| 41 | #ifdef CONFIG_SUSPEND |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 42 | static int omap4_pm_suspend(void) |
| 43 | { |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 44 | struct power_state *pwrst; |
| 45 | int state, ret = 0; |
| 46 | u32 cpu_id = smp_processor_id(); |
| 47 | |
| 48 | /* Save current powerdomain state */ |
| 49 | list_for_each_entry(pwrst, &pwrst_list, node) { |
| 50 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 51 | pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm); |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 52 | } |
| 53 | |
| 54 | /* Set targeted power domain states by suspend */ |
| 55 | list_for_each_entry(pwrst, &pwrst_list, node) { |
| 56 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 57 | pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF); |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 58 | } |
| 59 | |
| 60 | /* |
| 61 | * For MPUSS to hit power domain retention(CSWR or OSWR), |
| 62 | * CPU0 and CPU1 power domains need to be in OFF or DORMANT state, |
| 63 | * since CPU power domain CSWR is not supported by hardware |
| 64 | * Only master CPU follows suspend path. All other CPUs follow |
| 65 | * CPU hotplug path in system wide suspend. On OMAP4, CPU power |
| 66 | * domain CSWR is not supported by hardware. |
| 67 | * More details can be found in OMAP4430 TRM section 4.3.4.2. |
| 68 | */ |
| 69 | omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF); |
| 70 | |
| 71 | /* Restore next powerdomain state */ |
| 72 | list_for_each_entry(pwrst, &pwrst_list, node) { |
| 73 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); |
| 74 | if (state > pwrst->next_state) { |
Paul Walmsley | 7852ec0 | 2012-07-26 00:54:26 -0600 | [diff] [blame] | 75 | pr_info("Powerdomain (%s) didn't enter target state %d\n", |
| 76 | pwrst->pwrdm->name, pwrst->next_state); |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 77 | ret = -1; |
| 78 | } |
| 79 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 80 | pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state); |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 81 | } |
Rajendra Nayak | 6048009 | 2013-02-04 17:54:43 +0530 | [diff] [blame] | 82 | if (ret) { |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 83 | pr_crit("Could not enter target state in pm_suspend\n"); |
Rajendra Nayak | 6048009 | 2013-02-04 17:54:43 +0530 | [diff] [blame] | 84 | /* |
| 85 | * OMAP4 chip PM currently works only with certain (newer) |
| 86 | * versions of bootloaders. This is due to missing code in the |
| 87 | * kernel to properly reset and initialize some devices. |
| 88 | * Warn the user about the bootloader version being one of the |
| 89 | * possible causes. |
| 90 | * http://www.spinics.net/lists/arm-kernel/msg218641.html |
| 91 | */ |
| 92 | pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n"); |
| 93 | } else { |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 94 | pr_info("Successfully put all powerdomains to target state\n"); |
Rajendra Nayak | 6048009 | 2013-02-04 17:54:43 +0530 | [diff] [blame] | 95 | } |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 96 | |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 97 | return 0; |
| 98 | } |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 99 | #endif /* CONFIG_SUSPEND */ |
| 100 | |
| 101 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
| 102 | { |
| 103 | struct power_state *pwrst; |
| 104 | |
| 105 | if (!pwrdm->pwrsts) |
| 106 | return 0; |
| 107 | |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 108 | /* |
| 109 | * Skip CPU0 and CPU1 power domains. CPU1 is programmed |
| 110 | * through hotplug path and CPU0 explicitly programmed |
| 111 | * further down in the code path |
| 112 | */ |
| 113 | if (!strncmp(pwrdm->name, "cpu", 3)) |
| 114 | return 0; |
| 115 | |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 116 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
| 117 | if (!pwrst) |
| 118 | return -ENOMEM; |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 119 | |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 120 | pwrst->pwrdm = pwrdm; |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 121 | pwrst->next_state = PWRDM_POWER_RET; |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 122 | list_add(&pwrst->node, &pwrst_list); |
| 123 | |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 124 | return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 125 | } |
| 126 | |
| 127 | /** |
Santosh Shilimkar | 72826b9 | 2011-07-18 12:25:10 +0530 | [diff] [blame] | 128 | * omap_default_idle - OMAP4 default ilde routine.' |
| 129 | * |
| 130 | * Implements OMAP4 memory, IO ordering requirements which can't be addressed |
Paul Bolle | 6200632 | 2013-03-29 21:35:01 +0100 | [diff] [blame] | 131 | * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and |
| 132 | * by secondary CPU with CONFIG_CPU_IDLE. |
Santosh Shilimkar | 72826b9 | 2011-07-18 12:25:10 +0530 | [diff] [blame] | 133 | */ |
| 134 | static void omap_default_idle(void) |
| 135 | { |
Santosh Shilimkar | 72826b9 | 2011-07-18 12:25:10 +0530 | [diff] [blame] | 136 | omap_do_wfi(); |
Santosh Shilimkar | 72826b9 | 2011-07-18 12:25:10 +0530 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | /** |
Santosh Shilimkar | 705814b | 2012-04-12 16:51:47 +0530 | [diff] [blame] | 140 | * omap4_init_static_deps - Add OMAP4 static dependencies |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 141 | * |
Santosh Shilimkar | 705814b | 2012-04-12 16:51:47 +0530 | [diff] [blame] | 142 | * Add needed static clockdomain dependencies on OMAP4 devices. |
| 143 | * Return: 0 on success or 'err' on failures |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 144 | */ |
Santosh Shilimkar | 705814b | 2012-04-12 16:51:47 +0530 | [diff] [blame] | 145 | static inline int omap4_init_static_deps(void) |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 146 | { |
Santosh Shilimkar | 6cf3895 | 2013-02-16 17:55:08 +0530 | [diff] [blame] | 147 | struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm; |
Santosh Shilimkar | d5336a5 | 2013-02-16 18:04:54 +0530 | [diff] [blame] | 148 | struct clockdomain *ducati_clkdm, *l3_2_clkdm; |
Santosh Shilimkar | 705814b | 2012-04-12 16:51:47 +0530 | [diff] [blame] | 149 | int ret = 0; |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 150 | |
Santosh Shilimkar | 361b02f | 2011-03-11 16:13:09 +0530 | [diff] [blame] | 151 | if (omap_rev() == OMAP4430_REV_ES1_0) { |
| 152 | WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); |
| 153 | return -ENODEV; |
| 154 | } |
| 155 | |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 156 | pr_err("Power Management for TI OMAP4.\n"); |
Rajendra Nayak | 6048009 | 2013-02-04 17:54:43 +0530 | [diff] [blame] | 157 | /* |
| 158 | * OMAP4 chip PM currently works only with certain (newer) |
| 159 | * versions of bootloaders. This is due to missing code in the |
| 160 | * kernel to properly reset and initialize some devices. |
| 161 | * http://www.spinics.net/lists/arm-kernel/msg218641.html |
| 162 | */ |
| 163 | pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n"); |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 164 | |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 165 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
| 166 | if (ret) { |
| 167 | pr_err("Failed to setup powerdomains\n"); |
Santosh Shilimkar | 705814b | 2012-04-12 16:51:47 +0530 | [diff] [blame] | 168 | return ret; |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 169 | } |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 170 | |
Santosh Shilimkar | 12f2782 | 2011-03-08 18:24:30 +0530 | [diff] [blame] | 171 | /* |
| 172 | * The dynamic dependency between MPUSS -> MEMIF and |
| 173 | * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as |
| 174 | * expected. The hardware recommendation is to enable static |
| 175 | * dependencies for these to avoid system lock ups or random crashes. |
Santosh Shilimkar | 705814b | 2012-04-12 16:51:47 +0530 | [diff] [blame] | 176 | * The L4 wakeup depedency is added to workaround the OCP sync hardware |
| 177 | * BUG with 32K synctimer which lead to incorrect timer value read |
| 178 | * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which |
| 179 | * are part of L4 wakeup clockdomain. |
Santosh Shilimkar | 12f2782 | 2011-03-08 18:24:30 +0530 | [diff] [blame] | 180 | */ |
| 181 | mpuss_clkdm = clkdm_lookup("mpuss_clkdm"); |
| 182 | emif_clkdm = clkdm_lookup("l3_emif_clkdm"); |
| 183 | l3_1_clkdm = clkdm_lookup("l3_1_clkdm"); |
| 184 | l3_2_clkdm = clkdm_lookup("l3_2_clkdm"); |
Santosh Shilimkar | 12f2782 | 2011-03-08 18:24:30 +0530 | [diff] [blame] | 185 | ducati_clkdm = clkdm_lookup("ducati_clkdm"); |
Santosh Shilimkar | 6cf3895 | 2013-02-16 17:55:08 +0530 | [diff] [blame] | 186 | if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || |
Santosh Shilimkar | d5336a5 | 2013-02-16 18:04:54 +0530 | [diff] [blame] | 187 | (!l3_2_clkdm) || (!ducati_clkdm)) |
Santosh Shilimkar | 705814b | 2012-04-12 16:51:47 +0530 | [diff] [blame] | 188 | return -EINVAL; |
Santosh Shilimkar | 12f2782 | 2011-03-08 18:24:30 +0530 | [diff] [blame] | 189 | |
| 190 | ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm); |
| 191 | ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm); |
| 192 | ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm); |
Santosh Shilimkar | 12f2782 | 2011-03-08 18:24:30 +0530 | [diff] [blame] | 193 | ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm); |
| 194 | ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); |
| 195 | if (ret) { |
Paul Walmsley | 7852ec0 | 2012-07-26 00:54:26 -0600 | [diff] [blame] | 196 | pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n"); |
Santosh Shilimkar | 705814b | 2012-04-12 16:51:47 +0530 | [diff] [blame] | 197 | return -EINVAL; |
| 198 | } |
| 199 | |
| 200 | return ret; |
| 201 | } |
| 202 | |
| 203 | /** |
Nishanth Menon | de70af4 | 2014-01-20 14:06:37 -0600 | [diff] [blame] | 204 | * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices |
| 205 | * |
| 206 | * Initializes basic stuff for power management functionality. |
| 207 | */ |
| 208 | int __init omap4_pm_init_early(void) |
| 209 | { |
| 210 | if (cpu_is_omap446x()) |
| 211 | pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; |
| 212 | |
| 213 | return 0; |
| 214 | } |
| 215 | |
| 216 | /** |
Santosh Shilimkar | 705814b | 2012-04-12 16:51:47 +0530 | [diff] [blame] | 217 | * omap4_pm_init - Init routine for OMAP4+ devices |
| 218 | * |
| 219 | * Initializes all powerdomain and clockdomain target states |
| 220 | * and all PRCM settings. |
| 221 | * Return: Returns the error code returned by called functions. |
| 222 | */ |
| 223 | int __init omap4_pm_init(void) |
| 224 | { |
| 225 | int ret = 0; |
| 226 | |
| 227 | if (omap_rev() == OMAP4430_REV_ES1_0) { |
| 228 | WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); |
| 229 | return -ENODEV; |
| 230 | } |
| 231 | |
| 232 | pr_info("Power Management for TI OMAP4+ devices.\n"); |
| 233 | |
| 234 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
| 235 | if (ret) { |
| 236 | pr_err("Failed to setup powerdomains.\n"); |
Santosh Shilimkar | 12f2782 | 2011-03-08 18:24:30 +0530 | [diff] [blame] | 237 | goto err2; |
| 238 | } |
| 239 | |
Santosh Shilimkar | 705814b | 2012-04-12 16:51:47 +0530 | [diff] [blame] | 240 | if (cpu_is_omap44xx()) { |
| 241 | ret = omap4_init_static_deps(); |
| 242 | if (ret) |
| 243 | goto err2; |
| 244 | } |
| 245 | |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 246 | ret = omap4_mpuss_init(); |
| 247 | if (ret) { |
| 248 | pr_err("Failed to initialise OMAP4 MPUSS\n"); |
| 249 | goto err2; |
| 250 | } |
| 251 | |
Paul Walmsley | 92206fd | 2012-02-02 02:38:50 -0700 | [diff] [blame] | 252 | (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); |
Santosh Shilimkar | 3c50729 | 2011-01-05 22:03:17 +0530 | [diff] [blame] | 253 | |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 254 | #ifdef CONFIG_SUSPEND |
Paul Walmsley | 1416408 | 2012-02-02 02:30:50 -0700 | [diff] [blame] | 255 | omap_pm_suspend = omap4_pm_suspend; |
| 256 | #endif |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 257 | |
Nicolas Pitre | ae94091 | 2011-12-19 03:03:58 -0500 | [diff] [blame] | 258 | /* Overwrite the default cpu_do_idle() */ |
Nicolas Pitre | 0bcd24b | 2012-01-04 16:27:48 -0500 | [diff] [blame] | 259 | arm_pm_idle = omap_default_idle; |
Santosh Shilimkar | 72826b9 | 2011-07-18 12:25:10 +0530 | [diff] [blame] | 260 | |
Santosh Shilimkar | 705814b | 2012-04-12 16:51:47 +0530 | [diff] [blame] | 261 | if (cpu_is_omap44xx()) |
| 262 | omap4_idle_init(); |
Santosh Shilimkar | 9827266 | 2011-08-16 17:31:40 +0530 | [diff] [blame] | 263 | |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 264 | err2: |
| 265 | return ret; |
| 266 | } |