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gerrit-public.fairphone.software / kernel / msm-4.9 / 67ae8b9b7898b4587922a973f4735e64b7271314 / . / arch / arm / boot / dts / imx25-karo-tx25.dts
blob: 9b31faa96377ad0b5e0e00f30743f90e20ddae1c [file] [log] [blame]
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "imx25.dtsi"
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]14
15/ {
16 model = "Ka-Ro TX25";
17 compatible = "karo,imx25-tx25", "fsl,imx25";
18
Sascha Hauer48f51962014-05-07 15:19:00 +0200[diff] [blame]19 chosen {
20 stdout-path = &uart1;
21 };
22
Sascha Hauer974e5872014-05-09 19:59:55 +0800[diff] [blame]23 regulators {
24 compatible = "simple-bus";
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 reg_fec_phy: regulator@0 {
29 compatible = "regulator-fixed";
30 reg = <0>;
31 regulator-name = "fec-phy";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34 gpio = <&gpio4 9 0>;
35 enable-active-high;
36 };
37 };
38
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]39 memory {
40 reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
41 };
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]42};
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]43
Sascha Hauer8d690432014-05-09 08:11:17 +0200[diff] [blame]44&iomuxc {
45 pinctrl_uart1: uart1grp {
46 fsl,pins = <
47 MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
48 MX25_PAD_UART1_RXD__UART1_RXD 0x80000000
49 MX25_PAD_UART1_CTS__UART1_CTS 0x80000000
50 MX25_PAD_UART1_RTS__UART1_RTS 0x80000000
51 >;
52 };
53
54 pinctrl_fec: fecgrp {
55 fsl,pins = <
56 MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */
57 MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */
58 MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
59 MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000
60 MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
61 MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
62 MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
63 MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
64 MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
65 MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
66 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
67 >;
68 };
69
70 pinctrl_nfc: nfcgrp {
71 fsl,pins = <
72 MX25_PAD_NF_CE0__NF_CE0 0x80000000
73 MX25_PAD_NFWE_B__NFWE_B 0x80000000
74 MX25_PAD_NFRE_B__NFRE_B 0x80000000
75 MX25_PAD_NFALE__NFALE 0x80000000
76 MX25_PAD_NFCLE__NFCLE 0x80000000
77 MX25_PAD_NFWP_B__NFWP_B 0x80000000
78 MX25_PAD_NFRB__NFRB 0x80000000
79 MX25_PAD_D7__D7 0x80000000
80 MX25_PAD_D6__D6 0x80000000
81 MX25_PAD_D5__D5 0x80000000
82 MX25_PAD_D4__D4 0x80000000
83 MX25_PAD_D3__D3 0x80000000
84 MX25_PAD_D2__D2 0x80000000
85 MX25_PAD_D1__D1 0x80000000
86 MX25_PAD_D0__D0 0x80000000
87 >;
88 };
89};
90
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]91&uart1 {
Sascha Hauer8d690432014-05-09 08:11:17 +0200[diff] [blame]92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_uart1>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]94 status = "okay";
95};
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]96
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]97&fec {
Sascha Hauer8d690432014-05-09 08:11:17 +0200[diff] [blame]98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_fec>;
Sascha Hauer974e5872014-05-09 19:59:55 +0800[diff] [blame]100 phy-reset-gpios = <&gpio3 7 0>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]101 phy-mode = "rmii";
Sascha Hauer974e5872014-05-09 19:59:55 +0800[diff] [blame]102 phy-supply = <&reg_fec_phy>;
Fabio Estevam152fab62013-01-04 10:29:09 -0200[diff] [blame]103 status = "okay";
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]104};
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]105
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]106&nfc {
Sascha Hauer8d690432014-05-09 08:11:17 +0200[diff] [blame]107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_nfc>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]109 nand-on-flash-bbt;
Sascha Hauer1885e5d2014-05-09 08:11:19 +0200[diff] [blame]110 nand-ecc-mode = "hw";
111 nand-bus-width = <8>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]112 status = "okay";
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]113};