Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1 | /* |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 2 | * arch/arm/mach-tegra/tegra20_clocks.c |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2010 Google, Inc. |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 5 | * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved. |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 6 | * |
| 7 | * Author: |
| 8 | * Colin Cross <ccross@google.com> |
| 9 | * |
| 10 | * This software is licensed under the terms of the GNU General Public |
| 11 | * License version 2, as published by the Free Software Foundation, and |
| 12 | * may be copied, distributed, and modified under those terms. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | */ |
| 20 | |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/module.h> |
| 23 | #include <linux/list.h> |
| 24 | #include <linux/spinlock.h> |
| 25 | #include <linux/delay.h> |
| 26 | #include <linux/io.h> |
Jean-Christop PLAGNIOL-VILLARD | 6d803ba | 2010-11-17 10:04:33 +0100 | [diff] [blame] | 27 | #include <linux/clkdev.h> |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 28 | #include <linux/clk.h> |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 29 | |
| 30 | #include <mach/iomap.h> |
| 31 | |
| 32 | #include "clock.h" |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 33 | #include "fuse.h" |
Colin Cross | 6d29682 | 2010-11-22 18:37:54 -0800 | [diff] [blame] | 34 | #include "tegra2_emc.h" |
Joseph Lo | dab403e | 2012-08-16 17:31:48 +0800 | [diff] [blame] | 35 | #include "tegra_cpu_car.h" |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 36 | |
| 37 | #define RST_DEVICES 0x004 |
| 38 | #define RST_DEVICES_SET 0x300 |
| 39 | #define RST_DEVICES_CLR 0x304 |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 40 | #define RST_DEVICES_NUM 3 |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 41 | |
| 42 | #define CLK_OUT_ENB 0x010 |
| 43 | #define CLK_OUT_ENB_SET 0x320 |
| 44 | #define CLK_OUT_ENB_CLR 0x324 |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 45 | #define CLK_OUT_ENB_NUM 3 |
| 46 | |
| 47 | #define CLK_MASK_ARM 0x44 |
| 48 | #define MISC_CLK_ENB 0x48 |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 49 | |
| 50 | #define OSC_CTRL 0x50 |
| 51 | #define OSC_CTRL_OSC_FREQ_MASK (3<<30) |
| 52 | #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) |
| 53 | #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) |
| 54 | #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) |
| 55 | #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 56 | #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 57 | |
| 58 | #define OSC_FREQ_DET 0x58 |
| 59 | #define OSC_FREQ_DET_TRIG (1<<31) |
| 60 | |
| 61 | #define OSC_FREQ_DET_STATUS 0x5C |
| 62 | #define OSC_FREQ_DET_BUSY (1<<31) |
| 63 | #define OSC_FREQ_DET_CNT_MASK 0xFFFF |
| 64 | |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 65 | #define PERIPH_CLK_SOURCE_I2S1 0x100 |
| 66 | #define PERIPH_CLK_SOURCE_EMC 0x19c |
| 67 | #define PERIPH_CLK_SOURCE_OSC 0x1fc |
| 68 | #define PERIPH_CLK_SOURCE_NUM \ |
| 69 | ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4) |
| 70 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 71 | #define PERIPH_CLK_SOURCE_MASK (3<<30) |
| 72 | #define PERIPH_CLK_SOURCE_SHIFT 30 |
Simon Que | bb1dccf | 2011-12-16 20:11:22 +0100 | [diff] [blame] | 73 | #define PERIPH_CLK_SOURCE_PWM_MASK (7<<28) |
| 74 | #define PERIPH_CLK_SOURCE_PWM_SHIFT 28 |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 75 | #define PERIPH_CLK_SOURCE_ENABLE (1<<28) |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 76 | #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF |
| 77 | #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 78 | #define PERIPH_CLK_SOURCE_DIV_SHIFT 0 |
| 79 | |
Colin Cross | 9743b38 | 2011-02-12 18:24:32 -0800 | [diff] [blame] | 80 | #define SDMMC_CLK_INT_FB_SEL (1 << 23) |
| 81 | #define SDMMC_CLK_INT_FB_DLY_SHIFT 16 |
| 82 | #define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT) |
| 83 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 84 | #define PLL_BASE 0x0 |
| 85 | #define PLL_BASE_BYPASS (1<<31) |
| 86 | #define PLL_BASE_ENABLE (1<<30) |
| 87 | #define PLL_BASE_REF_ENABLE (1<<29) |
| 88 | #define PLL_BASE_OVERRIDE (1<<28) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 89 | #define PLL_BASE_DIVP_MASK (0x7<<20) |
| 90 | #define PLL_BASE_DIVP_SHIFT 20 |
| 91 | #define PLL_BASE_DIVN_MASK (0x3FF<<8) |
| 92 | #define PLL_BASE_DIVN_SHIFT 8 |
| 93 | #define PLL_BASE_DIVM_MASK (0x1F) |
| 94 | #define PLL_BASE_DIVM_SHIFT 0 |
| 95 | |
| 96 | #define PLL_OUT_RATIO_MASK (0xFF<<8) |
| 97 | #define PLL_OUT_RATIO_SHIFT 8 |
| 98 | #define PLL_OUT_OVERRIDE (1<<2) |
| 99 | #define PLL_OUT_CLKEN (1<<1) |
| 100 | #define PLL_OUT_RESET_DISABLE (1<<0) |
| 101 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 102 | #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc) |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 103 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 104 | #define PLL_MISC_DCCON_SHIFT 20 |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 105 | #define PLL_MISC_CPCON_SHIFT 8 |
| 106 | #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT) |
| 107 | #define PLL_MISC_LFCON_SHIFT 4 |
| 108 | #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT) |
| 109 | #define PLL_MISC_VCOCON_SHIFT 0 |
| 110 | #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT) |
| 111 | |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 112 | #define PLLU_BASE_POST_DIV (1<<20) |
| 113 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 114 | #define PLLD_MISC_CLKENABLE (1<<30) |
| 115 | #define PLLD_MISC_DIV_RST (1<<23) |
| 116 | #define PLLD_MISC_DCCON_SHIFT 12 |
| 117 | |
Mike Rapoport | 8d685bc | 2010-09-27 11:26:32 +0200 | [diff] [blame] | 118 | #define PLLE_MISC_READY (1 << 15) |
| 119 | |
Colin Cross | f151961 | 2011-02-12 16:05:31 -0800 | [diff] [blame] | 120 | #define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4) |
| 121 | #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8) |
| 122 | #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32)) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 123 | |
| 124 | #define SUPER_CLK_MUX 0x00 |
| 125 | #define SUPER_STATE_SHIFT 28 |
| 126 | #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT) |
| 127 | #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT) |
| 128 | #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT) |
| 129 | #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT) |
| 130 | #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT) |
| 131 | #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT) |
| 132 | #define SUPER_SOURCE_MASK 0xF |
| 133 | #define SUPER_FIQ_SOURCE_SHIFT 12 |
| 134 | #define SUPER_IRQ_SOURCE_SHIFT 8 |
| 135 | #define SUPER_RUN_SOURCE_SHIFT 4 |
| 136 | #define SUPER_IDLE_SOURCE_SHIFT 0 |
| 137 | |
| 138 | #define SUPER_CLK_DIVIDER 0x04 |
| 139 | |
| 140 | #define BUS_CLK_DISABLE (1<<3) |
| 141 | #define BUS_CLK_DIV_MASK 0x3 |
| 142 | |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 143 | #define PMC_CTRL 0x0 |
| 144 | #define PMC_CTRL_BLINK_ENB (1 << 7) |
| 145 | |
| 146 | #define PMC_DPD_PADS_ORIDE 0x1c |
| 147 | #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20) |
| 148 | |
| 149 | #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0 |
| 150 | #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff |
| 151 | #define PMC_BLINK_TIMER_ENB (1 << 15) |
| 152 | #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16 |
| 153 | #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff |
| 154 | |
Joseph Lo | dab403e | 2012-08-16 17:31:48 +0800 | [diff] [blame] | 155 | /* Tegra CPU clock and reset control regs */ |
| 156 | #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c |
| 157 | #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 |
| 158 | #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 |
| 159 | |
| 160 | #define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) |
| 161 | #define CPU_RESET(cpu) (0x1111ul << (cpu)) |
| 162 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 163 | static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 164 | static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 165 | |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 166 | /* |
| 167 | * Some clocks share a register with other clocks. Any clock op that |
| 168 | * non-atomically modifies a register used by another clock must lock |
| 169 | * clock_register_lock first. |
| 170 | */ |
| 171 | static DEFINE_SPINLOCK(clock_register_lock); |
| 172 | |
Colin Cross | 78f379b | 2010-10-20 19:19:58 -0700 | [diff] [blame] | 173 | /* |
| 174 | * Some peripheral clocks share an enable bit, so refcount the enable bits |
| 175 | * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U |
| 176 | */ |
| 177 | static int tegra_periph_clk_enable_refcount[3 * 32]; |
| 178 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 179 | #define clk_writel(value, reg) \ |
Olof Johansson | d395935 | 2011-09-08 17:56:59 -0700 | [diff] [blame] | 180 | __raw_writel(value, reg_clk_base + (reg)) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 181 | #define clk_readl(reg) \ |
Olof Johansson | d395935 | 2011-09-08 17:56:59 -0700 | [diff] [blame] | 182 | __raw_readl(reg_clk_base + (reg)) |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 183 | #define pmc_writel(value, reg) \ |
Olof Johansson | d395935 | 2011-09-08 17:56:59 -0700 | [diff] [blame] | 184 | __raw_writel(value, reg_pmc_base + (reg)) |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 185 | #define pmc_readl(reg) \ |
Olof Johansson | d395935 | 2011-09-08 17:56:59 -0700 | [diff] [blame] | 186 | __raw_readl(reg_pmc_base + (reg)) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 187 | |
Peter De Schrijver | 8e4fab2 | 2011-12-14 17:03:16 +0200 | [diff] [blame] | 188 | static unsigned long clk_measure_input_freq(void) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 189 | { |
| 190 | u32 clock_autodetect; |
| 191 | clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET); |
| 192 | do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY); |
| 193 | clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS); |
| 194 | if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) { |
| 195 | return 12000000; |
| 196 | } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) { |
| 197 | return 13000000; |
| 198 | } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) { |
| 199 | return 19200000; |
| 200 | } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) { |
| 201 | return 26000000; |
| 202 | } else { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 203 | pr_err("%s: Unexpected clock autodetect value %d", |
| 204 | __func__, clock_autodetect); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 205 | BUG(); |
| 206 | return 0; |
| 207 | } |
| 208 | } |
| 209 | |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 210 | static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 211 | { |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 212 | s64 divider_u71 = parent_rate * 2; |
| 213 | divider_u71 += rate - 1; |
| 214 | do_div(divider_u71, rate); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 215 | |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 216 | if (divider_u71 - 2 < 0) |
| 217 | return 0; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 218 | |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 219 | if (divider_u71 - 2 > 255) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 220 | return -EINVAL; |
| 221 | |
| 222 | return divider_u71 - 2; |
| 223 | } |
| 224 | |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 225 | static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 226 | { |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 227 | s64 divider_u16; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 228 | |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 229 | divider_u16 = parent_rate; |
| 230 | divider_u16 += rate - 1; |
| 231 | do_div(divider_u16, rate); |
| 232 | |
| 233 | if (divider_u16 - 1 < 0) |
| 234 | return 0; |
| 235 | |
Stephen Warren | eb70e1b | 2012-07-24 15:48:12 -0600 | [diff] [blame] | 236 | if (divider_u16 - 1 > 0xFFFF) |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 237 | return -EINVAL; |
| 238 | |
| 239 | return divider_u16 - 1; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 240 | } |
| 241 | |
Joseph Lo | b78c030 | 2012-08-17 14:51:21 +0800 | [diff] [blame] | 242 | static unsigned long tegra_clk_fixed_recalc_rate(struct clk_hw *hw, |
| 243 | unsigned long parent_rate) |
| 244 | { |
| 245 | return to_clk_tegra(hw)->fixed_rate; |
| 246 | } |
| 247 | |
| 248 | struct clk_ops tegra_clk_32k_ops = { |
| 249 | .recalc_rate = tegra_clk_fixed_recalc_rate, |
| 250 | }; |
| 251 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 252 | /* clk_m functions */ |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 253 | static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw, |
| 254 | unsigned long prate) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 255 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 256 | if (!to_clk_tegra(hw)->fixed_rate) |
| 257 | to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq(); |
| 258 | return to_clk_tegra(hw)->fixed_rate; |
| 259 | } |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 260 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 261 | static void tegra20_clk_m_init(struct clk_hw *hw) |
| 262 | { |
| 263 | struct clk_tegra *c = to_clk_tegra(hw); |
| 264 | u32 osc_ctrl = clk_readl(OSC_CTRL); |
| 265 | u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK; |
| 266 | |
| 267 | switch (c->fixed_rate) { |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 268 | case 12000000: |
| 269 | auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; |
| 270 | break; |
| 271 | case 13000000: |
| 272 | auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ; |
| 273 | break; |
| 274 | case 19200000: |
| 275 | auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ; |
| 276 | break; |
| 277 | case 26000000: |
| 278 | auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ; |
| 279 | break; |
| 280 | default: |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 281 | BUG(); |
| 282 | } |
| 283 | clk_writel(auto_clock_control, OSC_CTRL); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 284 | } |
| 285 | |
Prashant Gaikwad | 86edb87 | 2012-08-06 11:57:40 +0530 | [diff] [blame] | 286 | struct clk_ops tegra_clk_m_ops = { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 287 | .init = tegra20_clk_m_init, |
| 288 | .recalc_rate = tegra20_clk_m_recalc_rate, |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 289 | }; |
| 290 | |
| 291 | /* super clock functions */ |
| 292 | /* "super clocks" on tegra have two-stage muxes and a clock skipping |
| 293 | * super divider. We will ignore the clock skipping divider, since we |
| 294 | * can't lower the voltage when using the clock skip, but we can if we |
| 295 | * lower the PLL frequency. |
| 296 | */ |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 297 | static int tegra20_super_clk_is_enabled(struct clk_hw *hw) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 298 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 299 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 300 | u32 val; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 301 | |
| 302 | val = clk_readl(c->reg + SUPER_CLK_MUX); |
| 303 | BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && |
| 304 | ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); |
| 305 | c->state = ON; |
| 306 | return c->state; |
| 307 | } |
| 308 | |
| 309 | static int tegra20_super_clk_enable(struct clk_hw *hw) |
| 310 | { |
| 311 | struct clk_tegra *c = to_clk_tegra(hw); |
| 312 | clk_writel(0, c->reg + SUPER_CLK_DIVIDER); |
| 313 | return 0; |
| 314 | } |
| 315 | |
| 316 | static void tegra20_super_clk_disable(struct clk_hw *hw) |
| 317 | { |
| 318 | pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); |
| 319 | |
| 320 | /* oops - don't disable the CPU clock! */ |
| 321 | BUG(); |
| 322 | } |
| 323 | |
| 324 | static u8 tegra20_super_clk_get_parent(struct clk_hw *hw) |
| 325 | { |
| 326 | struct clk_tegra *c = to_clk_tegra(hw); |
| 327 | int val = clk_readl(c->reg + SUPER_CLK_MUX); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 328 | int source; |
| 329 | int shift; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 330 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 331 | BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && |
| 332 | ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); |
| 333 | shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? |
| 334 | SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; |
| 335 | source = (val >> shift) & SUPER_SOURCE_MASK; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 336 | return source; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 337 | } |
| 338 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 339 | static int tegra20_super_clk_set_parent(struct clk_hw *hw, u8 index) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 340 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 341 | struct clk_tegra *c = to_clk_tegra(hw); |
| 342 | u32 val = clk_readl(c->reg + SUPER_CLK_MUX); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 343 | int shift; |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 344 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 345 | BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && |
| 346 | ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); |
| 347 | shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? |
| 348 | SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 349 | val &= ~(SUPER_SOURCE_MASK << shift); |
| 350 | val |= index << shift; |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 351 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 352 | clk_writel(val, c->reg); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 353 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 354 | return 0; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 355 | } |
| 356 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 357 | /* FIX ME: Need to switch parents to change the source PLL rate */ |
| 358 | static unsigned long tegra20_super_clk_recalc_rate(struct clk_hw *hw, |
| 359 | unsigned long prate) |
Colin Cross | 9c7dc56 | 2011-02-12 21:25:23 -0800 | [diff] [blame] | 360 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 361 | return prate; |
Colin Cross | 9c7dc56 | 2011-02-12 21:25:23 -0800 | [diff] [blame] | 362 | } |
| 363 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 364 | static long tegra20_super_clk_round_rate(struct clk_hw *hw, unsigned long rate, |
| 365 | unsigned long *prate) |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 366 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 367 | return *prate; |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 368 | } |
| 369 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 370 | static int tegra20_super_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
| 371 | unsigned long parent_rate) |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 372 | { |
| 373 | return 0; |
| 374 | } |
| 375 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 376 | struct clk_ops tegra_super_ops = { |
| 377 | .is_enabled = tegra20_super_clk_is_enabled, |
| 378 | .enable = tegra20_super_clk_enable, |
| 379 | .disable = tegra20_super_clk_disable, |
| 380 | .set_parent = tegra20_super_clk_set_parent, |
| 381 | .get_parent = tegra20_super_clk_get_parent, |
| 382 | .set_rate = tegra20_super_clk_set_rate, |
| 383 | .round_rate = tegra20_super_clk_round_rate, |
| 384 | .recalc_rate = tegra20_super_clk_recalc_rate, |
| 385 | }; |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 386 | |
Prashant Gaikwad | b4350f4 | 2012-09-13 15:04:33 +0530 | [diff] [blame] | 387 | static unsigned long tegra20_twd_clk_recalc_rate(struct clk_hw *hw, |
| 388 | unsigned long parent_rate) |
| 389 | { |
| 390 | struct clk_tegra *c = to_clk_tegra(hw); |
| 391 | u64 rate = parent_rate; |
| 392 | |
| 393 | if (c->mul != 0 && c->div != 0) { |
| 394 | rate *= c->mul; |
| 395 | rate += c->div - 1; /* round up */ |
| 396 | do_div(rate, c->div); |
| 397 | } |
| 398 | |
| 399 | return rate; |
| 400 | } |
| 401 | |
| 402 | struct clk_ops tegra_twd_ops = { |
| 403 | .recalc_rate = tegra20_twd_clk_recalc_rate, |
| 404 | }; |
| 405 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 406 | static u8 tegra20_cop_clk_get_parent(struct clk_hw *hw) |
| 407 | { |
| 408 | return 0; |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 409 | } |
| 410 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 411 | struct clk_ops tegra_cop_ops = { |
| 412 | .get_parent = tegra20_cop_clk_get_parent, |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 413 | }; |
| 414 | |
Colin Cross | 9c7dc56 | 2011-02-12 21:25:23 -0800 | [diff] [blame] | 415 | /* virtual cop clock functions. Used to acquire the fake 'cop' clock to |
| 416 | * reset the COP block (i.e. AVP) */ |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 417 | void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert) |
Colin Cross | 9c7dc56 | 2011-02-12 21:25:23 -0800 | [diff] [blame] | 418 | { |
| 419 | unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR; |
| 420 | |
| 421 | pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert"); |
| 422 | clk_writel(1 << 1, reg); |
| 423 | } |
| 424 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 425 | /* bus clock functions */ |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 426 | static int tegra20_bus_clk_is_enabled(struct clk_hw *hw) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 427 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 428 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 429 | u32 val = clk_readl(c->reg); |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 430 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 431 | c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 432 | return c->state; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 433 | } |
| 434 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 435 | static int tegra20_bus_clk_enable(struct clk_hw *hw) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 436 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 437 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 438 | unsigned long flags; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 439 | u32 val; |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 440 | |
| 441 | spin_lock_irqsave(&clock_register_lock, flags); |
| 442 | |
| 443 | val = clk_readl(c->reg); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 444 | val &= ~(BUS_CLK_DISABLE << c->reg_shift); |
| 445 | clk_writel(val, c->reg); |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 446 | |
| 447 | spin_unlock_irqrestore(&clock_register_lock, flags); |
| 448 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 449 | return 0; |
| 450 | } |
| 451 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 452 | static void tegra20_bus_clk_disable(struct clk_hw *hw) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 453 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 454 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 455 | unsigned long flags; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 456 | u32 val; |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 457 | |
| 458 | spin_lock_irqsave(&clock_register_lock, flags); |
| 459 | |
| 460 | val = clk_readl(c->reg); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 461 | val |= BUS_CLK_DISABLE << c->reg_shift; |
| 462 | clk_writel(val, c->reg); |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 463 | |
| 464 | spin_unlock_irqrestore(&clock_register_lock, flags); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 465 | } |
| 466 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 467 | static unsigned long tegra20_bus_clk_recalc_rate(struct clk_hw *hw, |
| 468 | unsigned long prate) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 469 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 470 | struct clk_tegra *c = to_clk_tegra(hw); |
| 471 | u32 val = clk_readl(c->reg); |
| 472 | u64 rate = prate; |
| 473 | |
| 474 | c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; |
| 475 | c->mul = 1; |
| 476 | |
| 477 | if (c->mul != 0 && c->div != 0) { |
| 478 | rate *= c->mul; |
| 479 | rate += c->div - 1; /* round up */ |
| 480 | do_div(rate, c->div); |
| 481 | } |
| 482 | return rate; |
| 483 | } |
| 484 | |
| 485 | static int tegra20_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
| 486 | unsigned long parent_rate) |
| 487 | { |
| 488 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 489 | int ret = -EINVAL; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 490 | unsigned long flags; |
| 491 | u32 val; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 492 | int i; |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 493 | |
| 494 | spin_lock_irqsave(&clock_register_lock, flags); |
| 495 | |
| 496 | val = clk_readl(c->reg); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 497 | for (i = 1; i <= 4; i++) { |
| 498 | if (rate == parent_rate / i) { |
| 499 | val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); |
| 500 | val |= (i - 1) << c->reg_shift; |
| 501 | clk_writel(val, c->reg); |
| 502 | c->div = i; |
| 503 | c->mul = 1; |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 504 | ret = 0; |
| 505 | break; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 506 | } |
| 507 | } |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 508 | |
| 509 | spin_unlock_irqrestore(&clock_register_lock, flags); |
| 510 | |
| 511 | return ret; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 512 | } |
| 513 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 514 | static long tegra20_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate, |
| 515 | unsigned long *prate) |
| 516 | { |
| 517 | unsigned long parent_rate = *prate; |
| 518 | s64 divider; |
| 519 | |
| 520 | if (rate >= parent_rate) |
| 521 | return rate; |
| 522 | |
| 523 | divider = parent_rate; |
| 524 | divider += rate - 1; |
| 525 | do_div(divider, rate); |
| 526 | |
| 527 | if (divider < 0) |
| 528 | return divider; |
| 529 | |
| 530 | if (divider > 4) |
| 531 | divider = 4; |
| 532 | do_div(parent_rate, divider); |
| 533 | |
| 534 | return parent_rate; |
| 535 | } |
| 536 | |
Prashant Gaikwad | 86edb87 | 2012-08-06 11:57:40 +0530 | [diff] [blame] | 537 | struct clk_ops tegra_bus_ops = { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 538 | .is_enabled = tegra20_bus_clk_is_enabled, |
| 539 | .enable = tegra20_bus_clk_enable, |
| 540 | .disable = tegra20_bus_clk_disable, |
| 541 | .set_rate = tegra20_bus_clk_set_rate, |
| 542 | .round_rate = tegra20_bus_clk_round_rate, |
| 543 | .recalc_rate = tegra20_bus_clk_recalc_rate, |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 544 | }; |
| 545 | |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 546 | /* Blink output functions */ |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 547 | static int tegra20_blink_clk_is_enabled(struct clk_hw *hw) |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 548 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 549 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 550 | u32 val; |
| 551 | |
| 552 | val = pmc_readl(PMC_CTRL); |
| 553 | c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 554 | return c->state; |
| 555 | } |
| 556 | |
| 557 | static unsigned long tegra20_blink_clk_recalc_rate(struct clk_hw *hw, |
| 558 | unsigned long prate) |
| 559 | { |
| 560 | struct clk_tegra *c = to_clk_tegra(hw); |
| 561 | u64 rate = prate; |
| 562 | u32 val; |
| 563 | |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 564 | c->mul = 1; |
| 565 | val = pmc_readl(c->reg); |
| 566 | |
| 567 | if (val & PMC_BLINK_TIMER_ENB) { |
| 568 | unsigned int on_off; |
| 569 | |
| 570 | on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) & |
| 571 | PMC_BLINK_TIMER_DATA_ON_MASK; |
| 572 | val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT; |
| 573 | val &= PMC_BLINK_TIMER_DATA_OFF_MASK; |
| 574 | on_off += val; |
| 575 | /* each tick in the blink timer is 4 32KHz clocks */ |
| 576 | c->div = on_off * 4; |
| 577 | } else { |
| 578 | c->div = 1; |
| 579 | } |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 580 | |
| 581 | if (c->mul != 0 && c->div != 0) { |
| 582 | rate *= c->mul; |
| 583 | rate += c->div - 1; /* round up */ |
| 584 | do_div(rate, c->div); |
| 585 | } |
| 586 | return rate; |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 587 | } |
| 588 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 589 | static int tegra20_blink_clk_enable(struct clk_hw *hw) |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 590 | { |
| 591 | u32 val; |
| 592 | |
| 593 | val = pmc_readl(PMC_DPD_PADS_ORIDE); |
| 594 | pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); |
| 595 | |
| 596 | val = pmc_readl(PMC_CTRL); |
| 597 | pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL); |
| 598 | |
| 599 | return 0; |
| 600 | } |
| 601 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 602 | static void tegra20_blink_clk_disable(struct clk_hw *hw) |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 603 | { |
| 604 | u32 val; |
| 605 | |
| 606 | val = pmc_readl(PMC_CTRL); |
| 607 | pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL); |
| 608 | |
| 609 | val = pmc_readl(PMC_DPD_PADS_ORIDE); |
| 610 | pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); |
| 611 | } |
| 612 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 613 | static int tegra20_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
| 614 | unsigned long parent_rate) |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 615 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 616 | struct clk_tegra *c = to_clk_tegra(hw); |
| 617 | |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 618 | if (rate >= parent_rate) { |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 619 | c->div = 1; |
| 620 | pmc_writel(0, c->reg); |
| 621 | } else { |
| 622 | unsigned int on_off; |
| 623 | u32 val; |
| 624 | |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 625 | on_off = DIV_ROUND_UP(parent_rate / 8, rate); |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 626 | c->div = on_off * 8; |
| 627 | |
| 628 | val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) << |
| 629 | PMC_BLINK_TIMER_DATA_ON_SHIFT; |
| 630 | on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK; |
| 631 | on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT; |
| 632 | val |= on_off; |
| 633 | val |= PMC_BLINK_TIMER_ENB; |
| 634 | pmc_writel(val, c->reg); |
| 635 | } |
| 636 | |
| 637 | return 0; |
| 638 | } |
| 639 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 640 | static long tegra20_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate, |
| 641 | unsigned long *prate) |
| 642 | { |
| 643 | int div; |
| 644 | int mul; |
| 645 | long round_rate = *prate; |
| 646 | |
| 647 | mul = 1; |
| 648 | |
| 649 | if (rate >= *prate) { |
| 650 | div = 1; |
| 651 | } else { |
| 652 | div = DIV_ROUND_UP(*prate / 8, rate); |
| 653 | div *= 8; |
| 654 | } |
| 655 | |
| 656 | round_rate *= mul; |
| 657 | round_rate += div - 1; |
| 658 | do_div(round_rate, div); |
| 659 | |
| 660 | return round_rate; |
| 661 | } |
| 662 | |
Prashant Gaikwad | 86edb87 | 2012-08-06 11:57:40 +0530 | [diff] [blame] | 663 | struct clk_ops tegra_blink_clk_ops = { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 664 | .is_enabled = tegra20_blink_clk_is_enabled, |
| 665 | .enable = tegra20_blink_clk_enable, |
| 666 | .disable = tegra20_blink_clk_disable, |
| 667 | .set_rate = tegra20_blink_clk_set_rate, |
| 668 | .round_rate = tegra20_blink_clk_round_rate, |
| 669 | .recalc_rate = tegra20_blink_clk_recalc_rate, |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 670 | }; |
| 671 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 672 | /* PLL Functions */ |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 673 | static int tegra20_pll_clk_wait_for_lock(struct clk_tegra *c) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 674 | { |
Colin Cross | f151961 | 2011-02-12 16:05:31 -0800 | [diff] [blame] | 675 | udelay(c->u.pll.lock_delay); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 676 | return 0; |
| 677 | } |
| 678 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 679 | static int tegra20_pll_clk_is_enabled(struct clk_hw *hw) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 680 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 681 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 682 | u32 val = clk_readl(c->reg + PLL_BASE); |
| 683 | |
| 684 | c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 685 | return c->state; |
| 686 | } |
| 687 | |
| 688 | static unsigned long tegra20_pll_clk_recalc_rate(struct clk_hw *hw, |
| 689 | unsigned long prate) |
| 690 | { |
| 691 | struct clk_tegra *c = to_clk_tegra(hw); |
| 692 | u32 val = clk_readl(c->reg + PLL_BASE); |
| 693 | u64 rate = prate; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 694 | |
| 695 | if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 696 | const struct clk_pll_freq_table *sel; |
| 697 | for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { |
| 698 | if (sel->input_rate == prate && |
| 699 | sel->output_rate == c->u.pll.fixed_rate) { |
| 700 | c->mul = sel->n; |
| 701 | c->div = sel->m * sel->p; |
| 702 | break; |
| 703 | } |
| 704 | } |
| 705 | pr_err("Clock %s has unknown fixed frequency\n", |
| 706 | __clk_get_name(hw->clk)); |
| 707 | BUG(); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 708 | } else if (val & PLL_BASE_BYPASS) { |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 709 | c->mul = 1; |
| 710 | c->div = 1; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 711 | } else { |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 712 | c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; |
| 713 | c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; |
| 714 | if (c->flags & PLLU) |
| 715 | c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2; |
| 716 | else |
| 717 | c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 718 | } |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 719 | |
| 720 | if (c->mul != 0 && c->div != 0) { |
| 721 | rate *= c->mul; |
| 722 | rate += c->div - 1; /* round up */ |
| 723 | do_div(rate, c->div); |
| 724 | } |
| 725 | return rate; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 726 | } |
| 727 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 728 | static int tegra20_pll_clk_enable(struct clk_hw *hw) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 729 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 730 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 731 | u32 val; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 732 | pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 733 | |
| 734 | val = clk_readl(c->reg + PLL_BASE); |
| 735 | val &= ~PLL_BASE_BYPASS; |
| 736 | val |= PLL_BASE_ENABLE; |
| 737 | clk_writel(val, c->reg + PLL_BASE); |
| 738 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 739 | tegra20_pll_clk_wait_for_lock(c); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 740 | |
| 741 | return 0; |
| 742 | } |
| 743 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 744 | static void tegra20_pll_clk_disable(struct clk_hw *hw) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 745 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 746 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 747 | u32 val; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 748 | pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 749 | |
| 750 | val = clk_readl(c->reg); |
| 751 | val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); |
| 752 | clk_writel(val, c->reg); |
| 753 | } |
| 754 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 755 | static int tegra20_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
| 756 | unsigned long parent_rate) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 757 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 758 | struct clk_tegra *c = to_clk_tegra(hw); |
| 759 | unsigned long input_rate = parent_rate; |
Colin Cross | f151961 | 2011-02-12 16:05:31 -0800 | [diff] [blame] | 760 | const struct clk_pll_freq_table *sel; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 761 | u32 val; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 762 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 763 | pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 764 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 765 | if (c->flags & PLL_FIXED) { |
| 766 | int ret = 0; |
| 767 | if (rate != c->u.pll.fixed_rate) { |
| 768 | pr_err("%s: Can not change %s fixed rate %lu to %lu\n", |
| 769 | __func__, __clk_get_name(hw->clk), |
| 770 | c->u.pll.fixed_rate, rate); |
| 771 | ret = -EINVAL; |
| 772 | } |
| 773 | return ret; |
| 774 | } |
| 775 | |
Colin Cross | f151961 | 2011-02-12 16:05:31 -0800 | [diff] [blame] | 776 | for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 777 | if (sel->input_rate == input_rate && sel->output_rate == rate) { |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 778 | c->mul = sel->n; |
| 779 | c->div = sel->m * sel->p; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 780 | |
| 781 | val = clk_readl(c->reg + PLL_BASE); |
| 782 | if (c->flags & PLL_FIXED) |
| 783 | val |= PLL_BASE_OVERRIDE; |
| 784 | val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK | |
| 785 | PLL_BASE_DIVM_MASK); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 786 | val |= (sel->m << PLL_BASE_DIVM_SHIFT) | |
| 787 | (sel->n << PLL_BASE_DIVN_SHIFT); |
| 788 | BUG_ON(sel->p < 1 || sel->p > 2); |
| 789 | if (c->flags & PLLU) { |
| 790 | if (sel->p == 1) |
| 791 | val |= PLLU_BASE_POST_DIV; |
| 792 | } else { |
| 793 | if (sel->p == 2) |
| 794 | val |= 1 << PLL_BASE_DIVP_SHIFT; |
| 795 | } |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 796 | clk_writel(val, c->reg + PLL_BASE); |
| 797 | |
| 798 | if (c->flags & PLL_HAS_CPCON) { |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 799 | val = clk_readl(c->reg + PLL_MISC(c)); |
| 800 | val &= ~PLL_MISC_CPCON_MASK; |
| 801 | val |= sel->cpcon << PLL_MISC_CPCON_SHIFT; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 802 | clk_writel(val, c->reg + PLL_MISC(c)); |
| 803 | } |
| 804 | |
| 805 | if (c->state == ON) |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 806 | tegra20_pll_clk_enable(hw); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 807 | return 0; |
| 808 | } |
| 809 | } |
| 810 | return -EINVAL; |
| 811 | } |
| 812 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 813 | static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate, |
| 814 | unsigned long *prate) |
| 815 | { |
| 816 | struct clk_tegra *c = to_clk_tegra(hw); |
| 817 | const struct clk_pll_freq_table *sel; |
| 818 | unsigned long input_rate = *prate; |
Stephen Warren | 7a74a44 | 2012-09-10 17:02:45 -0600 | [diff] [blame] | 819 | u64 output_rate = *prate; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 820 | int mul; |
| 821 | int div; |
| 822 | |
| 823 | if (c->flags & PLL_FIXED) |
| 824 | return c->u.pll.fixed_rate; |
| 825 | |
| 826 | for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) |
| 827 | if (sel->input_rate == input_rate && sel->output_rate == rate) { |
| 828 | mul = sel->n; |
| 829 | div = sel->m * sel->p; |
| 830 | break; |
| 831 | } |
| 832 | |
| 833 | if (sel->input_rate == 0) |
| 834 | return -EINVAL; |
| 835 | |
| 836 | output_rate *= mul; |
| 837 | output_rate += div - 1; /* round up */ |
| 838 | do_div(output_rate, div); |
| 839 | |
| 840 | return output_rate; |
| 841 | } |
| 842 | |
Prashant Gaikwad | 86edb87 | 2012-08-06 11:57:40 +0530 | [diff] [blame] | 843 | struct clk_ops tegra_pll_ops = { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 844 | .is_enabled = tegra20_pll_clk_is_enabled, |
| 845 | .enable = tegra20_pll_clk_enable, |
| 846 | .disable = tegra20_pll_clk_disable, |
| 847 | .set_rate = tegra20_pll_clk_set_rate, |
| 848 | .recalc_rate = tegra20_pll_clk_recalc_rate, |
| 849 | .round_rate = tegra20_pll_clk_round_rate, |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 850 | }; |
| 851 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 852 | static void tegra20_pllx_clk_init(struct clk_hw *hw) |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 853 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 854 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 855 | |
Olof Johansson | 9a1086d | 2011-10-13 00:31:20 -0700 | [diff] [blame] | 856 | if (tegra_sku_id == 7) |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 857 | c->max_rate = 750000000; |
| 858 | } |
| 859 | |
Prashant Gaikwad | 86edb87 | 2012-08-06 11:57:40 +0530 | [diff] [blame] | 860 | struct clk_ops tegra_pllx_ops = { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 861 | .init = tegra20_pllx_clk_init, |
| 862 | .is_enabled = tegra20_pll_clk_is_enabled, |
| 863 | .enable = tegra20_pll_clk_enable, |
| 864 | .disable = tegra20_pll_clk_disable, |
| 865 | .set_rate = tegra20_pll_clk_set_rate, |
| 866 | .recalc_rate = tegra20_pll_clk_recalc_rate, |
| 867 | .round_rate = tegra20_pll_clk_round_rate, |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 868 | }; |
| 869 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 870 | static int tegra20_plle_clk_enable(struct clk_hw *hw) |
Mike Rapoport | 8d685bc | 2010-09-27 11:26:32 +0200 | [diff] [blame] | 871 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 872 | struct clk_tegra *c = to_clk_tegra(hw); |
Mike Rapoport | 8d685bc | 2010-09-27 11:26:32 +0200 | [diff] [blame] | 873 | u32 val; |
| 874 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 875 | pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); |
Mike Rapoport | 8d685bc | 2010-09-27 11:26:32 +0200 | [diff] [blame] | 876 | |
| 877 | mdelay(1); |
| 878 | |
| 879 | val = clk_readl(c->reg + PLL_BASE); |
| 880 | if (!(val & PLLE_MISC_READY)) |
| 881 | return -EBUSY; |
| 882 | |
| 883 | val = clk_readl(c->reg + PLL_BASE); |
| 884 | val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS; |
| 885 | clk_writel(val, c->reg + PLL_BASE); |
| 886 | |
| 887 | return 0; |
| 888 | } |
| 889 | |
Prashant Gaikwad | 86edb87 | 2012-08-06 11:57:40 +0530 | [diff] [blame] | 890 | struct clk_ops tegra_plle_ops = { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 891 | .is_enabled = tegra20_pll_clk_is_enabled, |
| 892 | .enable = tegra20_plle_clk_enable, |
| 893 | .set_rate = tegra20_pll_clk_set_rate, |
| 894 | .recalc_rate = tegra20_pll_clk_recalc_rate, |
| 895 | .round_rate = tegra20_pll_clk_round_rate, |
Mike Rapoport | 8d685bc | 2010-09-27 11:26:32 +0200 | [diff] [blame] | 896 | }; |
| 897 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 898 | /* Clock divider ops */ |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 899 | static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 900 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 901 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 902 | u32 val = clk_readl(c->reg); |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 903 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 904 | val >>= c->reg_shift; |
| 905 | c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; |
| 906 | if (!(val & PLL_OUT_RESET_DISABLE)) |
| 907 | c->state = OFF; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 908 | return c->state; |
| 909 | } |
| 910 | |
| 911 | static unsigned long tegra20_pll_div_clk_recalc_rate(struct clk_hw *hw, |
| 912 | unsigned long prate) |
| 913 | { |
| 914 | struct clk_tegra *c = to_clk_tegra(hw); |
| 915 | u64 rate = prate; |
| 916 | u32 val = clk_readl(c->reg); |
| 917 | u32 divu71; |
| 918 | |
| 919 | val >>= c->reg_shift; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 920 | |
| 921 | if (c->flags & DIV_U71) { |
| 922 | divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; |
| 923 | c->div = (divu71 + 2); |
| 924 | c->mul = 2; |
| 925 | } else if (c->flags & DIV_2) { |
| 926 | c->div = 2; |
| 927 | c->mul = 1; |
| 928 | } else { |
| 929 | c->div = 1; |
| 930 | c->mul = 1; |
| 931 | } |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 932 | |
| 933 | rate *= c->mul; |
| 934 | rate += c->div - 1; /* round up */ |
| 935 | do_div(rate, c->div); |
| 936 | |
| 937 | return rate; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 938 | } |
| 939 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 940 | static int tegra20_pll_div_clk_enable(struct clk_hw *hw) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 941 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 942 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 943 | unsigned long flags; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 944 | u32 new_val; |
| 945 | u32 val; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 946 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 947 | pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk)); |
| 948 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 949 | if (c->flags & DIV_U71) { |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 950 | spin_lock_irqsave(&clock_register_lock, flags); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 951 | val = clk_readl(c->reg); |
| 952 | new_val = val >> c->reg_shift; |
| 953 | new_val &= 0xFFFF; |
| 954 | |
| 955 | new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; |
| 956 | |
| 957 | val &= ~(0xFFFF << c->reg_shift); |
| 958 | val |= new_val << c->reg_shift; |
| 959 | clk_writel(val, c->reg); |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 960 | spin_unlock_irqrestore(&clock_register_lock, flags); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 961 | return 0; |
| 962 | } else if (c->flags & DIV_2) { |
| 963 | BUG_ON(!(c->flags & PLLD)); |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 964 | spin_lock_irqsave(&clock_register_lock, flags); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 965 | val = clk_readl(c->reg); |
| 966 | val &= ~PLLD_MISC_DIV_RST; |
| 967 | clk_writel(val, c->reg); |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 968 | spin_unlock_irqrestore(&clock_register_lock, flags); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 969 | return 0; |
| 970 | } |
| 971 | return -EINVAL; |
| 972 | } |
| 973 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 974 | static void tegra20_pll_div_clk_disable(struct clk_hw *hw) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 975 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 976 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 977 | unsigned long flags; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 978 | u32 new_val; |
| 979 | u32 val; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 980 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 981 | pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk)); |
| 982 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 983 | if (c->flags & DIV_U71) { |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 984 | spin_lock_irqsave(&clock_register_lock, flags); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 985 | val = clk_readl(c->reg); |
| 986 | new_val = val >> c->reg_shift; |
| 987 | new_val &= 0xFFFF; |
| 988 | |
| 989 | new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE); |
| 990 | |
| 991 | val &= ~(0xFFFF << c->reg_shift); |
| 992 | val |= new_val << c->reg_shift; |
| 993 | clk_writel(val, c->reg); |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 994 | spin_unlock_irqrestore(&clock_register_lock, flags); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 995 | } else if (c->flags & DIV_2) { |
| 996 | BUG_ON(!(c->flags & PLLD)); |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 997 | spin_lock_irqsave(&clock_register_lock, flags); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 998 | val = clk_readl(c->reg); |
| 999 | val |= PLLD_MISC_DIV_RST; |
| 1000 | clk_writel(val, c->reg); |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 1001 | spin_unlock_irqrestore(&clock_register_lock, flags); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1002 | } |
| 1003 | } |
| 1004 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1005 | static int tegra20_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
| 1006 | unsigned long parent_rate) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1007 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1008 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 1009 | unsigned long flags; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1010 | int divider_u71; |
| 1011 | u32 new_val; |
| 1012 | u32 val; |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 1013 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1014 | pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate); |
| 1015 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1016 | if (c->flags & DIV_U71) { |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 1017 | divider_u71 = clk_div71_get_divider(parent_rate, rate); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1018 | if (divider_u71 >= 0) { |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 1019 | spin_lock_irqsave(&clock_register_lock, flags); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1020 | val = clk_readl(c->reg); |
| 1021 | new_val = val >> c->reg_shift; |
| 1022 | new_val &= 0xFFFF; |
| 1023 | if (c->flags & DIV_U71_FIXED) |
| 1024 | new_val |= PLL_OUT_OVERRIDE; |
| 1025 | new_val &= ~PLL_OUT_RATIO_MASK; |
| 1026 | new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT; |
| 1027 | |
| 1028 | val &= ~(0xFFFF << c->reg_shift); |
| 1029 | val |= new_val << c->reg_shift; |
| 1030 | clk_writel(val, c->reg); |
| 1031 | c->div = divider_u71 + 2; |
| 1032 | c->mul = 2; |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 1033 | spin_unlock_irqrestore(&clock_register_lock, flags); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1034 | return 0; |
| 1035 | } |
| 1036 | } else if (c->flags & DIV_2) { |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 1037 | if (parent_rate == rate * 2) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1038 | return 0; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1039 | } |
| 1040 | return -EINVAL; |
| 1041 | } |
| 1042 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1043 | static long tegra20_pll_div_clk_round_rate(struct clk_hw *hw, unsigned long rate, |
| 1044 | unsigned long *prate) |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1045 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1046 | struct clk_tegra *c = to_clk_tegra(hw); |
| 1047 | unsigned long parent_rate = *prate; |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1048 | int divider; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1049 | |
| 1050 | pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1051 | |
| 1052 | if (c->flags & DIV_U71) { |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 1053 | divider = clk_div71_get_divider(parent_rate, rate); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1054 | if (divider < 0) |
| 1055 | return divider; |
Colin Cross | 421186e | 2011-02-12 18:21:47 -0800 | [diff] [blame] | 1056 | return DIV_ROUND_UP(parent_rate * 2, divider + 2); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1057 | } else if (c->flags & DIV_2) { |
Colin Cross | 421186e | 2011-02-12 18:21:47 -0800 | [diff] [blame] | 1058 | return DIV_ROUND_UP(parent_rate, 2); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1059 | } |
| 1060 | return -EINVAL; |
| 1061 | } |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1062 | |
Prashant Gaikwad | 86edb87 | 2012-08-06 11:57:40 +0530 | [diff] [blame] | 1063 | struct clk_ops tegra_pll_div_ops = { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1064 | .is_enabled = tegra20_pll_div_clk_is_enabled, |
| 1065 | .enable = tegra20_pll_div_clk_enable, |
| 1066 | .disable = tegra20_pll_div_clk_disable, |
| 1067 | .set_rate = tegra20_pll_div_clk_set_rate, |
| 1068 | .round_rate = tegra20_pll_div_clk_round_rate, |
| 1069 | .recalc_rate = tegra20_pll_div_clk_recalc_rate, |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1070 | }; |
| 1071 | |
| 1072 | /* Periph clk ops */ |
| 1073 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1074 | static int tegra20_periph_clk_is_enabled(struct clk_hw *hw) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1075 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1076 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1077 | |
| 1078 | c->state = ON; |
Colin Cross | 1be3d05 | 2011-02-21 16:44:07 -0800 | [diff] [blame] | 1079 | |
| 1080 | if (!c->u.periph.clk_num) |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1081 | goto out; |
Colin Cross | 1be3d05 | 2011-02-21 16:44:07 -0800 | [diff] [blame] | 1082 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1083 | if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & |
| 1084 | PERIPH_CLK_TO_ENB_BIT(c))) |
| 1085 | c->state = OFF; |
Colin Cross | 1be3d05 | 2011-02-21 16:44:07 -0800 | [diff] [blame] | 1086 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1087 | if (!(c->flags & PERIPH_NO_RESET)) |
| 1088 | if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) & |
| 1089 | PERIPH_CLK_TO_ENB_BIT(c)) |
| 1090 | c->state = OFF; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1091 | |
| 1092 | out: |
| 1093 | return c->state; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1094 | } |
| 1095 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1096 | static int tegra20_periph_clk_enable(struct clk_hw *hw) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1097 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1098 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | 78f379b | 2010-10-20 19:19:58 -0700 | [diff] [blame] | 1099 | unsigned long flags; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1100 | u32 val; |
| 1101 | |
| 1102 | pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1103 | |
Colin Cross | 1be3d05 | 2011-02-21 16:44:07 -0800 | [diff] [blame] | 1104 | if (!c->u.periph.clk_num) |
| 1105 | return 0; |
| 1106 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1107 | tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; |
| 1108 | if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) |
| 1109 | return 0; |
| 1110 | |
Colin Cross | 78f379b | 2010-10-20 19:19:58 -0700 | [diff] [blame] | 1111 | spin_lock_irqsave(&clock_register_lock, flags); |
| 1112 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1113 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), |
| 1114 | CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c)); |
| 1115 | if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) |
| 1116 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), |
| 1117 | RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); |
| 1118 | if (c->flags & PERIPH_EMC_ENB) { |
| 1119 | /* The EMC peripheral clock has 2 extra enable bits */ |
| 1120 | /* FIXME: Do they need to be disabled? */ |
| 1121 | val = clk_readl(c->reg); |
| 1122 | val |= 0x3 << 24; |
| 1123 | clk_writel(val, c->reg); |
| 1124 | } |
Colin Cross | 78f379b | 2010-10-20 19:19:58 -0700 | [diff] [blame] | 1125 | |
Colin Cross | 78f379b | 2010-10-20 19:19:58 -0700 | [diff] [blame] | 1126 | spin_unlock_irqrestore(&clock_register_lock, flags); |
| 1127 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1128 | return 0; |
| 1129 | } |
| 1130 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1131 | static void tegra20_periph_clk_disable(struct clk_hw *hw) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1132 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1133 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | 78f379b | 2010-10-20 19:19:58 -0700 | [diff] [blame] | 1134 | unsigned long flags; |
| 1135 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1136 | pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1137 | |
Colin Cross | 1be3d05 | 2011-02-21 16:44:07 -0800 | [diff] [blame] | 1138 | if (!c->u.periph.clk_num) |
| 1139 | return; |
| 1140 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1141 | tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--; |
| 1142 | |
| 1143 | if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0) |
| 1144 | return; |
| 1145 | |
Colin Cross | 78f379b | 2010-10-20 19:19:58 -0700 | [diff] [blame] | 1146 | spin_lock_irqsave(&clock_register_lock, flags); |
| 1147 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1148 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), |
| 1149 | CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); |
Colin Cross | 78f379b | 2010-10-20 19:19:58 -0700 | [diff] [blame] | 1150 | |
| 1151 | spin_unlock_irqrestore(&clock_register_lock, flags); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1152 | } |
| 1153 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1154 | void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1155 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1156 | struct clk_tegra *c = to_clk_tegra(hw); |
Dima Zavin | 2b84cb4f | 2010-09-02 19:11:11 -0700 | [diff] [blame] | 1157 | unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR; |
| 1158 | |
| 1159 | pr_debug("%s %s on clock %s\n", __func__, |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1160 | assert ? "assert" : "deassert", __clk_get_name(hw->clk)); |
Colin Cross | 1be3d05 | 2011-02-21 16:44:07 -0800 | [diff] [blame] | 1161 | |
| 1162 | BUG_ON(!c->u.periph.clk_num); |
| 1163 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1164 | if (!(c->flags & PERIPH_NO_RESET)) |
| 1165 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), |
Dima Zavin | 2b84cb4f | 2010-09-02 19:11:11 -0700 | [diff] [blame] | 1166 | base + PERIPH_CLK_TO_ENB_SET_REG(c)); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1167 | } |
| 1168 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1169 | static int tegra20_periph_clk_set_parent(struct clk_hw *hw, u8 index) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1170 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1171 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1172 | u32 val; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1173 | u32 mask; |
| 1174 | u32 shift; |
Simon Que | bb1dccf | 2011-12-16 20:11:22 +0100 | [diff] [blame] | 1175 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1176 | pr_debug("%s: %s %d\n", __func__, __clk_get_name(hw->clk), index); |
Simon Que | bb1dccf | 2011-12-16 20:11:22 +0100 | [diff] [blame] | 1177 | |
| 1178 | if (c->flags & MUX_PWM) { |
| 1179 | shift = PERIPH_CLK_SOURCE_PWM_SHIFT; |
| 1180 | mask = PERIPH_CLK_SOURCE_PWM_MASK; |
| 1181 | } else { |
| 1182 | shift = PERIPH_CLK_SOURCE_SHIFT; |
| 1183 | mask = PERIPH_CLK_SOURCE_MASK; |
| 1184 | } |
| 1185 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1186 | val = clk_readl(c->reg); |
| 1187 | val &= ~mask; |
| 1188 | val |= (index) << shift; |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1189 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1190 | clk_writel(val, c->reg); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1191 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1192 | return 0; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1193 | } |
| 1194 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1195 | static u8 tegra20_periph_clk_get_parent(struct clk_hw *hw) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1196 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1197 | struct clk_tegra *c = to_clk_tegra(hw); |
| 1198 | u32 val = clk_readl(c->reg); |
| 1199 | u32 mask; |
| 1200 | u32 shift; |
| 1201 | |
| 1202 | if (c->flags & MUX_PWM) { |
| 1203 | shift = PERIPH_CLK_SOURCE_PWM_SHIFT; |
| 1204 | mask = PERIPH_CLK_SOURCE_PWM_MASK; |
| 1205 | } else { |
| 1206 | shift = PERIPH_CLK_SOURCE_SHIFT; |
| 1207 | mask = PERIPH_CLK_SOURCE_MASK; |
| 1208 | } |
| 1209 | |
| 1210 | if (c->flags & MUX) |
| 1211 | return (val & mask) >> shift; |
| 1212 | else |
| 1213 | return 0; |
| 1214 | } |
| 1215 | |
| 1216 | static unsigned long tegra20_periph_clk_recalc_rate(struct clk_hw *hw, |
| 1217 | unsigned long prate) |
| 1218 | { |
| 1219 | struct clk_tegra *c = to_clk_tegra(hw); |
| 1220 | unsigned long rate = prate; |
| 1221 | u32 val = clk_readl(c->reg); |
| 1222 | |
| 1223 | if (c->flags & DIV_U71) { |
| 1224 | u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK; |
| 1225 | c->div = divu71 + 2; |
| 1226 | c->mul = 2; |
| 1227 | } else if (c->flags & DIV_U16) { |
| 1228 | u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK; |
| 1229 | c->div = divu16 + 1; |
| 1230 | c->mul = 1; |
| 1231 | } else { |
| 1232 | c->div = 1; |
| 1233 | c->mul = 1; |
| 1234 | return rate; |
| 1235 | } |
| 1236 | |
| 1237 | if (c->mul != 0 && c->div != 0) { |
| 1238 | rate *= c->mul; |
| 1239 | rate += c->div - 1; /* round up */ |
| 1240 | do_div(rate, c->div); |
| 1241 | } |
| 1242 | |
| 1243 | return rate; |
| 1244 | } |
| 1245 | |
| 1246 | static int tegra20_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
| 1247 | unsigned long parent_rate) |
| 1248 | { |
| 1249 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1250 | u32 val; |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1251 | int divider; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1252 | |
| 1253 | val = clk_readl(c->reg); |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 1254 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1255 | if (c->flags & DIV_U71) { |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 1256 | divider = clk_div71_get_divider(parent_rate, rate); |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1257 | |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1258 | if (divider >= 0) { |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1259 | val = clk_readl(c->reg); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1260 | val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK; |
| 1261 | val |= divider; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1262 | clk_writel(val, c->reg); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1263 | c->div = divider + 2; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1264 | c->mul = 2; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1265 | return 0; |
| 1266 | } |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1267 | } else if (c->flags & DIV_U16) { |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 1268 | divider = clk_div16_get_divider(parent_rate, rate); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1269 | if (divider >= 0) { |
| 1270 | val = clk_readl(c->reg); |
| 1271 | val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; |
| 1272 | val |= divider; |
| 1273 | clk_writel(val, c->reg); |
| 1274 | c->div = divider + 1; |
| 1275 | c->mul = 1; |
| 1276 | return 0; |
| 1277 | } |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 1278 | } else if (parent_rate <= rate) { |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1279 | c->div = 1; |
| 1280 | c->mul = 1; |
| 1281 | return 0; |
| 1282 | } |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1283 | |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1284 | return -EINVAL; |
| 1285 | } |
| 1286 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1287 | static long tegra20_periph_clk_round_rate(struct clk_hw *hw, |
| 1288 | unsigned long rate, unsigned long *prate) |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1289 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1290 | struct clk_tegra *c = to_clk_tegra(hw); |
| 1291 | unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk)); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1292 | int divider; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1293 | |
| 1294 | pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate); |
| 1295 | |
| 1296 | if (prate) |
| 1297 | parent_rate = *prate; |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1298 | |
| 1299 | if (c->flags & DIV_U71) { |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 1300 | divider = clk_div71_get_divider(parent_rate, rate); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1301 | if (divider < 0) |
| 1302 | return divider; |
| 1303 | |
Colin Cross | 421186e | 2011-02-12 18:21:47 -0800 | [diff] [blame] | 1304 | return DIV_ROUND_UP(parent_rate * 2, divider + 2); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1305 | } else if (c->flags & DIV_U16) { |
Colin Cross | 4729fd7 | 2011-02-12 16:43:05 -0800 | [diff] [blame] | 1306 | divider = clk_div16_get_divider(parent_rate, rate); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1307 | if (divider < 0) |
| 1308 | return divider; |
Colin Cross | 421186e | 2011-02-12 18:21:47 -0800 | [diff] [blame] | 1309 | return DIV_ROUND_UP(parent_rate, divider + 1); |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1310 | } |
| 1311 | return -EINVAL; |
| 1312 | } |
| 1313 | |
Prashant Gaikwad | 86edb87 | 2012-08-06 11:57:40 +0530 | [diff] [blame] | 1314 | struct clk_ops tegra_periph_clk_ops = { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1315 | .is_enabled = tegra20_periph_clk_is_enabled, |
| 1316 | .enable = tegra20_periph_clk_enable, |
| 1317 | .disable = tegra20_periph_clk_disable, |
| 1318 | .set_parent = tegra20_periph_clk_set_parent, |
| 1319 | .get_parent = tegra20_periph_clk_get_parent, |
| 1320 | .set_rate = tegra20_periph_clk_set_rate, |
| 1321 | .round_rate = tegra20_periph_clk_round_rate, |
| 1322 | .recalc_rate = tegra20_periph_clk_recalc_rate, |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1323 | }; |
| 1324 | |
Colin Cross | 6d29682 | 2010-11-22 18:37:54 -0800 | [diff] [blame] | 1325 | /* External memory controller clock ops */ |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1326 | static void tegra20_emc_clk_init(struct clk_hw *hw) |
Colin Cross | 6d29682 | 2010-11-22 18:37:54 -0800 | [diff] [blame] | 1327 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1328 | struct clk_tegra *c = to_clk_tegra(hw); |
| 1329 | c->max_rate = __clk_get_rate(hw->clk); |
Colin Cross | 6d29682 | 2010-11-22 18:37:54 -0800 | [diff] [blame] | 1330 | } |
| 1331 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1332 | static long tegra20_emc_clk_round_rate(struct clk_hw *hw, unsigned long rate, |
| 1333 | unsigned long *prate) |
Colin Cross | 6d29682 | 2010-11-22 18:37:54 -0800 | [diff] [blame] | 1334 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1335 | struct clk_tegra *c = to_clk_tegra(hw); |
Stephen Warren | e186ad7 | 2012-02-06 17:09:15 -0800 | [diff] [blame] | 1336 | long emc_rate; |
| 1337 | long clk_rate; |
Colin Cross | 6d29682 | 2010-11-22 18:37:54 -0800 | [diff] [blame] | 1338 | |
Stephen Warren | e186ad7 | 2012-02-06 17:09:15 -0800 | [diff] [blame] | 1339 | /* |
| 1340 | * The slowest entry in the EMC clock table that is at least as |
| 1341 | * fast as rate. |
| 1342 | */ |
| 1343 | emc_rate = tegra_emc_round_rate(rate); |
| 1344 | if (emc_rate < 0) |
Colin Cross | 6d29682 | 2010-11-22 18:37:54 -0800 | [diff] [blame] | 1345 | return c->max_rate; |
| 1346 | |
Stephen Warren | e186ad7 | 2012-02-06 17:09:15 -0800 | [diff] [blame] | 1347 | /* |
| 1348 | * The fastest rate the PLL will generate that is at most the |
| 1349 | * requested rate. |
| 1350 | */ |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1351 | clk_rate = tegra20_periph_clk_round_rate(hw, emc_rate, NULL); |
Colin Cross | 6d29682 | 2010-11-22 18:37:54 -0800 | [diff] [blame] | 1352 | |
Stephen Warren | e186ad7 | 2012-02-06 17:09:15 -0800 | [diff] [blame] | 1353 | /* |
| 1354 | * If this fails, and emc_rate > clk_rate, it's because the maximum |
| 1355 | * rate in the EMC tables is larger than the maximum rate of the EMC |
| 1356 | * clock. The EMC clock's max rate is the rate it was running when the |
| 1357 | * kernel booted. Such a mismatch is probably due to using the wrong |
| 1358 | * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25. |
| 1359 | */ |
| 1360 | WARN_ONCE(emc_rate != clk_rate, |
| 1361 | "emc_rate %ld != clk_rate %ld", |
| 1362 | emc_rate, clk_rate); |
| 1363 | |
| 1364 | return emc_rate; |
Colin Cross | 6d29682 | 2010-11-22 18:37:54 -0800 | [diff] [blame] | 1365 | } |
| 1366 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1367 | static int tegra20_emc_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
| 1368 | unsigned long parent_rate) |
Colin Cross | 6d29682 | 2010-11-22 18:37:54 -0800 | [diff] [blame] | 1369 | { |
| 1370 | int ret; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1371 | |
Colin Cross | 6d29682 | 2010-11-22 18:37:54 -0800 | [diff] [blame] | 1372 | /* |
| 1373 | * The Tegra2 memory controller has an interlock with the clock |
| 1374 | * block that allows memory shadowed registers to be updated, |
| 1375 | * and then transfer them to the main registers at the same |
| 1376 | * time as the clock update without glitches. |
| 1377 | */ |
| 1378 | ret = tegra_emc_set_rate(rate); |
| 1379 | if (ret < 0) |
| 1380 | return ret; |
| 1381 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1382 | ret = tegra20_periph_clk_set_rate(hw, rate, parent_rate); |
Colin Cross | 6d29682 | 2010-11-22 18:37:54 -0800 | [diff] [blame] | 1383 | udelay(1); |
| 1384 | |
| 1385 | return ret; |
| 1386 | } |
| 1387 | |
Prashant Gaikwad | 86edb87 | 2012-08-06 11:57:40 +0530 | [diff] [blame] | 1388 | struct clk_ops tegra_emc_clk_ops = { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1389 | .init = tegra20_emc_clk_init, |
| 1390 | .is_enabled = tegra20_periph_clk_is_enabled, |
| 1391 | .enable = tegra20_periph_clk_enable, |
| 1392 | .disable = tegra20_periph_clk_disable, |
| 1393 | .set_parent = tegra20_periph_clk_set_parent, |
| 1394 | .get_parent = tegra20_periph_clk_get_parent, |
| 1395 | .set_rate = tegra20_emc_clk_set_rate, |
| 1396 | .round_rate = tegra20_emc_clk_round_rate, |
| 1397 | .recalc_rate = tegra20_periph_clk_recalc_rate, |
Colin Cross | 6d29682 | 2010-11-22 18:37:54 -0800 | [diff] [blame] | 1398 | }; |
| 1399 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1400 | /* Clock doubler ops */ |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1401 | static int tegra20_clk_double_is_enabled(struct clk_hw *hw) |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1402 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1403 | struct clk_tegra *c = to_clk_tegra(hw); |
| 1404 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1405 | c->state = ON; |
Colin Cross | 1be3d05 | 2011-02-21 16:44:07 -0800 | [diff] [blame] | 1406 | |
| 1407 | if (!c->u.periph.clk_num) |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1408 | goto out; |
Colin Cross | 1be3d05 | 2011-02-21 16:44:07 -0800 | [diff] [blame] | 1409 | |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1410 | if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & |
| 1411 | PERIPH_CLK_TO_ENB_BIT(c))) |
| 1412 | c->state = OFF; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1413 | |
| 1414 | out: |
| 1415 | return c->state; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1416 | }; |
| 1417 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1418 | static unsigned long tegra20_clk_double_recalc_rate(struct clk_hw *hw, |
| 1419 | unsigned long prate) |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1420 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1421 | struct clk_tegra *c = to_clk_tegra(hw); |
| 1422 | u64 rate = prate; |
| 1423 | |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1424 | c->mul = 2; |
| 1425 | c->div = 1; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1426 | |
| 1427 | rate *= c->mul; |
| 1428 | rate += c->div - 1; /* round up */ |
| 1429 | do_div(rate, c->div); |
| 1430 | |
| 1431 | return rate; |
| 1432 | } |
| 1433 | |
| 1434 | static long tegra20_clk_double_round_rate(struct clk_hw *hw, unsigned long rate, |
| 1435 | unsigned long *prate) |
| 1436 | { |
| 1437 | unsigned long output_rate = *prate; |
| 1438 | |
| 1439 | do_div(output_rate, 2); |
| 1440 | return output_rate; |
| 1441 | } |
| 1442 | |
| 1443 | static int tegra20_clk_double_set_rate(struct clk_hw *hw, unsigned long rate, |
| 1444 | unsigned long parent_rate) |
| 1445 | { |
| 1446 | if (rate != 2 * parent_rate) |
| 1447 | return -EINVAL; |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1448 | return 0; |
| 1449 | } |
| 1450 | |
Prashant Gaikwad | 86edb87 | 2012-08-06 11:57:40 +0530 | [diff] [blame] | 1451 | struct clk_ops tegra_clk_double_ops = { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1452 | .is_enabled = tegra20_clk_double_is_enabled, |
| 1453 | .enable = tegra20_periph_clk_enable, |
| 1454 | .disable = tegra20_periph_clk_disable, |
| 1455 | .set_rate = tegra20_clk_double_set_rate, |
| 1456 | .recalc_rate = tegra20_clk_double_recalc_rate, |
| 1457 | .round_rate = tegra20_clk_double_round_rate, |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1458 | }; |
| 1459 | |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 1460 | /* Audio sync clock ops */ |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1461 | static int tegra20_audio_sync_clk_is_enabled(struct clk_hw *hw) |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1462 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1463 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1464 | u32 val = clk_readl(c->reg); |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1465 | |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1466 | c->state = (val & (1<<4)) ? OFF : ON; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1467 | return c->state; |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1468 | } |
| 1469 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1470 | static int tegra20_audio_sync_clk_enable(struct clk_hw *hw) |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1471 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1472 | struct clk_tegra *c = to_clk_tegra(hw); |
| 1473 | |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1474 | clk_writel(0, c->reg); |
| 1475 | return 0; |
| 1476 | } |
| 1477 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1478 | static void tegra20_audio_sync_clk_disable(struct clk_hw *hw) |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1479 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1480 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1481 | clk_writel(1, c->reg); |
| 1482 | } |
| 1483 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1484 | static u8 tegra20_audio_sync_clk_get_parent(struct clk_hw *hw) |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1485 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1486 | struct clk_tegra *c = to_clk_tegra(hw); |
| 1487 | u32 val = clk_readl(c->reg); |
| 1488 | int source; |
| 1489 | |
| 1490 | source = val & 0xf; |
| 1491 | return source; |
| 1492 | } |
| 1493 | |
| 1494 | static int tegra20_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index) |
| 1495 | { |
| 1496 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1497 | u32 val; |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1498 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1499 | val = clk_readl(c->reg); |
| 1500 | val &= ~0xf; |
| 1501 | val |= index; |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1502 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1503 | clk_writel(val, c->reg); |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1504 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1505 | return 0; |
Colin Cross | 71fc84c | 2010-06-07 20:49:46 -0700 | [diff] [blame] | 1506 | } |
| 1507 | |
Prashant Gaikwad | 86edb87 | 2012-08-06 11:57:40 +0530 | [diff] [blame] | 1508 | struct clk_ops tegra_audio_sync_clk_ops = { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1509 | .is_enabled = tegra20_audio_sync_clk_is_enabled, |
| 1510 | .enable = tegra20_audio_sync_clk_enable, |
| 1511 | .disable = tegra20_audio_sync_clk_disable, |
| 1512 | .set_parent = tegra20_audio_sync_clk_set_parent, |
| 1513 | .get_parent = tegra20_audio_sync_clk_get_parent, |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 1514 | }; |
| 1515 | |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 1516 | /* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */ |
| 1517 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1518 | static int tegra20_cdev_clk_is_enabled(struct clk_hw *hw) |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 1519 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1520 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 1521 | /* We could un-tristate the cdev1 or cdev2 pingroup here; this is |
| 1522 | * currently done in the pinmux code. */ |
| 1523 | c->state = ON; |
Colin Cross | 1be3d05 | 2011-02-21 16:44:07 -0800 | [diff] [blame] | 1524 | |
| 1525 | BUG_ON(!c->u.periph.clk_num); |
| 1526 | |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 1527 | if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & |
| 1528 | PERIPH_CLK_TO_ENB_BIT(c))) |
| 1529 | c->state = OFF; |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1530 | return c->state; |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 1531 | } |
| 1532 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1533 | static int tegra20_cdev_clk_enable(struct clk_hw *hw) |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 1534 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1535 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | 1be3d05 | 2011-02-21 16:44:07 -0800 | [diff] [blame] | 1536 | BUG_ON(!c->u.periph.clk_num); |
| 1537 | |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 1538 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), |
| 1539 | CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c)); |
| 1540 | return 0; |
| 1541 | } |
| 1542 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1543 | static void tegra20_cdev_clk_disable(struct clk_hw *hw) |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 1544 | { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1545 | struct clk_tegra *c = to_clk_tegra(hw); |
Colin Cross | 1be3d05 | 2011-02-21 16:44:07 -0800 | [diff] [blame] | 1546 | BUG_ON(!c->u.periph.clk_num); |
| 1547 | |
Colin Cross | cea62c8 | 2010-10-04 11:49:26 -0700 | [diff] [blame] | 1548 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), |
| 1549 | CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); |
| 1550 | } |
| 1551 | |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1552 | static unsigned long tegra20_cdev_recalc_rate(struct clk_hw *hw, |
| 1553 | unsigned long prate) |
| 1554 | { |
| 1555 | return to_clk_tegra(hw)->fixed_rate; |
| 1556 | } |
| 1557 | |
Prashant Gaikwad | 86edb87 | 2012-08-06 11:57:40 +0530 | [diff] [blame] | 1558 | struct clk_ops tegra_cdev_clk_ops = { |
Prashant Gaikwad | 92fe58f | 2012-08-06 11:57:43 +0530 | [diff] [blame] | 1559 | .is_enabled = tegra20_cdev_clk_is_enabled, |
| 1560 | .enable = tegra20_cdev_clk_enable, |
| 1561 | .disable = tegra20_cdev_clk_disable, |
| 1562 | .recalc_rate = tegra20_cdev_recalc_rate, |
Colin Cross | 310992c | 2011-02-12 16:14:03 -0800 | [diff] [blame] | 1563 | }; |
Joseph Lo | dab403e | 2012-08-16 17:31:48 +0800 | [diff] [blame] | 1564 | |
| 1565 | /* Tegra20 CPU clock and reset control functions */ |
| 1566 | static void tegra20_wait_cpu_in_reset(u32 cpu) |
| 1567 | { |
| 1568 | unsigned int reg; |
| 1569 | |
| 1570 | do { |
| 1571 | reg = readl(reg_clk_base + |
| 1572 | TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); |
| 1573 | cpu_relax(); |
| 1574 | } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ |
| 1575 | |
| 1576 | return; |
| 1577 | } |
| 1578 | |
| 1579 | static void tegra20_put_cpu_in_reset(u32 cpu) |
| 1580 | { |
| 1581 | writel(CPU_RESET(cpu), |
| 1582 | reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); |
| 1583 | dmb(); |
| 1584 | } |
| 1585 | |
| 1586 | static void tegra20_cpu_out_of_reset(u32 cpu) |
| 1587 | { |
| 1588 | writel(CPU_RESET(cpu), |
| 1589 | reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); |
| 1590 | wmb(); |
| 1591 | } |
| 1592 | |
| 1593 | static void tegra20_enable_cpu_clock(u32 cpu) |
| 1594 | { |
| 1595 | unsigned int reg; |
| 1596 | |
| 1597 | reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); |
| 1598 | writel(reg & ~CPU_CLOCK(cpu), |
| 1599 | reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); |
| 1600 | barrier(); |
| 1601 | reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); |
| 1602 | } |
| 1603 | |
| 1604 | static void tegra20_disable_cpu_clock(u32 cpu) |
| 1605 | { |
| 1606 | unsigned int reg; |
| 1607 | |
| 1608 | reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); |
| 1609 | writel(reg | CPU_CLOCK(cpu), |
| 1610 | reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); |
| 1611 | } |
| 1612 | |
| 1613 | static struct tegra_cpu_car_ops tegra20_cpu_car_ops = { |
| 1614 | .wait_for_reset = tegra20_wait_cpu_in_reset, |
| 1615 | .put_in_reset = tegra20_put_cpu_in_reset, |
| 1616 | .out_of_reset = tegra20_cpu_out_of_reset, |
| 1617 | .enable_clock = tegra20_enable_cpu_clock, |
| 1618 | .disable_clock = tegra20_disable_cpu_clock, |
| 1619 | }; |
| 1620 | |
| 1621 | void __init tegra20_cpu_car_ops_init(void) |
| 1622 | { |
| 1623 | tegra_cpu_car_ops = &tegra20_cpu_car_ops; |
| 1624 | } |