David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | /* |
| 13 | * Qualcomm Technologies, Inc. QPNP Pulse Width Modulation (PWM) driver |
| 14 | * |
| 15 | * The HW module is also called LPG (Light Pattern Generator). |
| 16 | */ |
| 17 | |
| 18 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 19 | |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/slab.h> |
| 22 | #include <linux/err.h> |
| 23 | #include <linux/spmi.h> |
| 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/regmap.h> |
| 26 | #include <linux/of.h> |
| 27 | #include <linux/of_device.h> |
| 28 | #include <linux/of_address.h> |
| 29 | #include <linux/radix-tree.h> |
| 30 | #include <linux/qpnp/pwm.h> |
| 31 | |
| 32 | #define QPNP_LPG_DRIVER_NAME "qcom,qpnp-pwm" |
| 33 | #define QPNP_LPG_CHANNEL_BASE "qpnp-lpg-channel-base" |
| 34 | #define QPNP_LPG_LUT_BASE "qpnp-lpg-lut-base" |
| 35 | |
| 36 | #define QPNP_PWM_MODE_ONLY_SUB_TYPE 0x0B |
| 37 | #define QPNP_LPG_CHAN_SUB_TYPE 0x2 |
| 38 | #define QPNP_LPG_S_CHAN_SUB_TYPE 0x11 |
| 39 | |
| 40 | /* LPG Control for LPG_PATTERN_CONFIG */ |
| 41 | #define QPNP_RAMP_DIRECTION_SHIFT 4 |
| 42 | #define QPNP_RAMP_DIRECTION_MASK 0x10 |
| 43 | #define QPNP_PATTERN_REPEAT_SHIFT 3 |
| 44 | #define QPNP_PATTERN_REPEAT_MASK 0x08 |
| 45 | #define QPNP_RAMP_TOGGLE_SHIFT 2 |
| 46 | #define QPNP_RAMP_TOGGLE_MASK 0x04 |
| 47 | #define QPNP_EN_PAUSE_HI_SHIFT 1 |
| 48 | #define QPNP_EN_PAUSE_HI_MASK 0x02 |
| 49 | #define QPNP_EN_PAUSE_LO_MASK 0x01 |
| 50 | |
| 51 | /* LPG Control for LPG_PWM_SIZE_CLK */ |
| 52 | #define QPNP_PWM_SIZE_SHIFT_SUB_TYPE 2 |
| 53 | #define QPNP_PWM_SIZE_MASK_SUB_TYPE 0x4 |
| 54 | #define QPNP_PWM_FREQ_CLK_SELECT_MASK_SUB_TYPE 0x03 |
| 55 | #define QPNP_PWM_SIZE_9_BIT_SUB_TYPE 0x01 |
| 56 | |
| 57 | #define QPNP_SET_PWM_CLK_SUB_TYPE(val, clk, pwm_size) \ |
| 58 | do { \ |
| 59 | val = (clk + 1) & QPNP_PWM_FREQ_CLK_SELECT_MASK_SUB_TYPE; \ |
| 60 | val |= (((pwm_size > 6 ? QPNP_PWM_SIZE_9_BIT_SUB_TYPE : 0) << \ |
| 61 | QPNP_PWM_SIZE_SHIFT_SUB_TYPE) & QPNP_PWM_SIZE_MASK_SUB_TYPE); \ |
| 62 | } while (0) |
| 63 | |
| 64 | #define QPNP_GET_PWM_SIZE_SUB_TYPE(reg) ((reg & QPNP_PWM_SIZE_MASK_SUB_TYPE) \ |
| 65 | >> QPNP_PWM_SIZE_SHIFT_SUB_TYPE) |
| 66 | |
| 67 | #define QPNP_PWM_SIZE_SHIFT 4 |
| 68 | #define QPNP_PWM_SIZE_MASK 0x30 |
| 69 | #define QPNP_PWM_FREQ_CLK_SELECT_MASK 0x03 |
| 70 | #define QPNP_MIN_PWM_BIT_SIZE 6 |
| 71 | #define QPNP_MAX_PWM_BIT_SIZE 9 |
| 72 | #define QPNP_PWM_SIZES_SUPPORTED 10 |
| 73 | |
| 74 | #define QPNP_SET_PWM_CLK(val, clk, pwm_size) \ |
| 75 | do { \ |
| 76 | val = (clk + 1) & QPNP_PWM_FREQ_CLK_SELECT_MASK; \ |
| 77 | val |= (((pwm_size - QPNP_MIN_PWM_BIT_SIZE) << \ |
| 78 | QPNP_PWM_SIZE_SHIFT) & QPNP_PWM_SIZE_MASK); \ |
| 79 | } while (0) |
| 80 | |
| 81 | #define QPNP_GET_PWM_SIZE(reg) ((reg & QPNP_PWM_SIZE_MASK) \ |
| 82 | >> QPNP_PWM_SIZE_SHIFT) |
| 83 | |
| 84 | /* LPG Control for LPG_PWM_FREQ_PREDIV_CLK */ |
| 85 | #define QPNP_PWM_FREQ_PRE_DIVIDE_SHIFT 5 |
| 86 | #define QPNP_PWM_FREQ_PRE_DIVIDE_MASK 0x60 |
| 87 | #define QPNP_PWM_FREQ_EXP_MASK 0x07 |
| 88 | |
| 89 | #define QPNP_SET_PWM_FREQ_PREDIV(val, pre_div, pre_div_exp) \ |
| 90 | do { \ |
| 91 | val = (pre_div << QPNP_PWM_FREQ_PRE_DIVIDE_SHIFT) & \ |
| 92 | QPNP_PWM_FREQ_PRE_DIVIDE_MASK; \ |
| 93 | val |= (pre_div_exp & QPNP_PWM_FREQ_EXP_MASK); \ |
| 94 | } while (0) |
| 95 | |
| 96 | /* LPG Control for LPG_PWM_TYPE_CONFIG */ |
| 97 | #define QPNP_EN_GLITCH_REMOVAL_SHIFT 5 |
| 98 | #define QPNP_EN_GLITCH_REMOVAL_MASK 0x20 |
| 99 | #define QPNP_EN_FULL_SCALE_SHIFT 3 |
| 100 | #define QPNP_EN_FULL_SCALE_MASK 0x08 |
| 101 | #define QPNP_EN_PHASE_STAGGER_SHIFT 2 |
| 102 | #define QPNP_EN_PHASE_STAGGER_MASK 0x04 |
| 103 | #define QPNP_PHASE_STAGGER_MASK 0x03 |
| 104 | |
| 105 | /* LPG Control for PWM_VALUE_LSB */ |
| 106 | #define QPNP_PWM_VALUE_LSB_MASK 0xFF |
| 107 | |
| 108 | /* LPG Control for PWM_VALUE_MSB */ |
| 109 | #define QPNP_PWM_VALUE_MSB_SHIFT 8 |
| 110 | #define QPNP_PWM_VALUE_MSB_MASK 0x01 |
| 111 | |
| 112 | /* LPG Control for ENABLE_CONTROL */ |
| 113 | #define QPNP_EN_PWM_HIGH_SHIFT 7 |
| 114 | #define QPNP_EN_PWM_HIGH_MASK 0x80 |
| 115 | #define QPNP_EN_PWM_LO_SHIFT 6 |
| 116 | #define QPNP_EN_PWM_LO_MASK 0x40 |
| 117 | #define QPNP_EN_PWM_OUTPUT_SHIFT 5 |
| 118 | #define QPNP_EN_PWM_OUTPUT_MASK 0x20 |
| 119 | #define QPNP_PWM_SRC_SELECT_SHIFT 2 |
| 120 | #define QPNP_PWM_SRC_SELECT_MASK 0x04 |
| 121 | #define QPNP_PWM_EN_RAMP_GEN_SHIFT 1 |
| 122 | #define QPNP_PWM_EN_RAMP_GEN_MASK 0x02 |
| 123 | |
| 124 | /* LPG Control for PWM_SYNC */ |
| 125 | #define QPNP_PWM_SYNC_VALUE 0x01 |
| 126 | #define QPNP_PWM_SYNC_MASK 0x01 |
| 127 | |
| 128 | /* LPG Control for RAMP_CONTROL */ |
| 129 | #define QPNP_RAMP_START_MASK 0x01 |
| 130 | |
| 131 | #define QPNP_ENABLE_LUT_V0(value) (value |= QPNP_RAMP_START_MASK) |
| 132 | #define QPNP_DISABLE_LUT_V0(value) (value &= ~QPNP_RAMP_START_MASK) |
| 133 | #define QPNP_ENABLE_LUT_V1(value, id) (value |= BIT(id)) |
| 134 | |
| 135 | /* LPG Control for RAMP_STEP_DURATION_LSB */ |
| 136 | #define QPNP_RAMP_STEP_DURATION_LSB_MASK 0xFF |
| 137 | |
| 138 | /* LPG Control for RAMP_STEP_DURATION_MSB */ |
| 139 | #define QPNP_RAMP_STEP_DURATION_MSB_SHIFT 8 |
| 140 | #define QPNP_RAMP_STEP_DURATION_MSB_MASK 0x01 |
| 141 | |
| 142 | #define QPNP_PWM_1KHZ 1024 |
| 143 | #define QPNP_GET_RAMP_STEP_DURATION(ramp_time_ms) \ |
| 144 | ((ramp_time_ms * QPNP_PWM_1KHZ) / 1000) |
| 145 | |
| 146 | /* LPG Control for PAUSE_HI_MULTIPLIER_LSB */ |
| 147 | #define QPNP_PAUSE_HI_MULTIPLIER_LSB_MASK 0xFF |
| 148 | |
| 149 | /* LPG Control for PAUSE_HI_MULTIPLIER_MSB */ |
| 150 | #define QPNP_PAUSE_HI_MULTIPLIER_MSB_SHIFT 8 |
| 151 | #define QPNP_PAUSE_HI_MULTIPLIER_MSB_MASK 0x1F |
| 152 | |
| 153 | /* LPG Control for PAUSE_LO_MULTIPLIER_LSB */ |
| 154 | #define QPNP_PAUSE_LO_MULTIPLIER_LSB_MASK 0xFF |
| 155 | |
| 156 | /* LPG Control for PAUSE_LO_MULTIPLIER_MSB */ |
| 157 | #define QPNP_PAUSE_LO_MULTIPLIER_MSB_SHIFT 8 |
| 158 | #define QPNP_PAUSE_LO_MULTIPLIER_MSB_MASK 0x1F |
| 159 | |
| 160 | /* LPG Control for HI_INDEX */ |
| 161 | #define QPNP_HI_INDEX_MASK 0x3F |
| 162 | |
| 163 | /* LPG Control for LO_INDEX */ |
| 164 | #define QPNP_LO_INDEX_MASK 0x3F |
| 165 | |
| 166 | /* LPG DTEST */ |
| 167 | #define QPNP_LPG_DTEST_LINE_MAX 4 |
| 168 | #define QPNP_LPG_DTEST_OUTPUT_MAX 5 |
| 169 | #define QPNP_LPG_DTEST_OUTPUT_MASK 0x07 |
| 170 | |
| 171 | /* PWM DTEST */ |
| 172 | #define QPNP_PWM_DTEST_LINE_MAX 2 |
| 173 | #define QPNP_PWM_DTEST_OUTPUT_MAX 2 |
| 174 | #define QPNP_PWM_DTEST_OUTPUT_MASK 0x03 |
| 175 | |
| 176 | #define NUM_CLOCKS 3 |
| 177 | #define QPNP_PWM_M_MAX 7 |
| 178 | #define NSEC_1024HZ (NSEC_PER_SEC / 1024) |
| 179 | #define NSEC_32768HZ (NSEC_PER_SEC / 32768) |
| 180 | #define NSEC_19P2MHZ (NSEC_PER_SEC / 19200000) |
| 181 | |
| 182 | #define NUM_LPG_PRE_DIVIDE 4 |
| 183 | |
| 184 | #define PRE_DIVIDE_1 1 |
| 185 | #define PRE_DIVIDE_3 3 |
| 186 | #define PRE_DIVIDE_5 5 |
| 187 | #define PRE_DIVIDE_6 6 |
| 188 | |
| 189 | #define SPMI_LPG_REG_BASE_OFFSET 0x40 |
| 190 | #define SPMI_LPG_REVISION2_OFFSET 0x1 |
| 191 | #define SPMI_LPG_REV1_RAMP_CONTROL_OFFSET 0x86 |
| 192 | #define SPMI_LPG_SUB_TYPE_OFFSET 0x5 |
| 193 | #define SPMI_LPG_PWM_SYNC 0x7 |
| 194 | #define SPMI_LPG_REG_ADDR(b, n) (b + SPMI_LPG_REG_BASE_OFFSET + (n)) |
| 195 | #define SPMI_MAX_BUF_LEN 8 |
| 196 | |
| 197 | #define QPNP_PWM_LUT_NOT_SUPPORTED 0x1 |
| 198 | |
| 199 | /* Supported PWM sizes */ |
| 200 | #define QPNP_PWM_SIZE_6_BIT 6 |
| 201 | #define QPNP_PWM_SIZE_7_BIT 7 |
| 202 | #define QPNP_PWM_SIZE_8_BIT 8 |
| 203 | #define QPNP_PWM_SIZE_9_BIT 9 |
| 204 | |
| 205 | #define QPNP_PWM_SIZE_6_9_BIT 0x9 |
| 206 | #define QPNP_PWM_SIZE_7_8_BIT 0x6 |
| 207 | #define QPNP_PWM_SIZE_6_7_9_BIT 0xB |
| 208 | |
| 209 | /* |
| 210 | * Registers that don't need to be cached are defined below from an offset |
| 211 | * of SPMI_LPG_REG_BASE_OFFSET. |
| 212 | */ |
| 213 | #define QPNP_LPG_SEC_ACCESS 0x90 |
| 214 | #define QPNP_LPG_DTEST 0xA2 |
| 215 | |
| 216 | /* Supported time levels */ |
| 217 | enum time_level { |
| 218 | LVL_NSEC, |
| 219 | LVL_USEC, |
| 220 | }; |
| 221 | |
| 222 | /* LPG revisions */ |
| 223 | enum qpnp_lpg_revision { |
| 224 | QPNP_LPG_REVISION_0 = 0x0, |
| 225 | QPNP_LPG_REVISION_1 = 0x1, |
| 226 | }; |
| 227 | |
| 228 | /* LPG LUT MODE STATE */ |
| 229 | enum qpnp_lut_state { |
| 230 | QPNP_LUT_ENABLE = 0x0, |
| 231 | QPNP_LUT_DISABLE = 0x1, |
| 232 | }; |
| 233 | |
| 234 | /* PWM MODE STATE */ |
| 235 | enum qpnp_pwm_state { |
| 236 | QPNP_PWM_ENABLE = 0x0, |
| 237 | QPNP_PWM_DISABLE = 0x1, |
| 238 | }; |
| 239 | |
| 240 | /* SPMI LPG registers */ |
| 241 | enum qpnp_lpg_registers_list { |
| 242 | QPNP_LPG_PATTERN_CONFIG, |
| 243 | QPNP_LPG_PWM_SIZE_CLK, |
| 244 | QPNP_LPG_PWM_FREQ_PREDIV_CLK, |
| 245 | QPNP_LPG_PWM_TYPE_CONFIG, |
| 246 | QPNP_PWM_VALUE_LSB, |
| 247 | QPNP_PWM_VALUE_MSB, |
| 248 | QPNP_ENABLE_CONTROL, |
| 249 | QPNP_RAMP_CONTROL, |
| 250 | QPNP_RAMP_STEP_DURATION_LSB = QPNP_RAMP_CONTROL + 9, |
| 251 | QPNP_RAMP_STEP_DURATION_MSB, |
| 252 | QPNP_PAUSE_HI_MULTIPLIER_LSB, |
| 253 | QPNP_PAUSE_HI_MULTIPLIER_MSB, |
| 254 | QPNP_PAUSE_LO_MULTIPLIER_LSB, |
| 255 | QPNP_PAUSE_LO_MULTIPLIER_MSB, |
| 256 | QPNP_HI_INDEX, |
| 257 | QPNP_LO_INDEX, |
| 258 | QPNP_TOTAL_LPG_SPMI_REGISTERS |
| 259 | }; |
| 260 | |
| 261 | /* |
| 262 | * Formula from HSID, |
| 263 | * pause_time (hi/lo) = (pause_cnt- 1)*(ramp_ms) |
| 264 | * OR, |
| 265 | * pause_cnt = (pause_time / ramp_ms) + 1 |
| 266 | */ |
| 267 | #define QPNP_SET_PAUSE_CNT(to_pause_cnt, from_pause, ramp_ms) \ |
| 268 | (to_pause_cnt = (from_pause / (ramp_ms ? ramp_ms : 1)) + 1) |
| 269 | |
| 270 | |
| 271 | static unsigned int pt_t[NUM_LPG_PRE_DIVIDE][NUM_CLOCKS] = { |
| 272 | { PRE_DIVIDE_1 * NSEC_1024HZ, |
| 273 | PRE_DIVIDE_1 * NSEC_32768HZ, |
| 274 | PRE_DIVIDE_1 * NSEC_19P2MHZ, |
| 275 | }, |
| 276 | { PRE_DIVIDE_3 * NSEC_1024HZ, |
| 277 | PRE_DIVIDE_3 * NSEC_32768HZ, |
| 278 | PRE_DIVIDE_3 * NSEC_19P2MHZ, |
| 279 | }, |
| 280 | { PRE_DIVIDE_5 * NSEC_1024HZ, |
| 281 | PRE_DIVIDE_5 * NSEC_32768HZ, |
| 282 | PRE_DIVIDE_5 * NSEC_19P2MHZ, |
| 283 | }, |
| 284 | { PRE_DIVIDE_6 * NSEC_1024HZ, |
| 285 | PRE_DIVIDE_6 * NSEC_32768HZ, |
| 286 | PRE_DIVIDE_6 * NSEC_19P2MHZ, |
| 287 | }, |
| 288 | }; |
| 289 | |
| 290 | struct qpnp_lut_config { |
| 291 | u8 *duty_pct_list; |
| 292 | int list_len; |
| 293 | int ramp_index; |
| 294 | int lo_index; |
| 295 | int hi_index; |
| 296 | int lut_pause_hi_cnt; |
| 297 | int lut_pause_lo_cnt; |
| 298 | int ramp_step_ms; |
| 299 | bool ramp_direction; |
| 300 | bool pattern_repeat; |
| 301 | bool ramp_toggle; |
| 302 | bool enable_pause_hi; |
| 303 | bool enable_pause_lo; |
| 304 | }; |
| 305 | |
| 306 | struct qpnp_lpg_config { |
| 307 | struct qpnp_lut_config lut_config; |
| 308 | u16 base_addr; |
| 309 | u16 lut_base_addr; |
| 310 | u16 lut_size; |
| 311 | }; |
| 312 | |
| 313 | struct _qpnp_pwm_config { |
| 314 | int pwm_value; |
| 315 | int pwm_period; /* in microseconds */ |
| 316 | int pwm_duty; /* in microseconds */ |
| 317 | struct pwm_period_config period; |
| 318 | int supported_sizes; |
| 319 | int force_pwm_size; |
| 320 | }; |
| 321 | |
| 322 | /* Public facing structure */ |
| 323 | struct qpnp_pwm_chip { |
| 324 | struct platform_device *pdev; |
| 325 | struct regmap *regmap; |
| 326 | struct pwm_chip chip; |
| 327 | bool enabled; |
| 328 | struct _qpnp_pwm_config pwm_config; |
| 329 | struct qpnp_lpg_config lpg_config; |
| 330 | spinlock_t lpg_lock; |
| 331 | enum qpnp_lpg_revision revision; |
| 332 | u8 sub_type; |
| 333 | u32 flags; |
| 334 | u8 qpnp_lpg_registers[QPNP_TOTAL_LPG_SPMI_REGISTERS]; |
| 335 | int channel_id; |
| 336 | const char *channel_owner; |
| 337 | u32 dtest_line; |
| 338 | u32 dtest_output; |
| 339 | bool in_test_mode; |
| 340 | }; |
| 341 | |
| 342 | /* Internal functions */ |
| 343 | static inline struct qpnp_pwm_chip *qpnp_pwm_from_pwm_dev( |
| 344 | struct pwm_device *pwm) |
| 345 | { |
| 346 | return container_of(pwm->chip, struct qpnp_pwm_chip, chip); |
| 347 | } |
| 348 | |
| 349 | static inline struct qpnp_pwm_chip *qpnp_pwm_from_pwm_chip( |
| 350 | struct pwm_chip *chip) |
| 351 | { |
| 352 | return container_of(chip, struct qpnp_pwm_chip, chip); |
| 353 | } |
| 354 | |
| 355 | static inline void qpnp_set_pattern_config(u8 *val, |
| 356 | struct qpnp_lut_config *lut_config) |
| 357 | { |
| 358 | *val = lut_config->enable_pause_lo & QPNP_EN_PAUSE_LO_MASK; |
| 359 | *val |= (lut_config->enable_pause_hi << QPNP_EN_PAUSE_HI_SHIFT) & |
| 360 | QPNP_EN_PAUSE_HI_MASK; |
| 361 | *val |= (lut_config->ramp_toggle << QPNP_RAMP_TOGGLE_SHIFT) & |
| 362 | QPNP_RAMP_TOGGLE_MASK; |
| 363 | *val |= (lut_config->pattern_repeat << QPNP_PATTERN_REPEAT_SHIFT) & |
| 364 | QPNP_PATTERN_REPEAT_MASK; |
| 365 | *val |= (lut_config->ramp_direction << QPNP_RAMP_DIRECTION_SHIFT) & |
| 366 | QPNP_RAMP_DIRECTION_MASK; |
| 367 | } |
| 368 | |
| 369 | static inline void qpnp_set_pwm_type_config(u8 *val, bool glitch, |
| 370 | bool full_scale, bool en_phase, bool phase) |
| 371 | { |
| 372 | *val = phase; |
| 373 | *val |= (en_phase << QPNP_EN_PHASE_STAGGER_SHIFT) & |
| 374 | QPNP_EN_PHASE_STAGGER_MASK; |
| 375 | *val |= (full_scale << QPNP_EN_FULL_SCALE_SHIFT) & |
| 376 | QPNP_EN_FULL_SCALE_MASK; |
| 377 | *val |= (glitch << QPNP_EN_GLITCH_REMOVAL_SHIFT) & |
| 378 | QPNP_EN_GLITCH_REMOVAL_MASK; |
| 379 | } |
| 380 | |
| 381 | static int qpnp_set_control(struct qpnp_pwm_chip *chip, bool pwm_hi, |
| 382 | bool pwm_lo, bool pwm_out, bool pwm_src, bool ramp_gen) |
| 383 | { |
| 384 | int value; |
| 385 | |
| 386 | value = (ramp_gen << QPNP_PWM_EN_RAMP_GEN_SHIFT) | |
| 387 | (pwm_src << QPNP_PWM_SRC_SELECT_SHIFT) | |
| 388 | (pwm_lo << QPNP_EN_PWM_LO_SHIFT) | |
| 389 | (pwm_hi << QPNP_EN_PWM_HIGH_SHIFT); |
| 390 | if (chip->sub_type != QPNP_LPG_S_CHAN_SUB_TYPE) |
| 391 | value |= (pwm_out << QPNP_EN_PWM_OUTPUT_SHIFT); |
| 392 | return value; |
| 393 | } |
| 394 | |
| 395 | #define QPNP_ENABLE_LUT_CONTROL(chip) \ |
| 396 | qpnp_set_control((chip), 0, 0, 0, 0, 1) |
| 397 | #define QPNP_ENABLE_PWM_CONTROL(chip) \ |
| 398 | qpnp_set_control((chip), 0, 0, 0, 1, 0) |
| 399 | #define QPNP_ENABLE_PWM_MODE(chip) \ |
| 400 | qpnp_set_control((chip), 1, 1, 1, 1, 0) |
| 401 | #define QPNP_ENABLE_PWM_MODE_GPLED_CHANNEL(chip) \ |
| 402 | qpnp_set_control((chip), 1, 1, 1, 1, 1) |
| 403 | #define QPNP_ENABLE_LPG_MODE(chip) \ |
| 404 | qpnp_set_control((chip), 1, 1, 1, 0, 1) |
| 405 | #define QPNP_DISABLE_PWM_MODE(chip) \ |
| 406 | qpnp_set_control((chip), 0, 0, 0, 1, 0) |
| 407 | #define QPNP_DISABLE_LPG_MODE(chip) \ |
| 408 | qpnp_set_control((chip), 0, 0, 0, 0, 1) |
| 409 | #define QPNP_IS_PWM_CONFIG_SELECTED(val) (val & QPNP_PWM_SRC_SELECT_MASK) |
| 410 | |
| 411 | #define QPNP_ENABLE_PWM_MODE_ONLY_SUB_TYPE 0x80 |
| 412 | #define QPNP_DISABLE_PWM_MODE_ONLY_SUB_TYPE 0x0 |
| 413 | #define QPNP_PWM_MODE_ONLY_ENABLE_DISABLE_MASK_SUB_TYPE 0x80 |
| 414 | |
| 415 | static inline void qpnp_convert_to_lut_flags(int *flags, |
| 416 | struct qpnp_lut_config *l_config) |
| 417 | { |
| 418 | *flags = ((l_config->ramp_direction ? PM_PWM_LUT_RAMP_UP : 0) | |
| 419 | (l_config->pattern_repeat ? PM_PWM_LUT_LOOP : 0)| |
| 420 | (l_config->ramp_toggle ? PM_PWM_LUT_REVERSE : 0) | |
| 421 | (l_config->enable_pause_hi ? PM_PWM_LUT_PAUSE_HI_EN : 0) | |
| 422 | (l_config->enable_pause_lo ? PM_PWM_LUT_PAUSE_LO_EN : 0)); |
| 423 | } |
| 424 | |
| 425 | static inline void qpnp_set_lut_params(struct lut_params *l_params, |
| 426 | struct qpnp_lut_config *l_config, int s_idx, int size) |
| 427 | { |
| 428 | l_params->start_idx = s_idx; |
| 429 | l_params->idx_len = size; |
| 430 | l_params->lut_pause_hi = l_config->lut_pause_hi_cnt; |
| 431 | l_params->lut_pause_lo = l_config->lut_pause_lo_cnt; |
| 432 | l_params->ramp_step_ms = l_config->ramp_step_ms; |
| 433 | qpnp_convert_to_lut_flags(&l_params->flags, l_config); |
| 434 | } |
| 435 | |
| 436 | static void qpnp_lpg_save(u8 *u8p, u8 mask, u8 val) |
| 437 | { |
| 438 | *u8p &= ~mask; |
| 439 | *u8p |= val & mask; |
| 440 | } |
| 441 | |
| 442 | static int qpnp_lpg_save_and_write(u8 value, u8 mask, u8 *reg, u16 addr, |
| 443 | u16 size, struct qpnp_pwm_chip *chip) |
| 444 | { |
| 445 | qpnp_lpg_save(reg, mask, value); |
| 446 | |
| 447 | return regmap_bulk_write(chip->regmap, addr, reg, size); |
| 448 | } |
| 449 | |
| 450 | /* |
| 451 | * PWM Frequency = Clock Frequency / (N * T) |
| 452 | * or |
| 453 | * PWM Period = Clock Period * (N * T) |
| 454 | * where |
| 455 | * N = 2^9 or 2^6 for 9-bit or 6-bit PWM size |
| 456 | * T = Pre-divide * 2^m, where m = 0..7 (exponent) |
| 457 | * |
| 458 | * This is the formula to figure out m for the best pre-divide and clock: |
| 459 | * (PWM Period / N) = (Pre-divide * Clock Period) * 2^m |
| 460 | */ |
| 461 | static void qpnp_lpg_calc_period(enum time_level tm_lvl, |
| 462 | unsigned int period_value, |
| 463 | struct qpnp_pwm_chip *chip) |
| 464 | { |
| 465 | int n, m, clk, div; |
| 466 | int best_m, best_div, best_clk; |
| 467 | unsigned int last_err, cur_err, min_err; |
| 468 | unsigned int tmp_p, period_n; |
| 469 | int supported_sizes = chip->pwm_config.supported_sizes; |
| 470 | int force_pwm_size = chip->pwm_config.force_pwm_size; |
| 471 | struct pwm_period_config *period = &chip->pwm_config.period; |
| 472 | |
| 473 | /* PWM Period / N */ |
| 474 | if (supported_sizes == QPNP_PWM_SIZE_7_8_BIT) |
| 475 | n = 7; |
| 476 | else |
| 477 | n = 6; |
| 478 | |
| 479 | if (tm_lvl == LVL_USEC) { |
| 480 | if (period_value < ((unsigned int)(-1) / NSEC_PER_USEC)) { |
| 481 | period_n = (period_value * NSEC_PER_USEC) >> n; |
| 482 | } else { |
| 483 | if (supported_sizes == QPNP_PWM_SIZE_7_8_BIT) |
| 484 | n = 8; |
| 485 | else |
| 486 | n = 9; |
| 487 | period_n = (period_value >> n) * NSEC_PER_USEC; |
| 488 | } |
| 489 | } else { |
| 490 | period_n = period_value >> n; |
| 491 | } |
| 492 | |
| 493 | if (force_pwm_size != 0) { |
| 494 | if (n < force_pwm_size) |
| 495 | period_n = period_n >> (force_pwm_size - n); |
| 496 | else |
| 497 | period_n = period_n << (n - force_pwm_size); |
| 498 | n = force_pwm_size; |
| 499 | pr_info("LPG channel '%d' pwm size is forced to=%d\n", |
| 500 | chip->channel_id, n); |
| 501 | } |
| 502 | |
| 503 | min_err = last_err = (unsigned int)(-1); |
| 504 | best_m = 0; |
| 505 | best_clk = 0; |
| 506 | best_div = 0; |
| 507 | for (clk = 0; clk < NUM_CLOCKS; clk++) { |
| 508 | for (div = 0; div < NUM_LPG_PRE_DIVIDE; div++) { |
| 509 | /* period_n = (PWM Period / N) */ |
| 510 | /* tmp_p = (Pre-divide * Clock Period) * 2^m */ |
| 511 | tmp_p = pt_t[div][clk]; |
| 512 | for (m = 0; m <= QPNP_PWM_M_MAX; m++) { |
| 513 | if (period_n > tmp_p) |
| 514 | cur_err = period_n - tmp_p; |
| 515 | else |
| 516 | cur_err = tmp_p - period_n; |
| 517 | |
| 518 | if (cur_err < min_err) { |
| 519 | min_err = cur_err; |
| 520 | best_m = m; |
| 521 | best_clk = clk; |
| 522 | best_div = div; |
| 523 | } |
| 524 | |
| 525 | if (m && cur_err > last_err) |
| 526 | /* Break for bigger cur_err */ |
| 527 | break; |
| 528 | |
| 529 | last_err = cur_err; |
| 530 | tmp_p <<= 1; |
| 531 | } |
| 532 | } |
| 533 | } |
| 534 | |
| 535 | /* Adapt to optimal pwm size, the higher the resolution the better */ |
| 536 | if (!force_pwm_size) { |
| 537 | if (supported_sizes == QPNP_PWM_SIZE_7_8_BIT) { |
| 538 | if (n == 7 && best_m >= 1) { |
| 539 | n += 1; |
| 540 | best_m -= 1; |
| 541 | } |
| 542 | } else if (n == 6) { |
| 543 | if (best_m >= 3) { |
| 544 | n += 3; |
| 545 | best_m -= 3; |
| 546 | } else if (best_m >= 1 && ( |
| 547 | chip->sub_type != QPNP_PWM_MODE_ONLY_SUB_TYPE && |
| 548 | chip->sub_type != QPNP_LPG_S_CHAN_SUB_TYPE)) { |
| 549 | n += 1; |
| 550 | best_m -= 1; |
| 551 | } |
| 552 | } |
| 553 | } |
| 554 | |
| 555 | period->pwm_size = n; |
| 556 | period->clk = best_clk; |
| 557 | period->pre_div = best_div; |
| 558 | period->pre_div_exp = best_m; |
| 559 | } |
| 560 | |
| 561 | static void qpnp_lpg_calc_pwm_value(struct _qpnp_pwm_config *pwm_config, |
| 562 | unsigned int period_value, |
| 563 | unsigned int duty_value) |
| 564 | { |
| 565 | unsigned int max_pwm_value, tmp; |
| 566 | |
| 567 | /* Figure out pwm_value with overflow handling */ |
| 568 | tmp = 1 << (sizeof(tmp) * 8 - pwm_config->period.pwm_size); |
| 569 | if (duty_value < tmp) { |
| 570 | tmp = duty_value << pwm_config->period.pwm_size; |
| 571 | pwm_config->pwm_value = tmp / period_value; |
| 572 | } else { |
| 573 | tmp = period_value >> pwm_config->period.pwm_size; |
| 574 | pwm_config->pwm_value = duty_value / tmp; |
| 575 | } |
| 576 | max_pwm_value = (1 << pwm_config->period.pwm_size) - 1; |
| 577 | if (pwm_config->pwm_value > max_pwm_value) |
| 578 | pwm_config->pwm_value = max_pwm_value; |
| 579 | pr_debug("pwm_value: %d\n", pwm_config->pwm_value); |
| 580 | } |
| 581 | |
| 582 | static int qpnp_lpg_change_table(struct qpnp_pwm_chip *chip, |
| 583 | int duty_pct[], int raw_value) |
| 584 | { |
| 585 | unsigned int pwm_value, max_pwm_value; |
| 586 | struct qpnp_lut_config *lut = &chip->lpg_config.lut_config; |
| 587 | int i, pwm_size, rc = 0; |
| 588 | int burst_size = SPMI_MAX_BUF_LEN; |
| 589 | int list_len = lut->list_len << 1; |
| 590 | int offset = (lut->lo_index << 1) - 2; |
| 591 | |
| 592 | pwm_size = QPNP_GET_PWM_SIZE( |
| 593 | chip->qpnp_lpg_registers[QPNP_LPG_PWM_SIZE_CLK]) + |
| 594 | QPNP_MIN_PWM_BIT_SIZE; |
| 595 | |
| 596 | max_pwm_value = (1 << pwm_size) - 1; |
| 597 | |
| 598 | if (unlikely(lut->list_len != (lut->hi_index - lut->lo_index + 1))) { |
| 599 | pr_err("LUT internal Data structure corruption detected\n"); |
| 600 | pr_err("LUT list size: %d\n", lut->list_len); |
| 601 | pr_err("However, index size is: %d\n", |
| 602 | (lut->hi_index - lut->lo_index + 1)); |
| 603 | return -EINVAL; |
| 604 | } |
| 605 | |
| 606 | for (i = 0; i < lut->list_len; i++) { |
| 607 | if (raw_value) |
| 608 | pwm_value = duty_pct[i]; |
| 609 | else |
| 610 | pwm_value = (duty_pct[i] << pwm_size) / 100; |
| 611 | |
| 612 | if (pwm_value > max_pwm_value) |
| 613 | pwm_value = max_pwm_value; |
| 614 | |
| 615 | if (chip->pwm_config.supported_sizes == QPNP_PWM_SIZE_7_8_BIT) { |
| 616 | lut->duty_pct_list[i] = pwm_value; |
| 617 | } else { |
| 618 | lut->duty_pct_list[i*2] = pwm_value; |
| 619 | lut->duty_pct_list[(i*2)+1] = (pwm_value >> |
| 620 | QPNP_PWM_VALUE_MSB_SHIFT) & QPNP_PWM_VALUE_MSB_MASK; |
| 621 | } |
| 622 | } |
| 623 | |
| 624 | /* |
| 625 | * For the Keypad Backlight Lookup Table (KPDBL_LUT), |
| 626 | * offset is lo_index. |
| 627 | */ |
| 628 | if (chip->pwm_config.supported_sizes == QPNP_PWM_SIZE_7_8_BIT) |
| 629 | offset = lut->lo_index; |
| 630 | |
| 631 | /* Write with max allowable burst mode, each entry is of two bytes */ |
| 632 | for (i = 0; i < list_len; i += burst_size) { |
| 633 | if (i + burst_size >= list_len) |
| 634 | burst_size = list_len - i; |
| 635 | rc = regmap_bulk_write(chip->regmap, |
| 636 | chip->lpg_config.lut_base_addr + offset + i, |
| 637 | lut->duty_pct_list + i, |
| 638 | burst_size); |
| 639 | } |
| 640 | |
| 641 | return rc; |
| 642 | } |
| 643 | |
| 644 | static void qpnp_lpg_save_period(struct qpnp_pwm_chip *chip) |
| 645 | { |
| 646 | u8 mask, val; |
| 647 | struct _qpnp_pwm_config *pwm_config = &chip->pwm_config; |
| 648 | |
| 649 | if (chip->sub_type == QPNP_PWM_MODE_ONLY_SUB_TYPE) { |
| 650 | QPNP_SET_PWM_CLK_SUB_TYPE(val, pwm_config->period.clk, |
| 651 | pwm_config->period.pwm_size); |
| 652 | mask = QPNP_PWM_SIZE_MASK_SUB_TYPE | |
| 653 | QPNP_PWM_FREQ_CLK_SELECT_MASK_SUB_TYPE; |
| 654 | } else { |
| 655 | QPNP_SET_PWM_CLK(val, pwm_config->period.clk, |
| 656 | pwm_config->period.pwm_size); |
| 657 | mask = QPNP_PWM_SIZE_MASK | QPNP_PWM_FREQ_CLK_SELECT_MASK; |
| 658 | } |
| 659 | |
| 660 | qpnp_lpg_save(&chip->qpnp_lpg_registers[QPNP_LPG_PWM_SIZE_CLK], |
| 661 | mask, val); |
| 662 | |
| 663 | QPNP_SET_PWM_FREQ_PREDIV(val, pwm_config->period.pre_div, |
| 664 | pwm_config->period.pre_div_exp); |
| 665 | |
| 666 | mask = QPNP_PWM_FREQ_PRE_DIVIDE_MASK | QPNP_PWM_FREQ_EXP_MASK; |
| 667 | |
| 668 | qpnp_lpg_save(&chip->qpnp_lpg_registers[QPNP_LPG_PWM_FREQ_PREDIV_CLK], |
| 669 | mask, val); |
| 670 | } |
| 671 | |
| 672 | static int qpnp_lpg_save_pwm_value(struct qpnp_pwm_chip *chip) |
| 673 | { |
| 674 | unsigned int max_pwm_value; |
| 675 | int pwm_size; |
| 676 | u8 mask, value; |
| 677 | struct _qpnp_pwm_config *pwm_config = &chip->pwm_config; |
| 678 | struct qpnp_lpg_config *lpg_config = &chip->lpg_config; |
| 679 | int rc; |
| 680 | |
| 681 | if (chip->sub_type == QPNP_PWM_MODE_ONLY_SUB_TYPE) |
| 682 | pwm_size = QPNP_GET_PWM_SIZE_SUB_TYPE( |
| 683 | chip->qpnp_lpg_registers[QPNP_LPG_PWM_SIZE_CLK]) ? |
| 684 | QPNP_MAX_PWM_BIT_SIZE : QPNP_MIN_PWM_BIT_SIZE; |
| 685 | else |
| 686 | pwm_size = QPNP_GET_PWM_SIZE( |
| 687 | chip->qpnp_lpg_registers[QPNP_LPG_PWM_SIZE_CLK]) + |
| 688 | QPNP_MIN_PWM_BIT_SIZE; |
| 689 | |
| 690 | max_pwm_value = (1 << pwm_size) - 1; |
| 691 | |
| 692 | if (pwm_config->pwm_value > max_pwm_value) |
| 693 | pwm_config->pwm_value = max_pwm_value; |
| 694 | |
| 695 | value = pwm_config->pwm_value; |
| 696 | mask = QPNP_PWM_VALUE_LSB_MASK; |
| 697 | |
| 698 | pr_debug("pwm_lsb value:%d\n", value & mask); |
| 699 | rc = qpnp_lpg_save_and_write(value, mask, |
| 700 | &chip->qpnp_lpg_registers[QPNP_PWM_VALUE_LSB], |
| 701 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 702 | QPNP_PWM_VALUE_LSB), 1, chip); |
| 703 | if (rc) |
| 704 | return rc; |
| 705 | |
| 706 | value = (pwm_config->pwm_value >> QPNP_PWM_VALUE_MSB_SHIFT) & |
| 707 | QPNP_PWM_VALUE_MSB_MASK; |
| 708 | |
| 709 | mask = QPNP_PWM_VALUE_MSB_MASK; |
| 710 | |
| 711 | pr_debug("pwm_msb value:%d\n", value); |
| 712 | rc = qpnp_lpg_save_and_write(value, mask, |
| 713 | &chip->qpnp_lpg_registers[QPNP_PWM_VALUE_MSB], |
| 714 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 715 | QPNP_PWM_VALUE_MSB), 1, chip); |
| 716 | if (rc) |
| 717 | return rc; |
| 718 | |
| 719 | if (chip->sub_type == QPNP_PWM_MODE_ONLY_SUB_TYPE || |
| 720 | chip->sub_type == QPNP_LPG_S_CHAN_SUB_TYPE) { |
| 721 | value = QPNP_PWM_SYNC_VALUE & QPNP_PWM_SYNC_MASK; |
| 722 | rc = regmap_write(chip->regmap, |
| 723 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 724 | SPMI_LPG_PWM_SYNC), |
| 725 | value); |
| 726 | } |
| 727 | |
| 728 | return rc; |
| 729 | } |
| 730 | |
| 731 | static int qpnp_lpg_configure_pattern(struct qpnp_pwm_chip *chip) |
| 732 | { |
| 733 | struct qpnp_lpg_config *lpg_config = &chip->lpg_config; |
| 734 | struct qpnp_lut_config *lut_config = &lpg_config->lut_config; |
| 735 | u8 value, mask; |
| 736 | |
| 737 | qpnp_set_pattern_config(&value, lut_config); |
| 738 | |
| 739 | mask = QPNP_RAMP_DIRECTION_MASK | QPNP_PATTERN_REPEAT_MASK | |
| 740 | QPNP_RAMP_TOGGLE_MASK | QPNP_EN_PAUSE_HI_MASK | |
| 741 | QPNP_EN_PAUSE_LO_MASK; |
| 742 | |
| 743 | return qpnp_lpg_save_and_write(value, mask, |
| 744 | &chip->qpnp_lpg_registers[QPNP_LPG_PATTERN_CONFIG], |
| 745 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 746 | QPNP_LPG_PATTERN_CONFIG), 1, chip); |
| 747 | } |
| 748 | |
| 749 | static int qpnp_lpg_glitch_removal(struct qpnp_pwm_chip *chip, bool enable) |
| 750 | { |
| 751 | struct qpnp_lpg_config *lpg_config = &chip->lpg_config; |
| 752 | u8 value, mask; |
| 753 | |
| 754 | qpnp_set_pwm_type_config(&value, enable ? 1 : 0, 0, 0, 0); |
| 755 | |
| 756 | mask = QPNP_EN_GLITCH_REMOVAL_MASK | QPNP_EN_FULL_SCALE_MASK | |
| 757 | QPNP_EN_PHASE_STAGGER_MASK | QPNP_PHASE_STAGGER_MASK; |
| 758 | |
| 759 | pr_debug("pwm_type_config: %d\n", value); |
| 760 | return qpnp_lpg_save_and_write(value, mask, |
| 761 | &chip->qpnp_lpg_registers[QPNP_LPG_PWM_TYPE_CONFIG], |
| 762 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 763 | QPNP_LPG_PWM_TYPE_CONFIG), 1, chip); |
| 764 | } |
| 765 | |
| 766 | static int qpnp_lpg_configure_pwm(struct qpnp_pwm_chip *chip) |
| 767 | { |
| 768 | struct qpnp_lpg_config *lpg_config = &chip->lpg_config; |
| 769 | int rc; |
| 770 | |
| 771 | pr_debug("pwm_size_clk: %d\n", |
| 772 | chip->qpnp_lpg_registers[QPNP_LPG_PWM_SIZE_CLK]); |
| 773 | rc = regmap_write(chip->regmap, |
| 774 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 775 | QPNP_LPG_PWM_SIZE_CLK), |
| 776 | *&chip->qpnp_lpg_registers[QPNP_LPG_PWM_SIZE_CLK]); |
| 777 | |
| 778 | if (rc) |
| 779 | return rc; |
| 780 | |
| 781 | pr_debug("pwm_freq_prediv_clk: %d\n", |
| 782 | chip->qpnp_lpg_registers[QPNP_LPG_PWM_FREQ_PREDIV_CLK]); |
| 783 | rc = regmap_write(chip->regmap, |
| 784 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 785 | QPNP_LPG_PWM_FREQ_PREDIV_CLK), |
| 786 | *&chip->qpnp_lpg_registers[QPNP_LPG_PWM_FREQ_PREDIV_CLK]); |
| 787 | if (rc) |
| 788 | return rc; |
| 789 | |
| 790 | /* Disable glitch removal when LPG/PWM is configured */ |
| 791 | rc = qpnp_lpg_glitch_removal(chip, false); |
| 792 | if (rc) { |
| 793 | pr_err("Error in disabling glitch control, rc=%d\n", rc); |
| 794 | return rc; |
| 795 | } |
| 796 | return rc; |
| 797 | } |
| 798 | |
| 799 | static int qpnp_configure_pwm_control(struct qpnp_pwm_chip *chip) |
| 800 | { |
| 801 | struct qpnp_lpg_config *lpg_config = &chip->lpg_config; |
| 802 | u8 value, mask; |
| 803 | |
| 804 | if (chip->sub_type == QPNP_PWM_MODE_ONLY_SUB_TYPE) |
| 805 | return 0; |
| 806 | |
| 807 | value = QPNP_ENABLE_PWM_CONTROL(chip); |
| 808 | |
| 809 | mask = QPNP_EN_PWM_HIGH_MASK | QPNP_EN_PWM_LO_MASK | |
| 810 | QPNP_PWM_SRC_SELECT_MASK | QPNP_PWM_EN_RAMP_GEN_MASK; |
| 811 | if (chip->sub_type != QPNP_LPG_S_CHAN_SUB_TYPE) |
| 812 | mask |= QPNP_EN_PWM_OUTPUT_MASK; |
| 813 | |
| 814 | return qpnp_lpg_save_and_write(value, mask, |
| 815 | &chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL], |
| 816 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 817 | QPNP_ENABLE_CONTROL), 1, chip); |
| 818 | |
| 819 | } |
| 820 | |
| 821 | static int qpnp_configure_lpg_control(struct qpnp_pwm_chip *chip) |
| 822 | { |
| 823 | struct qpnp_lpg_config *lpg_config = &chip->lpg_config; |
| 824 | u8 value, mask; |
| 825 | |
| 826 | value = QPNP_ENABLE_LUT_CONTROL(chip); |
| 827 | |
| 828 | mask = QPNP_EN_PWM_HIGH_MASK | QPNP_EN_PWM_LO_MASK | |
| 829 | QPNP_PWM_SRC_SELECT_MASK | QPNP_PWM_EN_RAMP_GEN_MASK; |
| 830 | if (chip->sub_type != QPNP_LPG_S_CHAN_SUB_TYPE) |
| 831 | mask |= QPNP_EN_PWM_OUTPUT_MASK; |
| 832 | |
| 833 | return qpnp_lpg_save_and_write(value, mask, |
| 834 | &chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL], |
| 835 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 836 | QPNP_ENABLE_CONTROL), 1, chip); |
| 837 | |
| 838 | } |
| 839 | |
| 840 | static int qpnp_lpg_configure_ramp_step_duration(struct qpnp_pwm_chip *chip) |
| 841 | { |
| 842 | struct qpnp_lpg_config *lpg_config = &chip->lpg_config; |
| 843 | struct qpnp_lut_config lut_config = lpg_config->lut_config; |
| 844 | int rc, value; |
| 845 | u8 val, mask; |
| 846 | |
| 847 | value = QPNP_GET_RAMP_STEP_DURATION(lut_config.ramp_step_ms); |
| 848 | val = value & QPNP_RAMP_STEP_DURATION_LSB_MASK; |
| 849 | mask = QPNP_RAMP_STEP_DURATION_LSB_MASK; |
| 850 | |
| 851 | rc = qpnp_lpg_save_and_write(val, mask, |
| 852 | &chip->qpnp_lpg_registers[QPNP_RAMP_STEP_DURATION_LSB], |
| 853 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 854 | QPNP_RAMP_STEP_DURATION_LSB), 1, chip); |
| 855 | if (rc) |
| 856 | return rc; |
| 857 | |
| 858 | val = (value >> QPNP_RAMP_STEP_DURATION_MSB_SHIFT) & |
| 859 | QPNP_RAMP_STEP_DURATION_MSB_MASK; |
| 860 | |
| 861 | mask = QPNP_RAMP_STEP_DURATION_MSB_MASK; |
| 862 | |
| 863 | return qpnp_lpg_save_and_write(val, mask, |
| 864 | &chip->qpnp_lpg_registers[QPNP_RAMP_STEP_DURATION_MSB], |
| 865 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 866 | QPNP_RAMP_STEP_DURATION_MSB), 1, chip); |
| 867 | } |
| 868 | |
| 869 | static int qpnp_lpg_configure_pause(struct qpnp_pwm_chip *chip) |
| 870 | { |
| 871 | struct qpnp_lpg_config *lpg_config = &chip->lpg_config; |
| 872 | struct qpnp_lut_config lut_config = lpg_config->lut_config; |
| 873 | u8 value, mask; |
| 874 | int rc = 0; |
| 875 | |
| 876 | if (lut_config.enable_pause_hi) { |
| 877 | value = lut_config.lut_pause_hi_cnt; |
| 878 | mask = QPNP_PAUSE_HI_MULTIPLIER_LSB_MASK; |
| 879 | |
| 880 | rc = qpnp_lpg_save_and_write(value, mask, |
| 881 | &chip->qpnp_lpg_registers[QPNP_PAUSE_HI_MULTIPLIER_LSB], |
| 882 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 883 | QPNP_PAUSE_HI_MULTIPLIER_LSB), 1, chip); |
| 884 | if (rc) |
| 885 | return rc; |
| 886 | |
| 887 | value = (lut_config.lut_pause_hi_cnt >> |
| 888 | QPNP_PAUSE_HI_MULTIPLIER_MSB_SHIFT) & |
| 889 | QPNP_PAUSE_HI_MULTIPLIER_MSB_MASK; |
| 890 | |
| 891 | mask = QPNP_PAUSE_HI_MULTIPLIER_MSB_MASK; |
| 892 | |
| 893 | rc = qpnp_lpg_save_and_write(value, mask, |
| 894 | &chip->qpnp_lpg_registers[QPNP_PAUSE_HI_MULTIPLIER_MSB], |
| 895 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 896 | QPNP_PAUSE_HI_MULTIPLIER_MSB), 1, chip); |
| 897 | } else { |
| 898 | value = 0; |
| 899 | mask = QPNP_PAUSE_HI_MULTIPLIER_LSB_MASK; |
| 900 | |
| 901 | rc = qpnp_lpg_save_and_write(value, mask, |
| 902 | &chip->qpnp_lpg_registers[QPNP_PAUSE_HI_MULTIPLIER_LSB], |
| 903 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 904 | QPNP_PAUSE_HI_MULTIPLIER_LSB), 1, chip); |
| 905 | if (rc) |
| 906 | return rc; |
| 907 | |
| 908 | mask = QPNP_PAUSE_HI_MULTIPLIER_MSB_MASK; |
| 909 | |
| 910 | rc = qpnp_lpg_save_and_write(value, mask, |
| 911 | &chip->qpnp_lpg_registers[QPNP_PAUSE_HI_MULTIPLIER_MSB], |
| 912 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 913 | QPNP_PAUSE_HI_MULTIPLIER_MSB), 1, chip); |
| 914 | if (rc) |
| 915 | return rc; |
| 916 | |
| 917 | } |
| 918 | |
| 919 | if (lut_config.enable_pause_lo) { |
| 920 | value = lut_config.lut_pause_lo_cnt; |
| 921 | mask = QPNP_PAUSE_LO_MULTIPLIER_LSB_MASK; |
| 922 | |
| 923 | rc = qpnp_lpg_save_and_write(value, mask, |
| 924 | &chip->qpnp_lpg_registers[QPNP_PAUSE_LO_MULTIPLIER_LSB], |
| 925 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 926 | QPNP_PAUSE_LO_MULTIPLIER_LSB), 1, chip); |
| 927 | if (rc) |
| 928 | return rc; |
| 929 | |
| 930 | value = (lut_config.lut_pause_lo_cnt >> |
| 931 | QPNP_PAUSE_LO_MULTIPLIER_MSB_SHIFT) & |
| 932 | QPNP_PAUSE_LO_MULTIPLIER_MSB_MASK; |
| 933 | |
| 934 | mask = QPNP_PAUSE_LO_MULTIPLIER_MSB_MASK; |
| 935 | |
| 936 | rc = qpnp_lpg_save_and_write(value, mask, |
| 937 | &chip->qpnp_lpg_registers[QPNP_PAUSE_LO_MULTIPLIER_MSB], |
| 938 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 939 | QPNP_PAUSE_LO_MULTIPLIER_MSB), 1, chip); |
| 940 | } else { |
| 941 | value = 0; |
| 942 | mask = QPNP_PAUSE_LO_MULTIPLIER_LSB_MASK; |
| 943 | |
| 944 | rc = qpnp_lpg_save_and_write(value, mask, |
| 945 | &chip->qpnp_lpg_registers[QPNP_PAUSE_LO_MULTIPLIER_LSB], |
| 946 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 947 | QPNP_PAUSE_LO_MULTIPLIER_LSB), 1, chip); |
| 948 | if (rc) |
| 949 | return rc; |
| 950 | |
| 951 | mask = QPNP_PAUSE_LO_MULTIPLIER_MSB_MASK; |
| 952 | |
| 953 | rc = qpnp_lpg_save_and_write(value, mask, |
| 954 | &chip->qpnp_lpg_registers[QPNP_PAUSE_LO_MULTIPLIER_MSB], |
| 955 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 956 | QPNP_PAUSE_LO_MULTIPLIER_MSB), 1, chip); |
| 957 | return rc; |
| 958 | } |
| 959 | |
| 960 | return rc; |
| 961 | } |
| 962 | |
| 963 | static int qpnp_lpg_configure_index(struct qpnp_pwm_chip *chip) |
| 964 | { |
| 965 | struct qpnp_lpg_config *lpg_config = &chip->lpg_config; |
| 966 | struct qpnp_lut_config lut_config = lpg_config->lut_config; |
| 967 | u8 value, mask; |
| 968 | int rc = 0; |
| 969 | |
| 970 | value = lut_config.hi_index; |
| 971 | mask = QPNP_HI_INDEX_MASK; |
| 972 | |
| 973 | rc = qpnp_lpg_save_and_write(value, mask, |
| 974 | &chip->qpnp_lpg_registers[QPNP_HI_INDEX], |
| 975 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 976 | QPNP_HI_INDEX), 1, chip); |
| 977 | if (rc) |
| 978 | return rc; |
| 979 | |
| 980 | value = lut_config.lo_index; |
| 981 | mask = QPNP_LO_INDEX_MASK; |
| 982 | |
| 983 | rc = qpnp_lpg_save_and_write(value, mask, |
| 984 | &chip->qpnp_lpg_registers[QPNP_LO_INDEX], |
| 985 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 986 | QPNP_LO_INDEX), 1, chip); |
| 987 | |
| 988 | return rc; |
| 989 | } |
| 990 | |
| 991 | static int qpnp_lpg_change_lut(struct qpnp_pwm_chip *chip) |
| 992 | { |
| 993 | int rc; |
| 994 | |
| 995 | rc = qpnp_lpg_configure_pattern(chip); |
| 996 | if (rc) { |
| 997 | pr_err("Failed to configure LUT pattern"); |
| 998 | return rc; |
| 999 | } |
| 1000 | rc = qpnp_lpg_configure_pwm(chip); |
| 1001 | if (rc) { |
| 1002 | pr_err("Failed to configure LUT pattern"); |
| 1003 | return rc; |
| 1004 | } |
| 1005 | rc = qpnp_configure_lpg_control(chip); |
| 1006 | if (rc) { |
| 1007 | pr_err("Failed to configure pause registers"); |
| 1008 | return rc; |
| 1009 | } |
| 1010 | rc = qpnp_lpg_configure_ramp_step_duration(chip); |
| 1011 | if (rc) { |
| 1012 | pr_err("Failed to configure duty time"); |
| 1013 | return rc; |
| 1014 | } |
| 1015 | rc = qpnp_lpg_configure_pause(chip); |
| 1016 | if (rc) { |
| 1017 | pr_err("Failed to configure pause registers"); |
| 1018 | return rc; |
| 1019 | } |
| 1020 | rc = qpnp_lpg_configure_index(chip); |
| 1021 | if (rc) { |
| 1022 | pr_err("Failed to configure index registers"); |
| 1023 | return rc; |
| 1024 | } |
| 1025 | return rc; |
| 1026 | } |
| 1027 | |
| 1028 | static int qpnp_dtest_config(struct qpnp_pwm_chip *chip, bool enable) |
| 1029 | { |
| 1030 | struct qpnp_lpg_config *lpg_config = &chip->lpg_config; |
| 1031 | u8 value; |
| 1032 | u8 mask; |
| 1033 | u16 addr; |
| 1034 | int rc = 0; |
| 1035 | |
| 1036 | value = 0xA5; |
| 1037 | |
| 1038 | addr = SPMI_LPG_REG_ADDR(lpg_config->base_addr, QPNP_LPG_SEC_ACCESS); |
| 1039 | |
| 1040 | rc = regmap_write(chip->regmap, addr, value); |
| 1041 | |
| 1042 | if (rc) { |
| 1043 | pr_err("Couldn't set the access for test mode\n"); |
| 1044 | return rc; |
| 1045 | } |
| 1046 | |
| 1047 | addr = SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 1048 | QPNP_LPG_DTEST + chip->dtest_line - 1); |
| 1049 | |
| 1050 | if (chip->sub_type == QPNP_PWM_MODE_ONLY_SUB_TYPE) |
| 1051 | mask = QPNP_PWM_DTEST_OUTPUT_MASK; |
| 1052 | else |
| 1053 | mask = QPNP_LPG_DTEST_OUTPUT_MASK; |
| 1054 | |
| 1055 | if (enable) |
| 1056 | value = chip->dtest_output & mask; |
| 1057 | else |
| 1058 | value = 0; |
| 1059 | |
| 1060 | pr_debug("Setting TEST mode for channel %d addr:%x value: %x\n", |
| 1061 | chip->channel_id, addr, value); |
| 1062 | |
| 1063 | rc = regmap_write(chip->regmap, addr, value); |
| 1064 | |
| 1065 | return rc; |
| 1066 | } |
| 1067 | |
| 1068 | static int qpnp_lpg_configure_lut_state(struct qpnp_pwm_chip *chip, |
| 1069 | enum qpnp_lut_state state) |
| 1070 | { |
| 1071 | struct qpnp_lpg_config *lpg_config = &chip->lpg_config; |
| 1072 | u8 value1, value2, mask1, mask2; |
| 1073 | u8 *reg1, *reg2; |
| 1074 | u16 addr, addr1; |
| 1075 | int rc; |
| 1076 | bool test_enable; |
| 1077 | |
| 1078 | value1 = chip->qpnp_lpg_registers[QPNP_RAMP_CONTROL]; |
| 1079 | reg1 = &chip->qpnp_lpg_registers[QPNP_RAMP_CONTROL]; |
| 1080 | reg2 = &chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL]; |
| 1081 | mask2 = QPNP_EN_PWM_HIGH_MASK | QPNP_EN_PWM_LO_MASK | |
| 1082 | QPNP_PWM_SRC_SELECT_MASK | QPNP_PWM_EN_RAMP_GEN_MASK; |
| 1083 | if (chip->sub_type != QPNP_LPG_S_CHAN_SUB_TYPE) |
| 1084 | mask2 |= QPNP_EN_PWM_OUTPUT_MASK; |
| 1085 | |
| 1086 | if (chip->sub_type == QPNP_LPG_CHAN_SUB_TYPE |
| 1087 | && chip->revision == QPNP_LPG_REVISION_0) { |
| 1088 | if (state == QPNP_LUT_ENABLE) { |
| 1089 | QPNP_ENABLE_LUT_V0(value1); |
| 1090 | value2 = QPNP_ENABLE_LPG_MODE(chip); |
| 1091 | } else { |
| 1092 | QPNP_DISABLE_LUT_V0(value1); |
| 1093 | value2 = QPNP_DISABLE_LPG_MODE(chip); |
| 1094 | } |
| 1095 | mask1 = QPNP_RAMP_START_MASK; |
| 1096 | addr1 = SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 1097 | QPNP_RAMP_CONTROL); |
| 1098 | } else if ((chip->sub_type == QPNP_LPG_CHAN_SUB_TYPE |
| 1099 | && chip->revision == QPNP_LPG_REVISION_1) |
| 1100 | || chip->sub_type == QPNP_LPG_S_CHAN_SUB_TYPE) { |
| 1101 | if (state == QPNP_LUT_ENABLE) { |
| 1102 | QPNP_ENABLE_LUT_V1(value1, |
| 1103 | lpg_config->lut_config.ramp_index); |
| 1104 | value2 = QPNP_ENABLE_LPG_MODE(chip); |
| 1105 | } else { |
| 1106 | value2 = QPNP_DISABLE_LPG_MODE(chip); |
| 1107 | } |
| 1108 | mask1 = value1; |
| 1109 | addr1 = lpg_config->lut_base_addr + |
| 1110 | SPMI_LPG_REV1_RAMP_CONTROL_OFFSET; |
| 1111 | } else { |
| 1112 | pr_err("Unsupported LPG subtype 0x%02x, revision 0x%02x\n", |
| 1113 | chip->sub_type, chip->revision); |
| 1114 | return -EINVAL; |
| 1115 | } |
| 1116 | |
| 1117 | addr = SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 1118 | QPNP_ENABLE_CONTROL); |
| 1119 | |
| 1120 | if (chip->in_test_mode) { |
| 1121 | test_enable = (state == QPNP_LUT_ENABLE) ? 1 : 0; |
| 1122 | rc = qpnp_dtest_config(chip, test_enable); |
| 1123 | if (rc) |
| 1124 | pr_err("Failed to configure TEST mode\n"); |
| 1125 | } |
| 1126 | |
| 1127 | rc = qpnp_lpg_save_and_write(value2, mask2, reg2, |
| 1128 | addr, 1, chip); |
| 1129 | if (rc) |
| 1130 | return rc; |
| 1131 | |
| 1132 | if (state == QPNP_LUT_ENABLE |
| 1133 | || (chip->sub_type == QPNP_LPG_CHAN_SUB_TYPE |
| 1134 | && chip->revision == QPNP_LPG_REVISION_0)) |
| 1135 | rc = qpnp_lpg_save_and_write(value1, mask1, reg1, |
| 1136 | addr1, 1, chip); |
| 1137 | return rc; |
| 1138 | } |
| 1139 | |
| 1140 | static inline int qpnp_enable_pwm_mode(struct qpnp_pwm_chip *chip) |
| 1141 | { |
| 1142 | if (chip->pwm_config.supported_sizes == QPNP_PWM_SIZE_7_8_BIT) |
| 1143 | return QPNP_ENABLE_PWM_MODE_GPLED_CHANNEL(chip); |
| 1144 | return QPNP_ENABLE_PWM_MODE(chip); |
| 1145 | } |
| 1146 | |
| 1147 | static int qpnp_lpg_configure_pwm_state(struct qpnp_pwm_chip *chip, |
| 1148 | enum qpnp_pwm_state state) |
| 1149 | { |
| 1150 | struct qpnp_lpg_config *lpg_config = &chip->lpg_config; |
| 1151 | u8 value, mask; |
| 1152 | int rc; |
| 1153 | bool test_enable; |
| 1154 | |
| 1155 | if (chip->sub_type == QPNP_PWM_MODE_ONLY_SUB_TYPE) { |
| 1156 | if (state == QPNP_PWM_ENABLE) |
| 1157 | value = QPNP_ENABLE_PWM_MODE_ONLY_SUB_TYPE; |
| 1158 | else |
| 1159 | value = QPNP_DISABLE_PWM_MODE_ONLY_SUB_TYPE; |
| 1160 | |
| 1161 | mask = QPNP_PWM_MODE_ONLY_ENABLE_DISABLE_MASK_SUB_TYPE; |
| 1162 | } else { |
| 1163 | if (state == QPNP_PWM_ENABLE) |
| 1164 | value = qpnp_enable_pwm_mode(chip); |
| 1165 | else |
| 1166 | value = QPNP_DISABLE_PWM_MODE(chip); |
| 1167 | |
| 1168 | mask = QPNP_EN_PWM_HIGH_MASK | QPNP_EN_PWM_LO_MASK | |
| 1169 | QPNP_PWM_SRC_SELECT_MASK | QPNP_PWM_EN_RAMP_GEN_MASK; |
| 1170 | if (chip->sub_type != QPNP_LPG_S_CHAN_SUB_TYPE) |
| 1171 | mask |= QPNP_EN_PWM_OUTPUT_MASK; |
| 1172 | } |
| 1173 | |
| 1174 | if (chip->in_test_mode) { |
| 1175 | test_enable = (state == QPNP_PWM_ENABLE) ? 1 : 0; |
| 1176 | rc = qpnp_dtest_config(chip, test_enable); |
| 1177 | if (rc) |
| 1178 | pr_err("Failed to configure TEST mode\n"); |
| 1179 | } |
| 1180 | |
| 1181 | pr_debug("pwm_enable_control: %d\n", value); |
| 1182 | rc = qpnp_lpg_save_and_write(value, mask, |
| 1183 | &chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL], |
| 1184 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 1185 | QPNP_ENABLE_CONTROL), 1, chip); |
| 1186 | if (rc) |
| 1187 | goto out; |
| 1188 | |
| 1189 | /* |
| 1190 | * Due to LPG hardware bug, in the PWM mode, having enabled PWM, |
| 1191 | * We have to write PWM values one more time. |
| 1192 | */ |
| 1193 | if (state == QPNP_PWM_ENABLE) |
| 1194 | return qpnp_lpg_save_pwm_value(chip); |
| 1195 | |
| 1196 | out: |
| 1197 | return rc; |
| 1198 | } |
| 1199 | |
| 1200 | static int _pwm_config(struct qpnp_pwm_chip *chip, |
| 1201 | enum time_level tm_lvl, |
| 1202 | int duty_value, int period_value) |
| 1203 | { |
| 1204 | int rc; |
| 1205 | struct _qpnp_pwm_config *pwm_config = &chip->pwm_config; |
| 1206 | struct pwm_period_config *period = &pwm_config->period; |
| 1207 | |
| 1208 | pwm_config->pwm_duty = (tm_lvl == LVL_USEC) ? duty_value : |
| 1209 | duty_value / NSEC_PER_USEC; |
| 1210 | qpnp_lpg_calc_pwm_value(pwm_config, period_value, duty_value); |
| 1211 | rc = qpnp_lpg_save_pwm_value(chip); |
| 1212 | if (rc) |
| 1213 | goto out; |
| 1214 | rc = qpnp_lpg_configure_pwm(chip); |
| 1215 | if (rc) |
| 1216 | goto out; |
| 1217 | rc = qpnp_configure_pwm_control(chip); |
| 1218 | if (rc) |
| 1219 | goto out; |
| 1220 | |
| 1221 | if (!rc && chip->enabled) { |
| 1222 | rc = qpnp_lpg_configure_pwm_state(chip, QPNP_PWM_ENABLE); |
| 1223 | if (rc) { |
| 1224 | pr_err("Error in configuring pwm state, rc=%d\n", rc); |
| 1225 | return rc; |
| 1226 | } |
| 1227 | |
| 1228 | /* Enable the glitch removal after PWM is enabled */ |
| 1229 | rc = qpnp_lpg_glitch_removal(chip, true); |
| 1230 | if (rc) { |
| 1231 | pr_err("Error in enabling glitch control, rc=%d\n", rc); |
| 1232 | return rc; |
| 1233 | } |
| 1234 | } |
| 1235 | |
| 1236 | pr_debug("duty/period=%u/%u %s: pwm_value=%d (of %d)\n", |
| 1237 | (unsigned int)duty_value, (unsigned int)period_value, |
| 1238 | (tm_lvl == LVL_USEC) ? "usec" : "nsec", |
| 1239 | pwm_config->pwm_value, 1 << period->pwm_size); |
| 1240 | |
| 1241 | out: |
| 1242 | return rc; |
| 1243 | } |
| 1244 | |
| 1245 | static int _pwm_lut_config(struct qpnp_pwm_chip *chip, int period_us, |
| 1246 | int duty_pct[], struct lut_params lut_params) |
| 1247 | { |
| 1248 | struct qpnp_lpg_config *lpg_config; |
| 1249 | struct qpnp_lut_config *lut_config; |
| 1250 | struct pwm_period_config *period; |
| 1251 | struct _qpnp_pwm_config *pwm_config; |
| 1252 | int start_idx = lut_params.start_idx; |
| 1253 | int len = lut_params.idx_len; |
| 1254 | int flags = lut_params.flags; |
| 1255 | int raw_lut, ramp_step_ms; |
| 1256 | int rc = 0; |
| 1257 | |
| 1258 | pwm_config = &chip->pwm_config; |
| 1259 | lpg_config = &chip->lpg_config; |
| 1260 | lut_config = &lpg_config->lut_config; |
| 1261 | period = &pwm_config->period; |
| 1262 | |
| 1263 | if (flags & PM_PWM_LUT_NO_TABLE) |
| 1264 | goto after_table_write; |
| 1265 | |
| 1266 | raw_lut = 0; |
| 1267 | if (flags & PM_PWM_LUT_USE_RAW_VALUE) |
| 1268 | raw_lut = 1; |
| 1269 | |
| 1270 | lut_config->list_len = len; |
| 1271 | lut_config->lo_index = start_idx + 1; |
| 1272 | lut_config->hi_index = start_idx + len; |
| 1273 | |
| 1274 | rc = qpnp_lpg_change_table(chip, duty_pct, raw_lut); |
| 1275 | if (rc) { |
| 1276 | pr_err("qpnp_lpg_change_table: rc=%d\n", rc); |
| 1277 | return -EINVAL; |
| 1278 | } |
| 1279 | |
| 1280 | after_table_write: |
| 1281 | ramp_step_ms = lut_params.ramp_step_ms; |
| 1282 | |
| 1283 | if (ramp_step_ms > PM_PWM_LUT_RAMP_STEP_TIME_MAX) |
| 1284 | ramp_step_ms = PM_PWM_LUT_RAMP_STEP_TIME_MAX; |
| 1285 | |
| 1286 | QPNP_SET_PAUSE_CNT(lut_config->lut_pause_lo_cnt, |
| 1287 | lut_params.lut_pause_lo, ramp_step_ms); |
| 1288 | if (lut_config->lut_pause_lo_cnt > PM_PWM_MAX_PAUSE_CNT) |
| 1289 | lut_config->lut_pause_lo_cnt = PM_PWM_MAX_PAUSE_CNT; |
| 1290 | |
| 1291 | QPNP_SET_PAUSE_CNT(lut_config->lut_pause_hi_cnt, |
| 1292 | lut_params.lut_pause_hi, ramp_step_ms); |
| 1293 | if (lut_config->lut_pause_hi_cnt > PM_PWM_MAX_PAUSE_CNT) |
| 1294 | lut_config->lut_pause_hi_cnt = PM_PWM_MAX_PAUSE_CNT; |
| 1295 | |
| 1296 | lut_config->ramp_step_ms = ramp_step_ms; |
| 1297 | |
| 1298 | lut_config->ramp_direction = !!(flags & PM_PWM_LUT_RAMP_UP); |
| 1299 | lut_config->pattern_repeat = !!(flags & PM_PWM_LUT_LOOP); |
| 1300 | lut_config->ramp_toggle = !!(flags & PM_PWM_LUT_REVERSE); |
| 1301 | lut_config->enable_pause_hi = !!(flags & PM_PWM_LUT_PAUSE_HI_EN); |
| 1302 | lut_config->enable_pause_lo = !!(flags & PM_PWM_LUT_PAUSE_LO_EN); |
| 1303 | |
| 1304 | rc = qpnp_lpg_change_lut(chip); |
| 1305 | |
| 1306 | if (!rc && chip->enabled) |
| 1307 | rc = qpnp_lpg_configure_lut_state(chip, QPNP_LUT_ENABLE); |
| 1308 | |
| 1309 | return rc; |
| 1310 | } |
| 1311 | |
| 1312 | static int _pwm_enable(struct qpnp_pwm_chip *chip) |
| 1313 | { |
| 1314 | int rc = 0; |
| 1315 | unsigned long flags; |
| 1316 | |
| 1317 | spin_lock_irqsave(&chip->lpg_lock, flags); |
| 1318 | |
| 1319 | if (QPNP_IS_PWM_CONFIG_SELECTED( |
| 1320 | chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL]) || |
| 1321 | chip->flags & QPNP_PWM_LUT_NOT_SUPPORTED) { |
| 1322 | rc = qpnp_lpg_configure_pwm_state(chip, QPNP_PWM_ENABLE); |
| 1323 | } else if (!(chip->flags & QPNP_PWM_LUT_NOT_SUPPORTED)) { |
| 1324 | rc = qpnp_lpg_configure_lut_state(chip, QPNP_LUT_ENABLE); |
| 1325 | } |
| 1326 | |
| 1327 | if (!rc) |
| 1328 | chip->enabled = true; |
| 1329 | |
| 1330 | spin_unlock_irqrestore(&chip->lpg_lock, flags); |
| 1331 | |
| 1332 | return rc; |
| 1333 | } |
| 1334 | |
| 1335 | /* APIs */ |
| 1336 | /** |
| 1337 | * qpnp_pwm_free - free a PWM device |
| 1338 | * @pwm_chip: the PWM chip |
| 1339 | * @pwm: the PWM device |
| 1340 | */ |
| 1341 | static void qpnp_pwm_free(struct pwm_chip *pwm_chip, |
| 1342 | struct pwm_device *pwm) |
| 1343 | { |
| 1344 | struct qpnp_pwm_chip *chip = qpnp_pwm_from_pwm_chip(pwm_chip); |
| 1345 | unsigned long flags; |
| 1346 | |
| 1347 | spin_lock_irqsave(&chip->lpg_lock, flags); |
| 1348 | |
| 1349 | qpnp_lpg_configure_pwm_state(chip, QPNP_PWM_DISABLE); |
| 1350 | if (!(chip->flags & QPNP_PWM_LUT_NOT_SUPPORTED)) |
| 1351 | qpnp_lpg_configure_lut_state(chip, QPNP_LUT_DISABLE); |
| 1352 | |
| 1353 | chip->enabled = false; |
| 1354 | spin_unlock_irqrestore(&chip->lpg_lock, flags); |
| 1355 | } |
| 1356 | |
| 1357 | /** |
| 1358 | * qpnp_pwm_config - change a PWM device configuration |
| 1359 | * @pwm: the PWM device |
| 1360 | * @period_ns: period in nanoseconds |
| 1361 | * @duty_ns: duty cycle in nanoseconds |
| 1362 | */ |
| 1363 | static int qpnp_pwm_config(struct pwm_chip *pwm_chip, |
| 1364 | struct pwm_device *pwm, int duty_ns, int period_ns) |
| 1365 | { |
| 1366 | int rc; |
| 1367 | unsigned long flags; |
| 1368 | struct qpnp_pwm_chip *chip = qpnp_pwm_from_pwm_chip(pwm_chip); |
| 1369 | int prev_period_us = chip->pwm_config.pwm_period; |
| 1370 | |
| 1371 | if ((unsigned int)period_ns < PM_PWM_PERIOD_MIN * NSEC_PER_USEC) { |
| 1372 | pr_err("Invalid pwm handle or parameters\n"); |
| 1373 | return -EINVAL; |
| 1374 | } |
| 1375 | |
| 1376 | spin_lock_irqsave(&chip->lpg_lock, flags); |
| 1377 | |
| 1378 | if (prev_period_us > INT_MAX / NSEC_PER_USEC || |
| 1379 | prev_period_us * NSEC_PER_USEC != period_ns) { |
| 1380 | qpnp_lpg_calc_period(LVL_NSEC, period_ns, chip); |
| 1381 | qpnp_lpg_save_period(chip); |
| 1382 | pwm->state.period = period_ns; |
| 1383 | chip->pwm_config.pwm_period = period_ns / NSEC_PER_USEC; |
| 1384 | } |
| 1385 | |
| 1386 | rc = _pwm_config(chip, LVL_NSEC, duty_ns, period_ns); |
| 1387 | |
| 1388 | spin_unlock_irqrestore(&chip->lpg_lock, flags); |
| 1389 | |
| 1390 | if (rc) |
| 1391 | pr_err("Failed to configure PWM mode\n"); |
| 1392 | |
| 1393 | return rc; |
| 1394 | } |
| 1395 | |
| 1396 | /** |
| 1397 | * qpnp_pwm_enable - start a PWM output toggling |
| 1398 | * @pwm_chip: the PWM chip |
| 1399 | * @pwm: the PWM device |
| 1400 | */ |
| 1401 | static int qpnp_pwm_enable(struct pwm_chip *pwm_chip, |
| 1402 | struct pwm_device *pwm) |
| 1403 | { |
| 1404 | int rc; |
| 1405 | struct qpnp_pwm_chip *chip = qpnp_pwm_from_pwm_chip(pwm_chip); |
| 1406 | |
| 1407 | rc = _pwm_enable(chip); |
| 1408 | if (rc) |
| 1409 | pr_err("Failed to enable PWM channel: %d\n", chip->channel_id); |
| 1410 | |
| 1411 | return rc; |
| 1412 | } |
| 1413 | |
| 1414 | /** |
| 1415 | * qpnp_pwm_disable - stop a PWM output toggling |
| 1416 | * @pwm_chip: the PWM chip |
| 1417 | * @pwm: the PWM device |
| 1418 | */ |
| 1419 | static void qpnp_pwm_disable(struct pwm_chip *pwm_chip, |
| 1420 | struct pwm_device *pwm) |
| 1421 | { |
| 1422 | |
| 1423 | struct qpnp_pwm_chip *chip = qpnp_pwm_from_pwm_chip(pwm_chip); |
| 1424 | unsigned long flags; |
| 1425 | int rc = 0; |
| 1426 | |
| 1427 | spin_lock_irqsave(&chip->lpg_lock, flags); |
| 1428 | |
| 1429 | if (QPNP_IS_PWM_CONFIG_SELECTED( |
| 1430 | chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL]) || |
| 1431 | chip->flags & QPNP_PWM_LUT_NOT_SUPPORTED) |
| 1432 | rc = qpnp_lpg_configure_pwm_state(chip, |
| 1433 | QPNP_PWM_DISABLE); |
| 1434 | else if (!(chip->flags & QPNP_PWM_LUT_NOT_SUPPORTED)) |
| 1435 | rc = qpnp_lpg_configure_lut_state(chip, |
| 1436 | QPNP_LUT_DISABLE); |
| 1437 | |
| 1438 | if (!rc) |
| 1439 | chip->enabled = false; |
| 1440 | |
| 1441 | spin_unlock_irqrestore(&chip->lpg_lock, flags); |
| 1442 | |
| 1443 | if (rc) |
| 1444 | pr_err("Failed to disable PWM channel: %d\n", |
| 1445 | chip->channel_id); |
| 1446 | } |
| 1447 | |
| 1448 | static int _pwm_change_mode(struct qpnp_pwm_chip *chip, enum pm_pwm_mode mode) |
| 1449 | { |
| 1450 | int rc; |
| 1451 | |
| 1452 | if (mode) |
| 1453 | rc = qpnp_configure_lpg_control(chip); |
| 1454 | else |
| 1455 | rc = qpnp_configure_pwm_control(chip); |
| 1456 | |
| 1457 | if (rc) |
| 1458 | pr_err("Failed to change the mode\n"); |
| 1459 | return rc; |
| 1460 | } |
| 1461 | |
| 1462 | /** |
| 1463 | * pwm_change_mode - Change the PWM mode configuration |
| 1464 | * @pwm: the PWM device |
| 1465 | * @mode: Mode selection value |
| 1466 | */ |
| 1467 | int pwm_change_mode(struct pwm_device *pwm, enum pm_pwm_mode mode) |
| 1468 | { |
| 1469 | int rc; |
| 1470 | unsigned long flags; |
| 1471 | struct qpnp_pwm_chip *chip; |
| 1472 | |
| 1473 | if (pwm == NULL || IS_ERR(pwm) || pwm->chip == NULL) { |
| 1474 | pr_err("Invalid pwm handle or no pwm_chip\n"); |
| 1475 | return -EINVAL; |
| 1476 | } |
| 1477 | |
| 1478 | if (mode < PM_PWM_MODE_PWM || mode > PM_PWM_MODE_LPG) { |
| 1479 | pr_err("Invalid mode value\n"); |
| 1480 | return -EINVAL; |
| 1481 | } |
| 1482 | |
| 1483 | chip = qpnp_pwm_from_pwm_dev(pwm); |
| 1484 | |
| 1485 | spin_lock_irqsave(&chip->lpg_lock, flags); |
| 1486 | rc = _pwm_change_mode(chip, mode); |
| 1487 | spin_unlock_irqrestore(&chip->lpg_lock, flags); |
| 1488 | |
| 1489 | return rc; |
| 1490 | } |
| 1491 | EXPORT_SYMBOL(pwm_change_mode); |
| 1492 | |
| 1493 | /** |
| 1494 | * pwm_config_period - change PWM period |
| 1495 | * |
| 1496 | * @pwm: the PWM device |
| 1497 | * @pwm_p: period in struct qpnp_lpg_period |
| 1498 | */ |
| 1499 | int pwm_config_period(struct pwm_device *pwm, |
| 1500 | struct pwm_period_config *period) |
| 1501 | { |
| 1502 | struct _qpnp_pwm_config *pwm_config; |
| 1503 | struct qpnp_lpg_config *lpg_config; |
| 1504 | struct qpnp_pwm_chip *chip; |
| 1505 | unsigned long flags; |
| 1506 | int rc = 0; |
| 1507 | |
| 1508 | if (pwm == NULL || IS_ERR(pwm) || period == NULL) |
| 1509 | return -EINVAL; |
| 1510 | if (pwm->chip == NULL) |
| 1511 | return -ENODEV; |
| 1512 | |
| 1513 | chip = qpnp_pwm_from_pwm_dev(pwm); |
| 1514 | pwm_config = &chip->pwm_config; |
| 1515 | lpg_config = &chip->lpg_config; |
| 1516 | |
| 1517 | spin_lock_irqsave(&chip->lpg_lock, flags); |
| 1518 | |
| 1519 | pwm_config->period.pwm_size = period->pwm_size; |
| 1520 | pwm_config->period.clk = period->clk; |
| 1521 | pwm_config->period.pre_div = period->pre_div; |
| 1522 | pwm_config->period.pre_div_exp = period->pre_div_exp; |
| 1523 | |
| 1524 | qpnp_lpg_save_period(chip); |
| 1525 | |
| 1526 | rc = regmap_write(chip->regmap, |
| 1527 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 1528 | QPNP_LPG_PWM_SIZE_CLK), |
| 1529 | *&chip->qpnp_lpg_registers[QPNP_LPG_PWM_SIZE_CLK]); |
| 1530 | |
| 1531 | if (rc) { |
| 1532 | pr_err("Write failed: QPNP_LPG_PWM_SIZE_CLK register, rc: %d\n", |
| 1533 | rc); |
| 1534 | goto out_unlock; |
| 1535 | } |
| 1536 | |
| 1537 | rc = regmap_write(chip->regmap, |
| 1538 | SPMI_LPG_REG_ADDR(lpg_config->base_addr, |
| 1539 | QPNP_LPG_PWM_FREQ_PREDIV_CLK), |
| 1540 | *&chip->qpnp_lpg_registers[QPNP_LPG_PWM_FREQ_PREDIV_CLK]); |
| 1541 | if (rc) { |
| 1542 | pr_err("Failed to write to QPNP_LPG_PWM_FREQ_PREDIV_CLK\n"); |
| 1543 | pr_err("register, rc = %d\n", rc); |
| 1544 | } |
| 1545 | |
| 1546 | out_unlock: |
| 1547 | spin_unlock_irqrestore(&chip->lpg_lock, flags); |
| 1548 | return rc; |
| 1549 | } |
| 1550 | EXPORT_SYMBOL(pwm_config_period); |
| 1551 | |
| 1552 | /** |
| 1553 | * pwm_config_pwm_value - change a PWM device configuration |
| 1554 | * @pwm: the PWM device |
| 1555 | * @pwm_value: the duty cycle in raw PWM value (< 2^pwm_size) |
| 1556 | */ |
| 1557 | int pwm_config_pwm_value(struct pwm_device *pwm, int pwm_value) |
| 1558 | { |
| 1559 | struct qpnp_lpg_config *lpg_config; |
| 1560 | struct _qpnp_pwm_config *pwm_config; |
| 1561 | struct qpnp_pwm_chip *chip; |
| 1562 | unsigned long flags; |
| 1563 | int rc = 0; |
| 1564 | |
| 1565 | if (pwm == NULL || IS_ERR(pwm)) { |
| 1566 | pr_err("Invalid parameter passed\n"); |
| 1567 | return -EINVAL; |
| 1568 | } |
| 1569 | |
| 1570 | if (pwm->chip == NULL) { |
| 1571 | pr_err("Invalid device handle\n"); |
| 1572 | return -ENODEV; |
| 1573 | } |
| 1574 | |
| 1575 | chip = qpnp_pwm_from_pwm_dev(pwm); |
| 1576 | lpg_config = &chip->lpg_config; |
| 1577 | pwm_config = &chip->pwm_config; |
| 1578 | |
| 1579 | spin_lock_irqsave(&chip->lpg_lock, flags); |
| 1580 | |
| 1581 | if (pwm_config->pwm_value == pwm_value) |
| 1582 | goto out_unlock; |
| 1583 | |
| 1584 | pwm_config->pwm_value = pwm_value; |
| 1585 | |
| 1586 | rc = qpnp_lpg_save_pwm_value(chip); |
| 1587 | |
| 1588 | if (rc) |
| 1589 | pr_err("Could not update PWM value for channel %d rc=%d\n", |
| 1590 | chip->channel_id, rc); |
| 1591 | |
| 1592 | out_unlock: |
| 1593 | spin_unlock_irqrestore(&chip->lpg_lock, flags); |
| 1594 | return rc; |
| 1595 | } |
| 1596 | EXPORT_SYMBOL(pwm_config_pwm_value); |
| 1597 | |
| 1598 | /** |
| 1599 | * pwm_config_us - change a PWM device configuration |
| 1600 | * @pwm: the PWM device |
| 1601 | * @period_us: period in microseconds |
| 1602 | * @duty_us: duty cycle in microseconds |
| 1603 | */ |
| 1604 | int pwm_config_us(struct pwm_device *pwm, int duty_us, int period_us) |
| 1605 | { |
| 1606 | int rc; |
| 1607 | unsigned long flags; |
| 1608 | struct qpnp_pwm_chip *chip; |
| 1609 | |
| 1610 | if (pwm == NULL || IS_ERR(pwm) || |
| 1611 | duty_us > period_us || |
| 1612 | (unsigned int)period_us > PM_PWM_PERIOD_MAX || |
| 1613 | (unsigned int)period_us < PM_PWM_PERIOD_MIN) { |
| 1614 | pr_err("Invalid pwm handle or parameters\n"); |
| 1615 | return -EINVAL; |
| 1616 | } |
| 1617 | |
| 1618 | chip = qpnp_pwm_from_pwm_dev(pwm); |
| 1619 | |
| 1620 | spin_lock_irqsave(&chip->lpg_lock, flags); |
| 1621 | |
| 1622 | if (chip->pwm_config.pwm_period != period_us) { |
| 1623 | qpnp_lpg_calc_period(LVL_USEC, period_us, chip); |
| 1624 | qpnp_lpg_save_period(chip); |
| 1625 | chip->pwm_config.pwm_period = period_us; |
| 1626 | if ((unsigned int)period_us > |
| 1627 | (unsigned int)(-1) / NSEC_PER_USEC) |
| 1628 | pwm->state.period = 0; |
| 1629 | else |
| 1630 | pwm->state.period |
| 1631 | = (unsigned int)period_us * NSEC_PER_USEC; |
| 1632 | } |
| 1633 | |
| 1634 | rc = _pwm_config(chip, LVL_USEC, duty_us, period_us); |
| 1635 | |
| 1636 | spin_unlock_irqrestore(&chip->lpg_lock, flags); |
| 1637 | |
| 1638 | if (rc) |
| 1639 | pr_err("Failed to configure PWM mode\n"); |
| 1640 | |
| 1641 | return rc; |
| 1642 | } |
| 1643 | EXPORT_SYMBOL(pwm_config_us); |
| 1644 | |
| 1645 | /** |
| 1646 | * pwm_lut_config - change LPG LUT device configuration |
| 1647 | * @pwm: the PWM device |
| 1648 | * @period_us: period in micro second |
| 1649 | * @duty_pct: array of duty cycles in percent, like 20, 50. |
| 1650 | * @lut_params: Lookup table parameters |
| 1651 | */ |
| 1652 | int pwm_lut_config(struct pwm_device *pwm, int period_us, |
| 1653 | int duty_pct[], struct lut_params lut_params) |
| 1654 | { |
| 1655 | unsigned long flags; |
| 1656 | struct qpnp_pwm_chip *chip; |
| 1657 | int rc = 0; |
| 1658 | |
| 1659 | if (pwm == NULL || IS_ERR(pwm) || !lut_params.idx_len) { |
| 1660 | pr_err("Invalid pwm handle or idx_len=0\n"); |
| 1661 | return -EINVAL; |
| 1662 | } |
| 1663 | |
| 1664 | if (pwm->chip == NULL) |
| 1665 | return -ENODEV; |
| 1666 | |
| 1667 | if (duty_pct == NULL && !(lut_params.flags & PM_PWM_LUT_NO_TABLE)) { |
| 1668 | pr_err("Invalid duty_pct with flag\n"); |
| 1669 | return -EINVAL; |
| 1670 | } |
| 1671 | |
| 1672 | chip = qpnp_pwm_from_pwm_dev(pwm); |
| 1673 | |
| 1674 | if (chip->flags & QPNP_PWM_LUT_NOT_SUPPORTED) { |
| 1675 | pr_err("LUT mode isn't supported\n"); |
| 1676 | return -EINVAL; |
| 1677 | } |
| 1678 | |
| 1679 | if ((lut_params.start_idx + lut_params.idx_len) > |
| 1680 | chip->lpg_config.lut_size) { |
| 1681 | pr_err("Exceed LUT limit\n"); |
| 1682 | return -EINVAL; |
| 1683 | } |
| 1684 | |
| 1685 | if ((unsigned int)period_us > PM_PWM_PERIOD_MAX || |
| 1686 | (unsigned int)period_us < PM_PWM_PERIOD_MIN) { |
| 1687 | pr_err("Period out of range\n"); |
| 1688 | return -EINVAL; |
| 1689 | } |
| 1690 | |
| 1691 | spin_lock_irqsave(&chip->lpg_lock, flags); |
| 1692 | |
| 1693 | if (chip->pwm_config.pwm_period != period_us) { |
| 1694 | qpnp_lpg_calc_period(LVL_USEC, period_us, chip); |
| 1695 | qpnp_lpg_save_period(chip); |
| 1696 | chip->pwm_config.pwm_period = period_us; |
| 1697 | } |
| 1698 | |
| 1699 | rc = _pwm_lut_config(chip, period_us, duty_pct, lut_params); |
| 1700 | |
| 1701 | spin_unlock_irqrestore(&chip->lpg_lock, flags); |
| 1702 | |
| 1703 | if (rc) |
| 1704 | pr_err("Failed to configure LUT\n"); |
| 1705 | |
| 1706 | return rc; |
| 1707 | } |
| 1708 | EXPORT_SYMBOL(pwm_lut_config); |
| 1709 | |
| 1710 | static int qpnp_parse_pwm_dt_config(struct device_node *of_pwm_node, |
| 1711 | struct device_node *of_parent, struct qpnp_pwm_chip *chip) |
| 1712 | { |
| 1713 | int rc, period; |
| 1714 | |
| 1715 | rc = of_property_read_u32(of_parent, "qcom,period", (u32 *)&period); |
| 1716 | if (rc) { |
| 1717 | pr_err("node is missing PWM Period prop"); |
| 1718 | return rc; |
| 1719 | } |
| 1720 | |
| 1721 | rc = of_property_read_u32(of_pwm_node, "qcom,duty", |
| 1722 | &chip->pwm_config.pwm_duty); |
| 1723 | if (rc) { |
| 1724 | pr_err("node is missing PWM Duty prop"); |
| 1725 | return rc; |
| 1726 | } |
| 1727 | |
| 1728 | if (period < chip->pwm_config.pwm_duty || period > PM_PWM_PERIOD_MAX || |
| 1729 | period < PM_PWM_PERIOD_MIN) { |
| 1730 | pr_err("Invalid pwm period(%d) or duty(%d)\n", period, |
| 1731 | chip->pwm_config.pwm_duty); |
| 1732 | return -EINVAL; |
| 1733 | } |
| 1734 | |
| 1735 | qpnp_lpg_calc_period(LVL_USEC, period, chip); |
| 1736 | qpnp_lpg_save_period(chip); |
| 1737 | chip->pwm_config.pwm_period = period; |
| 1738 | |
| 1739 | rc = _pwm_config(chip, LVL_USEC, chip->pwm_config.pwm_duty, period); |
| 1740 | |
| 1741 | return rc; |
| 1742 | } |
| 1743 | |
| 1744 | static int qpnp_parse_lpg_dt_config(struct device_node *of_lpg_node, |
| 1745 | struct device_node *of_parent, struct qpnp_pwm_chip *chip) |
| 1746 | { |
| 1747 | int rc, period, list_size, start_idx, *duty_pct_list; |
| 1748 | struct qpnp_lpg_config *lpg_config = &chip->lpg_config; |
| 1749 | struct qpnp_lut_config *lut_config = &lpg_config->lut_config; |
| 1750 | struct lut_params lut_params; |
| 1751 | |
| 1752 | rc = of_property_read_u32(of_parent, "qcom,period", &period); |
| 1753 | if (rc) { |
| 1754 | pr_err("node is missing PWM Period prop\n"); |
| 1755 | return rc; |
| 1756 | } |
| 1757 | |
| 1758 | if (!of_get_property(of_lpg_node, "qcom,duty-percents", &list_size)) { |
| 1759 | pr_err("node is missing duty-pct list\n"); |
| 1760 | return rc; |
| 1761 | } |
| 1762 | |
| 1763 | rc = of_property_read_u32(of_lpg_node, "cell-index", &start_idx); |
| 1764 | if (rc) { |
| 1765 | pr_err("Missing start index\n"); |
| 1766 | return rc; |
| 1767 | } |
| 1768 | |
| 1769 | list_size /= sizeof(u32); |
| 1770 | |
| 1771 | if (list_size + start_idx > lpg_config->lut_size) { |
| 1772 | pr_err("duty pct list size overflows\n"); |
| 1773 | return -EINVAL; |
| 1774 | } |
| 1775 | |
| 1776 | duty_pct_list = kcalloc(list_size, sizeof(*duty_pct_list), GFP_KERNEL); |
| 1777 | if (!duty_pct_list) |
| 1778 | return -ENOMEM; |
| 1779 | |
| 1780 | rc = of_property_read_u32_array(of_lpg_node, "qcom,duty-percents", |
| 1781 | duty_pct_list, list_size); |
| 1782 | if (rc) { |
| 1783 | pr_err("invalid or missing property: qcom,duty-pcts-list\n"); |
| 1784 | goto out; |
| 1785 | } |
| 1786 | |
| 1787 | /* Read optional properties */ |
| 1788 | rc = of_property_read_u32(of_lpg_node, "qcom,ramp-step-duration", |
| 1789 | &lut_config->ramp_step_ms); |
| 1790 | if (rc && rc != -EINVAL) |
| 1791 | goto out; |
| 1792 | |
| 1793 | rc = of_property_read_u32(of_lpg_node, "qcom,lpg-lut-pause-hi", |
| 1794 | &lut_config->lut_pause_hi_cnt); |
| 1795 | if (rc && rc != -EINVAL) |
| 1796 | goto out; |
| 1797 | |
| 1798 | rc = of_property_read_u32(of_lpg_node, "qcom,lpg-lut-pause-lo", |
| 1799 | &lut_config->lut_pause_lo_cnt); |
| 1800 | if (rc && rc != -EINVAL) |
| 1801 | goto out; |
| 1802 | |
| 1803 | rc = of_property_read_u32(of_lpg_node, "qcom,lpg-lut-ramp-direction", |
| 1804 | (u32 *)&lut_config->ramp_direction); |
| 1805 | if (rc && rc != -EINVAL) |
| 1806 | goto out; |
| 1807 | |
| 1808 | rc = of_property_read_u32(of_lpg_node, "qcom,lpg-lut-pattern-repeat", |
| 1809 | (u32 *)&lut_config->pattern_repeat); |
| 1810 | if (rc && rc != -EINVAL) |
| 1811 | goto out; |
| 1812 | |
| 1813 | rc = of_property_read_u32(of_lpg_node, "qcom,lpg-lut-ramp-toggle", |
| 1814 | (u32 *)&lut_config->ramp_toggle); |
| 1815 | if (rc && rc != -EINVAL) |
| 1816 | goto out; |
| 1817 | |
| 1818 | rc = of_property_read_u32(of_lpg_node, "qcom,lpg-lut-enable-pause-hi", |
| 1819 | (u32 *)&lut_config->enable_pause_hi); |
| 1820 | if (rc && rc != -EINVAL) |
| 1821 | goto out; |
| 1822 | |
| 1823 | rc = of_property_read_u32(of_lpg_node, "qcom,lpg-lut-enable-pause-lo", |
| 1824 | (u32 *)&lut_config->enable_pause_lo); |
| 1825 | if (rc && rc != -EINVAL) |
| 1826 | goto out; |
| 1827 | rc = 0; |
| 1828 | |
| 1829 | qpnp_set_lut_params(&lut_params, lut_config, start_idx, list_size); |
| 1830 | |
| 1831 | _pwm_lut_config(chip, period, duty_pct_list, lut_params); |
| 1832 | |
| 1833 | out: |
| 1834 | kfree(duty_pct_list); |
| 1835 | return rc; |
| 1836 | } |
| 1837 | |
| 1838 | static int qpnp_lpg_get_rev_subtype(struct qpnp_pwm_chip *chip) |
| 1839 | { |
| 1840 | int rc; |
| 1841 | uint val; |
| 1842 | |
| 1843 | rc = regmap_read(chip->regmap, |
| 1844 | chip->lpg_config.base_addr + SPMI_LPG_SUB_TYPE_OFFSET, |
| 1845 | &val); |
| 1846 | |
| 1847 | if (rc) { |
| 1848 | pr_err("Couldn't read subtype rc: %d\n", rc); |
| 1849 | goto out; |
| 1850 | } |
| 1851 | chip->sub_type = (u8)val; |
| 1852 | |
| 1853 | rc = regmap_read(chip->regmap, |
| 1854 | chip->lpg_config.base_addr + SPMI_LPG_REVISION2_OFFSET, |
| 1855 | &val); |
| 1856 | |
| 1857 | if (rc) { |
| 1858 | pr_err("Couldn't read revision2 rc: %d\n", rc); |
| 1859 | goto out; |
| 1860 | } |
| 1861 | chip->revision = (u8)val; |
| 1862 | |
| 1863 | if (chip->revision < QPNP_LPG_REVISION_0 || |
| 1864 | chip->revision > QPNP_LPG_REVISION_1) { |
| 1865 | pr_err("Unknown LPG revision detected, rev:%d\n", |
| 1866 | chip->revision); |
| 1867 | rc = -EINVAL; |
| 1868 | goto out; |
| 1869 | } |
| 1870 | |
| 1871 | if (chip->sub_type != QPNP_PWM_MODE_ONLY_SUB_TYPE |
| 1872 | && chip->sub_type != QPNP_LPG_CHAN_SUB_TYPE |
| 1873 | && chip->sub_type != QPNP_LPG_S_CHAN_SUB_TYPE) { |
| 1874 | pr_err("Unknown LPG/PWM subtype detected, subtype:%d\n", |
| 1875 | chip->sub_type); |
| 1876 | rc = -EINVAL; |
| 1877 | } |
| 1878 | out: |
| 1879 | pr_debug("LPG rev 0x%02x subtype 0x%02x rc: %d\n", chip->revision, |
| 1880 | chip->sub_type, rc); |
| 1881 | return rc; |
| 1882 | } |
| 1883 | |
| 1884 | /* Fill in lpg device elements based on values found in device tree. */ |
| 1885 | static int qpnp_parse_dt_config(struct platform_device *pdev, |
| 1886 | struct qpnp_pwm_chip *chip) |
| 1887 | { |
| 1888 | int rc, enable, lut_entry_size, list_size, i; |
| 1889 | const char *label; |
| 1890 | const __be32 *prop; |
| 1891 | u32 size; |
| 1892 | struct device_node *node; |
| 1893 | int found_pwm_subnode = 0; |
| 1894 | int found_lpg_subnode = 0; |
| 1895 | struct device_node *of_node = pdev->dev.of_node; |
| 1896 | struct qpnp_lpg_config *lpg_config = &chip->lpg_config; |
| 1897 | struct qpnp_lut_config *lut_config = &lpg_config->lut_config; |
| 1898 | struct _qpnp_pwm_config *pwm_config = &chip->pwm_config; |
| 1899 | int force_pwm_size = 0; |
| 1900 | int pwm_size_list[QPNP_PWM_SIZES_SUPPORTED]; |
| 1901 | |
| 1902 | rc = of_property_read_u32(of_node, "qcom,channel-id", |
| 1903 | &chip->channel_id); |
| 1904 | if (rc) { |
| 1905 | dev_err(&pdev->dev, "%s: node is missing LPG channel id\n", |
| 1906 | __func__); |
| 1907 | return -EINVAL; |
| 1908 | } |
| 1909 | |
| 1910 | if (!of_get_property(of_node, "qcom,supported-sizes", &list_size)) { |
| 1911 | pr_err("Missing qcom,supported-size list\n"); |
| 1912 | return -EINVAL; |
| 1913 | } |
| 1914 | |
| 1915 | list_size /= sizeof(u32); |
| 1916 | if (list_size > QPNP_PWM_SIZES_SUPPORTED) { |
| 1917 | pr_err(" qcom,supported-size list is too big\n"); |
| 1918 | return -EINVAL; |
| 1919 | } |
| 1920 | |
| 1921 | rc = of_property_read_u32_array(of_node, "qcom,supported-sizes", |
| 1922 | pwm_size_list, list_size); |
| 1923 | |
| 1924 | if (rc) { |
| 1925 | pr_err("Invalid qcom,supported-size property\n"); |
| 1926 | return rc; |
| 1927 | } |
| 1928 | |
| 1929 | for (i = 0; i < list_size; i++) { |
| 1930 | pwm_config->supported_sizes |= |
| 1931 | (1 << (pwm_size_list[i] - QPNP_MIN_PWM_BIT_SIZE)); |
| 1932 | } |
| 1933 | |
| 1934 | if (!(pwm_config->supported_sizes == QPNP_PWM_SIZE_6_9_BIT || |
| 1935 | pwm_config->supported_sizes == QPNP_PWM_SIZE_7_8_BIT || |
| 1936 | pwm_config->supported_sizes == QPNP_PWM_SIZE_6_7_9_BIT)) { |
| 1937 | pr_err("PWM sizes list qcom,supported-size is not proper\n"); |
| 1938 | return -EINVAL; |
| 1939 | } |
| 1940 | |
| 1941 | /* |
| 1942 | * For cetrain LPG channels PWM size can be forced. So that |
| 1943 | * for every requested pwm period closest pwm frequency is |
| 1944 | * selected in qpnp_lpg_calc_period() for the forced pwm size. |
| 1945 | */ |
| 1946 | rc = of_property_read_u32(of_node, "qcom,force-pwm-size", |
| 1947 | &force_pwm_size); |
| 1948 | if (pwm_config->supported_sizes == QPNP_PWM_SIZE_7_8_BIT) { |
| 1949 | if (!(force_pwm_size == QPNP_PWM_SIZE_7_BIT || |
| 1950 | force_pwm_size == QPNP_PWM_SIZE_8_BIT)) |
| 1951 | force_pwm_size = 0; |
| 1952 | } else if (chip->sub_type == QPNP_PWM_MODE_ONLY_SUB_TYPE) { |
| 1953 | if (!(force_pwm_size == QPNP_PWM_SIZE_6_BIT || |
| 1954 | force_pwm_size == QPNP_PWM_SIZE_9_BIT)) |
| 1955 | force_pwm_size = 0; |
| 1956 | } else if (pwm_config->supported_sizes == QPNP_PWM_SIZE_6_7_9_BIT) { |
| 1957 | if (!(force_pwm_size == QPNP_PWM_SIZE_6_BIT || |
| 1958 | force_pwm_size == QPNP_PWM_SIZE_7_BIT || |
| 1959 | force_pwm_size == QPNP_PWM_SIZE_9_BIT)) |
| 1960 | force_pwm_size = 0; |
| 1961 | } |
| 1962 | |
| 1963 | pwm_config->force_pwm_size = force_pwm_size; |
| 1964 | |
| 1965 | |
| 1966 | prop = of_get_address_by_name(pdev->dev.of_node, QPNP_LPG_CHANNEL_BASE, |
| 1967 | 0, 0); |
| 1968 | if (!prop) { |
| 1969 | dev_err(&pdev->dev, "Couldnt find channel's base addr rc %d\n", |
| 1970 | rc); |
| 1971 | return rc; |
| 1972 | } |
| 1973 | lpg_config->base_addr = be32_to_cpu(*prop); |
| 1974 | |
| 1975 | rc = qpnp_lpg_get_rev_subtype(chip); |
| 1976 | if (rc) |
| 1977 | return rc; |
| 1978 | |
| 1979 | prop = of_get_address_by_name(pdev->dev.of_node, QPNP_LPG_LUT_BASE, |
| 1980 | 0, 0); |
| 1981 | if (!prop) { |
| 1982 | chip->flags |= QPNP_PWM_LUT_NOT_SUPPORTED; |
| 1983 | } else { |
| 1984 | lpg_config->lut_base_addr = be32_to_cpu(*prop); |
| 1985 | rc = of_property_read_u32(of_node, "qcom,lpg-lut-size", &size); |
| 1986 | if (rc < 0) { |
| 1987 | dev_err(&pdev->dev, "Error reading qcom,lpg-lut-size, rc=%d\n", |
| 1988 | rc); |
| 1989 | return rc; |
| 1990 | } |
| 1991 | |
| 1992 | /* |
| 1993 | * Each entry of LUT is of 2 bytes for generic LUT and of 1 byte |
| 1994 | * for KPDBL/GLED LUT. |
| 1995 | */ |
| 1996 | lpg_config->lut_size = size >> 1; |
| 1997 | lut_entry_size = sizeof(u16); |
| 1998 | |
| 1999 | if (pwm_config->supported_sizes == QPNP_PWM_SIZE_7_8_BIT) { |
| 2000 | lpg_config->lut_size = size; |
| 2001 | lut_entry_size = sizeof(u8); |
| 2002 | } |
| 2003 | |
| 2004 | lut_config->duty_pct_list = kcalloc(lpg_config->lut_size, |
| 2005 | lut_entry_size, GFP_KERNEL); |
| 2006 | if (!lut_config->duty_pct_list) |
| 2007 | return -ENOMEM; |
| 2008 | |
| 2009 | rc = of_property_read_u32(of_node, "qcom,ramp-index", |
| 2010 | &lut_config->ramp_index); |
| 2011 | if (rc) { |
| 2012 | pr_err("Missing LPG qcom,ramp-index property\n"); |
| 2013 | kfree(lut_config->duty_pct_list); |
| 2014 | return rc; |
| 2015 | } |
| 2016 | } |
| 2017 | |
| 2018 | rc = of_property_read_u32(of_node, "qcom,dtest-line", |
| 2019 | &chip->dtest_line); |
| 2020 | if (rc) { |
| 2021 | chip->in_test_mode = 0; |
| 2022 | } else { |
| 2023 | rc = of_property_read_u32(of_node, "qcom,dtest-output", |
| 2024 | &chip->dtest_output); |
| 2025 | if (rc) { |
| 2026 | pr_err("Missing DTEST output configuration\n"); |
| 2027 | return rc; |
| 2028 | } |
| 2029 | chip->in_test_mode = 1; |
| 2030 | } |
| 2031 | |
| 2032 | if (chip->in_test_mode) { |
| 2033 | if ((chip->sub_type == QPNP_PWM_MODE_ONLY_SUB_TYPE) && |
| 2034 | (chip->dtest_line > QPNP_PWM_DTEST_LINE_MAX || |
| 2035 | chip->dtest_output > QPNP_PWM_DTEST_OUTPUT_MAX)) { |
| 2036 | pr_err("DTEST line/output values are improper for PWM channel %d\n", |
| 2037 | chip->channel_id); |
| 2038 | return -EINVAL; |
| 2039 | } else if (chip->dtest_line > QPNP_LPG_DTEST_LINE_MAX || |
| 2040 | chip->dtest_output > QPNP_LPG_DTEST_OUTPUT_MAX) { |
| 2041 | pr_err("DTEST line/output values are improper for LPG channel %d\n", |
| 2042 | chip->channel_id); |
| 2043 | return -EINVAL; |
| 2044 | } |
| 2045 | } |
| 2046 | |
| 2047 | for_each_child_of_node(of_node, node) { |
| 2048 | rc = of_property_read_string(node, "label", &label); |
| 2049 | if (rc) { |
| 2050 | dev_err(&pdev->dev, "%s: Missing label property\n", |
| 2051 | __func__); |
| 2052 | goto out; |
| 2053 | } |
| 2054 | if (!strcmp(label, "pwm")) { |
| 2055 | rc = qpnp_parse_pwm_dt_config(node, of_node, chip); |
| 2056 | if (rc) |
| 2057 | goto out; |
| 2058 | found_pwm_subnode = 1; |
| 2059 | } else if (!strcmp(label, "lpg") && |
| 2060 | !(chip->flags & QPNP_PWM_LUT_NOT_SUPPORTED)) { |
| 2061 | rc = qpnp_parse_lpg_dt_config(node, of_node, chip); |
| 2062 | if (rc) |
| 2063 | goto out; |
| 2064 | found_lpg_subnode = 1; |
| 2065 | } else { |
| 2066 | dev_err(&pdev->dev, |
| 2067 | "%s: Invalid value for lable prop", |
| 2068 | __func__); |
| 2069 | } |
| 2070 | } |
| 2071 | |
| 2072 | rc = of_property_read_u32(of_node, "qcom,mode-select", &enable); |
| 2073 | if (rc) |
| 2074 | goto read_opt_props; |
| 2075 | |
| 2076 | if ((enable == PM_PWM_MODE_PWM && found_pwm_subnode == 0) || |
| 2077 | (enable == PM_PWM_MODE_LPG && found_lpg_subnode == 0)) { |
| 2078 | dev_err(&pdev->dev, "%s: Invalid mode select\n", __func__); |
| 2079 | rc = -EINVAL; |
| 2080 | goto out; |
| 2081 | } |
| 2082 | |
| 2083 | _pwm_change_mode(chip, enable); |
| 2084 | _pwm_enable(chip); |
| 2085 | |
| 2086 | read_opt_props: |
| 2087 | /* Initialize optional config parameters from DT if provided */ |
| 2088 | of_property_read_string(node, "qcom,channel-owner", |
| 2089 | &chip->channel_owner); |
| 2090 | |
| 2091 | return 0; |
| 2092 | |
| 2093 | out: |
| 2094 | kfree(lut_config->duty_pct_list); |
| 2095 | return rc; |
| 2096 | } |
| 2097 | |
| 2098 | static struct pwm_ops qpnp_pwm_ops = { |
| 2099 | .enable = qpnp_pwm_enable, |
| 2100 | .disable = qpnp_pwm_disable, |
| 2101 | .config = qpnp_pwm_config, |
| 2102 | .free = qpnp_pwm_free, |
| 2103 | .owner = THIS_MODULE, |
| 2104 | }; |
| 2105 | |
| 2106 | static int qpnp_pwm_probe(struct platform_device *pdev) |
| 2107 | { |
| 2108 | struct qpnp_pwm_chip *pwm_chip; |
| 2109 | int rc; |
| 2110 | |
| 2111 | pwm_chip = kzalloc(sizeof(*pwm_chip), GFP_KERNEL); |
| 2112 | if (pwm_chip == NULL) |
| 2113 | return -ENOMEM; |
| 2114 | |
| 2115 | pwm_chip->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
| 2116 | if (!pwm_chip->regmap) { |
| 2117 | dev_err(&pdev->dev, "Couldn't get parent's regmap\n"); |
| 2118 | return -EINVAL; |
| 2119 | } |
| 2120 | |
| 2121 | spin_lock_init(&pwm_chip->lpg_lock); |
| 2122 | |
| 2123 | pwm_chip->pdev = pdev; |
| 2124 | dev_set_drvdata(&pdev->dev, pwm_chip); |
| 2125 | |
| 2126 | rc = qpnp_parse_dt_config(pdev, pwm_chip); |
| 2127 | |
| 2128 | if (rc) { |
| 2129 | pr_err("Failed parsing DT parameters, rc=%d\n", rc); |
| 2130 | goto failed_config; |
| 2131 | } |
| 2132 | |
| 2133 | pwm_chip->chip.dev = &pdev->dev; |
| 2134 | pwm_chip->chip.ops = &qpnp_pwm_ops; |
| 2135 | pwm_chip->chip.base = -1; |
| 2136 | pwm_chip->chip.npwm = 1; |
| 2137 | |
| 2138 | rc = pwmchip_add(&pwm_chip->chip); |
| 2139 | if (rc < 0) { |
| 2140 | pr_err("pwmchip_add() failed: %d\n", rc); |
| 2141 | goto failed_insert; |
| 2142 | } |
| 2143 | |
| 2144 | if (pwm_chip->channel_owner) |
| 2145 | pwm_chip->chip.pwms[0].label = pwm_chip->channel_owner; |
| 2146 | |
| 2147 | pr_debug("PWM device channel:%d probed successfully\n", |
| 2148 | pwm_chip->channel_id); |
| 2149 | return 0; |
| 2150 | |
| 2151 | failed_insert: |
| 2152 | kfree(pwm_chip->lpg_config.lut_config.duty_pct_list); |
| 2153 | failed_config: |
| 2154 | dev_set_drvdata(&pdev->dev, NULL); |
| 2155 | kfree(pwm_chip); |
| 2156 | return rc; |
| 2157 | } |
| 2158 | |
| 2159 | static int qpnp_pwm_remove(struct platform_device *pdev) |
| 2160 | { |
| 2161 | struct qpnp_pwm_chip *pwm_chip; |
| 2162 | struct qpnp_lpg_config *lpg_config; |
| 2163 | |
| 2164 | pwm_chip = dev_get_drvdata(&pdev->dev); |
| 2165 | |
| 2166 | dev_set_drvdata(&pdev->dev, NULL); |
| 2167 | |
| 2168 | if (pwm_chip) { |
| 2169 | lpg_config = &pwm_chip->lpg_config; |
| 2170 | pwmchip_remove(&pwm_chip->chip); |
| 2171 | kfree(lpg_config->lut_config.duty_pct_list); |
| 2172 | kfree(pwm_chip); |
| 2173 | } |
| 2174 | |
| 2175 | return 0; |
| 2176 | } |
| 2177 | |
| 2178 | static const struct of_device_id spmi_match_table[] = { |
| 2179 | { .compatible = QPNP_LPG_DRIVER_NAME, }, |
| 2180 | {} |
| 2181 | }; |
| 2182 | |
| 2183 | static const struct platform_device_id qpnp_lpg_id[] = { |
| 2184 | { QPNP_LPG_DRIVER_NAME, 0 }, |
| 2185 | { } |
| 2186 | }; |
| 2187 | MODULE_DEVICE_TABLE(spmi, qpnp_lpg_id); |
| 2188 | |
| 2189 | static struct platform_driver qpnp_lpg_driver = { |
| 2190 | .driver = { |
| 2191 | .name = QPNP_LPG_DRIVER_NAME, |
| 2192 | .of_match_table = spmi_match_table, |
| 2193 | .owner = THIS_MODULE, |
| 2194 | }, |
| 2195 | .probe = qpnp_pwm_probe, |
| 2196 | .remove = qpnp_pwm_remove, |
| 2197 | .id_table = qpnp_lpg_id, |
| 2198 | }; |
| 2199 | |
| 2200 | /** |
| 2201 | * qpnp_lpg_init() - register spmi driver for qpnp-lpg |
| 2202 | */ |
| 2203 | int __init qpnp_lpg_init(void) |
| 2204 | { |
| 2205 | return platform_driver_register(&qpnp_lpg_driver); |
| 2206 | } |
| 2207 | |
| 2208 | static void __exit qpnp_lpg_exit(void) |
| 2209 | { |
| 2210 | platform_driver_unregister(&qpnp_lpg_driver); |
| 2211 | } |
| 2212 | |
| 2213 | MODULE_DESCRIPTION("QPNP PMIC LPG driver"); |
| 2214 | MODULE_LICENSE("GPL v2"); |
| 2215 | MODULE_ALIAS("platform:" QPNP_LPG_DRIVER_NAME); |
| 2216 | |
| 2217 | subsys_initcall(qpnp_lpg_init); |
| 2218 | module_exit(qpnp_lpg_exit); |