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Shawn Guod9654dc2014-05-13 21:46:16 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/irqchip.h>
10#include <linux/of_platform.h>
Fugang Duan8f0b2872014-09-24 10:11:19 +080011#include <linux/phy.h>
12#include <linux/regmap.h>
13#include <linux/mfd/syscon.h>
14#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
Shawn Guod9654dc2014-05-13 21:46:16 +080015#include <asm/mach/arch.h>
16#include <asm/mach/map.h>
17
18#include "common.h"
Anson Huanga25d67a2014-06-20 13:44:05 +080019#include "cpuidle.h"
Shawn Guod9654dc2014-05-13 21:46:16 +080020
Fugang Duan8f0b2872014-09-24 10:11:19 +080021static int ar8031_phy_fixup(struct phy_device *dev)
22{
23 u16 val;
24
25 /* Set RGMII IO voltage to 1.8V */
26 phy_write(dev, 0x1d, 0x1f);
27 phy_write(dev, 0x1e, 0x8);
28
29 /* introduce tx clock delay */
30 phy_write(dev, 0x1d, 0x5);
31 val = phy_read(dev, 0x1e);
32 val |= 0x0100;
33 phy_write(dev, 0x1e, val);
34
35 return 0;
36}
37
38#define PHY_ID_AR8031 0x004dd074
39static void __init imx6sx_enet_phy_init(void)
40{
41 if (IS_BUILTIN(CONFIG_PHYLIB))
42 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
43 ar8031_phy_fixup);
44}
45
46static void __init imx6sx_enet_clk_sel(void)
47{
48 struct regmap *gpr;
49
50 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");
51 if (!IS_ERR(gpr)) {
52 regmap_update_bits(gpr, IOMUXC_GPR1,
53 IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0);
54 regmap_update_bits(gpr, IOMUXC_GPR1,
55 IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0);
56 } else {
57 pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");
58 }
59}
60
61static inline void imx6sx_enet_init(void)
62{
63 imx6sx_enet_phy_init();
64 imx6sx_enet_clk_sel();
65}
66
Shawn Guod9654dc2014-05-13 21:46:16 +080067static void __init imx6sx_init_machine(void)
68{
69 struct device *parent;
70
Shawn Guod9654dc2014-05-13 21:46:16 +080071 parent = imx_soc_device_init();
72 if (parent == NULL)
73 pr_warn("failed to initialize soc device\n");
74
Kefeng Wang435ebcb2016-06-01 14:53:05 +080075 of_platform_default_populate(NULL, NULL, parent);
Shawn Guod9654dc2014-05-13 21:46:16 +080076
Fugang Duan8f0b2872014-09-24 10:11:19 +080077 imx6sx_enet_init();
Shawn Guod9654dc2014-05-13 21:46:16 +080078 imx_anatop_init();
Anson Huangff843d62014-06-20 13:20:54 +080079 imx6sx_pm_init();
Shawn Guod9654dc2014-05-13 21:46:16 +080080}
81
82static void __init imx6sx_init_irq(void)
83{
Marc Zyngier14517562015-03-13 16:05:37 +000084 imx_gpc_check_dt();
Shawn Guod9654dc2014-05-13 21:46:16 +080085 imx_init_revision_from_anatop();
86 imx_init_l2cache();
87 imx_src_init();
Shawn Guod9654dc2014-05-13 21:46:16 +080088 irqchip_init();
Shawn Guo35e29162015-04-29 13:07:03 +080089 imx6_pm_ccm_init("fsl,imx6sx-ccm");
Shawn Guod9654dc2014-05-13 21:46:16 +080090}
91
Anson Huanga25d67a2014-06-20 13:44:05 +080092static void __init imx6sx_init_late(void)
93{
Anson Huang05136f02014-12-17 12:24:12 +080094 imx6sx_cpuidle_init();
Anson Huang47526e42014-06-25 17:10:12 +080095
96 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
97 platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
Anson Huanga25d67a2014-06-20 13:44:05 +080098}
99
Shawn Guo8756dd92014-07-01 16:03:00 +0800100static const char * const imx6sx_dt_compat[] __initconst = {
Shawn Guod9654dc2014-05-13 21:46:16 +0800101 "fsl,imx6sx",
102 NULL,
103};
104
105DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
Andrey Smirnov510aca62016-06-18 18:09:31 -0700106 .l2c_aux_val = 0,
107 .l2c_aux_mask = ~0,
Shawn Guod9654dc2014-05-13 21:46:16 +0800108 .init_irq = imx6sx_init_irq,
109 .init_machine = imx6sx_init_machine,
110 .dt_compat = imx6sx_dt_compat,
Anson Huanga25d67a2014-06-20 13:44:05 +0800111 .init_late = imx6sx_init_late,
Shawn Guod9654dc2014-05-13 21:46:16 +0800112MACHINE_END