blob: 806506c03a79de988ae5dad19a6fbfeb0637268b [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
David Howells760285e2012-10-02 18:01:07 +010028#include <drm/drmP.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020029#include "radeon.h"
David Howells760285e2012-10-02 18:01:07 +010030#include <drm/radeon_drm.h>
Marek Olšák6759a0a2012-08-09 16:34:17 +020031#include "radeon_asic.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020032
Dave Airlie6a9ee8a2010-02-01 15:38:10 +100033#include <linux/vga_switcheroo.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090034#include <linux/slab.h>
Dave Airlie10ebc0b2012-09-17 14:40:31 +100035#include <linux/pm_runtime.h>
Alex Deucherf482a142012-07-17 14:02:34 -040036/**
37 * radeon_driver_unload_kms - Main unload function for KMS.
38 *
39 * @dev: drm dev pointer
40 *
41 * This is the main unload function for KMS (all asics).
42 * It calls radeon_modeset_fini() to tear down the
43 * displays, and radeon_device_fini() to tear down
44 * the rest of the device (CP, writeback, etc.).
45 * Returns 0 on success.
46 */
Jerome Glissecf0fe452009-12-09 18:21:55 +010047int radeon_driver_unload_kms(struct drm_device *dev)
48{
49 struct radeon_device *rdev = dev->dev_private;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020050
Jerome Glissecf0fe452009-12-09 18:21:55 +010051 if (rdev == NULL)
52 return 0;
Dave Airlie10ebc0b2012-09-17 14:40:31 +100053
Alex Deucher0cd9cb72013-04-12 19:15:52 -040054 if (rdev->rmmio == NULL)
55 goto done_free;
Dave Airlie10ebc0b2012-09-17 14:40:31 +100056
57 pm_runtime_get_sync(dev->dev);
58
Alex Deucherc4917072012-07-31 17:14:35 -040059 radeon_acpi_fini(rdev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +100060
Jerome Glissecf0fe452009-12-09 18:21:55 +010061 radeon_modeset_fini(rdev);
62 radeon_device_fini(rdev);
Alex Deucher0cd9cb72013-04-12 19:15:52 -040063
64done_free:
Jerome Glissecf0fe452009-12-09 18:21:55 +010065 kfree(rdev);
66 dev->dev_private = NULL;
67 return 0;
68}
69
Alex Deucherf482a142012-07-17 14:02:34 -040070/**
71 * radeon_driver_load_kms - Main load function for KMS.
72 *
73 * @dev: drm dev pointer
74 * @flags: device flags
75 *
76 * This is the main load function for KMS (all asics).
77 * It calls radeon_device_init() to set up the non-display
78 * parts of the chip (asic init, CP, writeback, etc.), and
79 * radeon_modeset_init() to set up the display parts
80 * (crtcs, encoders, hotplug detect, etc.).
81 * Returns 0 on success, error on failure.
82 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +020083int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
84{
85 struct radeon_device *rdev;
Alberto Miloned7a29522010-07-06 11:40:24 -040086 int r, acpi_status;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020087
88 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
89 if (rdev == NULL) {
90 return -ENOMEM;
91 }
92 dev->dev_private = (void *)rdev;
93
94 /* update BUS flag */
Dave Airlie8410ea32010-12-15 03:16:38 +100095 if (drm_pci_device_is_agp(dev)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +020096 flags |= RADEON_IS_AGP;
Jon Mason58b65422011-06-27 16:07:50 +000097 } else if (pci_is_pcie(dev->pdev)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +020098 flags |= RADEON_IS_PCIE;
99 } else {
100 flags |= RADEON_IS_PCI;
101 }
102
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +0200103 /* radeon_device_init should report only fatal error
104 * like memory allocation failure or iomapping failure,
105 * or memory manager initialization failure, it must
106 * properly initialize the GPU MC controller and permit
107 * VRAM allocation
108 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200109 r = radeon_device_init(rdev, dev, dev->pdev, flags);
110 if (r) {
Jerome Glissecf0fe452009-12-09 18:21:55 +0100111 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
112 goto out;
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +0200113 }
Alberto Miloned7a29522010-07-06 11:40:24 -0400114
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +0200115 /* Again modeset_init should fail only on fatal error
116 * otherwise it should provide enough functionalities
117 * for shadowfb to run
118 */
119 r = radeon_modeset_init(rdev);
Jerome Glissecf0fe452009-12-09 18:21:55 +0100120 if (r)
121 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
Luca Tettamantifda4b252012-07-30 21:20:35 +0200122
123 /* Call ACPI methods: require modeset init
124 * but failure is not fatal
125 */
126 if (!r) {
127 acpi_status = radeon_acpi_init(rdev);
128 if (acpi_status)
129 dev_dbg(&dev->pdev->dev,
130 "Error during ACPI methods call\n");
131 }
132
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000133 if (radeon_runtime_pm != 0) {
134 pm_runtime_use_autosuspend(dev->dev);
135 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
136 pm_runtime_set_active(dev->dev);
137 pm_runtime_allow(dev->dev);
138 pm_runtime_mark_last_busy(dev->dev);
139 pm_runtime_put_autosuspend(dev->dev);
140 }
141
Jerome Glissecf0fe452009-12-09 18:21:55 +0100142out:
143 if (r)
144 radeon_driver_unload_kms(dev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000145
146
Jerome Glissecf0fe452009-12-09 18:21:55 +0100147 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200148}
149
Alex Deucherf482a142012-07-17 14:02:34 -0400150/**
151 * radeon_set_filp_rights - Set filp right.
152 *
153 * @dev: drm dev pointer
154 * @owner: drm file
155 * @applier: drm file
156 * @value: value
157 *
158 * Sets the filp rights for the device (all asics).
159 */
Marek Olšák9eba4a92011-01-05 05:46:48 +0100160static void radeon_set_filp_rights(struct drm_device *dev,
161 struct drm_file **owner,
162 struct drm_file *applier,
163 uint32_t *value)
164{
165 mutex_lock(&dev->struct_mutex);
166 if (*value == 1) {
167 /* wants rights */
168 if (!*owner)
169 *owner = applier;
170 } else if (*value == 0) {
171 /* revokes rights */
172 if (*owner == applier)
173 *owner = NULL;
174 }
175 *value = *owner == applier ? 1 : 0;
176 mutex_unlock(&dev->struct_mutex);
177}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200178
179/*
Marek Olšák9eba4a92011-01-05 05:46:48 +0100180 * Userspace get information ioctl
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200181 */
Alex Deucherf482a142012-07-17 14:02:34 -0400182/**
183 * radeon_info_ioctl - answer a device specific request.
184 *
185 * @rdev: radeon device pointer
186 * @data: request object
187 * @filp: drm filp
188 *
189 * This function is used to pass device specific parameters to the userspace
190 * drivers. Examples include: pci device id, pipeline parms, tiling params,
191 * etc. (all asics).
192 * Returns 0 on success, -EINVAL on failure.
193 */
Rashika Kheria55203452014-01-06 20:53:07 +0530194static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200195{
196 struct radeon_device *rdev = dev->dev_private;
Marek Olšák6759a0a2012-08-09 16:34:17 +0200197 struct drm_radeon_info *info = data;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200198 struct radeon_mode_info *minfo = &rdev->mode_info;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400199 uint32_t *value, value_tmp, *value_ptr, value_size;
200 uint64_t value64;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200201 struct drm_crtc *crtc;
202 int i, found;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200203
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200204 value_ptr = (uint32_t *)((unsigned long)info->value);
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400205 value = &value_tmp;
206 value_size = sizeof(uint32_t);
Dr. David Alan Gilbertd8ab3552010-08-02 09:43:52 +1000207
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200208 switch (info->request) {
209 case RADEON_INFO_DEVICE_ID:
Ville Syrjäläffbab09b2013-10-04 14:53:40 +0300210 *value = dev->pdev->device;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200211 break;
212 case RADEON_INFO_NUM_GB_PIPES:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400213 *value = rdev->num_gb_pipes;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200214 break;
Alex Deucherf779b3e2009-08-19 19:11:39 -0400215 case RADEON_INFO_NUM_Z_PIPES:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400216 *value = rdev->num_z_pipes;
Alex Deucherf779b3e2009-08-19 19:11:39 -0400217 break;
Jerome Glisse733289c2009-09-16 15:24:21 +0200218 case RADEON_INFO_ACCEL_WORKING:
Alex Deucher148a03b2010-06-03 19:00:03 -0400219 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
220 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400221 *value = false;
Alex Deucher148a03b2010-06-03 19:00:03 -0400222 else
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400223 *value = rdev->accel_working;
Jerome Glisse733289c2009-09-16 15:24:21 +0200224 break;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200225 case RADEON_INFO_CRTC_FROM_ID:
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100226 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400227 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
228 return -EFAULT;
229 }
Jerome Glissebc35afd2010-05-12 18:01:13 +0200230 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
231 crtc = (struct drm_crtc *)minfo->crtcs[i];
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400232 if (crtc && crtc->base.id == *value) {
Alex Deucher0baf2d82010-07-21 14:05:35 -0400233 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400234 *value = radeon_crtc->crtc_id;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200235 found = 1;
236 break;
237 }
238 }
239 if (!found) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400240 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
Jerome Glissebc35afd2010-05-12 18:01:13 +0200241 return -EINVAL;
242 }
243 break;
Alex Deucher148a03b2010-06-03 19:00:03 -0400244 case RADEON_INFO_ACCEL_WORKING2:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400245 *value = rdev->accel_working;
Alex Deucher148a03b2010-06-03 19:00:03 -0400246 break;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400247 case RADEON_INFO_TILING_CONFIG:
Alex Deucher64f759c2012-07-06 17:40:32 -0400248 if (rdev->family >= CHIP_BONAIRE)
249 *value = rdev->config.cik.tile_config;
250 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400251 *value = rdev->config.si.tile_config;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400252 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400253 *value = rdev->config.cayman.tile_config;
Alex Deucherfecf1d02011-03-02 20:07:29 -0500254 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400255 *value = rdev->config.evergreen.tile_config;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400256 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400257 *value = rdev->config.rv770.tile_config;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400258 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400259 *value = rdev->config.r600.tile_config;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400260 else {
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000261 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400262 return -EINVAL;
263 }
Alex Deucherb824b362010-08-12 08:25:47 -0400264 break;
Dave Airlieab9e1f52010-07-13 11:11:11 +1000265 case RADEON_INFO_WANT_HYPERZ:
Marek Olšák43861f72010-08-07 03:36:34 +0200266 /* The "value" here is both an input and output parameter.
267 * If the input value is 1, filp requests hyper-z access.
268 * If the input value is 0, filp revokes its hyper-z access.
269 *
270 * When returning, the value is 1 if filp owns hyper-z access,
271 * 0 otherwise. */
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100272 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400273 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
274 return -EFAULT;
275 }
276 if (*value >= 2) {
277 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
Marek Olšák43861f72010-08-07 03:36:34 +0200278 return -EINVAL;
Dave Airlieab9e1f52010-07-13 11:11:11 +1000279 }
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400280 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
Marek Olšák9eba4a92011-01-05 05:46:48 +0100281 break;
282 case RADEON_INFO_WANT_CMASK:
283 /* The same logic as Hyper-Z. */
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100284 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400285 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
286 return -EFAULT;
287 }
288 if (*value >= 2) {
289 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
Marek Olšák9eba4a92011-01-05 05:46:48 +0100290 return -EINVAL;
Marek Olšák43861f72010-08-07 03:36:34 +0200291 }
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400292 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400293 break;
Alex Deucher58bbf012011-01-24 17:14:26 -0500294 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
295 /* return clock value in KHz */
Alex Deucher454d2e22013-02-14 10:04:02 -0500296 if (rdev->asic->get_xclk)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400297 *value = radeon_get_xclk(rdev) * 10;
Alex Deucher454d2e22013-02-14 10:04:02 -0500298 else
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400299 *value = rdev->clock.spll.reference_freq * 10;
Alex Deucher58bbf012011-01-24 17:14:26 -0500300 break;
Dave Airlie486af182011-03-01 14:32:27 +1000301 case RADEON_INFO_NUM_BACKENDS:
Alex Deucher64f759c2012-07-06 17:40:32 -0400302 if (rdev->family >= CHIP_BONAIRE)
303 *value = rdev->config.cik.max_backends_per_se *
304 rdev->config.cik.max_shader_engines;
305 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400306 *value = rdev->config.si.max_backends_per_se *
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400307 rdev->config.si.max_shader_engines;
308 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400309 *value = rdev->config.cayman.max_backends_per_se *
Alex Deucherfecf1d02011-03-02 20:07:29 -0500310 rdev->config.cayman.max_shader_engines;
311 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400312 *value = rdev->config.evergreen.max_backends;
Dave Airlie486af182011-03-01 14:32:27 +1000313 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400314 *value = rdev->config.rv770.max_backends;
Dave Airlie486af182011-03-01 14:32:27 +1000315 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400316 *value = rdev->config.r600.max_backends;
Dave Airlie486af182011-03-01 14:32:27 +1000317 else {
318 return -EINVAL;
319 }
320 break;
Alex Deucher65659452011-04-26 13:27:43 -0400321 case RADEON_INFO_NUM_TILE_PIPES:
Alex Deucher64f759c2012-07-06 17:40:32 -0400322 if (rdev->family >= CHIP_BONAIRE)
323 *value = rdev->config.cik.max_tile_pipes;
324 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400325 *value = rdev->config.si.max_tile_pipes;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400326 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400327 *value = rdev->config.cayman.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400328 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400329 *value = rdev->config.evergreen.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400330 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400331 *value = rdev->config.rv770.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400332 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400333 *value = rdev->config.r600.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400334 else {
335 return -EINVAL;
336 }
337 break;
Alex Deucher8aeb96f2011-05-03 19:28:02 -0400338 case RADEON_INFO_FUSION_GART_WORKING:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400339 *value = 1;
Alex Deucher8aeb96f2011-05-03 19:28:02 -0400340 break;
Alex Deuchere55b9422011-07-15 19:53:52 +0000341 case RADEON_INFO_BACKEND_MAP:
Alex Deucher64f759c2012-07-06 17:40:32 -0400342 if (rdev->family >= CHIP_BONAIRE)
Michel Dänzer1ddce272013-11-18 18:25:59 +0900343 *value = rdev->config.cik.backend_map;
Alex Deucher64f759c2012-07-06 17:40:32 -0400344 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400345 *value = rdev->config.si.backend_map;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400346 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400347 *value = rdev->config.cayman.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000348 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400349 *value = rdev->config.evergreen.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000350 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400351 *value = rdev->config.rv770.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000352 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400353 *value = rdev->config.r600.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000354 else {
355 return -EINVAL;
356 }
357 break;
Jerome Glisse721604a2012-01-05 22:11:05 -0500358 case RADEON_INFO_VA_START:
359 /* this is where we report if vm is supported or not */
360 if (rdev->family < CHIP_CAYMAN)
361 return -EINVAL;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400362 *value = RADEON_VA_RESERVED_SIZE;
Jerome Glisse721604a2012-01-05 22:11:05 -0500363 break;
364 case RADEON_INFO_IB_VM_MAX_SIZE:
365 /* this is where we report if vm is supported or not */
366 if (rdev->family < CHIP_CAYMAN)
367 return -EINVAL;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400368 *value = RADEON_IB_VM_MAX_SIZE;
Jerome Glisse721604a2012-01-05 22:11:05 -0500369 break;
Tom Stellard609c1e12012-03-20 17:17:55 -0400370 case RADEON_INFO_MAX_PIPES:
Alex Deucher64f759c2012-07-06 17:40:32 -0400371 if (rdev->family >= CHIP_BONAIRE)
372 *value = rdev->config.cik.max_cu_per_sh;
373 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400374 *value = rdev->config.si.max_cu_per_sh;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400375 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400376 *value = rdev->config.cayman.max_pipes_per_simd;
Tom Stellard609c1e12012-03-20 17:17:55 -0400377 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400378 *value = rdev->config.evergreen.max_pipes;
Tom Stellard609c1e12012-03-20 17:17:55 -0400379 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400380 *value = rdev->config.rv770.max_pipes;
Tom Stellard609c1e12012-03-20 17:17:55 -0400381 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400382 *value = rdev->config.r600.max_pipes;
Tom Stellard609c1e12012-03-20 17:17:55 -0400383 else {
384 return -EINVAL;
385 }
386 break;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400387 case RADEON_INFO_TIMESTAMP:
388 if (rdev->family < CHIP_R600) {
389 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
390 return -EINVAL;
391 }
392 value = (uint32_t*)&value64;
393 value_size = sizeof(uint64_t);
394 value64 = radeon_get_gpu_clock_counter(rdev);
395 break;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500396 case RADEON_INFO_MAX_SE:
Alex Deucher64f759c2012-07-06 17:40:32 -0400397 if (rdev->family >= CHIP_BONAIRE)
398 *value = rdev->config.cik.max_shader_engines;
399 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400400 *value = rdev->config.si.max_shader_engines;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500401 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400402 *value = rdev->config.cayman.max_shader_engines;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500403 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400404 *value = rdev->config.evergreen.num_ses;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500405 else
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400406 *value = 1;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500407 break;
408 case RADEON_INFO_MAX_SH_PER_SE:
Alex Deucher64f759c2012-07-06 17:40:32 -0400409 if (rdev->family >= CHIP_BONAIRE)
410 *value = rdev->config.cik.max_sh_per_se;
411 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400412 *value = rdev->config.si.max_sh_per_se;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500413 else
414 return -EINVAL;
415 break;
Samuel Lia0a53aa2013-04-08 17:25:47 -0400416 case RADEON_INFO_FASTFB_WORKING:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400417 *value = rdev->fastfb_working;
Samuel Lia0a53aa2013-04-08 17:25:47 -0400418 break;
Christian König902aaef2013-04-09 10:35:42 -0400419 case RADEON_INFO_RING_WORKING:
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100420 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400421 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
422 return -EFAULT;
423 }
424 switch (*value) {
Christian König902aaef2013-04-09 10:35:42 -0400425 case RADEON_CS_RING_GFX:
426 case RADEON_CS_RING_COMPUTE:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400427 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
Christian König902aaef2013-04-09 10:35:42 -0400428 break;
429 case RADEON_CS_RING_DMA:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400430 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
431 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
Christian König902aaef2013-04-09 10:35:42 -0400432 break;
433 case RADEON_CS_RING_UVD:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400434 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
Christian König902aaef2013-04-09 10:35:42 -0400435 break;
Christian Königf7ba8b02014-01-27 10:16:06 -0700436 case RADEON_CS_RING_VCE:
437 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
438 break;
Christian König902aaef2013-04-09 10:35:42 -0400439 default:
440 return -EINVAL;
441 }
442 break;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400443 case RADEON_INFO_SI_TILE_MODE_ARRAY:
Alex Deucher64f759c2012-07-06 17:40:32 -0400444 if (rdev->family >= CHIP_BONAIRE) {
Alex Deucher39aee492013-04-10 13:41:25 -0400445 value = rdev->config.cik.tile_mode_array;
446 value_size = sizeof(uint32_t)*32;
447 } else if (rdev->family >= CHIP_TAHITI) {
448 value = rdev->config.si.tile_mode_array;
449 value_size = sizeof(uint32_t)*32;
450 } else {
451 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
Alex Deucher64f759c2012-07-06 17:40:32 -0400452 return -EINVAL;
453 }
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400454 break;
Michel Dänzer32f79a82013-11-18 18:26:00 +0900455 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
456 if (rdev->family >= CHIP_BONAIRE) {
457 value = rdev->config.cik.macrotile_mode_array;
458 value_size = sizeof(uint32_t)*16;
459 } else {
460 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
461 return -EINVAL;
462 }
463 break;
Tom Stellarde5b9e752013-08-16 17:47:39 -0400464 case RADEON_INFO_SI_CP_DMA_COMPUTE:
465 *value = 1;
466 break;
Marek Olšák439a1cf2013-12-22 02:18:01 +0100467 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
468 if (rdev->family >= CHIP_BONAIRE) {
469 *value = rdev->config.cik.backend_enable_mask;
470 } else if (rdev->family >= CHIP_TAHITI) {
471 *value = rdev->config.si.backend_enable_mask;
472 } else {
473 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
474 }
475 break;
Alex Deucherf5f1f892014-01-20 18:20:29 -0500476 case RADEON_INFO_MAX_SCLK:
477 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
478 rdev->pm.dpm_enabled)
479 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
480 else
481 *value = rdev->pm.default_sclk * 10;
482 break;
Christian König98ccc292014-01-23 09:50:49 -0700483 case RADEON_INFO_VCE_FW_VERSION:
484 *value = rdev->vce.fw_version;
485 break;
486 case RADEON_INFO_VCE_FB_VERSION:
487 *value = rdev->vce.fb_version;
488 break;
Marek Olšák67e8e3f2014-03-02 00:56:18 +0100489 case RADEON_INFO_NUM_BYTES_MOVED:
490 value = (uint32_t*)&value64;
491 value_size = sizeof(uint64_t);
492 value64 = atomic64_read(&rdev->num_bytes_moved);
493 break;
494 case RADEON_INFO_VRAM_USAGE:
495 value = (uint32_t*)&value64;
496 value_size = sizeof(uint64_t);
497 value64 = atomic64_read(&rdev->vram_usage);
498 break;
499 case RADEON_INFO_GTT_USAGE:
500 value = (uint32_t*)&value64;
501 value_size = sizeof(uint64_t);
502 value64 = atomic64_read(&rdev->gtt_usage);
503 break;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200504 default:
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000505 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200506 return -EINVAL;
507 }
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100508 if (copy_to_user(value_ptr, (char*)value, value_size)) {
Marek Olšák6759a0a2012-08-09 16:34:17 +0200509 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200510 return -EFAULT;
511 }
512 return 0;
513}
514
515
516/*
517 * Outdated mess for old drm with Xorg being in charge (void function now).
518 */
Alex Deucherf482a142012-07-17 14:02:34 -0400519/**
Alex Deucherf482a142012-07-17 14:02:34 -0400520 * radeon_driver_firstopen_kms - drm callback for last close
521 *
522 * @dev: drm dev pointer
523 *
524 * Switch vga switcheroo state after last close (all asics).
525 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200526void radeon_driver_lastclose_kms(struct drm_device *dev)
527{
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000528 vga_switcheroo_process_delayed_switch();
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200529}
530
Alex Deucherf482a142012-07-17 14:02:34 -0400531/**
532 * radeon_driver_open_kms - drm callback for open
533 *
534 * @dev: drm dev pointer
535 * @file_priv: drm file
536 *
537 * On device open, init vm on cayman+ (all asics).
538 * Returns 0 on success, error on failure.
539 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200540int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
541{
Jerome Glisse721604a2012-01-05 22:11:05 -0500542 struct radeon_device *rdev = dev->dev_private;
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000543 int r;
Jerome Glisse721604a2012-01-05 22:11:05 -0500544
545 file_priv->driver_priv = NULL;
546
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000547 r = pm_runtime_get_sync(dev->dev);
548 if (r < 0)
549 return r;
550
Jerome Glisse721604a2012-01-05 22:11:05 -0500551 /* new gpu have virtual address space support */
552 if (rdev->family >= CHIP_CAYMAN) {
553 struct radeon_fpriv *fpriv;
Christian Königd72d43c2012-10-09 13:31:18 +0200554 struct radeon_bo_va *bo_va;
Jerome Glisse721604a2012-01-05 22:11:05 -0500555 int r;
556
557 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
558 if (unlikely(!fpriv)) {
559 return -ENOMEM;
560 }
561
Christian Königd72d43c2012-10-09 13:31:18 +0200562 radeon_vm_init(rdev, &fpriv->vm);
563
564 /* map the ib pool buffer read only into
565 * virtual address space */
566 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
567 rdev->ring_tmp_bo.bo);
568 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
569 RADEON_VM_PAGE_READABLE |
570 RADEON_VM_PAGE_SNOOPED);
Jerome Glisse721604a2012-01-05 22:11:05 -0500571 if (r) {
572 radeon_vm_fini(rdev, &fpriv->vm);
573 kfree(fpriv);
574 return r;
575 }
576
577 file_priv->driver_priv = fpriv;
578 }
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000579
580 pm_runtime_mark_last_busy(dev->dev);
581 pm_runtime_put_autosuspend(dev->dev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200582 return 0;
583}
584
Alex Deucherf482a142012-07-17 14:02:34 -0400585/**
586 * radeon_driver_postclose_kms - drm callback for post close
587 *
588 * @dev: drm dev pointer
589 * @file_priv: drm file
590 *
591 * On device post close, tear down vm on cayman+ (all asics).
592 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200593void radeon_driver_postclose_kms(struct drm_device *dev,
594 struct drm_file *file_priv)
595{
Jerome Glisse721604a2012-01-05 22:11:05 -0500596 struct radeon_device *rdev = dev->dev_private;
597
598 /* new gpu have virtual address space support */
599 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
600 struct radeon_fpriv *fpriv = file_priv->driver_priv;
Christian Königd72d43c2012-10-09 13:31:18 +0200601 struct radeon_bo_va *bo_va;
602 int r;
603
604 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
605 if (!r) {
606 bo_va = radeon_vm_bo_find(&fpriv->vm,
607 rdev->ring_tmp_bo.bo);
608 if (bo_va)
609 radeon_vm_bo_rmv(rdev, bo_va);
610 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
611 }
Jerome Glisse721604a2012-01-05 22:11:05 -0500612
613 radeon_vm_fini(rdev, &fpriv->vm);
614 kfree(fpriv);
615 file_priv->driver_priv = NULL;
616 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200617}
618
Alex Deucherf482a142012-07-17 14:02:34 -0400619/**
620 * radeon_driver_preclose_kms - drm callback for pre close
621 *
622 * @dev: drm dev pointer
623 * @file_priv: drm file
624 *
625 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
626 * (all asics).
627 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200628void radeon_driver_preclose_kms(struct drm_device *dev,
629 struct drm_file *file_priv)
630{
Dave Airlieab9e1f52010-07-13 11:11:11 +1000631 struct radeon_device *rdev = dev->dev_private;
632 if (rdev->hyperz_filp == file_priv)
633 rdev->hyperz_filp = NULL;
Marek Olšákdca0d612011-01-27 22:46:15 +0100634 if (rdev->cmask_filp == file_priv)
635 rdev->cmask_filp = NULL;
Christian Königf2ba57b2013-04-08 12:41:29 +0200636 radeon_uvd_free_handles(rdev, file_priv);
Christian Königd93f7932013-05-23 12:10:04 +0200637 radeon_vce_free_handles(rdev, file_priv);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200638}
639
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200640/*
641 * VBlank related functions.
642 */
Alex Deucherf482a142012-07-17 14:02:34 -0400643/**
644 * radeon_get_vblank_counter_kms - get frame count
645 *
646 * @dev: drm dev pointer
647 * @crtc: crtc to get the frame count from
648 *
649 * Gets the frame count on the requested crtc (all asics).
650 * Returns frame count on success, -EINVAL on failure.
651 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200652u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
653{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200654 struct radeon_device *rdev = dev->dev_private;
655
Dave Airlie9c950a42010-04-23 13:21:58 +1000656 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200657 DRM_ERROR("Invalid crtc %d\n", crtc);
658 return -EINVAL;
659 }
660
661 return radeon_get_vblank_counter(rdev, crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200662}
663
Alex Deucherf482a142012-07-17 14:02:34 -0400664/**
665 * radeon_enable_vblank_kms - enable vblank interrupt
666 *
667 * @dev: drm dev pointer
668 * @crtc: crtc to enable vblank interrupt for
669 *
670 * Enable the interrupt on the requested crtc (all asics).
671 * Returns 0 on success, -EINVAL on failure.
672 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200673int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
674{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200675 struct radeon_device *rdev = dev->dev_private;
Christian Koenigfb982572012-05-17 01:33:30 +0200676 unsigned long irqflags;
677 int r;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200678
Dave Airlie9c950a42010-04-23 13:21:58 +1000679 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200680 DRM_ERROR("Invalid crtc %d\n", crtc);
681 return -EINVAL;
682 }
683
Christian Koenigfb982572012-05-17 01:33:30 +0200684 spin_lock_irqsave(&rdev->irq.lock, irqflags);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200685 rdev->irq.crtc_vblank_int[crtc] = true;
Christian Koenigfb982572012-05-17 01:33:30 +0200686 r = radeon_irq_set(rdev);
687 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
688 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200689}
690
Alex Deucherf482a142012-07-17 14:02:34 -0400691/**
692 * radeon_disable_vblank_kms - disable vblank interrupt
693 *
694 * @dev: drm dev pointer
695 * @crtc: crtc to disable vblank interrupt for
696 *
697 * Disable the interrupt on the requested crtc (all asics).
698 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200699void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
700{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200701 struct radeon_device *rdev = dev->dev_private;
Christian Koenigfb982572012-05-17 01:33:30 +0200702 unsigned long irqflags;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200703
Dave Airlie9c950a42010-04-23 13:21:58 +1000704 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200705 DRM_ERROR("Invalid crtc %d\n", crtc);
706 return;
707 }
708
Christian Koenigfb982572012-05-17 01:33:30 +0200709 spin_lock_irqsave(&rdev->irq.lock, irqflags);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200710 rdev->irq.crtc_vblank_int[crtc] = false;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200711 radeon_irq_set(rdev);
Christian Koenigfb982572012-05-17 01:33:30 +0200712 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200713}
714
Alex Deucherf482a142012-07-17 14:02:34 -0400715/**
716 * radeon_get_vblank_timestamp_kms - get vblank timestamp
717 *
718 * @dev: drm dev pointer
719 * @crtc: crtc to get the timestamp for
720 * @max_error: max error
721 * @vblank_time: time value
722 * @flags: flags passed to the driver
723 *
724 * Gets the timestamp on the requested crtc based on the
725 * scanout position. (all asics).
726 * Returns postive status flags on success, negative error on failure.
727 */
Mario Kleinerf5a80202010-10-23 04:42:17 +0200728int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
729 int *max_error,
730 struct timeval *vblank_time,
731 unsigned flags)
732{
733 struct drm_crtc *drmcrtc;
734 struct radeon_device *rdev = dev->dev_private;
735
736 if (crtc < 0 || crtc >= dev->num_crtcs) {
737 DRM_ERROR("Invalid crtc %d\n", crtc);
738 return -EINVAL;
739 }
740
741 /* Get associated drm_crtc: */
742 drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
743
744 /* Helper routine in DRM core does all the work: */
745 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
746 vblank_time, flags,
Ville Syrjälä7da903e2013-10-26 17:57:31 +0300747 drmcrtc, &drmcrtc->hwmode);
Mario Kleinerf5a80202010-10-23 04:42:17 +0200748}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200749
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200750#define KMS_INVALID_IOCTL(name) \
Rashika Kheriaf6e2e402014-01-06 21:06:44 +0530751static int name(struct drm_device *dev, void *data, struct drm_file \
752 *file_priv) \
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200753{ \
754 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
755 return -EINVAL; \
756}
757
758/*
759 * All these ioctls are invalid in kms world.
760 */
761KMS_INVALID_IOCTL(radeon_cp_init_kms)
762KMS_INVALID_IOCTL(radeon_cp_start_kms)
763KMS_INVALID_IOCTL(radeon_cp_stop_kms)
764KMS_INVALID_IOCTL(radeon_cp_reset_kms)
765KMS_INVALID_IOCTL(radeon_cp_idle_kms)
766KMS_INVALID_IOCTL(radeon_cp_resume_kms)
767KMS_INVALID_IOCTL(radeon_engine_reset_kms)
768KMS_INVALID_IOCTL(radeon_fullscreen_kms)
769KMS_INVALID_IOCTL(radeon_cp_swap_kms)
770KMS_INVALID_IOCTL(radeon_cp_clear_kms)
771KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
772KMS_INVALID_IOCTL(radeon_cp_indices_kms)
773KMS_INVALID_IOCTL(radeon_cp_texture_kms)
774KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
775KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
776KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
777KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
778KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
779KMS_INVALID_IOCTL(radeon_cp_flip_kms)
780KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
781KMS_INVALID_IOCTL(radeon_mem_free_kms)
782KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
783KMS_INVALID_IOCTL(radeon_irq_emit_kms)
784KMS_INVALID_IOCTL(radeon_irq_wait_kms)
785KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
786KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
787KMS_INVALID_IOCTL(radeon_surface_free_kms)
788
789
Rob Clarkbaa70942013-08-02 13:27:49 -0400790const struct drm_ioctl_desc radeon_ioctls_kms[] = {
Dave Airlie1b2f1482010-08-14 20:20:34 +1000791 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
792 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
793 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
794 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
795 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
796 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
797 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
798 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
799 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
800 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
801 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
802 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
803 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
804 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
805 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
806 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
807 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
808 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
809 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
810 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
811 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
812 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
813 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
814 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
815 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
816 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
817 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200818 /* KMS */
Christian Königf33bcab2013-08-25 18:29:03 +0200819 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
820 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
821 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
822 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
Dave Airlie1b2f1482010-08-14 20:20:34 +1000823 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
824 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
Christian Königf33bcab2013-08-25 18:29:03 +0200825 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
826 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
827 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
828 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
829 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
830 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
831 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
Marek Olšákbda72d52014-03-02 00:56:17 +0100832 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200833};
834int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);