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Catalin Marinas4f04d8f2012-03-05 11:49:27 +00001/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_MMU_H
17#define __ASM_MMU_H
18
Will Deacon5914b112017-08-10 14:10:28 +010019
20#define USER_ASID_FLAG (UL(1) << 48)
Will Deacond7013ed2017-12-01 17:33:48 +000021#define TTBR_ASID_MASK (UL(0xffff) << 48)
Will Deacon5914b112017-08-10 14:10:28 +010022
Will Deacond6ca4552017-11-14 13:58:08 +000023#ifndef __ASSEMBLY__
24
Mark Rutland47320012018-04-12 12:11:13 +010025#include <linux/percpu.h>
26
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000027typedef struct {
Will Deacon5aec7152015-10-06 18:46:24 +010028 atomic64_t id;
29 void *vdso;
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000030} mm_context_t;
31
Will Deacon5aec7152015-10-06 18:46:24 +010032/*
33 * This macro is only used by the TLBI code, which cannot race with an
34 * ASID change and therefore doesn't need to reload the counter using
35 * atomic64_read.
36 */
37#define ASID(mm) ((mm)->context.id.counter & 0xffff)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000038
Will Deacond6ca4552017-11-14 13:58:08 +000039static inline bool arm64_kernel_unmapped_at_el0(void)
40{
Will Deaconf79ff2d2017-11-14 14:38:19 +000041 return IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0) &&
Suzuki K Poulosefe64d7d2016-11-08 13:56:20 +000042 cpus_have_const_cap(ARM64_UNMAP_KERNEL_AT_EL0);
Will Deacond6ca4552017-11-14 13:58:08 +000043}
44
Mark Rutland47320012018-04-12 12:11:13 +010045typedef void (*bp_hardening_cb_t)(void);
46
47struct bp_hardening_data {
48 int hyp_vectors_slot;
49 bp_hardening_cb_t fn;
50};
51
52#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
53extern char __bp_harden_hyp_vecs_start[], __bp_harden_hyp_vecs_end[];
54
55DECLARE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
56
57static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void)
58{
59 return this_cpu_ptr(&bp_hardening_data);
60}
61
62static inline void arm64_apply_bp_hardening(void)
63{
64 struct bp_hardening_data *d;
65
66 if (!cpus_have_cap(ARM64_HARDEN_BRANCH_PREDICTOR))
67 return;
68
69 d = arm64_get_bp_hardening_data();
70 if (d->fn)
71 d->fn();
72}
73#else
74static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void)
75{
76 return NULL;
77}
78
79static inline void arm64_apply_bp_hardening(void) { }
80#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
81
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000082extern void paging_init(void);
David Daney3194ac62016-04-08 15:50:26 -070083extern void bootmem_init(void);
Catalin Marinas2475ff92012-10-23 14:55:08 +010084extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);
Mark Salter0bf757c2014-04-07 15:39:51 -070085extern void init_mem_pgprot(void);
Ard Biesheuvel8ce837c2014-10-20 15:42:07 +020086extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys,
87 unsigned long virt, phys_addr_t size,
Ard Biesheuvel53e1b322016-06-29 14:51:26 +020088 pgprot_t prot, bool allow_block_mappings);
Ard Biesheuvel61bd93c2015-06-01 13:40:32 +020089extern void *fixmap_remap_fdt(phys_addr_t dt_phys);
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000090
Will Deacond6ca4552017-11-14 13:58:08 +000091#endif /* !__ASSEMBLY__ */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000092#endif