Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file contains the 64-bit "server" PowerPC variant |
| 3 | * of the low level exception handling including exception |
| 4 | * vectors, exception return, part of the slb and stab |
| 5 | * handling and other fixed offset specific things. |
| 6 | * |
| 7 | * This file is meant to be #included from head_64.S due to |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 8 | * position dependent assembly. |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 9 | * |
| 10 | * Most of this originates from head_64.S and thus has the same |
| 11 | * copyright history. |
| 12 | * |
| 13 | */ |
| 14 | |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 15 | #include <asm/hw_irq.h> |
Benjamin Herrenschmidt | 8aa34ab | 2009-07-14 20:52:52 +0000 | [diff] [blame] | 16 | #include <asm/exception-64s.h> |
Stephen Rothwell | 46f5221 | 2010-11-18 15:06:17 +0000 | [diff] [blame] | 17 | #include <asm/ptrace.h> |
Shreyas B. Prabhu | 7cba160 | 2014-12-10 00:26:52 +0530 | [diff] [blame] | 18 | #include <asm/cpuidle.h> |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 19 | #include <asm/head-64.h> |
Benjamin Herrenschmidt | 8aa34ab | 2009-07-14 20:52:52 +0000 | [diff] [blame] | 20 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 21 | /* |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 22 | * There are a few constraints to be concerned with. |
| 23 | * - Real mode exceptions code/data must be located at their physical location. |
| 24 | * - Virtual mode exceptions must be mapped at their 0xc000... location. |
| 25 | * - Fixed location code must not call directly beyond the __end_interrupts |
| 26 | * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence |
| 27 | * must be used. |
| 28 | * - LOAD_HANDLER targets must be within first 64K of physical 0 / |
| 29 | * virtual 0xc00... |
| 30 | * - Conditional branch targets must be within +/-32K of caller. |
| 31 | * |
| 32 | * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and |
| 33 | * therefore don't have to run in physically located code or rfid to |
| 34 | * virtual mode kernel code. However on relocatable kernels they do have |
| 35 | * to branch to KERNELBASE offset because the rest of the kernel (outside |
| 36 | * the exception vectors) may be located elsewhere. |
| 37 | * |
| 38 | * Virtual exceptions correspond with physical, except their entry points |
| 39 | * are offset by 0xc000000000000000 and also tend to get an added 0x4000 |
| 40 | * offset applied. Virtual exceptions are enabled with the Alternate |
| 41 | * Interrupt Location (AIL) bit set in the LPCR. However this does not |
| 42 | * guarantee they will be delivered virtually. Some conditions (see the ISA) |
| 43 | * cause exceptions to be delivered in real mode. |
| 44 | * |
| 45 | * It's impossible to receive interrupts below 0x300 via AIL. |
| 46 | * |
| 47 | * KVM: None of the virtual exceptions are from the guest. Anything that |
| 48 | * escalated to HV=1 from HV=0 is delivered via real mode handlers. |
| 49 | * |
| 50 | * |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 51 | * We layout physical memory as follows: |
| 52 | * 0x0000 - 0x00ff : Secondary processor spin code |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 53 | * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors |
| 54 | * 0x1900 - 0x3fff : Real mode trampolines |
| 55 | * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors |
| 56 | * 0x5900 - 0x6fff : Relon mode trampolines |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 57 | * 0x7000 - 0x7fff : FWNMI data area |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 58 | * 0x8000 - .... : Common interrupt handlers, remaining early |
| 59 | * setup code, rest of kernel. |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 60 | */ |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 61 | OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) |
| 62 | OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) |
| 63 | OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) |
| 64 | OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) |
| 65 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) |
| 66 | /* |
| 67 | * Data area reserved for FWNMI option. |
| 68 | * This address (0x7000) is fixed by the RPA. |
| 69 | * pseries and powernv need to keep the whole page from |
| 70 | * 0x7000 to 0x8000 free for use by the firmware |
| 71 | */ |
| 72 | ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) |
| 73 | OPEN_TEXT_SECTION(0x8000) |
| 74 | #else |
| 75 | OPEN_TEXT_SECTION(0x7000) |
| 76 | #endif |
| 77 | |
| 78 | USE_FIXED_SECTION(real_vectors) |
| 79 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 80 | /* |
| 81 | * This is the start of the interrupt handlers for pSeries |
| 82 | * This code runs with relocation off. |
| 83 | * Code from here to __end_interrupts gets copied down to real |
| 84 | * address 0x100 when we are running a relocatable kernel. |
| 85 | * Therefore any relative branches in this section must only |
| 86 | * branch to labels in this section. |
| 87 | */ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 88 | .globl __start_interrupts |
| 89 | __start_interrupts: |
| 90 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 91 | EXC_REAL_BEGIN(system_reset, 0x100, 0x200) |
Benjamin Herrenschmidt | 948cf67 | 2011-01-24 18:42:41 +1100 | [diff] [blame] | 92 | SET_SCRATCH0(r13) |
| 93 | #ifdef CONFIG_PPC_P7_NAP |
| 94 | BEGIN_FTR_SECTION |
| 95 | /* Running native on arch 2.06 or later, check if we are |
Shreyas B. Prabhu | 77b54e9 | 2014-12-10 00:26:53 +0530 | [diff] [blame] | 96 | * waking up from nap/sleep/winkle. |
Benjamin Herrenschmidt | 948cf67 | 2011-01-24 18:42:41 +1100 | [diff] [blame] | 97 | */ |
| 98 | mfspr r13,SPRN_SRR1 |
Paul Mackerras | 371fefd | 2011-06-29 00:23:08 +0000 | [diff] [blame] | 99 | rlwinm. r13,r13,47-31,30,31 |
| 100 | beq 9f |
| 101 | |
Shreyas B. Prabhu | 7cba160 | 2014-12-10 00:26:52 +0530 | [diff] [blame] | 102 | cmpwi cr3,r13,2 |
Paul Mackerras | 371fefd | 2011-06-29 00:23:08 +0000 | [diff] [blame] | 103 | GET_PACA(r13) |
Shreyas B. Prabhu | 5fa6b6b | 2016-07-08 11:50:46 +0530 | [diff] [blame] | 104 | bl pnv_restore_hyp_resource |
Shreyas B. Prabhu | 77b54e9 | 2014-12-10 00:26:53 +0530 | [diff] [blame] | 105 | |
Shreyas B. Prabhu | 7cba160 | 2014-12-10 00:26:52 +0530 | [diff] [blame] | 106 | li r0,PNV_THREAD_RUNNING |
| 107 | stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ |
Paul Mackerras | 371fefd | 2011-06-29 00:23:08 +0000 | [diff] [blame] | 108 | |
Aneesh Kumar K.V | 3a167bea | 2013-10-07 22:17:53 +0530 | [diff] [blame] | 109 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
Paul Mackerras | f0888f7 | 2012-02-03 00:54:17 +0000 | [diff] [blame] | 110 | li r0,KVM_HWTHREAD_IN_KERNEL |
| 111 | stb r0,HSTATE_HWTHREAD_STATE(r13) |
| 112 | /* Order setting hwthread_state vs. testing hwthread_req */ |
| 113 | sync |
| 114 | lbz r0,HSTATE_HWTHREAD_REQ(r13) |
| 115 | cmpwi r0,0 |
| 116 | beq 1f |
Paul Mackerras | 371fefd | 2011-06-29 00:23:08 +0000 | [diff] [blame] | 117 | b kvm_start_guest |
| 118 | 1: |
| 119 | #endif |
| 120 | |
Paul Mackerras | 56548fc | 2014-12-03 14:48:40 +1100 | [diff] [blame] | 121 | /* Return SRR1 from power7_nap() */ |
| 122 | mfspr r3,SPRN_SRR1 |
Shreyas B. Prabhu | 1706567 | 2016-07-08 11:50:44 +0530 | [diff] [blame] | 123 | blt cr3,2f |
Shreyas B. Prabhu | 5fa6b6b | 2016-07-08 11:50:46 +0530 | [diff] [blame] | 124 | b pnv_wakeup_loss |
| 125 | 2: b pnv_wakeup_noloss |
Vaidyanathan Srinivasan | aca79d2 | 2014-02-26 05:38:25 +0530 | [diff] [blame] | 126 | |
Paul Mackerras | 371fefd | 2011-06-29 00:23:08 +0000 | [diff] [blame] | 127 | 9: |
Paul Mackerras | 969391c | 2011-06-29 00:26:11 +0000 | [diff] [blame] | 128 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
Benjamin Herrenschmidt | 948cf67 | 2011-01-24 18:42:41 +1100 | [diff] [blame] | 129 | #endif /* CONFIG_PPC_P7_NAP */ |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 130 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
| 131 | NOTEST, 0x100) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 132 | EXC_REAL_END(system_reset, 0x100, 0x200) |
Nicholas Piggin | 582baf4 | 2016-09-21 17:43:30 +1000 | [diff] [blame] | 133 | EXC_VIRT_NONE(0x4100, 0x4200) |
| 134 | EXC_COMMON(system_reset_common, 0x100, system_reset_exception) |
| 135 | |
| 136 | #ifdef CONFIG_PPC_PSERIES |
| 137 | /* |
| 138 | * Vectors for the FWNMI option. Share common code. |
| 139 | */ |
| 140 | TRAMP_REAL_BEGIN(system_reset_fwnmi) |
| 141 | SET_SCRATCH0(r13) /* save r13 */ |
| 142 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
| 143 | NOTEST, 0x100) |
| 144 | #endif /* CONFIG_PPC_PSERIES */ |
| 145 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 146 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 147 | EXC_REAL_BEGIN(machine_check, 0x200, 0x300) |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 148 | /* This is moved out of line as it can be patched by FW, but |
| 149 | * some code path might still want to branch into the original |
| 150 | * vector |
| 151 | */ |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 152 | SET_SCRATCH0(r13) /* save r13 */ |
Mahesh Salgaonkar | bc14c49 | 2016-08-05 17:34:13 +0530 | [diff] [blame] | 153 | /* |
| 154 | * Running native on arch 2.06 or later, we may wakeup from winkle |
| 155 | * inside machine check. If yes, then last bit of HSPGR0 would be set |
| 156 | * to 1. Hence clear it unconditionally. |
Mahesh Salgaonkar | 1c51089 | 2013-10-30 20:04:31 +0530 | [diff] [blame] | 157 | */ |
Mahesh Salgaonkar | bc14c49 | 2016-08-05 17:34:13 +0530 | [diff] [blame] | 158 | GET_PACA(r13) |
| 159 | clrrdi r13,r13,1 |
| 160 | SET_PACA(r13) |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 161 | EXCEPTION_PROLOG_0(PACA_EXMC) |
Mahesh Salgaonkar | 1e9b450 | 2013-10-30 20:04:08 +0530 | [diff] [blame] | 162 | BEGIN_FTR_SECTION |
Mahesh Salgaonkar | 2513767 | 2016-03-01 11:17:46 +0530 | [diff] [blame] | 163 | b machine_check_powernv_early |
Mahesh Salgaonkar | 1e9b450 | 2013-10-30 20:04:08 +0530 | [diff] [blame] | 164 | FTR_SECTION_ELSE |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 165 | b machine_check_pSeries_0 |
Mahesh Salgaonkar | 1e9b450 | 2013-10-30 20:04:08 +0530 | [diff] [blame] | 166 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 167 | EXC_REAL_END(machine_check, 0x200, 0x300) |
Nicholas Piggin | afcf009 | 2016-09-21 17:43:31 +1000 | [diff] [blame] | 168 | EXC_VIRT_NONE(0x4200, 0x4300) |
| 169 | TRAMP_REAL_BEGIN(machine_check_powernv_early) |
| 170 | BEGIN_FTR_SECTION |
| 171 | EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) |
| 172 | /* |
| 173 | * Register contents: |
| 174 | * R13 = PACA |
| 175 | * R9 = CR |
| 176 | * Original R9 to R13 is saved on PACA_EXMC |
| 177 | * |
| 178 | * Switch to mc_emergency stack and handle re-entrancy (we limit |
| 179 | * the nested MCE upto level 4 to avoid stack overflow). |
| 180 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 |
| 181 | * |
| 182 | * We use paca->in_mce to check whether this is the first entry or |
| 183 | * nested machine check. We increment paca->in_mce to track nested |
| 184 | * machine checks. |
| 185 | * |
| 186 | * If this is the first entry then set stack pointer to |
| 187 | * paca->mc_emergency_sp, otherwise r1 is already pointing to |
| 188 | * stack frame on mc_emergency stack. |
| 189 | * |
| 190 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a |
| 191 | * checkstop if we get another machine check exception before we do |
| 192 | * rfid with MSR_ME=1. |
| 193 | */ |
| 194 | mr r11,r1 /* Save r1 */ |
| 195 | lhz r10,PACA_IN_MCE(r13) |
| 196 | cmpwi r10,0 /* Are we in nested machine check */ |
| 197 | bne 0f /* Yes, we are. */ |
| 198 | /* First machine check entry */ |
| 199 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ |
| 200 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ |
| 201 | addi r10,r10,1 /* increment paca->in_mce */ |
| 202 | sth r10,PACA_IN_MCE(r13) |
| 203 | /* Limit nested MCE to level 4 to avoid stack overflow */ |
| 204 | cmpwi r10,4 |
| 205 | bgt 2f /* Check if we hit limit of 4 */ |
| 206 | std r11,GPR1(r1) /* Save r1 on the stack. */ |
| 207 | std r11,0(r1) /* make stack chain pointer */ |
| 208 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ |
| 209 | std r11,_NIP(r1) |
| 210 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ |
| 211 | std r11,_MSR(r1) |
| 212 | mfspr r11,SPRN_DAR /* Save DAR */ |
| 213 | std r11,_DAR(r1) |
| 214 | mfspr r11,SPRN_DSISR /* Save DSISR */ |
| 215 | std r11,_DSISR(r1) |
| 216 | std r9,_CCR(r1) /* Save CR in stackframe */ |
| 217 | /* Save r9 through r13 from EXMC save area to stack frame. */ |
| 218 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) |
| 219 | mfmsr r11 /* get MSR value */ |
| 220 | ori r11,r11,MSR_ME /* turn on ME bit */ |
| 221 | ori r11,r11,MSR_RI /* turn on RI bit */ |
| 222 | LOAD_HANDLER(r12, machine_check_handle_early) |
| 223 | 1: mtspr SPRN_SRR0,r12 |
| 224 | mtspr SPRN_SRR1,r11 |
| 225 | rfid |
| 226 | b . /* prevent speculative execution */ |
| 227 | 2: |
| 228 | /* Stack overflow. Stay on emergency stack and panic. |
| 229 | * Keep the ME bit off while panic-ing, so that if we hit |
| 230 | * another machine check we checkstop. |
| 231 | */ |
| 232 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ |
| 233 | ld r11,PACAKMSR(r13) |
| 234 | LOAD_HANDLER(r12, unrecover_mce) |
| 235 | li r10,MSR_ME |
| 236 | andc r11,r11,r10 /* Turn off MSR_ME */ |
| 237 | b 1b |
| 238 | b . /* prevent speculative execution */ |
| 239 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
| 240 | |
| 241 | TRAMP_REAL_BEGIN(machine_check_pSeries) |
| 242 | .globl machine_check_fwnmi |
| 243 | machine_check_fwnmi: |
| 244 | SET_SCRATCH0(r13) /* save r13 */ |
| 245 | EXCEPTION_PROLOG_0(PACA_EXMC) |
| 246 | machine_check_pSeries_0: |
| 247 | EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) |
| 248 | /* |
| 249 | * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the |
| 250 | * difference that MSR_RI is not enabled, because PACA_EXMC is being |
| 251 | * used, so nested machine check corrupts it. machine_check_common |
| 252 | * enables MSR_RI. |
| 253 | */ |
| 254 | ld r10,PACAKMSR(r13) |
| 255 | xori r10,r10,MSR_RI |
| 256 | mfspr r11,SPRN_SRR0 |
| 257 | LOAD_HANDLER(r12, machine_check_common) |
| 258 | mtspr SPRN_SRR0,r12 |
| 259 | mfspr r12,SPRN_SRR1 |
| 260 | mtspr SPRN_SRR1,r10 |
| 261 | rfid |
| 262 | b . /* prevent speculative execution */ |
| 263 | |
| 264 | TRAMP_KVM_SKIP(PACA_EXMC, 0x200) |
| 265 | |
| 266 | EXC_COMMON_BEGIN(machine_check_common) |
| 267 | /* |
| 268 | * Machine check is different because we use a different |
| 269 | * save area: PACA_EXMC instead of PACA_EXGEN. |
| 270 | */ |
| 271 | mfspr r10,SPRN_DAR |
| 272 | std r10,PACA_EXMC+EX_DAR(r13) |
| 273 | mfspr r10,SPRN_DSISR |
| 274 | stw r10,PACA_EXMC+EX_DSISR(r13) |
| 275 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) |
| 276 | FINISH_NAP |
| 277 | RECONCILE_IRQ_STATE(r10, r11) |
| 278 | ld r3,PACA_EXMC+EX_DAR(r13) |
| 279 | lwz r4,PACA_EXMC+EX_DSISR(r13) |
| 280 | /* Enable MSR_RI when finished with PACA_EXMC */ |
| 281 | li r10,MSR_RI |
| 282 | mtmsrd r10,1 |
| 283 | std r3,_DAR(r1) |
| 284 | std r4,_DSISR(r1) |
| 285 | bl save_nvgprs |
| 286 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 287 | bl machine_check_exception |
| 288 | b ret_from_except |
| 289 | |
| 290 | #define MACHINE_CHECK_HANDLER_WINDUP \ |
| 291 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ |
| 292 | li r0,MSR_RI; \ |
| 293 | mfmsr r9; /* get MSR value */ \ |
| 294 | andc r9,r9,r0; \ |
| 295 | mtmsrd r9,1; /* Clear MSR_RI */ \ |
| 296 | /* Move original SRR0 and SRR1 into the respective regs */ \ |
| 297 | ld r9,_MSR(r1); \ |
| 298 | mtspr SPRN_SRR1,r9; \ |
| 299 | ld r3,_NIP(r1); \ |
| 300 | mtspr SPRN_SRR0,r3; \ |
| 301 | ld r9,_CTR(r1); \ |
| 302 | mtctr r9; \ |
| 303 | ld r9,_XER(r1); \ |
| 304 | mtxer r9; \ |
| 305 | ld r9,_LINK(r1); \ |
| 306 | mtlr r9; \ |
| 307 | REST_GPR(0, r1); \ |
| 308 | REST_8GPRS(2, r1); \ |
| 309 | REST_GPR(10, r1); \ |
| 310 | ld r11,_CCR(r1); \ |
| 311 | mtcr r11; \ |
| 312 | /* Decrement paca->in_mce. */ \ |
| 313 | lhz r12,PACA_IN_MCE(r13); \ |
| 314 | subi r12,r12,1; \ |
| 315 | sth r12,PACA_IN_MCE(r13); \ |
| 316 | REST_GPR(11, r1); \ |
| 317 | REST_2GPRS(12, r1); \ |
| 318 | /* restore original r1. */ \ |
| 319 | ld r1,GPR1(r1) |
| 320 | |
| 321 | /* |
| 322 | * Handle machine check early in real mode. We come here with |
| 323 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. |
| 324 | */ |
| 325 | EXC_COMMON_BEGIN(machine_check_handle_early) |
| 326 | std r0,GPR0(r1) /* Save r0 */ |
| 327 | EXCEPTION_PROLOG_COMMON_3(0x200) |
| 328 | bl save_nvgprs |
| 329 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 330 | bl machine_check_early |
| 331 | std r3,RESULT(r1) /* Save result */ |
| 332 | ld r12,_MSR(r1) |
| 333 | #ifdef CONFIG_PPC_P7_NAP |
| 334 | /* |
| 335 | * Check if thread was in power saving mode. We come here when any |
| 336 | * of the following is true: |
| 337 | * a. thread wasn't in power saving mode |
| 338 | * b. thread was in power saving mode with no state loss, |
| 339 | * supervisor state loss or hypervisor state loss. |
| 340 | * |
| 341 | * Go back to nap/sleep/winkle mode again if (b) is true. |
| 342 | */ |
| 343 | rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */ |
| 344 | beq 4f /* No, it wasn;t */ |
| 345 | /* Thread was in power saving mode. Go back to nap again. */ |
| 346 | cmpwi r11,2 |
| 347 | blt 3f |
| 348 | /* Supervisor/Hypervisor state loss */ |
| 349 | li r0,1 |
| 350 | stb r0,PACA_NAPSTATELOST(r13) |
| 351 | 3: bl machine_check_queue_event |
| 352 | MACHINE_CHECK_HANDLER_WINDUP |
| 353 | GET_PACA(r13) |
| 354 | ld r1,PACAR1(r13) |
| 355 | /* |
| 356 | * Check what idle state this CPU was in and go back to same mode |
| 357 | * again. |
| 358 | */ |
| 359 | lbz r3,PACA_THREAD_IDLE_STATE(r13) |
| 360 | cmpwi r3,PNV_THREAD_NAP |
| 361 | bgt 10f |
| 362 | IDLE_STATE_ENTER_SEQ(PPC_NAP) |
| 363 | /* No return */ |
| 364 | 10: |
| 365 | cmpwi r3,PNV_THREAD_SLEEP |
| 366 | bgt 2f |
| 367 | IDLE_STATE_ENTER_SEQ(PPC_SLEEP) |
| 368 | /* No return */ |
| 369 | |
| 370 | 2: |
| 371 | /* |
| 372 | * Go back to winkle. Please note that this thread was woken up in |
| 373 | * machine check from winkle and have not restored the per-subcore |
| 374 | * state. Hence before going back to winkle, set last bit of HSPGR0 |
| 375 | * to 1. This will make sure that if this thread gets woken up |
| 376 | * again at reset vector 0x100 then it will get chance to restore |
| 377 | * the subcore state. |
| 378 | */ |
| 379 | ori r13,r13,1 |
| 380 | SET_PACA(r13) |
| 381 | IDLE_STATE_ENTER_SEQ(PPC_WINKLE) |
| 382 | /* No return */ |
| 383 | 4: |
| 384 | #endif |
| 385 | /* |
| 386 | * Check if we are coming from hypervisor userspace. If yes then we |
| 387 | * continue in host kernel in V mode to deliver the MC event. |
| 388 | */ |
| 389 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ |
| 390 | beq 5f |
| 391 | andi. r11,r12,MSR_PR /* See if coming from user. */ |
| 392 | bne 9f /* continue in V mode if we are. */ |
| 393 | |
| 394 | 5: |
| 395 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
| 396 | /* |
| 397 | * We are coming from kernel context. Check if we are coming from |
| 398 | * guest. if yes, then we can continue. We will fall through |
| 399 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. |
| 400 | */ |
| 401 | lbz r11,HSTATE_IN_GUEST(r13) |
| 402 | cmpwi r11,0 /* Check if coming from guest */ |
| 403 | bne 9f /* continue if we are. */ |
| 404 | #endif |
| 405 | /* |
| 406 | * At this point we are not sure about what context we come from. |
| 407 | * Queue up the MCE event and return from the interrupt. |
| 408 | * But before that, check if this is an un-recoverable exception. |
| 409 | * If yes, then stay on emergency stack and panic. |
| 410 | */ |
| 411 | andi. r11,r12,MSR_RI |
| 412 | bne 2f |
| 413 | 1: mfspr r11,SPRN_SRR0 |
| 414 | LOAD_HANDLER(r10,unrecover_mce) |
| 415 | mtspr SPRN_SRR0,r10 |
| 416 | ld r10,PACAKMSR(r13) |
| 417 | /* |
| 418 | * We are going down. But there are chances that we might get hit by |
| 419 | * another MCE during panic path and we may run into unstable state |
| 420 | * with no way out. Hence, turn ME bit off while going down, so that |
| 421 | * when another MCE is hit during panic path, system will checkstop |
| 422 | * and hypervisor will get restarted cleanly by SP. |
| 423 | */ |
| 424 | li r3,MSR_ME |
| 425 | andc r10,r10,r3 /* Turn off MSR_ME */ |
| 426 | mtspr SPRN_SRR1,r10 |
| 427 | rfid |
| 428 | b . |
| 429 | 2: |
| 430 | /* |
| 431 | * Check if we have successfully handled/recovered from error, if not |
| 432 | * then stay on emergency stack and panic. |
| 433 | */ |
| 434 | ld r3,RESULT(r1) /* Load result */ |
| 435 | cmpdi r3,0 /* see if we handled MCE successfully */ |
| 436 | |
| 437 | beq 1b /* if !handled then panic */ |
| 438 | /* |
| 439 | * Return from MC interrupt. |
| 440 | * Queue up the MCE event so that we can log it later, while |
| 441 | * returning from kernel or opal call. |
| 442 | */ |
| 443 | bl machine_check_queue_event |
| 444 | MACHINE_CHECK_HANDLER_WINDUP |
| 445 | rfid |
| 446 | 9: |
| 447 | /* Deliver the machine check to host kernel in V mode. */ |
| 448 | MACHINE_CHECK_HANDLER_WINDUP |
| 449 | b machine_check_pSeries |
| 450 | |
| 451 | EXC_COMMON_BEGIN(unrecover_mce) |
| 452 | /* Invoke machine_check_exception to print MCE event and panic. */ |
| 453 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 454 | bl machine_check_exception |
| 455 | /* |
| 456 | * We will not reach here. Even if we did, there is no way out. Call |
| 457 | * unrecoverable_exception and die. |
| 458 | */ |
| 459 | 1: addi r3,r1,STACK_FRAME_OVERHEAD |
| 460 | bl unrecoverable_exception |
| 461 | b 1b |
| 462 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 463 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 464 | EXC_REAL(data_access, 0x300, 0x380) |
Nicholas Piggin | 80795e6 | 2016-09-21 17:43:32 +1000 | [diff] [blame] | 465 | EXC_VIRT(data_access, 0x4300, 0x4380, 0x300) |
| 466 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) |
| 467 | |
| 468 | EXC_COMMON_BEGIN(data_access_common) |
| 469 | /* |
| 470 | * Here r13 points to the paca, r9 contains the saved CR, |
| 471 | * SRR0 and SRR1 are saved in r11 and r12, |
| 472 | * r9 - r13 are saved in paca->exgen. |
| 473 | */ |
| 474 | mfspr r10,SPRN_DAR |
| 475 | std r10,PACA_EXGEN+EX_DAR(r13) |
| 476 | mfspr r10,SPRN_DSISR |
| 477 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
| 478 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) |
| 479 | RECONCILE_IRQ_STATE(r10, r11) |
| 480 | ld r12,_MSR(r1) |
| 481 | ld r3,PACA_EXGEN+EX_DAR(r13) |
| 482 | lwz r4,PACA_EXGEN+EX_DSISR(r13) |
| 483 | li r5,0x300 |
| 484 | std r3,_DAR(r1) |
| 485 | std r4,_DSISR(r1) |
| 486 | BEGIN_MMU_FTR_SECTION |
| 487 | b do_hash_page /* Try to handle as hpte fault */ |
| 488 | MMU_FTR_SECTION_ELSE |
| 489 | b handle_page_fault |
| 490 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) |
| 491 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 492 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 493 | EXC_REAL_BEGIN(data_access_slb, 0x380, 0x400) |
Paul Mackerras | 673b189 | 2011-04-05 13:59:58 +1000 | [diff] [blame] | 494 | SET_SCRATCH0(r13) |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 495 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 496 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 497 | std r3,PACA_EXSLB+EX_R3(r13) |
| 498 | mfspr r3,SPRN_DAR |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 499 | mfspr r12,SPRN_SRR1 |
Paul Mackerras | f0f558b | 2016-09-02 21:49:21 +1000 | [diff] [blame] | 500 | crset 4*cr6+eq |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 501 | #ifndef CONFIG_RELOCATABLE |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 502 | b slb_miss_realmode |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 503 | #else |
| 504 | /* |
Anton Blanchard | ad0289e | 2014-02-04 16:04:52 +1100 | [diff] [blame] | 505 | * We can't just use a direct branch to slb_miss_realmode |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 506 | * because the distance from here to there depends on where |
| 507 | * the kernel ends up being put. |
| 508 | */ |
| 509 | mfctr r11 |
Anton Blanchard | ad0289e | 2014-02-04 16:04:52 +1100 | [diff] [blame] | 510 | LOAD_HANDLER(r10, slb_miss_realmode) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 511 | mtctr r10 |
| 512 | bctr |
| 513 | #endif |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 514 | EXC_REAL_END(data_access_slb, 0x380, 0x400) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 515 | |
Nicholas Piggin | 2b9af6e | 2016-09-21 17:43:33 +1000 | [diff] [blame] | 516 | EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x4400) |
| 517 | SET_SCRATCH0(r13) |
| 518 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
| 519 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) |
| 520 | std r3,PACA_EXSLB+EX_R3(r13) |
| 521 | mfspr r3,SPRN_DAR |
| 522 | mfspr r12,SPRN_SRR1 |
| 523 | crset 4*cr6+eq |
| 524 | #ifndef CONFIG_RELOCATABLE |
| 525 | b slb_miss_realmode |
| 526 | #else |
| 527 | /* |
| 528 | * We can't just use a direct branch to slb_miss_realmode |
| 529 | * because the distance from here to there depends on where |
| 530 | * the kernel ends up being put. |
| 531 | */ |
| 532 | mfctr r11 |
| 533 | LOAD_HANDLER(r10, slb_miss_realmode) |
| 534 | mtctr r10 |
| 535 | bctr |
| 536 | #endif |
| 537 | EXC_VIRT_END(data_access_slb, 0x4380, 0x4400) |
| 538 | TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) |
| 539 | |
| 540 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 541 | EXC_REAL(instruction_access, 0x400, 0x480) |
Nicholas Piggin | 27ce77d | 2016-09-21 17:43:34 +1000 | [diff] [blame] | 542 | EXC_VIRT(instruction_access, 0x4400, 0x4480, 0x400) |
| 543 | TRAMP_KVM(PACA_EXGEN, 0x400) |
| 544 | |
| 545 | EXC_COMMON_BEGIN(instruction_access_common) |
| 546 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) |
| 547 | RECONCILE_IRQ_STATE(r10, r11) |
| 548 | ld r12,_MSR(r1) |
| 549 | ld r3,_NIP(r1) |
| 550 | andis. r4,r12,0x5820 |
| 551 | li r5,0x400 |
| 552 | std r3,_DAR(r1) |
| 553 | std r4,_DSISR(r1) |
| 554 | BEGIN_MMU_FTR_SECTION |
| 555 | b do_hash_page /* Try to handle as hpte fault */ |
| 556 | MMU_FTR_SECTION_ELSE |
| 557 | b handle_page_fault |
| 558 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) |
| 559 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 560 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 561 | EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x500) |
Paul Mackerras | 673b189 | 2011-04-05 13:59:58 +1000 | [diff] [blame] | 562 | SET_SCRATCH0(r13) |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 563 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 564 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 565 | std r3,PACA_EXSLB+EX_R3(r13) |
| 566 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 567 | mfspr r12,SPRN_SRR1 |
Paul Mackerras | f0f558b | 2016-09-02 21:49:21 +1000 | [diff] [blame] | 568 | crclr 4*cr6+eq |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 569 | #ifndef CONFIG_RELOCATABLE |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 570 | b slb_miss_realmode |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 571 | #else |
| 572 | mfctr r11 |
Anton Blanchard | ad0289e | 2014-02-04 16:04:52 +1100 | [diff] [blame] | 573 | LOAD_HANDLER(r10, slb_miss_realmode) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 574 | mtctr r10 |
| 575 | bctr |
| 576 | #endif |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 577 | EXC_REAL_END(instruction_access_slb, 0x480, 0x500) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 578 | |
Nicholas Piggin | 8d04631 | 2016-09-21 17:43:35 +1000 | [diff] [blame] | 579 | EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x4500) |
| 580 | SET_SCRATCH0(r13) |
| 581 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
| 582 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) |
| 583 | std r3,PACA_EXSLB+EX_R3(r13) |
| 584 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ |
| 585 | mfspr r12,SPRN_SRR1 |
| 586 | crclr 4*cr6+eq |
| 587 | #ifndef CONFIG_RELOCATABLE |
| 588 | b slb_miss_realmode |
| 589 | #else |
| 590 | mfctr r11 |
| 591 | LOAD_HANDLER(r10, slb_miss_realmode) |
| 592 | mtctr r10 |
| 593 | bctr |
| 594 | #endif |
| 595 | EXC_VIRT_END(instruction_access_slb, 0x4480, 0x4500) |
| 596 | TRAMP_KVM(PACA_EXSLB, 0x480) |
| 597 | |
| 598 | |
| 599 | /* This handler is used by both 0x380 and 0x480 slb miss interrupts */ |
| 600 | EXC_COMMON_BEGIN(slb_miss_realmode) |
| 601 | /* |
| 602 | * r13 points to the PACA, r9 contains the saved CR, |
| 603 | * r12 contain the saved SRR1, SRR0 is still ready for return |
| 604 | * r3 has the faulting address |
| 605 | * r9 - r13 are saved in paca->exslb. |
| 606 | * r3 is saved in paca->slb_r3 |
| 607 | * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss |
| 608 | * We assume we aren't going to take any exceptions during this |
| 609 | * procedure. |
| 610 | */ |
| 611 | mflr r10 |
| 612 | #ifdef CONFIG_RELOCATABLE |
| 613 | mtctr r11 |
| 614 | #endif |
| 615 | |
| 616 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ |
| 617 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ |
| 618 | std r3,PACA_EXSLB+EX_DAR(r13) |
| 619 | |
| 620 | crset 4*cr0+eq |
| 621 | #ifdef CONFIG_PPC_STD_MMU_64 |
| 622 | BEGIN_MMU_FTR_SECTION |
| 623 | bl slb_allocate_realmode |
| 624 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) |
| 625 | #endif |
| 626 | |
| 627 | ld r10,PACA_EXSLB+EX_LR(r13) |
| 628 | ld r3,PACA_EXSLB+EX_R3(r13) |
| 629 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ |
| 630 | mtlr r10 |
| 631 | |
| 632 | beq 8f /* if bad address, make full stack frame */ |
| 633 | |
| 634 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ |
| 635 | beq- 2f |
| 636 | |
| 637 | /* All done -- return from exception. */ |
| 638 | |
| 639 | .machine push |
| 640 | .machine "power4" |
| 641 | mtcrf 0x80,r9 |
| 642 | mtcrf 0x02,r9 /* I/D indication is in cr6 */ |
| 643 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ |
| 644 | .machine pop |
| 645 | |
| 646 | RESTORE_PPR_PACA(PACA_EXSLB, r9) |
| 647 | ld r9,PACA_EXSLB+EX_R9(r13) |
| 648 | ld r10,PACA_EXSLB+EX_R10(r13) |
| 649 | ld r11,PACA_EXSLB+EX_R11(r13) |
| 650 | ld r12,PACA_EXSLB+EX_R12(r13) |
| 651 | ld r13,PACA_EXSLB+EX_R13(r13) |
| 652 | rfid |
| 653 | b . /* prevent speculative execution */ |
| 654 | |
| 655 | 2: mfspr r11,SPRN_SRR0 |
| 656 | LOAD_HANDLER(r10,unrecov_slb) |
| 657 | mtspr SPRN_SRR0,r10 |
| 658 | ld r10,PACAKMSR(r13) |
| 659 | mtspr SPRN_SRR1,r10 |
| 660 | rfid |
| 661 | b . |
| 662 | |
| 663 | 8: mfspr r11,SPRN_SRR0 |
| 664 | LOAD_HANDLER(r10,bad_addr_slb) |
| 665 | mtspr SPRN_SRR0,r10 |
| 666 | ld r10,PACAKMSR(r13) |
| 667 | mtspr SPRN_SRR1,r10 |
| 668 | rfid |
| 669 | b . |
| 670 | |
| 671 | EXC_COMMON_BEGIN(unrecov_slb) |
| 672 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) |
| 673 | RECONCILE_IRQ_STATE(r10, r11) |
| 674 | bl save_nvgprs |
| 675 | 1: addi r3,r1,STACK_FRAME_OVERHEAD |
| 676 | bl unrecoverable_exception |
| 677 | b 1b |
| 678 | |
| 679 | EXC_COMMON_BEGIN(bad_addr_slb) |
| 680 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) |
| 681 | RECONCILE_IRQ_STATE(r10, r11) |
| 682 | ld r3, PACA_EXSLB+EX_DAR(r13) |
| 683 | std r3, _DAR(r1) |
| 684 | beq cr6, 2f |
| 685 | li r10, 0x480 /* fix trap number for I-SLB miss */ |
| 686 | std r10, _TRAP(r1) |
| 687 | 2: bl save_nvgprs |
| 688 | addi r3, r1, STACK_FRAME_OVERHEAD |
| 689 | bl slb_miss_bad_addr |
| 690 | b ret_from_except |
| 691 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 692 | EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x600) |
Benjamin Herrenschmidt | b3e6b5d | 2011-04-05 14:27:11 +1000 | [diff] [blame] | 693 | .globl hardware_interrupt_hv; |
Benjamin Herrenschmidt | b3e6b5d | 2011-04-05 14:27:11 +1000 | [diff] [blame] | 694 | hardware_interrupt_hv: |
Benjamin Herrenschmidt | a5d4f3a | 2011-04-05 14:20:31 +1000 | [diff] [blame] | 695 | BEGIN_FTR_SECTION |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 696 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 697 | EXC_HV, SOFTEN_TEST_HV) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 698 | do_kvm_H0x500: |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 699 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 700 | FTR_SECTION_ELSE |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 701 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
Paul Mackerras | 31a40e2 | 2015-11-12 16:44:42 +1100 | [diff] [blame] | 702 | EXC_STD, SOFTEN_TEST_PR) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 703 | do_kvm_0x500: |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 704 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500) |
Paul Mackerras | 969391c | 2011-06-29 00:26:11 +0000 | [diff] [blame] | 705 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 706 | EXC_REAL_END(hardware_interrupt, 0x500, 0x600) |
Benjamin Herrenschmidt | a5d4f3a | 2011-04-05 14:20:31 +1000 | [diff] [blame] | 707 | |
Nicholas Piggin | c138e58 | 2016-09-21 17:43:36 +1000 | [diff] [blame] | 708 | EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x4600) |
| 709 | .globl hardware_interrupt_relon_hv; |
| 710 | hardware_interrupt_relon_hv: |
| 711 | BEGIN_FTR_SECTION |
| 712 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) |
| 713 | FTR_SECTION_ELSE |
| 714 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) |
| 715 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
| 716 | EXC_VIRT_END(hardware_interrupt, 0x4500, 0x4600) |
| 717 | |
| 718 | EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) |
| 719 | |
| 720 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 721 | EXC_REAL(alignment, 0x600, 0x700) |
Nicholas Piggin | f9aa671 | 2016-09-21 17:43:37 +1000 | [diff] [blame] | 722 | EXC_VIRT(alignment, 0x4600, 0x4700, 0x600) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 723 | TRAMP_KVM(PACA_EXGEN, 0x600) |
Nicholas Piggin | f9aa671 | 2016-09-21 17:43:37 +1000 | [diff] [blame] | 724 | EXC_COMMON_BEGIN(alignment_common) |
| 725 | mfspr r10,SPRN_DAR |
| 726 | std r10,PACA_EXGEN+EX_DAR(r13) |
| 727 | mfspr r10,SPRN_DSISR |
| 728 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
| 729 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) |
| 730 | ld r3,PACA_EXGEN+EX_DAR(r13) |
| 731 | lwz r4,PACA_EXGEN+EX_DSISR(r13) |
| 732 | std r3,_DAR(r1) |
| 733 | std r4,_DSISR(r1) |
| 734 | bl save_nvgprs |
| 735 | RECONCILE_IRQ_STATE(r10, r11) |
| 736 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 737 | bl alignment_exception |
| 738 | b ret_from_except |
| 739 | |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 740 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 741 | EXC_REAL(program_check, 0x700, 0x800) |
Nicholas Piggin | 11e8734 | 2016-09-21 17:43:38 +1000 | [diff] [blame] | 742 | EXC_VIRT(program_check, 0x4700, 0x4800, 0x700) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 743 | TRAMP_KVM(PACA_EXGEN, 0x700) |
Nicholas Piggin | 11e8734 | 2016-09-21 17:43:38 +1000 | [diff] [blame] | 744 | EXC_COMMON_BEGIN(program_check_common) |
| 745 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) |
| 746 | bl save_nvgprs |
| 747 | RECONCILE_IRQ_STATE(r10, r11) |
| 748 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 749 | bl program_check_exception |
| 750 | b ret_from_except |
| 751 | |
Paul Mackerras | a485c70 | 2013-04-25 17:51:40 +0000 | [diff] [blame] | 752 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 753 | EXC_REAL(fp_unavailable, 0x800, 0x900) |
Nicholas Piggin | c78d9b9 | 2016-09-21 17:43:39 +1000 | [diff] [blame] | 754 | EXC_VIRT(fp_unavailable, 0x4800, 0x4900, 0x800) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 755 | TRAMP_KVM(PACA_EXGEN, 0x800) |
Nicholas Piggin | c78d9b9 | 2016-09-21 17:43:39 +1000 | [diff] [blame] | 756 | EXC_COMMON_BEGIN(fp_unavailable_common) |
| 757 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) |
| 758 | bne 1f /* if from user, just load it up */ |
| 759 | bl save_nvgprs |
| 760 | RECONCILE_IRQ_STATE(r10, r11) |
| 761 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 762 | bl kernel_fp_unavailable_exception |
| 763 | BUG_OPCODE |
| 764 | 1: |
| 765 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 766 | BEGIN_FTR_SECTION |
| 767 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in |
| 768 | * transaction), go do TM stuff |
| 769 | */ |
| 770 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) |
| 771 | bne- 2f |
| 772 | END_FTR_SECTION_IFSET(CPU_FTR_TM) |
| 773 | #endif |
| 774 | bl load_up_fpu |
| 775 | b fast_exception_return |
| 776 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 777 | 2: /* User process was in a transaction */ |
| 778 | bl save_nvgprs |
| 779 | RECONCILE_IRQ_STATE(r10, r11) |
| 780 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 781 | bl fp_unavailable_tm |
| 782 | b ret_from_except |
| 783 | #endif |
| 784 | |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 785 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 786 | EXC_REAL_MASKABLE(decrementer, 0x900, 0x980) |
Nicholas Piggin | 39c0da5 | 2016-09-21 17:43:40 +1000 | [diff] [blame] | 787 | EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x4980, 0x900) |
| 788 | TRAMP_KVM(PACA_EXGEN, 0x900) |
| 789 | EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) |
| 790 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 791 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 792 | EXC_REAL_HV(hdecrementer, 0x980, 0xa00) |
Nicholas Piggin | facc6d7 | 2016-09-21 17:43:41 +1000 | [diff] [blame] | 793 | EXC_VIRT_HV(hdecrementer, 0x4980, 0x4a00, 0x980) |
| 794 | TRAMP_KVM_HV(PACA_EXGEN, 0x980) |
| 795 | EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) |
| 796 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 797 | |
| 798 | EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0xb00) |
Nicholas Piggin | ca24316 | 2016-09-21 17:43:42 +1000 | [diff] [blame] | 799 | EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x4b00, 0xa00) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 800 | TRAMP_KVM(PACA_EXGEN, 0xa00) |
Nicholas Piggin | ca24316 | 2016-09-21 17:43:42 +1000 | [diff] [blame] | 801 | #ifdef CONFIG_PPC_DOORBELL |
| 802 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) |
| 803 | #else |
| 804 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) |
| 805 | #endif |
| 806 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 807 | |
| 808 | EXC_REAL(trap_0b, 0xb00, 0xc00) |
Nicholas Piggin | 341215d | 2016-09-21 17:43:43 +1000 | [diff] [blame] | 809 | EXC_VIRT(trap_0b, 0x4b00, 0x4c00, 0xb00) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 810 | TRAMP_KVM(PACA_EXGEN, 0xb00) |
Nicholas Piggin | 341215d | 2016-09-21 17:43:43 +1000 | [diff] [blame] | 811 | EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) |
| 812 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 813 | |
Nicholas Piggin | d807ad3 | 2016-09-21 17:43:44 +1000 | [diff] [blame] | 814 | #define LOAD_SYSCALL_HANDLER(reg) \ |
| 815 | ld reg,PACAKBASE(r13); \ |
| 816 | ori reg,reg,(ABS_ADDR(system_call_common))@l; |
| 817 | |
| 818 | /* Syscall routine is used twice, in reloc-off and reloc-on paths */ |
| 819 | #define SYSCALL_PSERIES_1 \ |
| 820 | BEGIN_FTR_SECTION \ |
| 821 | cmpdi r0,0x1ebe ; \ |
| 822 | beq- 1f ; \ |
| 823 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ |
| 824 | mr r9,r13 ; \ |
| 825 | GET_PACA(r13) ; \ |
| 826 | mfspr r11,SPRN_SRR0 ; \ |
| 827 | 0: |
| 828 | |
| 829 | #define SYSCALL_PSERIES_2_RFID \ |
| 830 | mfspr r12,SPRN_SRR1 ; \ |
| 831 | LOAD_SYSCALL_HANDLER(r10) ; \ |
| 832 | mtspr SPRN_SRR0,r10 ; \ |
| 833 | ld r10,PACAKMSR(r13) ; \ |
| 834 | mtspr SPRN_SRR1,r10 ; \ |
| 835 | rfid ; \ |
| 836 | b . ; /* prevent speculative execution */ |
| 837 | |
| 838 | #define SYSCALL_PSERIES_3 \ |
| 839 | /* Fast LE/BE switch system call */ \ |
| 840 | 1: mfspr r12,SPRN_SRR1 ; \ |
| 841 | xori r12,r12,MSR_LE ; \ |
| 842 | mtspr SPRN_SRR1,r12 ; \ |
| 843 | rfid ; /* return to userspace */ \ |
| 844 | b . ; /* prevent speculative execution */ |
| 845 | |
| 846 | #if defined(CONFIG_RELOCATABLE) |
| 847 | /* |
| 848 | * We can't branch directly so we do it via the CTR which |
| 849 | * is volatile across system calls. |
| 850 | */ |
| 851 | #define SYSCALL_PSERIES_2_DIRECT \ |
| 852 | LOAD_SYSCALL_HANDLER(r12) ; \ |
| 853 | mtctr r12 ; \ |
| 854 | mfspr r12,SPRN_SRR1 ; \ |
| 855 | li r10,MSR_RI ; \ |
| 856 | mtmsrd r10,1 ; \ |
| 857 | bctr ; |
| 858 | #else |
| 859 | /* We can branch directly */ |
| 860 | #define SYSCALL_PSERIES_2_DIRECT \ |
| 861 | mfspr r12,SPRN_SRR1 ; \ |
| 862 | li r10,MSR_RI ; \ |
| 863 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ |
| 864 | b system_call_common ; |
| 865 | #endif |
| 866 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 867 | EXC_REAL_BEGIN(system_call, 0xc00, 0xd00) |
Suresh E. Warrier | 8b91a25 | 2014-11-03 15:46:42 +1100 | [diff] [blame] | 868 | /* |
| 869 | * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems |
| 870 | * that support it) before changing to HMT_MEDIUM. That allows the KVM |
| 871 | * code to save that value into the guest state (it is the guest's PPR |
| 872 | * value). Otherwise just change to HMT_MEDIUM as userspace has |
| 873 | * already saved the PPR. |
| 874 | */ |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 875 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
| 876 | SET_SCRATCH0(r13) |
| 877 | GET_PACA(r13) |
| 878 | std r9,PACA_EXGEN+EX_R9(r13) |
Suresh E. Warrier | 8b91a25 | 2014-11-03 15:46:42 +1100 | [diff] [blame] | 879 | OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); |
| 880 | HMT_MEDIUM; |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 881 | std r10,PACA_EXGEN+EX_R10(r13) |
Suresh E. Warrier | 8b91a25 | 2014-11-03 15:46:42 +1100 | [diff] [blame] | 882 | OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR); |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 883 | mfcr r9 |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 884 | KVMTEST_PR(0xc00) |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 885 | GET_SCRATCH0(r13) |
Suresh E. Warrier | 8b91a25 | 2014-11-03 15:46:42 +1100 | [diff] [blame] | 886 | #else |
| 887 | HMT_MEDIUM; |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 888 | #endif |
Michael Neuling | 742415d | 2012-11-02 17:16:01 +1100 | [diff] [blame] | 889 | SYSCALL_PSERIES_1 |
| 890 | SYSCALL_PSERIES_2_RFID |
| 891 | SYSCALL_PSERIES_3 |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 892 | EXC_REAL_END(system_call, 0xc00, 0xd00) |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 893 | |
Nicholas Piggin | d807ad3 | 2016-09-21 17:43:44 +1000 | [diff] [blame] | 894 | EXC_VIRT_BEGIN(system_call, 0x4c00, 0x4d00) |
| 895 | HMT_MEDIUM |
| 896 | SYSCALL_PSERIES_1 |
| 897 | SYSCALL_PSERIES_2_DIRECT |
| 898 | SYSCALL_PSERIES_3 |
| 899 | EXC_VIRT_END(system_call, 0x4c00, 0x4d00) |
| 900 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 901 | TRAMP_KVM(PACA_EXGEN, 0xc00) |
| 902 | |
Nicholas Piggin | d807ad3 | 2016-09-21 17:43:44 +1000 | [diff] [blame] | 903 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 904 | EXC_REAL(single_step, 0xd00, 0xe00) |
Nicholas Piggin | bc6675c | 2016-09-21 17:43:45 +1000 | [diff] [blame] | 905 | EXC_VIRT(single_step, 0x4d00, 0x4e00, 0xd00) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 906 | TRAMP_KVM(PACA_EXGEN, 0xd00) |
Nicholas Piggin | bc6675c | 2016-09-21 17:43:45 +1000 | [diff] [blame] | 907 | EXC_COMMON(single_step_common, 0xd00, single_step_exception) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 908 | |
Benjamin Herrenschmidt | b3e6b5d | 2011-04-05 14:27:11 +1000 | [diff] [blame] | 909 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 910 | __EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0xe20) |
Nicholas Piggin | f5c32c1 | 2016-09-21 17:43:46 +1000 | [diff] [blame] | 911 | __TRAMP_REAL_REAL_OOL_HV(h_data_storage, 0xe00) |
| 912 | EXC_VIRT_BEGIN(unused, 0x4e00, 0x4e20) |
| 913 | b . /* Can't happen, see v2.07 Book III-S section 6.5 */ |
| 914 | EXC_VIRT_END(unused, 0x4e00, 0x4e20) |
| 915 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) |
| 916 | EXC_COMMON_BEGIN(h_data_storage_common) |
| 917 | mfspr r10,SPRN_HDAR |
| 918 | std r10,PACA_EXGEN+EX_DAR(r13) |
| 919 | mfspr r10,SPRN_HDSISR |
| 920 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
| 921 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) |
| 922 | bl save_nvgprs |
| 923 | RECONCILE_IRQ_STATE(r10, r11) |
| 924 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 925 | bl unknown_exception |
| 926 | b ret_from_except |
| 927 | EXC_COMMON(trap_0e_common, 0xe00, unknown_exception) |
| 928 | |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 929 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 930 | __EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0xe40) |
Nicholas Piggin | 82517ca | 2016-09-21 17:43:47 +1000 | [diff] [blame] | 931 | __TRAMP_REAL_REAL_OOL_HV(h_instr_storage, 0xe20) |
| 932 | EXC_VIRT_BEGIN(unused, 0x4e20, 0x4e40) |
| 933 | b . /* Can't happen, see v2.07 Book III-S section 6.5 */ |
| 934 | EXC_VIRT_END(unused, 0x4e20, 0x4e40) |
| 935 | TRAMP_KVM_HV(PACA_EXGEN, 0xe20) |
| 936 | EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) |
| 937 | |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 938 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 939 | __EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0xe60) |
Nicholas Piggin | 031b402 | 2016-09-21 17:43:48 +1000 | [diff] [blame] | 940 | __TRAMP_REAL_REAL_OOL_HV(emulation_assist, 0xe40) |
| 941 | __EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x4e60) |
| 942 | __TRAMP_REAL_VIRT_OOL_HV(emulation_assist, 0xe40) |
| 943 | TRAMP_KVM_HV(PACA_EXGEN, 0xe40) |
| 944 | EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) |
| 945 | |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 946 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 947 | __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0xe80, hmi_exception_early) |
Nicholas Piggin | 62f9b03 | 2016-09-21 17:43:49 +1000 | [diff] [blame] | 948 | __TRAMP_REAL_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) |
| 949 | EXC_VIRT_BEGIN(unused, 0x4e60, 0x4e80) |
| 950 | b . /* Can't happen, see v2.07 Book III-S section 6.5 */ |
| 951 | EXC_VIRT_END(unused, 0x4e60, 0x4e80) |
| 952 | TRAMP_KVM_HV(PACA_EXGEN, 0xe60) |
| 953 | TRAMP_REAL_BEGIN(hmi_exception_early) |
| 954 | EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) |
| 955 | mr r10,r1 /* Save r1 */ |
| 956 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ |
| 957 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ |
| 958 | std r9,_CCR(r1) /* save CR in stackframe */ |
| 959 | mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ |
| 960 | std r11,_NIP(r1) /* save HSRR0 in stackframe */ |
| 961 | mfspr r12,SPRN_HSRR1 /* Save SRR1 */ |
| 962 | std r12,_MSR(r1) /* save SRR1 in stackframe */ |
| 963 | std r10,0(r1) /* make stack chain pointer */ |
| 964 | std r0,GPR0(r1) /* save r0 in stackframe */ |
| 965 | std r10,GPR1(r1) /* save r1 in stackframe */ |
| 966 | EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) |
| 967 | EXCEPTION_PROLOG_COMMON_3(0xe60) |
| 968 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 969 | bl hmi_exception_realmode |
| 970 | /* Windup the stack. */ |
| 971 | /* Move original HSRR0 and HSRR1 into the respective regs */ |
| 972 | ld r9,_MSR(r1) |
| 973 | mtspr SPRN_HSRR1,r9 |
| 974 | ld r3,_NIP(r1) |
| 975 | mtspr SPRN_HSRR0,r3 |
| 976 | ld r9,_CTR(r1) |
| 977 | mtctr r9 |
| 978 | ld r9,_XER(r1) |
| 979 | mtxer r9 |
| 980 | ld r9,_LINK(r1) |
| 981 | mtlr r9 |
| 982 | REST_GPR(0, r1) |
| 983 | REST_8GPRS(2, r1) |
| 984 | REST_GPR(10, r1) |
| 985 | ld r11,_CCR(r1) |
| 986 | mtcr r11 |
| 987 | REST_GPR(11, r1) |
| 988 | REST_2GPRS(12, r1) |
| 989 | /* restore original r1. */ |
| 990 | ld r1,GPR1(r1) |
| 991 | |
| 992 | /* |
| 993 | * Go to virtual mode and pull the HMI event information from |
| 994 | * firmware. |
| 995 | */ |
| 996 | .globl hmi_exception_after_realmode |
| 997 | hmi_exception_after_realmode: |
| 998 | SET_SCRATCH0(r13) |
| 999 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
| 1000 | b tramp_real_hmi_exception |
| 1001 | |
| 1002 | EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception) |
| 1003 | |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 1004 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1005 | __EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0xea0) |
Nicholas Piggin | 9bcb81b | 2016-09-21 17:43:50 +1000 | [diff] [blame] | 1006 | __TRAMP_REAL_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80) |
| 1007 | __EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x4ea0) |
| 1008 | __TRAMP_REAL_VIRT_OOL_MASKABLE_HV(h_doorbell, 0xe80) |
| 1009 | TRAMP_KVM_HV(PACA_EXGEN, 0xe80) |
| 1010 | #ifdef CONFIG_PPC_DOORBELL |
| 1011 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) |
| 1012 | #else |
| 1013 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) |
| 1014 | #endif |
| 1015 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1016 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1017 | __EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0xec0) |
Nicholas Piggin | 7440877 | 2016-09-21 17:43:51 +1000 | [diff] [blame] | 1018 | __TRAMP_REAL_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0) |
| 1019 | __EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x4ec0) |
| 1020 | __TRAMP_REAL_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0xea0) |
| 1021 | TRAMP_KVM_HV(PACA_EXGEN, 0xea0) |
| 1022 | EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) |
| 1023 | |
Benjamin Herrenschmidt | 9baaef0a | 2016-07-08 16:37:06 +1000 | [diff] [blame] | 1024 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1025 | EXC_REAL_NONE(0xec0, 0xf00) |
Nicholas Piggin | bda7fea | 2016-09-21 17:43:52 +1000 | [diff] [blame] | 1026 | EXC_VIRT_NONE(0x4ec0, 0x4f00) |
| 1027 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1028 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1029 | __EXC_REAL_OOL(performance_monitor, 0xf00, 0xf20) |
Nicholas Piggin | b1c7f15 | 2016-09-21 17:43:53 +1000 | [diff] [blame] | 1030 | __TRAMP_REAL_REAL_OOL(performance_monitor, 0xf00) |
| 1031 | __EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x4f20) |
| 1032 | __TRAMP_REAL_VIRT_OOL(performance_monitor, 0xf00) |
| 1033 | TRAMP_KVM(PACA_EXGEN, 0xf00) |
| 1034 | EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) |
| 1035 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1036 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1037 | __EXC_REAL_OOL(altivec_unavailable, 0xf20, 0xf40) |
Nicholas Piggin | d1a0ca9 | 2016-09-21 17:43:54 +1000 | [diff] [blame] | 1038 | __TRAMP_REAL_REAL_OOL(altivec_unavailable, 0xf20) |
| 1039 | __EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x4f40) |
| 1040 | __TRAMP_REAL_VIRT_OOL(altivec_unavailable, 0xf20) |
| 1041 | TRAMP_KVM(PACA_EXGEN, 0xf20) |
| 1042 | EXC_COMMON_BEGIN(altivec_unavailable_common) |
| 1043 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) |
| 1044 | #ifdef CONFIG_ALTIVEC |
| 1045 | BEGIN_FTR_SECTION |
| 1046 | beq 1f |
| 1047 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 1048 | BEGIN_FTR_SECTION_NESTED(69) |
| 1049 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in |
| 1050 | * transaction), go do TM stuff |
| 1051 | */ |
| 1052 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) |
| 1053 | bne- 2f |
| 1054 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) |
| 1055 | #endif |
| 1056 | bl load_up_altivec |
| 1057 | b fast_exception_return |
| 1058 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 1059 | 2: /* User process was in a transaction */ |
| 1060 | bl save_nvgprs |
| 1061 | RECONCILE_IRQ_STATE(r10, r11) |
| 1062 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 1063 | bl altivec_unavailable_tm |
| 1064 | b ret_from_except |
| 1065 | #endif |
| 1066 | 1: |
| 1067 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
| 1068 | #endif |
| 1069 | bl save_nvgprs |
| 1070 | RECONCILE_IRQ_STATE(r10, r11) |
| 1071 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 1072 | bl altivec_unavailable_exception |
| 1073 | b ret_from_except |
| 1074 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1075 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1076 | __EXC_REAL_OOL(vsx_unavailable, 0xf40, 0xf60) |
Nicholas Piggin | 792cbdd | 2016-09-21 17:43:55 +1000 | [diff] [blame] | 1077 | __TRAMP_REAL_REAL_OOL(vsx_unavailable, 0xf40) |
| 1078 | __EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x4f60) |
| 1079 | __TRAMP_REAL_VIRT_OOL(vsx_unavailable, 0xf40) |
| 1080 | TRAMP_KVM(PACA_EXGEN, 0xf40) |
| 1081 | EXC_COMMON_BEGIN(vsx_unavailable_common) |
| 1082 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) |
| 1083 | #ifdef CONFIG_VSX |
| 1084 | BEGIN_FTR_SECTION |
| 1085 | beq 1f |
| 1086 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 1087 | BEGIN_FTR_SECTION_NESTED(69) |
| 1088 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in |
| 1089 | * transaction), go do TM stuff |
| 1090 | */ |
| 1091 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) |
| 1092 | bne- 2f |
| 1093 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) |
| 1094 | #endif |
| 1095 | b load_up_vsx |
| 1096 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 1097 | 2: /* User process was in a transaction */ |
| 1098 | bl save_nvgprs |
| 1099 | RECONCILE_IRQ_STATE(r10, r11) |
| 1100 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 1101 | bl vsx_unavailable_tm |
| 1102 | b ret_from_except |
| 1103 | #endif |
| 1104 | 1: |
| 1105 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) |
| 1106 | #endif |
| 1107 | bl save_nvgprs |
| 1108 | RECONCILE_IRQ_STATE(r10, r11) |
| 1109 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 1110 | bl vsx_unavailable_exception |
| 1111 | b ret_from_except |
| 1112 | |
Michael Neuling | d0c0c9a | 2013-02-13 16:21:38 +0000 | [diff] [blame] | 1113 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1114 | __EXC_REAL_OOL(facility_unavailable, 0xf60, 0xf80) |
Nicholas Piggin | 1134713 | 2016-09-21 17:43:56 +1000 | [diff] [blame] | 1115 | __TRAMP_REAL_REAL_OOL(facility_unavailable, 0xf60) |
| 1116 | __EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x4f80) |
| 1117 | __TRAMP_REAL_VIRT_OOL(facility_unavailable, 0xf60) |
| 1118 | TRAMP_KVM(PACA_EXGEN, 0xf60) |
| 1119 | EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) |
| 1120 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1121 | |
| 1122 | __EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0xfa0) |
Nicholas Piggin | 14b0072 | 2016-09-21 17:43:57 +1000 | [diff] [blame] | 1123 | __TRAMP_REAL_REAL_OOL_HV(h_facility_unavailable, 0xf80) |
| 1124 | __EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x4fa0) |
| 1125 | __TRAMP_REAL_VIRT_OOL_HV(h_facility_unavailable, 0xf80) |
| 1126 | TRAMP_KVM_HV(PACA_EXGEN, 0xf80) |
| 1127 | EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) |
| 1128 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1129 | |
| 1130 | EXC_REAL_NONE(0xfa0, 0x1200) |
Nicholas Piggin | e46b964 | 2016-09-21 17:43:58 +1000 | [diff] [blame] | 1131 | EXC_VIRT_NONE(0x4fa0, 0x5200) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1132 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1133 | #ifdef CONFIG_CBE_RAS |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1134 | EXC_REAL_HV(cbe_system_error, 0x1200, 0x1300) |
Nicholas Piggin | ff1b320 | 2016-09-21 17:43:59 +1000 | [diff] [blame] | 1135 | EXC_VIRT_NONE(0x5200, 0x5300) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1136 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) |
Nicholas Piggin | ff1b320 | 2016-09-21 17:43:59 +1000 | [diff] [blame] | 1137 | EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1138 | #else /* CONFIG_CBE_RAS */ |
| 1139 | EXC_REAL_NONE(0x1200, 0x1300) |
| 1140 | #endif |
| 1141 | |
Nicholas Piggin | ff1b320 | 2016-09-21 17:43:59 +1000 | [diff] [blame] | 1142 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1143 | EXC_REAL(instruction_breakpoint, 0x1300, 0x1400) |
Nicholas Piggin | 4e96dbb | 2016-09-21 17:44:00 +1000 | [diff] [blame] | 1144 | EXC_VIRT(instruction_breakpoint, 0x5300, 0x5400, 0x1300) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1145 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) |
Nicholas Piggin | 4e96dbb | 2016-09-21 17:44:00 +1000 | [diff] [blame] | 1146 | EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) |
| 1147 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1148 | |
| 1149 | EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x1600) |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1150 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 1151 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
Paul Mackerras | 630573c | 2013-08-12 16:12:06 +1000 | [diff] [blame] | 1152 | EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1153 | |
| 1154 | #ifdef CONFIG_PPC_DENORMALISATION |
| 1155 | mfspr r10,SPRN_HSRR1 |
| 1156 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ |
| 1157 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ |
| 1158 | addi r11,r11,-4 /* HSRR0 is next instruction */ |
| 1159 | bne+ denorm_assist |
| 1160 | #endif |
| 1161 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1162 | KVMTEST_PR(0x1500) |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1163 | EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1164 | EXC_REAL_END(denorm_exception_hv, 0x1500, 0x1600) |
| 1165 | |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1166 | #ifdef CONFIG_PPC_DENORMALISATION |
| 1167 | EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x5600) |
| 1168 | b exc_real_0x1500_denorm_exception_hv |
| 1169 | EXC_VIRT_END(denorm_exception, 0x5500, 0x5600) |
| 1170 | #else |
| 1171 | EXC_VIRT_NONE(0x5500, 0x5600) |
| 1172 | #endif |
| 1173 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1174 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500) |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1175 | |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1176 | #ifdef CONFIG_PPC_DENORMALISATION |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1177 | TRAMP_REAL_BEGIN(denorm_assist) |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1178 | BEGIN_FTR_SECTION |
| 1179 | /* |
| 1180 | * To denormalise we need to move a copy of the register to itself. |
| 1181 | * For POWER6 do that here for all FP regs. |
| 1182 | */ |
| 1183 | mfmsr r10 |
| 1184 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) |
| 1185 | xori r10,r10,(MSR_FE0|MSR_FE1) |
| 1186 | mtmsrd r10 |
| 1187 | sync |
Michael Neuling | d7c67fb | 2013-05-29 21:33:18 +0000 | [diff] [blame] | 1188 | |
| 1189 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 |
| 1190 | #define FMR4(n) FMR2(n) ; FMR2(n+2) |
| 1191 | #define FMR8(n) FMR4(n) ; FMR4(n+4) |
| 1192 | #define FMR16(n) FMR8(n) ; FMR8(n+8) |
| 1193 | #define FMR32(n) FMR16(n) ; FMR16(n+16) |
| 1194 | FMR32(0) |
| 1195 | |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1196 | FTR_SECTION_ELSE |
| 1197 | /* |
| 1198 | * To denormalise we need to move a copy of the register to itself. |
| 1199 | * For POWER7 do that here for the first 32 VSX registers only. |
| 1200 | */ |
| 1201 | mfmsr r10 |
| 1202 | oris r10,r10,MSR_VSX@h |
| 1203 | mtmsrd r10 |
| 1204 | sync |
Michael Neuling | d7c67fb | 2013-05-29 21:33:18 +0000 | [diff] [blame] | 1205 | |
| 1206 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) |
| 1207 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) |
| 1208 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) |
| 1209 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) |
| 1210 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) |
| 1211 | XVCPSGNDP32(0) |
| 1212 | |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1213 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
Michael Neuling | fb0fce3 | 2013-05-29 21:33:19 +0000 | [diff] [blame] | 1214 | |
| 1215 | BEGIN_FTR_SECTION |
| 1216 | b denorm_done |
| 1217 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) |
| 1218 | /* |
| 1219 | * To denormalise we need to move a copy of the register to itself. |
| 1220 | * For POWER8 we need to do that for all 64 VSX registers |
| 1221 | */ |
| 1222 | XVCPSGNDP32(32) |
| 1223 | denorm_done: |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1224 | mtspr SPRN_HSRR0,r11 |
| 1225 | mtcrf 0x80,r9 |
| 1226 | ld r9,PACA_EXGEN+EX_R9(r13) |
Haren Myneni | 44e9309 | 2012-12-06 21:51:04 +0000 | [diff] [blame] | 1227 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
Paul Mackerras | 630573c | 2013-08-12 16:12:06 +1000 | [diff] [blame] | 1228 | BEGIN_FTR_SECTION |
| 1229 | ld r10,PACA_EXGEN+EX_CFAR(r13) |
| 1230 | mtspr SPRN_CFAR,r10 |
| 1231 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1232 | ld r10,PACA_EXGEN+EX_R10(r13) |
| 1233 | ld r11,PACA_EXGEN+EX_R11(r13) |
| 1234 | ld r12,PACA_EXGEN+EX_R12(r13) |
| 1235 | ld r13,PACA_EXGEN+EX_R13(r13) |
| 1236 | HRFID |
| 1237 | b . |
| 1238 | #endif |
| 1239 | |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1240 | EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) |
| 1241 | |
| 1242 | |
| 1243 | #ifdef CONFIG_CBE_RAS |
| 1244 | EXC_REAL_HV(cbe_maintenance, 0x1600, 0x1700) |
Nicholas Piggin | 69a7934 | 2016-09-21 17:44:02 +1000 | [diff] [blame^] | 1245 | EXC_VIRT_NONE(0x5600, 0x5700) |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1246 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) |
Nicholas Piggin | 69a7934 | 2016-09-21 17:44:02 +1000 | [diff] [blame^] | 1247 | EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1248 | #else /* CONFIG_CBE_RAS */ |
| 1249 | EXC_REAL_NONE(0x1600, 0x1700) |
| 1250 | #endif |
| 1251 | |
Nicholas Piggin | 69a7934 | 2016-09-21 17:44:02 +1000 | [diff] [blame^] | 1252 | |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1253 | EXC_REAL(altivec_assist, 0x1700, 0x1800) |
| 1254 | |
| 1255 | TRAMP_KVM(PACA_EXGEN, 0x1700) |
| 1256 | |
| 1257 | #ifdef CONFIG_CBE_RAS |
| 1258 | EXC_REAL_HV(cbe_thermal, 0x1800, 0x1900) |
| 1259 | |
| 1260 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) |
| 1261 | |
| 1262 | #else /* CONFIG_CBE_RAS */ |
| 1263 | EXC_REAL_NONE(0x1800, 0x1900) |
| 1264 | #endif |
| 1265 | |
| 1266 | |
| 1267 | /*** Out of line interrupts support ***/ |
| 1268 | |
| 1269 | /* moved from 0x200 */ |
| 1270 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1271 | /* |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1272 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
| 1273 | * - If it was a decrementer interrupt, we bump the dec to max and and return. |
| 1274 | * - If it was a doorbell we return immediately since doorbells are edge |
| 1275 | * triggered and won't automatically refire. |
Mahesh Salgaonkar | 0869b6f | 2014-07-29 18:40:01 +0530 | [diff] [blame] | 1276 | * - If it was a HMI we return immediately since we handled it in realmode |
| 1277 | * and it won't refire. |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1278 | * - else we hard disable and return. |
| 1279 | * This is called with r10 containing the value to OR to the paca field. |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1280 | */ |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1281 | #define MASKED_INTERRUPT(_H) \ |
| 1282 | masked_##_H##interrupt: \ |
| 1283 | std r11,PACA_EXGEN+EX_R11(r13); \ |
| 1284 | lbz r11,PACAIRQHAPPENED(r13); \ |
| 1285 | or r11,r11,r10; \ |
| 1286 | stb r11,PACAIRQHAPPENED(r13); \ |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1287 | cmpwi r10,PACA_IRQ_DEC; \ |
| 1288 | bne 1f; \ |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1289 | lis r10,0x7fff; \ |
| 1290 | ori r10,r10,0xffff; \ |
| 1291 | mtspr SPRN_DEC,r10; \ |
| 1292 | b 2f; \ |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1293 | 1: cmpwi r10,PACA_IRQ_DBELL; \ |
| 1294 | beq 2f; \ |
Mahesh Salgaonkar | 0869b6f | 2014-07-29 18:40:01 +0530 | [diff] [blame] | 1295 | cmpwi r10,PACA_IRQ_HMI; \ |
| 1296 | beq 2f; \ |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1297 | mfspr r10,SPRN_##_H##SRR1; \ |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1298 | rldicl r10,r10,48,1; /* clear MSR_EE */ \ |
| 1299 | rotldi r10,r10,16; \ |
| 1300 | mtspr SPRN_##_H##SRR1,r10; \ |
| 1301 | 2: mtcrf 0x80,r9; \ |
| 1302 | ld r9,PACA_EXGEN+EX_R9(r13); \ |
| 1303 | ld r10,PACA_EXGEN+EX_R10(r13); \ |
| 1304 | ld r11,PACA_EXGEN+EX_R11(r13); \ |
| 1305 | GET_SCRATCH0(r13); \ |
| 1306 | ##_H##rfid; \ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1307 | b . |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 1308 | |
| 1309 | /* |
| 1310 | * Real mode exceptions actually use this too, but alternate |
| 1311 | * instruction code patches (which end up in the common .text area) |
| 1312 | * cannot reach these if they are put there. |
| 1313 | */ |
| 1314 | USE_FIXED_SECTION(virt_trampolines) |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1315 | MASKED_INTERRUPT() |
| 1316 | MASKED_INTERRUPT(H) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1317 | |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1318 | /* |
| 1319 | * Called from arch_local_irq_enable when an interrupt needs |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1320 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate |
| 1321 | * which kind of interrupt. MSR:EE is already off. We generate a |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1322 | * stackframe like if a real interrupt had happened. |
| 1323 | * |
| 1324 | * Note: While MSR:EE is off, we need to make sure that _MSR |
| 1325 | * in the generated frame has EE set to 1 or the exception |
| 1326 | * handler will not properly re-enable them. |
| 1327 | */ |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 1328 | USE_TEXT_SECTION() |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1329 | _GLOBAL(__replay_interrupt) |
| 1330 | /* We are going to jump to the exception common code which |
| 1331 | * will retrieve various register values from the PACA which |
| 1332 | * we don't give a damn about, so we don't bother storing them. |
| 1333 | */ |
| 1334 | mfmsr r12 |
| 1335 | mflr r11 |
| 1336 | mfcr r9 |
| 1337 | ori r12,r12,MSR_EE |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1338 | cmpwi r3,0x900 |
| 1339 | beq decrementer_common |
| 1340 | cmpwi r3,0x500 |
| 1341 | beq hardware_interrupt_common |
| 1342 | BEGIN_FTR_SECTION |
| 1343 | cmpwi r3,0xe80 |
| 1344 | beq h_doorbell_common |
Benjamin Herrenschmidt | 9baaef0a | 2016-07-08 16:37:06 +1000 | [diff] [blame] | 1345 | cmpwi r3,0xea0 |
| 1346 | beq h_virt_irq_common |
Mahesh Salgaonkar | fd7bacb | 2016-05-15 09:44:26 +0530 | [diff] [blame] | 1347 | cmpwi r3,0xe60 |
| 1348 | beq hmi_exception_common |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1349 | FTR_SECTION_ELSE |
| 1350 | cmpwi r3,0xa00 |
| 1351 | beq doorbell_super_common |
| 1352 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
| 1353 | blr |
Benjamin Herrenschmidt | a5d4f3a | 2011-04-05 14:20:31 +1000 | [diff] [blame] | 1354 | |
Paul Mackerras | 4f6c11d | 2013-09-20 14:52:50 +1000 | [diff] [blame] | 1355 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1356 | TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) |
Paul Mackerras | 4f6c11d | 2013-09-20 14:52:50 +1000 | [diff] [blame] | 1357 | /* |
| 1358 | * Here all GPRs are unchanged from when the interrupt happened |
| 1359 | * except for r13, which is saved in SPRG_SCRATCH0. |
| 1360 | */ |
| 1361 | mfspr r13, SPRN_SRR0 |
| 1362 | addi r13, r13, 4 |
| 1363 | mtspr SPRN_SRR0, r13 |
| 1364 | GET_SCRATCH0(r13) |
| 1365 | rfid |
| 1366 | b . |
| 1367 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1368 | TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) |
Paul Mackerras | 4f6c11d | 2013-09-20 14:52:50 +1000 | [diff] [blame] | 1369 | /* |
| 1370 | * Here all GPRs are unchanged from when the interrupt happened |
| 1371 | * except for r13, which is saved in SPRG_SCRATCH0. |
| 1372 | */ |
| 1373 | mfspr r13, SPRN_HSRR0 |
| 1374 | addi r13, r13, 4 |
| 1375 | mtspr SPRN_HSRR0, r13 |
| 1376 | GET_SCRATCH0(r13) |
| 1377 | hrfid |
| 1378 | b . |
| 1379 | #endif |
| 1380 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1381 | /* |
Hari Bathini | 057b6d7 | 2016-04-08 03:30:34 +0530 | [diff] [blame] | 1382 | * Ensure that any handlers that get invoked from the exception prologs |
| 1383 | * above are below the first 64KB (0x10000) of the kernel image because |
| 1384 | * the prologs assemble the addresses of these handlers using the |
| 1385 | * LOAD_HANDLER macro, which uses an ori instruction. |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1386 | */ |
| 1387 | |
| 1388 | /*** Common interrupt handlers ***/ |
| 1389 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1390 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1391 | #ifdef CONFIG_ALTIVEC |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1392 | EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1393 | #else |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1394 | EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1395 | #endif |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1396 | |
Michael Neuling | c1fb681 | 2012-11-02 17:21:43 +1100 | [diff] [blame] | 1397 | /* |
| 1398 | * Relocation-on interrupts: A subset of the interrupts can be delivered |
| 1399 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering |
| 1400 | * it. Addresses are the same as the original interrupt addresses, but |
| 1401 | * offset by 0xc000000000004000. |
| 1402 | * It's impossible to receive interrupts below 0x300 via this mechanism. |
| 1403 | * KVM: None of these traps are from the guest ; anything that escalated |
| 1404 | * to HV=1 from HV=0 is delivered via real mode handlers. |
| 1405 | */ |
| 1406 | |
| 1407 | /* |
| 1408 | * This uses the standard macro, since the original 0x300 vector |
| 1409 | * only has extra guff for STAB-based processors -- which never |
| 1410 | * come here. |
| 1411 | */ |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1412 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1413 | EXC_VIRT(altivec_assist, 0x5700, 0x5800, 0x1700) |
| 1414 | |
| 1415 | EXC_VIRT_NONE(0x5800, 0x5900) |
| 1416 | |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 1417 | EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1418 | b __ppc64_runlatch_on |
Benjamin Herrenschmidt | fe1952f | 2012-03-01 12:45:27 +1100 | [diff] [blame] | 1419 | |
Benjamin Herrenschmidt | 6138340 | 2013-01-10 17:44:19 +1100 | [diff] [blame] | 1420 | /* Equivalents to the above handlers for relocation-on interrupt vectors */ |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 1421 | USE_FIXED_SECTION(virt_trampolines) |
Hari Bathini | 8ed8ab4 | 2016-04-15 22:48:02 +1000 | [diff] [blame] | 1422 | /* |
| 1423 | * The __end_interrupts marker must be past the out-of-line (OOL) |
| 1424 | * handlers, so that they are copied to real address 0x100 when running |
| 1425 | * a relocatable kernel. This ensures they can be reached from the short |
| 1426 | * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch |
| 1427 | * directly, without using LOAD_HANDLER(). |
| 1428 | */ |
| 1429 | .align 7 |
| 1430 | .globl __end_interrupts |
| 1431 | __end_interrupts: |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 1432 | DEFINE_FIXED_SYMBOL(__end_interrupts) |
Benjamin Herrenschmidt | 6138340 | 2013-01-10 17:44:19 +1100 | [diff] [blame] | 1433 | |
Benjamin Herrenschmidt | b88d4bc | 2016-07-16 17:58:25 -0500 | [diff] [blame] | 1434 | #ifdef CONFIG_CBE_RAS |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1435 | EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) |
Benjamin Herrenschmidt | b88d4bc | 2016-07-16 17:58:25 -0500 | [diff] [blame] | 1436 | #endif /* CONFIG_CBE_RAS */ |
| 1437 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1438 | |
Chen Gang | 087aa03 | 2013-03-25 09:31:31 +0800 | [diff] [blame] | 1439 | #ifdef CONFIG_PPC_970_NAP |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1440 | TRAMP_REAL_BEGIN(power4_fixup_nap) |
Chen Gang | 087aa03 | 2013-03-25 09:31:31 +0800 | [diff] [blame] | 1441 | andc r9,r9,r10 |
| 1442 | std r9,TI_LOCAL_FLAGS(r11) |
| 1443 | ld r10,_LINK(r1) /* make idle task do the */ |
| 1444 | std r10,_NIP(r1) /* equivalent of a blr */ |
| 1445 | blr |
| 1446 | #endif |
| 1447 | |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 1448 | CLOSE_FIXED_SECTION(real_vectors); |
| 1449 | CLOSE_FIXED_SECTION(real_trampolines); |
| 1450 | CLOSE_FIXED_SECTION(virt_vectors); |
| 1451 | CLOSE_FIXED_SECTION(virt_trampolines); |
| 1452 | |
| 1453 | USE_TEXT_SECTION() |
| 1454 | |
Chen Gang | 087aa03 | 2013-03-25 09:31:31 +0800 | [diff] [blame] | 1455 | /* |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1456 | * Hash table stuff |
| 1457 | */ |
| 1458 | .align 7 |
Anton Blanchard | 6a3bab9 | 2014-02-04 16:06:11 +1100 | [diff] [blame] | 1459 | do_hash_page: |
Aneesh Kumar K.V | caca285 | 2016-04-29 23:26:07 +1000 | [diff] [blame] | 1460 | #ifdef CONFIG_PPC_STD_MMU_64 |
K.Prasad | 9c7cc23 | 2010-03-29 23:59:25 +0000 | [diff] [blame] | 1461 | andis. r0,r4,0xa410 /* weird error? */ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1462 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
K.Prasad | 9c7cc23 | 2010-03-29 23:59:25 +0000 | [diff] [blame] | 1463 | andis. r0,r4,DSISR_DABRMATCH@h |
| 1464 | bne- handle_dabr_fault |
Stuart Yoder | 9778b69 | 2012-07-05 04:41:35 +0000 | [diff] [blame] | 1465 | CURRENT_THREAD_INFO(r11, r1) |
Paul Mackerras | 9c1e105 | 2009-08-17 15:17:54 +1000 | [diff] [blame] | 1466 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
| 1467 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ |
| 1468 | bne 77f /* then don't call hash_page now */ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1469 | |
| 1470 | /* |
| 1471 | * r3 contains the faulting address |
Aneesh Kumar K.V | 106713a | 2015-12-01 09:06:44 +0530 | [diff] [blame] | 1472 | * r4 msr |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1473 | * r5 contains the trap number |
Aneesh Kumar K.V | aefa568 | 2014-12-04 11:00:14 +0530 | [diff] [blame] | 1474 | * r6 contains dsisr |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1475 | * |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1476 | * at return r3 = 0 for success, 1 for page fault, negative for error |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1477 | */ |
Aneesh Kumar K.V | 106713a | 2015-12-01 09:06:44 +0530 | [diff] [blame] | 1478 | mr r4,r12 |
Aneesh Kumar K.V | aefa568 | 2014-12-04 11:00:14 +0530 | [diff] [blame] | 1479 | ld r6,_DSISR(r1) |
Aneesh Kumar K.V | 106713a | 2015-12-01 09:06:44 +0530 | [diff] [blame] | 1480 | bl __hash_page /* build HPTE if possible */ |
| 1481 | cmpdi r3,0 /* see if __hash_page succeeded */ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1482 | |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1483 | /* Success */ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1484 | beq fast_exc_return_irq /* Return from exception on success */ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1485 | |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1486 | /* Error */ |
| 1487 | blt- 13f |
Aneesh Kumar K.V | caca285 | 2016-04-29 23:26:07 +1000 | [diff] [blame] | 1488 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1489 | |
Benjamin Herrenschmidt | a546498 | 2012-03-07 16:48:45 +1100 | [diff] [blame] | 1490 | /* Here we have a page fault that hash_page can't handle. */ |
| 1491 | handle_page_fault: |
| 1492 | 11: ld r4,_DAR(r1) |
| 1493 | ld r5,_DSISR(r1) |
| 1494 | addi r3,r1,STACK_FRAME_OVERHEAD |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1495 | bl do_page_fault |
Benjamin Herrenschmidt | a546498 | 2012-03-07 16:48:45 +1100 | [diff] [blame] | 1496 | cmpdi r3,0 |
| 1497 | beq+ 12f |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1498 | bl save_nvgprs |
Benjamin Herrenschmidt | a546498 | 2012-03-07 16:48:45 +1100 | [diff] [blame] | 1499 | mr r5,r3 |
| 1500 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 1501 | lwz r4,_DAR(r1) |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1502 | bl bad_page_fault |
| 1503 | b ret_from_except |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1504 | |
K.Prasad | 9c7cc23 | 2010-03-29 23:59:25 +0000 | [diff] [blame] | 1505 | /* We have a data breakpoint exception - handle it */ |
| 1506 | handle_dabr_fault: |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1507 | bl save_nvgprs |
K.Prasad | 9c7cc23 | 2010-03-29 23:59:25 +0000 | [diff] [blame] | 1508 | ld r4,_DAR(r1) |
| 1509 | ld r5,_DSISR(r1) |
| 1510 | addi r3,r1,STACK_FRAME_OVERHEAD |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1511 | bl do_break |
| 1512 | 12: b ret_from_except_lite |
K.Prasad | 9c7cc23 | 2010-03-29 23:59:25 +0000 | [diff] [blame] | 1513 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1514 | |
Aneesh Kumar K.V | caca285 | 2016-04-29 23:26:07 +1000 | [diff] [blame] | 1515 | #ifdef CONFIG_PPC_STD_MMU_64 |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1516 | /* We have a page fault that hash_page could handle but HV refused |
| 1517 | * the PTE insertion |
| 1518 | */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1519 | 13: bl save_nvgprs |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1520 | mr r5,r3 |
| 1521 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 1522 | ld r4,_DAR(r1) |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1523 | bl low_hash_fault |
| 1524 | b ret_from_except |
Aneesh Kumar K.V | caca285 | 2016-04-29 23:26:07 +1000 | [diff] [blame] | 1525 | #endif |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1526 | |
Paul Mackerras | 9c1e105 | 2009-08-17 15:17:54 +1000 | [diff] [blame] | 1527 | /* |
| 1528 | * We come here as a result of a DSI at a point where we don't want |
| 1529 | * to call hash_page, such as when we are accessing memory (possibly |
| 1530 | * user memory) inside a PMU interrupt that occurred while interrupts |
| 1531 | * were soft-disabled. We want to invoke the exception handler for |
| 1532 | * the access, or panic if there isn't a handler. |
| 1533 | */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1534 | 77: bl save_nvgprs |
Paul Mackerras | 9c1e105 | 2009-08-17 15:17:54 +1000 | [diff] [blame] | 1535 | mr r4,r3 |
| 1536 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 1537 | li r5,SIGSEGV |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1538 | bl bad_page_fault |
| 1539 | b ret_from_except |
Michael Ellerman | 4e2bf01 | 2014-07-15 20:25:02 +1000 | [diff] [blame] | 1540 | |
| 1541 | /* |
| 1542 | * Here we have detected that the kernel stack pointer is bad. |
| 1543 | * R9 contains the saved CR, r13 points to the paca, |
| 1544 | * r10 contains the (bad) kernel stack pointer, |
| 1545 | * r11 and r12 contain the saved SRR0 and SRR1. |
| 1546 | * We switch to using an emergency stack, save the registers there, |
| 1547 | * and call kernel_bad_stack(), which panics. |
| 1548 | */ |
| 1549 | bad_stack: |
| 1550 | ld r1,PACAEMERGSP(r13) |
| 1551 | subi r1,r1,64+INT_FRAME_SIZE |
| 1552 | std r9,_CCR(r1) |
| 1553 | std r10,GPR1(r1) |
| 1554 | std r11,_NIP(r1) |
| 1555 | std r12,_MSR(r1) |
| 1556 | mfspr r11,SPRN_DAR |
| 1557 | mfspr r12,SPRN_DSISR |
| 1558 | std r11,_DAR(r1) |
| 1559 | std r12,_DSISR(r1) |
| 1560 | mflr r10 |
| 1561 | mfctr r11 |
| 1562 | mfxer r12 |
| 1563 | std r10,_LINK(r1) |
| 1564 | std r11,_CTR(r1) |
| 1565 | std r12,_XER(r1) |
| 1566 | SAVE_GPR(0,r1) |
| 1567 | SAVE_GPR(2,r1) |
| 1568 | ld r10,EX_R3(r3) |
| 1569 | std r10,GPR3(r1) |
| 1570 | SAVE_GPR(4,r1) |
| 1571 | SAVE_4GPRS(5,r1) |
| 1572 | ld r9,EX_R9(r3) |
| 1573 | ld r10,EX_R10(r3) |
| 1574 | SAVE_2GPRS(9,r1) |
| 1575 | ld r9,EX_R11(r3) |
| 1576 | ld r10,EX_R12(r3) |
| 1577 | ld r11,EX_R13(r3) |
| 1578 | std r9,GPR11(r1) |
| 1579 | std r10,GPR12(r1) |
| 1580 | std r11,GPR13(r1) |
| 1581 | BEGIN_FTR_SECTION |
| 1582 | ld r10,EX_CFAR(r3) |
| 1583 | std r10,ORIG_GPR3(r1) |
| 1584 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) |
| 1585 | SAVE_8GPRS(14,r1) |
| 1586 | SAVE_10GPRS(22,r1) |
| 1587 | lhz r12,PACA_TRAP_SAVE(r13) |
| 1588 | std r12,_TRAP(r1) |
| 1589 | addi r11,r1,INT_FRAME_SIZE |
| 1590 | std r11,0(r1) |
| 1591 | li r12,0 |
| 1592 | std r12,0(r11) |
| 1593 | ld r2,PACATOC(r13) |
| 1594 | ld r11,exception_marker@toc(r2) |
| 1595 | std r12,RESULT(r1) |
| 1596 | std r11,STACK_FRAME_OVERHEAD-16(r1) |
| 1597 | 1: addi r3,r1,STACK_FRAME_OVERHEAD |
| 1598 | bl kernel_bad_stack |
| 1599 | b 1b |