| Philippe De Muyter | ea49f8ff | 2010-09-20 13:11:11 +0200 | [diff] [blame] | 1 | /****************************************************************************/ |
| 2 | |
| 3 | /* |
| 4 | * mcfslt.h -- ColdFire internal Slice (SLT) timer support defines. |
| 5 | * |
| 6 | * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) |
| 7 | * (C) Copyright 2009, Philippe De Muyter (phdm@macqel.be) |
| 8 | */ |
| 9 | |
| 10 | /****************************************************************************/ |
| 11 | #ifndef mcfslt_h |
| 12 | #define mcfslt_h |
| 13 | /****************************************************************************/ |
| 14 | |
| 15 | /* |
| 16 | * Get address specific defines for the 547x. |
| 17 | */ |
| 18 | #define MCFSLT_TIMER0 0x900 /* Base address of TIMER0 */ |
| 19 | #define MCFSLT_TIMER1 0x910 /* Base address of TIMER1 */ |
| 20 | |
| 21 | |
| 22 | /* |
| 23 | * Define the SLT timer register set addresses. |
| 24 | */ |
| 25 | #define MCFSLT_STCNT 0x00 /* Terminal count */ |
| 26 | #define MCFSLT_SCR 0x04 /* Control */ |
| 27 | #define MCFSLT_SCNT 0x08 /* Current count */ |
| 28 | #define MCFSLT_SSR 0x0C /* Status */ |
| 29 | |
| 30 | /* |
| 31 | * Bit definitions for the SCR control register. |
| 32 | */ |
| 33 | #define MCFSLT_SCR_RUN 0x04000000 /* Run mode (continuous) */ |
| 34 | #define MCFSLT_SCR_IEN 0x02000000 /* Interrupt enable */ |
| 35 | #define MCFSLT_SCR_TEN 0x01000000 /* Timer enable */ |
| 36 | |
| 37 | /* |
| 38 | * Bit definitions for the SSR status register. |
| 39 | */ |
| 40 | #define MCFSLT_SSR_BE 0x02000000 /* Bus error condition */ |
| 41 | #define MCFSLT_SSR_TE 0x01000000 /* Timeout condition */ |
| 42 | |
| 43 | /****************************************************************************/ |
| 44 | #endif /* mcfslt_h */ |