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gerrit-public.fairphone.software / kernel / msm-4.9 / 6a878184c202395ea17212f111ab9ec4b5f6d6ee / . / drivers / isdn / hisax / hisax.h
blob: 1b85ce166af8c48b13fe74930d45a66555b7ca63 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/* $Id: hisax.h,v 2.64.2.4 2004/02/11 13:21:33 keil Exp $
2 *
3 * Basic declarations, defines and prototypes
4 *
5 * This software may be used and distributed according to the terms
6 * of the GNU General Public License, incorporated herein by reference.
7 *
8 */
9#include <linux/config.h>
10#include <linux/errno.h>
11#include <linux/fs.h>
12#include <linux/major.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]13#include <asm/io.h>
14#include <linux/delay.h>
15#include <linux/kernel.h>
16#include <linux/signal.h>
17#include <linux/slab.h>
18#include <linux/mm.h>
19#include <linux/mman.h>
20#include <linux/ioport.h>
21#include <linux/timer.h>
22#include <linux/wait.h>
23#include <linux/isdnif.h>
24#include <linux/tty.h>
25#include <linux/serial_reg.h>
26#include <linux/netdevice.h>
27
28#define ERROR_STATISTIC
29
30#define REQUEST 0
31#define CONFIRM 1
32#define INDICATION 2
33#define RESPONSE 3
34
35#define HW_ENABLE 0x0000
36#define HW_RESET 0x0004
37#define HW_POWERUP 0x0008
38#define HW_ACTIVATE 0x0010
39#define HW_DEACTIVATE 0x0018
40
41#define HW_INFO1 0x0010
42#define HW_INFO2 0x0020
43#define HW_INFO3 0x0030
44#define HW_INFO4 0x0040
45#define HW_INFO4_P8 0x0040
46#define HW_INFO4_P10 0x0048
47#define HW_RSYNC 0x0060
48#define HW_TESTLOOP 0x0070
49#define CARD_RESET 0x00F0
50#define CARD_INIT 0x00F2
51#define CARD_RELEASE 0x00F3
52#define CARD_TEST 0x00F4
53#define CARD_AUX_IND 0x00F5
54
55#define PH_ACTIVATE 0x0100
56#define PH_DEACTIVATE 0x0110
57#define PH_DATA 0x0120
58#define PH_PULL 0x0130
59#define PH_TESTLOOP 0x0140
60#define PH_PAUSE 0x0150
61#define MPH_ACTIVATE 0x0180
62#define MPH_DEACTIVATE 0x0190
63#define MPH_INFORMATION 0x01A0
64
65#define DL_ESTABLISH 0x0200
66#define DL_RELEASE 0x0210
67#define DL_DATA 0x0220
68#define DL_FLUSH 0x0224
69#define DL_UNIT_DATA 0x0230
70
71#define MDL_BC_RELEASE 0x0278 // Formula-n enter:now
72#define MDL_BC_ASSIGN 0x027C // Formula-n enter:now
73#define MDL_ASSIGN 0x0280
74#define MDL_REMOVE 0x0284
75#define MDL_ERROR 0x0288
76#define MDL_INFO_SETUP 0x02E0
77#define MDL_INFO_CONN 0x02E4
78#define MDL_INFO_REL 0x02E8
79
80#define CC_SETUP 0x0300
81#define CC_RESUME 0x0304
82#define CC_MORE_INFO 0x0310
83#define CC_IGNORE 0x0320
84#define CC_REJECT 0x0324
85#define CC_SETUP_COMPL 0x0330
86#define CC_PROCEEDING 0x0340
87#define CC_ALERTING 0x0344
88#define CC_PROGRESS 0x0348
89#define CC_CONNECT 0x0350
90#define CC_CHARGE 0x0354
91#define CC_NOTIFY 0x0358
92#define CC_DISCONNECT 0x0360
93#define CC_RELEASE 0x0368
94#define CC_SUSPEND 0x0370
95#define CC_PROCEED_SEND 0x0374
96#define CC_REDIR 0x0378
97#define CC_T302 0x0382
98#define CC_T303 0x0383
99#define CC_T304 0x0384
100#define CC_T305 0x0385
101#define CC_T308_1 0x0388
102#define CC_T308_2 0x038A
103#define CC_T309 0x0309
104#define CC_T310 0x0390
105#define CC_T313 0x0393
106#define CC_T318 0x0398
107#define CC_T319 0x0399
108#define CC_TSPID 0x03A0
109#define CC_NOSETUP_RSP 0x03E0
110#define CC_SETUP_ERR 0x03E1
111#define CC_SUSPEND_ERR 0x03E2
112#define CC_RESUME_ERR 0x03E3
113#define CC_CONNECT_ERR 0x03E4
114#define CC_RELEASE_ERR 0x03E5
115#define CC_RESTART 0x03F4
116#define CC_TDSS1_IO 0x13F4 /* DSS1 IO user timer */
117#define CC_TNI1_IO 0x13F5 /* NI1 IO user timer */
118
119/* define maximum number of possible waiting incoming calls */
120#define MAX_WAITING_CALLS 2
121
122
123#ifdef __KERNEL__
124
125/* include l3dss1 & ni1 specific process structures, but no other defines */
126#ifdef CONFIG_HISAX_EURO
127 #define l3dss1_process
128 #include "l3dss1.h"
129 #undef l3dss1_process
130#endif /* CONFIG_HISAX_EURO */
131
132#ifdef CONFIG_HISAX_NI1
133 #define l3ni1_process
134 #include "l3ni1.h"
135 #undef l3ni1_process
136#endif /* CONFIG_HISAX_NI1 */
137
138#define MAX_DFRAME_LEN 260
139#define MAX_DFRAME_LEN_L1 300
140#define HSCX_BUFMAX 4096
141#define MAX_DATA_SIZE (HSCX_BUFMAX - 4)
142#define MAX_DATA_MEM (HSCX_BUFMAX + 64)
143#define RAW_BUFMAX (((HSCX_BUFMAX*6)/5) + 5)
144#define MAX_HEADER_LEN 4
145#define MAX_WINDOW 8
146#define MAX_MON_FRAME 32
147#define MAX_DLOG_SPACE 2048
148#define MAX_BLOG_SPACE 256
149
150/* #define I4L_IRQ_FLAG SA_INTERRUPT */
151#define I4L_IRQ_FLAG 0
152
153/*
154 * Statemachine
155 */
156
157struct FsmInst;
158
159typedef void (* FSMFNPTR)(struct FsmInst *, int, void *);
160
161struct Fsm {
162 FSMFNPTR *jumpmatrix;
163 int state_count, event_count;
164 char **strEvent, **strState;
165};
166
167struct FsmInst {
168 struct Fsm *fsm;
169 int state;
170 int debug;
171 void *userdata;
172 int userint;
173 void (*printdebug) (struct FsmInst *, char *, ...);
174};
175
176struct FsmNode {
177 int state, event;
178 void (*routine) (struct FsmInst *, int, void *);
179};
180
181struct FsmTimer {
182 struct FsmInst *fi;
183 struct timer_list tl;
184 int event;
185 void *arg;
186};
187
188struct L3Timer {
189 struct l3_process *pc;
190 struct timer_list tl;
191 int event;
192};
193
194#define FLG_L1_ACTIVATING 1
195#define FLG_L1_ACTIVATED 2
196#define FLG_L1_DEACTTIMER 3
197#define FLG_L1_ACTTIMER 4
198#define FLG_L1_T3RUN 5
199#define FLG_L1_PULL_REQ 6
200#define FLG_L1_UINT 7
201
202struct Layer1 {
203 void *hardware;
204 struct BCState *bcs;
205 struct PStack **stlistp;
206 long Flags;
207 struct FsmInst l1m;
208 struct FsmTimer timer;
209 void (*l1l2) (struct PStack *, int, void *);
210 void (*l1hw) (struct PStack *, int, void *);
211 void (*l1tei) (struct PStack *, int, void *);
212 int mode, bc;
213 int delay;
214};
215
216#define GROUP_TEI 127
217#define TEI_SAPI 63
218#define CTRL_SAPI 0
219#define PACKET_NOACK 250
220
221/* Layer2 Flags */
222
223#define FLG_LAPB 0
224#define FLG_LAPD 1
225#define FLG_ORIG 2
226#define FLG_MOD128 3
227#define FLG_PEND_REL 4
228#define FLG_L3_INIT 5
229#define FLG_T200_RUN 6
230#define FLG_ACK_PEND 7
231#define FLG_REJEXC 8
232#define FLG_OWN_BUSY 9
233#define FLG_PEER_BUSY 10
234#define FLG_DCHAN_BUSY 11
235#define FLG_L1_ACTIV 12
236#define FLG_ESTAB_PEND 13
237#define FLG_PTP 14
238#define FLG_FIXED_TEI 15
239#define FLG_L2BLOCK 16
240
241struct Layer2 {
242 int tei;
243 int sap;
244 int maxlen;
245 u_long flag;
246 spinlock_t lock;
247 u_int vs, va, vr;
248 int rc;
249 unsigned int window;
250 unsigned int sow;
251 struct sk_buff *windowar[MAX_WINDOW];
252 struct sk_buff_head i_queue;
253 struct sk_buff_head ui_queue;
254 void (*l2l1) (struct PStack *, int, void *);
255 void (*l2l3) (struct PStack *, int, void *);
256 void (*l2tei) (struct PStack *, int, void *);
257 struct FsmInst l2m;
258 struct FsmTimer t200, t203;
259 int T200, N200, T203;
260 int debug;
261 char debug_id[16];
262};
263
264struct Layer3 {
265 void (*l3l4) (struct PStack *, int, void *);
266 void (*l3ml3) (struct PStack *, int, void *);
267 void (*l3l2) (struct PStack *, int, void *);
268 struct FsmInst l3m;
269 struct FsmTimer l3m_timer;
270 struct sk_buff_head squeue;
271 struct l3_process *proc;
272 struct l3_process *global;
273 int N303;
274 int debug;
275 char debug_id[8];
276};
277
278struct LLInterface {
279 void (*l4l3) (struct PStack *, int, void *);
280 int (*l4l3_proto) (struct PStack *, isdn_ctrl *);
281 void *userdata;
282 u_long flag;
283};
284
285#define FLG_LLI_L1WAKEUP 1
286#define FLG_LLI_L2WAKEUP 2
287
288struct Management {
289 int ri;
290 struct FsmInst tei_m;
291 struct FsmTimer t202;
292 int T202, N202, debug;
293 void (*layer) (struct PStack *, int, void *);
294};
295
296#define NO_CAUSE 254
297
298struct Param {
299 u_char cause;
300 u_char loc;
301 u_char diag[6];
302 int bchannel;
303 int chargeinfo;
304 int spv; /* SPV Flag */
305 setup_parm setup; /* from isdnif.h numbers and Serviceindicator */
306 u_char moderate; /* transfer mode and rate (bearer octet 4) */
307};
308
309
310struct PStack {
311 struct PStack *next;
312 struct Layer1 l1;
313 struct Layer2 l2;
314 struct Layer3 l3;
315 struct LLInterface lli;
316 struct Management ma;
317 int protocol; /* EDSS1, 1TR6 or NI1 */
318
319 /* protocol specific data fields */
320 union
321 { u_char uuuu; /* only as dummy */
322#ifdef CONFIG_HISAX_EURO
323 dss1_stk_priv dss1; /* private dss1 data */
324#endif /* CONFIG_HISAX_EURO */
325#ifdef CONFIG_HISAX_NI1
326 ni1_stk_priv ni1; /* private ni1 data */
327#endif /* CONFIG_HISAX_NI1 */
328 } prot;
329};
330
331struct l3_process {
332 int callref;
333 int state;
334 struct L3Timer timer;
335 int N303;
336 int debug;
337 struct Param para;
338 struct Channel *chan;
339 struct PStack *st;
340 struct l3_process *next;
341 ulong redir_result;
342
343 /* protocol specific data fields */
344 union
345 { u_char uuuu; /* only when euro not defined, avoiding empty union */
346#ifdef CONFIG_HISAX_EURO
347 dss1_proc_priv dss1; /* private dss1 data */
348#endif /* CONFIG_HISAX_EURO */
349#ifdef CONFIG_HISAX_NI1
350 ni1_proc_priv ni1; /* private ni1 data */
351#endif /* CONFIG_HISAX_NI1 */
352 } prot;
353};
354
355struct hscx_hw {
356 int hscx;
357 int rcvidx;
358 int count; /* Current skb sent count */
359 u_char *rcvbuf; /* B-Channel receive Buffer */
360 u_char tsaxr0;
361 u_char tsaxr1;
362};
363
364struct w6692B_hw {
365 int bchan;
366 int rcvidx;
367 int count; /* Current skb sent count */
368 u_char *rcvbuf; /* B-Channel receive Buffer */
369};
370
371struct isar_reg {
372 unsigned long Flags;
373 volatile u_char bstat;
374 volatile u_char iis;
375 volatile u_char cmsb;
376 volatile u_char clsb;
377 volatile u_char par[8];
378};
379
380struct isar_hw {
381 int dpath;
382 int rcvidx;
383 int txcnt;
384 int mml;
385 u_char state;
386 u_char cmd;
387 u_char mod;
388 u_char newcmd;
389 u_char newmod;
390 char try_mod;
391 struct timer_list ftimer;
392 u_char *rcvbuf; /* B-Channel receive Buffer */
393 u_char conmsg[16];
394 struct isar_reg *reg;
395};
396
397struct hdlc_stat_reg {
398#ifdef __BIG_ENDIAN
Jan Blunck6a878182006-01-08 01:05:07 -0800[diff] [blame^]399 u_char fill;
400 u_char mode;
401 u_char xml;
402 u_char cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]403#else
Jan Blunck6a878182006-01-08 01:05:07 -0800[diff] [blame^]404 u_char cmd;
405 u_char xml;
406 u_char mode;
407 u_char fill;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]408#endif
Jan Blunck6a878182006-01-08 01:05:07 -0800[diff] [blame^]409} __attribute__((packed));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]410
411struct hdlc_hw {
412 union {
413 u_int ctrl;
414 struct hdlc_stat_reg sr;
415 } ctrl;
416 u_int stat;
417 int rcvidx;
418 int count; /* Current skb sent count */
419 u_char *rcvbuf; /* B-Channel receive Buffer */
420};
421
422struct hfcB_hw {
423 unsigned int *send;
424 int f1;
425 int f2;
426};
427
428struct tiger_hw {
429 u_int *send;
430 u_int *s_irq;
431 u_int *s_end;
432 u_int *sendp;
433 u_int *rec;
434 int free;
435 u_char *rcvbuf;
436 u_char *sendbuf;
437 u_char *sp;
438 int sendcnt;
439 u_int s_tot;
440 u_int r_bitcnt;
441 u_int r_tot;
442 u_int r_err;
443 u_int r_fcs;
444 u_char r_state;
445 u_char r_one;
446 u_char r_val;
447 u_char s_state;
448};
449
450struct amd7930_hw {
451 u_char *tx_buff;
452 u_char *rv_buff;
453 int rv_buff_in;
454 int rv_buff_out;
455 struct sk_buff *rv_skb;
456 struct hdlc_state *hdlc_state;
457 struct work_struct tq_rcv;
458 struct work_struct tq_xmt;
459};
460
461#define BC_FLG_INIT 1
462#define BC_FLG_ACTIV 2
463#define BC_FLG_BUSY 3
464#define BC_FLG_NOFRAME 4
465#define BC_FLG_HALF 5
466#define BC_FLG_EMPTY 6
467#define BC_FLG_ORIG 7
468#define BC_FLG_DLEETX 8
469#define BC_FLG_LASTDLE 9
470#define BC_FLG_FIRST 10
471#define BC_FLG_LASTDATA 11
472#define BC_FLG_NMD_DATA 12
473#define BC_FLG_FTI_RUN 13
474#define BC_FLG_LL_OK 14
475#define BC_FLG_LL_CONN 15
476#define BC_FLG_FTI_FTS 16
477#define BC_FLG_FRH_WAIT 17
478
479#define L1_MODE_NULL 0
480#define L1_MODE_TRANS 1
481#define L1_MODE_HDLC 2
482#define L1_MODE_EXTRN 3
483#define L1_MODE_HDLC_56K 4
484#define L1_MODE_MODEM 7
485#define L1_MODE_V32 8
486#define L1_MODE_FAX 9
487
488struct BCState {
489 int channel;
490 int mode;
491 u_long Flag;
492 struct IsdnCardState *cs;
493 int tx_cnt; /* B-Channel transmit counter */
494 struct sk_buff *tx_skb; /* B-Channel transmit Buffer */
495 struct sk_buff_head rqueue; /* B-Channel receive Queue */
496 struct sk_buff_head squeue; /* B-Channel send Queue */
497 int ackcnt;
498 spinlock_t aclock;
499 struct PStack *st;
500 u_char *blog;
501 u_char *conmsg;
502 struct timer_list transbusy;
503 struct work_struct tqueue;
504 u_long event;
505 int (*BC_SetStack) (struct PStack *, struct BCState *);
506 void (*BC_Close) (struct BCState *);
507#ifdef ERROR_STATISTIC
508 int err_crc;
509 int err_tx;
510 int err_rdo;
511 int err_inv;
512#endif
513 union {
514 struct hscx_hw hscx;
515 struct hdlc_hw hdlc;
516 struct isar_hw isar;
517 struct hfcB_hw hfc;
518 struct tiger_hw tiger;
519 struct amd7930_hw amd7930;
520 struct w6692B_hw w6692;
521 struct hisax_b_if *b_if;
522 } hw;
523};
524
525struct Channel {
526 struct PStack *b_st, *d_st;
527 struct IsdnCardState *cs;
528 struct BCState *bcs;
529 int chan;
530 int incoming;
531 struct FsmInst fi;
532 struct FsmTimer drel_timer, dial_timer;
533 int debug;
534 int l2_protocol, l2_active_protocol;
535 int l3_protocol;
536 int data_open;
537 struct l3_process *proc;
538 setup_parm setup; /* from isdnif.h numbers and Serviceindicator */
539 u_long Flags; /* for remembering action done in l4 */
540 int leased;
541};
542
543struct elsa_hw {
544 struct pci_dev *dev;
545 unsigned long base;
546 unsigned int cfg;
547 unsigned int ctrl;
548 unsigned int ale;
549 unsigned int isac;
550 unsigned int itac;
551 unsigned int hscx;
552 unsigned int trig;
553 unsigned int timer;
554 unsigned int counter;
555 unsigned int status;
556 struct timer_list tl;
557 unsigned int MFlag;
558 struct BCState *bcs;
559 u_char *transbuf;
560 u_char *rcvbuf;
561 unsigned int transp;
562 unsigned int rcvp;
563 unsigned int transcnt;
564 unsigned int rcvcnt;
565 u_char IER;
566 u_char FCR;
567 u_char LCR;
568 u_char MCR;
569 u_char ctrl_reg;
570};
571
572struct teles3_hw {
573 unsigned int cfg_reg;
574 signed int isac;
575 signed int hscx[2];
576 signed int isacfifo;
577 signed int hscxfifo[2];
578};
579
580struct teles0_hw {
581 unsigned int cfg_reg;
582 void __iomem *membase;
583 unsigned long phymem;
584};
585
586struct avm_hw {
587 unsigned int cfg_reg;
588 unsigned int isac;
589 unsigned int hscx[2];
590 unsigned int isacfifo;
591 unsigned int hscxfifo[2];
592 unsigned int counter;
593 struct pci_dev *dev;
594};
595
596struct ix1_hw {
597 unsigned int cfg_reg;
598 unsigned int isac_ale;
599 unsigned int isac;
600 unsigned int hscx_ale;
601 unsigned int hscx;
602};
603
604struct diva_hw {
605 unsigned long cfg_reg;
606 unsigned long pci_cfg;
607 unsigned int ctrl;
608 unsigned long isac_adr;
609 unsigned int isac;
610 unsigned long hscx_adr;
611 unsigned int hscx;
612 unsigned int status;
613 struct timer_list tl;
614 u_char ctrl_reg;
615 struct pci_dev *dev;
616};
617
618struct asus_hw {
619 unsigned int cfg_reg;
620 unsigned int adr;
621 unsigned int isac;
622 unsigned int hscx;
623 unsigned int u7;
624 unsigned int pots;
625};
626
627
628struct hfc_hw {
629 unsigned int addr;
630 unsigned int fifosize;
631 unsigned char cirm;
632 unsigned char ctmt;
633 unsigned char cip;
634 u_char isac_spcr;
635 struct timer_list timer;
636};
637
638struct sedl_hw {
639 unsigned int cfg_reg;
640 unsigned int adr;
641 unsigned int isac;
642 unsigned int hscx;
643 unsigned int reset_on;
644 unsigned int reset_off;
645 struct isar_reg isar;
646 unsigned int chip;
647 unsigned int bus;
648 struct pci_dev *dev;
649};
650
651struct spt_hw {
652 unsigned int cfg_reg;
653 unsigned int isac;
654 unsigned int hscx[2];
655 unsigned char res_irq;
656};
657
658struct mic_hw {
659 unsigned int cfg_reg;
660 unsigned int adr;
661 unsigned int isac;
662 unsigned int hscx;
663};
664
665struct njet_hw {
666 unsigned long base;
667 unsigned int isac;
668 unsigned int auxa;
669 unsigned char auxd;
670 unsigned char dmactrl;
671 unsigned char ctrl_reg;
672 unsigned char irqmask0;
673 unsigned char irqstat0;
674 unsigned char last_is0;
675 struct pci_dev *dev;
676};
677
678struct hfcPCI_hw {
679 unsigned char cirm;
680 unsigned char ctmt;
681 unsigned char conn;
682 unsigned char mst_m;
683 unsigned char int_m1;
684 unsigned char int_m2;
685 unsigned char int_s1;
686 unsigned char sctrl;
687 unsigned char sctrl_r;
688 unsigned char sctrl_e;
689 unsigned char trm;
690 unsigned char stat;
691 unsigned char fifo;
692 unsigned char fifo_en;
693 unsigned char bswapped;
694 unsigned char nt_mode;
695 int nt_timer;
696 struct pci_dev *dev;
697 unsigned char *pci_io; /* start of PCI IO memory */
698 void *share_start; /* shared memory for Fifos start */
699 void *fifos; /* FIFO memory */
700 int last_bfifo_cnt[2]; /* marker saving last b-fifo frame count */
701 struct timer_list timer;
702};
703
704struct hfcSX_hw {
705 unsigned long base;
706 unsigned char cirm;
707 unsigned char ctmt;
708 unsigned char conn;
709 unsigned char mst_m;
710 unsigned char int_m1;
711 unsigned char int_m2;
712 unsigned char int_s1;
713 unsigned char sctrl;
714 unsigned char sctrl_r;
715 unsigned char sctrl_e;
716 unsigned char trm;
717 unsigned char stat;
718 unsigned char fifo;
719 unsigned char bswapped;
720 unsigned char nt_mode;
721 unsigned char chip;
722 int b_fifo_size;
723 unsigned char last_fifo;
724 void *extra;
725 int nt_timer;
726 struct timer_list timer;
727};
728
729struct hfcD_hw {
730 unsigned int addr;
731 unsigned int bfifosize;
732 unsigned int dfifosize;
733 unsigned char cirm;
734 unsigned char ctmt;
735 unsigned char cip;
736 unsigned char conn;
737 unsigned char mst_m;
738 unsigned char int_m1;
739 unsigned char int_m2;
740 unsigned char int_s1;
741 unsigned char sctrl;
742 unsigned char stat;
743 unsigned char fifo;
744 unsigned char f1;
745 unsigned char f2;
746 unsigned int *send;
747 struct timer_list timer;
748};
749
750struct isurf_hw {
751 unsigned int reset;
752 unsigned long phymem;
753 void __iomem *isac;
754 void __iomem *isar;
755 struct isar_reg isar_r;
756};
757
758struct saphir_hw {
759 struct pci_dev *dev;
760 unsigned int cfg_reg;
761 unsigned int ale;
762 unsigned int isac;
763 unsigned int hscx;
764 struct timer_list timer;
765};
766
767struct bkm_hw {
768 struct pci_dev *dev;
769 unsigned long base;
770 /* A4T stuff */
771 unsigned long isac_adr;
772 unsigned int isac_ale;
773 unsigned long jade_adr;
774 unsigned int jade_ale;
775 /* Scitel Quadro stuff */
776 unsigned long plx_adr;
777 unsigned long data_adr;
778};
779
780struct gazel_hw {
781 struct pci_dev *dev;
782 unsigned int cfg_reg;
783 unsigned int pciaddr[2];
784 signed int ipac;
785 signed int isac;
786 signed int hscx[2];
787 signed int isacfifo;
788 signed int hscxfifo[2];
789 unsigned char timeslot;
790 unsigned char iom2;
791};
792
793struct w6692_hw {
794 struct pci_dev *dev;
795 unsigned int iobase;
796 struct timer_list timer;
797};
798
799#ifdef CONFIG_HISAX_TESTEMU
800struct te_hw {
801 unsigned char *sfifo;
802 unsigned char *sfifo_w;
803 unsigned char *sfifo_r;
804 unsigned char *sfifo_e;
805 int sfifo_cnt;
806 unsigned int stat;
807 wait_queue_head_t rwaitq;
808 wait_queue_head_t swaitq;
809};
810#endif
811
812struct arcofi_msg {
813 struct arcofi_msg *next;
814 u_char receive;
815 u_char len;
816 u_char msg[10];
817};
818
819struct isac_chip {
820 int ph_state;
821 u_char *mon_tx;
822 u_char *mon_rx;
823 int mon_txp;
824 int mon_txc;
825 int mon_rxp;
826 struct arcofi_msg *arcofi_list;
827 struct timer_list arcofitimer;
828 wait_queue_head_t arcofi_wait;
829 u_char arcofi_bc;
830 u_char arcofi_state;
831 u_char mocr;
832 u_char adf2;
833};
834
835struct hfcd_chip {
836 int ph_state;
837};
838
839struct hfcpci_chip {
840 int ph_state;
841};
842
843struct hfcsx_chip {
844 int ph_state;
845};
846
847struct w6692_chip {
848 int ph_state;
849};
850
851struct amd7930_chip {
852 u_char lmr1;
853 u_char ph_state;
854 u_char old_state;
855 u_char flg_t3;
856 unsigned int tx_xmtlen;
857 struct timer_list timer3;
858 void (*ph_command) (struct IsdnCardState *, u_char, char *);
859 void (*setIrqMask) (struct IsdnCardState *, u_char);
860};
861
862struct icc_chip {
863 int ph_state;
864 u_char *mon_tx;
865 u_char *mon_rx;
866 int mon_txp;
867 int mon_txc;
868 int mon_rxp;
869 struct arcofi_msg *arcofi_list;
870 struct timer_list arcofitimer;
871 wait_queue_head_t arcofi_wait;
872 u_char arcofi_bc;
873 u_char arcofi_state;
874 u_char mocr;
875 u_char adf2;
876};
877
878#define HW_IOM1 0
879#define HW_IPAC 1
880#define HW_ISAR 2
881#define HW_ARCOFI 3
882#define FLG_TWO_DCHAN 4
883#define FLG_L1_DBUSY 5
884#define FLG_DBUSY_TIMER 6
885#define FLG_LOCK_ATOMIC 7
886#define FLG_ARCOFI_TIMER 8
887#define FLG_ARCOFI_ERROR 9
888#define FLG_HW_L1_UINT 10
889
890struct IsdnCardState {
891 spinlock_t lock;
892 u_char typ;
893 u_char subtyp;
894 int protocol;
895 u_int irq;
896 u_long irq_flags;
897 u_long HW_Flags;
898 int *busy_flag;
899 int chanlimit; /* limited number of B-chans to use */
900 int logecho; /* log echo if supported by card */
901 union {
902 struct elsa_hw elsa;
903 struct teles0_hw teles0;
904 struct teles3_hw teles3;
905 struct avm_hw avm;
906 struct ix1_hw ix1;
907 struct diva_hw diva;
908 struct asus_hw asus;
909 struct hfc_hw hfc;
910 struct sedl_hw sedl;
911 struct spt_hw spt;
912 struct mic_hw mic;
913 struct njet_hw njet;
914 struct hfcD_hw hfcD;
915 struct hfcPCI_hw hfcpci;
916 struct hfcSX_hw hfcsx;
917 struct ix1_hw niccy;
918 struct isurf_hw isurf;
919 struct saphir_hw saphir;
920#ifdef CONFIG_HISAX_TESTEMU
921 struct te_hw te;
922#endif
923 struct bkm_hw ax;
924 struct gazel_hw gazel;
925 struct w6692_hw w6692;
926 struct hisax_d_if *hisax_d_if;
927 } hw;
928 int myid;
929 isdn_if iif;
930 spinlock_t statlock;
931 u_char *status_buf;
932 u_char *status_read;
933 u_char *status_write;
934 u_char *status_end;
935 u_char (*readisac) (struct IsdnCardState *, u_char);
936 void (*writeisac) (struct IsdnCardState *, u_char, u_char);
937 void (*readisacfifo) (struct IsdnCardState *, u_char *, int);
938 void (*writeisacfifo) (struct IsdnCardState *, u_char *, int);
939 u_char (*BC_Read_Reg) (struct IsdnCardState *, int, u_char);
940 void (*BC_Write_Reg) (struct IsdnCardState *, int, u_char, u_char);
941 void (*BC_Send_Data) (struct BCState *);
942 int (*cardmsg) (struct IsdnCardState *, int, void *);
943 void (*setstack_d) (struct PStack *, struct IsdnCardState *);
944 void (*DC_Close) (struct IsdnCardState *);
945 int (*irq_func) (int, void *, struct pt_regs *);
946 int (*auxcmd) (struct IsdnCardState *, isdn_ctrl *);
947 struct Channel channel[2+MAX_WAITING_CALLS];
948 struct BCState bcs[2+MAX_WAITING_CALLS];
949 struct PStack *stlist;
950 struct sk_buff_head rq, sq; /* D-channel queues */
951 int cardnr;
952 char *dlog;
953 int debug;
954 union {
955 struct isac_chip isac;
956 struct hfcd_chip hfcd;
957 struct hfcpci_chip hfcpci;
958 struct hfcsx_chip hfcsx;
959 struct w6692_chip w6692;
960 struct amd7930_chip amd7930;
961 struct icc_chip icc;
962 } dc;
963 u_char *rcvbuf;
964 int rcvidx;
965 struct sk_buff *tx_skb;
966 int tx_cnt;
967 u_long event;
968 struct work_struct tqueue;
969 struct timer_list dbusytimer;
970#ifdef ERROR_STATISTIC
971 int err_crc;
972 int err_tx;
973 int err_rx;
974#endif
975};
976
977
978#define schedule_event(s, ev) do {test_and_set_bit(ev, &s->event);schedule_work(&s->tqueue); } while(0)
979
980#define MON0_RX 1
981#define MON1_RX 2
982#define MON0_TX 4
983#define MON1_TX 8
984
985
986#ifdef ISDN_CHIP_ISAC
987#undef ISDN_CHIP_ISAC
988#endif
989
990#ifdef CONFIG_HISAX_16_0
991#define CARD_TELES0 1
992#ifndef ISDN_CHIP_ISAC
993#define ISDN_CHIP_ISAC 1
994#endif
995#else
996#define CARD_TELES0 0
997#endif
998
999#ifdef CONFIG_HISAX_16_3
1000#define CARD_TELES3 1
1001#ifndef ISDN_CHIP_ISAC
1002#define ISDN_CHIP_ISAC 1
1003#endif
1004#else
1005#define CARD_TELES3 0
1006#endif
1007
1008#ifdef CONFIG_HISAX_TELESPCI
1009#define CARD_TELESPCI 1
1010#ifndef ISDN_CHIP_ISAC
1011#define ISDN_CHIP_ISAC 1
1012#endif
1013#else
1014#define CARD_TELESPCI 0
1015#endif
1016
1017#ifdef CONFIG_HISAX_AVM_A1
1018#define CARD_AVM_A1 1
1019#ifndef ISDN_CHIP_ISAC
1020#define ISDN_CHIP_ISAC 1
1021#endif
1022#else
1023#define CARD_AVM_A1 0
1024#endif
1025
1026#ifdef CONFIG_HISAX_AVM_A1_PCMCIA
1027#define CARD_AVM_A1_PCMCIA 1
1028#ifndef ISDN_CHIP_ISAC
1029#define ISDN_CHIP_ISAC 1
1030#endif
1031#else
1032#define CARD_AVM_A1_PCMCIA 0
1033#endif
1034
1035#ifdef CONFIG_HISAX_FRITZPCI
1036#define CARD_FRITZPCI 1
1037#ifndef ISDN_CHIP_ISAC
1038#define ISDN_CHIP_ISAC 1
1039#endif
1040#else
1041#define CARD_FRITZPCI 0
1042#endif
1043
1044#ifdef CONFIG_HISAX_ELSA
1045#define CARD_ELSA 1
1046#ifndef ISDN_CHIP_ISAC
1047#define ISDN_CHIP_ISAC 1
1048#endif
1049#else
1050#define CARD_ELSA 0
1051#endif
1052
1053#ifdef CONFIG_HISAX_IX1MICROR2
1054#define CARD_IX1MICROR2 1
1055#ifndef ISDN_CHIP_ISAC
1056#define ISDN_CHIP_ISAC 1
1057#endif
1058#else
1059#define CARD_IX1MICROR2 0
1060#endif
1061
1062#ifdef CONFIG_HISAX_DIEHLDIVA
1063#define CARD_DIEHLDIVA 1
1064#ifndef ISDN_CHIP_ISAC
1065#define ISDN_CHIP_ISAC 1
1066#endif
1067#else
1068#define CARD_DIEHLDIVA 0
1069#endif
1070
1071#ifdef CONFIG_HISAX_ASUSCOM
1072#define CARD_ASUSCOM 1
1073#ifndef ISDN_CHIP_ISAC
1074#define ISDN_CHIP_ISAC 1
1075#endif
1076#else
1077#define CARD_ASUSCOM 0
1078#endif
1079
1080#ifdef CONFIG_HISAX_TELEINT
1081#define CARD_TELEINT 1
1082#ifndef ISDN_CHIP_ISAC
1083#define ISDN_CHIP_ISAC 1
1084#endif
1085#else
1086#define CARD_TELEINT 0
1087#endif
1088
1089#ifdef CONFIG_HISAX_SEDLBAUER
1090#define CARD_SEDLBAUER 1
1091#ifndef ISDN_CHIP_ISAC
1092#define ISDN_CHIP_ISAC 1
1093#endif
1094#else
1095#define CARD_SEDLBAUER 0
1096#endif
1097
1098#ifdef CONFIG_HISAX_SPORTSTER
1099#define CARD_SPORTSTER 1
1100#ifndef ISDN_CHIP_ISAC
1101#define ISDN_CHIP_ISAC 1
1102#endif
1103#else
1104#define CARD_SPORTSTER 0
1105#endif
1106
1107#ifdef CONFIG_HISAX_MIC
1108#define CARD_MIC 1
1109#ifndef ISDN_CHIP_ISAC
1110#define ISDN_CHIP_ISAC 1
1111#endif
1112#else
1113#define CARD_MIC 0
1114#endif
1115
1116#ifdef CONFIG_HISAX_NETJET
1117#define CARD_NETJET_S 1
1118#ifndef ISDN_CHIP_ISAC
1119#define ISDN_CHIP_ISAC 1
1120#endif
1121#else
1122#define CARD_NETJET_S 0
1123#endif
1124
1125#ifdef CONFIG_HISAX_HFCS
1126#define CARD_HFCS 1
1127#else
1128#define CARD_HFCS 0
1129#endif
1130
1131#ifdef CONFIG_HISAX_HFC_PCI
1132#define CARD_HFC_PCI 1
1133#else
1134#define CARD_HFC_PCI 0
1135#endif
1136
1137#ifdef CONFIG_HISAX_HFC_SX
1138#define CARD_HFC_SX 1
1139#else
1140#define CARD_HFC_SX 0
1141#endif
1142
1143#ifdef CONFIG_HISAX_AMD7930
1144#define CARD_AMD7930 1
1145#else
1146#define CARD_AMD7930 0
1147#endif
1148
1149#ifdef CONFIG_HISAX_NICCY
1150#define CARD_NICCY 1
1151#ifndef ISDN_CHIP_ISAC
1152#define ISDN_CHIP_ISAC 1
1153#endif
1154#else
1155#define CARD_NICCY 0
1156#endif
1157
1158#ifdef CONFIG_HISAX_ISURF
1159#define CARD_ISURF 1
1160#ifndef ISDN_CHIP_ISAC
1161#define ISDN_CHIP_ISAC 1
1162#endif
1163#else
1164#define CARD_ISURF 0
1165#endif
1166
1167#ifdef CONFIG_HISAX_S0BOX
1168#define CARD_S0BOX 1
1169#ifndef ISDN_CHIP_ISAC
1170#define ISDN_CHIP_ISAC 1
1171#endif
1172#else
1173#define CARD_S0BOX 0
1174#endif
1175
1176#ifdef CONFIG_HISAX_HSTSAPHIR
1177#define CARD_HSTSAPHIR 1
1178#ifndef ISDN_CHIP_ISAC
1179#define ISDN_CHIP_ISAC 1
1180#endif
1181#else
1182#define CARD_HSTSAPHIR 0
1183#endif
1184
1185#ifdef CONFIG_HISAX_TESTEMU
1186#define CARD_TESTEMU 1
1187#define ISDN_CTYPE_TESTEMU 99
1188#undef ISDN_CTYPE_COUNT
1189#define ISDN_CTYPE_COUNT ISDN_CTYPE_TESTEMU
1190#else
1191#define CARD_TESTEMU 0
1192#endif
1193
1194#ifdef CONFIG_HISAX_BKM_A4T
1195#define CARD_BKM_A4T 1
1196#ifndef ISDN_CHIP_ISAC
1197#define ISDN_CHIP_ISAC 1
1198#endif
1199#else
1200#define CARD_BKM_A4T 0
1201#endif
1202
1203#ifdef CONFIG_HISAX_SCT_QUADRO
1204#define CARD_SCT_QUADRO 1
1205#ifndef ISDN_CHIP_ISAC
1206#define ISDN_CHIP_ISAC 1
1207#endif
1208#else
1209#define CARD_SCT_QUADRO 0
1210#endif
1211
1212#ifdef CONFIG_HISAX_GAZEL
1213#define CARD_GAZEL 1
1214#ifndef ISDN_CHIP_ISAC
1215#define ISDN_CHIP_ISAC 1
1216#endif
1217#else
1218#define CARD_GAZEL 0
1219#endif
1220
1221#ifdef CONFIG_HISAX_W6692
1222#define CARD_W6692 1
1223#ifndef ISDN_CHIP_W6692
1224#define ISDN_CHIP_W6692 1
1225#endif
1226#else
1227#define CARD_W6692 0
1228#endif
1229
1230#ifdef CONFIG_HISAX_NETJET_U
1231#define CARD_NETJET_U 1
1232#ifndef ISDN_CHIP_ICC
1233#define ISDN_CHIP_ICC 1
1234#endif
1235#ifndef HISAX_UINTERFACE
1236#define HISAX_UINTERFACE 1
1237#endif
1238#else
1239#define CARD_NETJET_U 0
1240#endif
1241
1242#ifdef CONFIG_HISAX_ENTERNOW_PCI
1243#define CARD_FN_ENTERNOW_PCI 1
viro@ZenIV.linux.org.ukf7184042005-09-07 23:19:41 +0100[diff] [blame]1244#else
1245#define CARD_FN_ENTERNOW_PCI 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1246#endif
1247
1248#define TEI_PER_CARD 1
1249
1250/* L1 Debug */
1251#define L1_DEB_WARN 0x01
1252#define L1_DEB_INTSTAT 0x02
1253#define L1_DEB_ISAC 0x04
1254#define L1_DEB_ISAC_FIFO 0x08
1255#define L1_DEB_HSCX 0x10
1256#define L1_DEB_HSCX_FIFO 0x20
1257#define L1_DEB_LAPD 0x40
1258#define L1_DEB_IPAC 0x80
1259#define L1_DEB_RECEIVE_FRAME 0x100
1260#define L1_DEB_MONITOR 0x200
1261#define DEB_DLOG_HEX 0x400
1262#define DEB_DLOG_VERBOSE 0x800
1263
1264#define L2FRAME_DEBUG
1265
1266#ifdef L2FRAME_DEBUG
1267extern void Logl2Frame(struct IsdnCardState *cs, struct sk_buff *skb, char *buf, int dir);
1268#endif
1269
1270#include "hisax_cfg.h"
1271
1272void init_bcstate(struct IsdnCardState *cs, int bc);
1273
1274void setstack_HiSax(struct PStack *st, struct IsdnCardState *cs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1275void HiSax_addlist(struct IsdnCardState *sp, struct PStack *st);
1276void HiSax_rmlist(struct IsdnCardState *sp, struct PStack *st);
1277
1278void setstack_l1_B(struct PStack *st);
1279
1280void setstack_tei(struct PStack *st);
1281void setstack_manager(struct PStack *st);
1282
1283void setstack_isdnl2(struct PStack *st, char *debug_id);
1284void releasestack_isdnl2(struct PStack *st);
1285void setstack_transl2(struct PStack *st);
1286void releasestack_transl2(struct PStack *st);
1287void lli_writewakeup(struct PStack *st, int len);
1288
1289void setstack_l3dc(struct PStack *st, struct Channel *chanp);
1290void setstack_l3bc(struct PStack *st, struct Channel *chanp);
1291void releasestack_isdnl3(struct PStack *st);
1292
1293u_char *findie(u_char * p, int size, u_char ie, int wanted_set);
1294int getcallref(u_char * p);
1295int newcallref(void);
1296
1297int FsmNew(struct Fsm *fsm, struct FsmNode *fnlist, int fncount);
1298void FsmFree(struct Fsm *fsm);
1299int FsmEvent(struct FsmInst *fi, int event, void *arg);
1300void FsmChangeState(struct FsmInst *fi, int newstate);
1301void FsmInitTimer(struct FsmInst *fi, struct FsmTimer *ft);
1302int FsmAddTimer(struct FsmTimer *ft, int millisec, int event,
1303 void *arg, int where);
1304void FsmRestartTimer(struct FsmTimer *ft, int millisec, int event,
1305 void *arg, int where);
1306void FsmDelTimer(struct FsmTimer *ft, int where);
1307int jiftime(char *s, long mark);
1308
1309int HiSax_command(isdn_ctrl * ic);
1310int HiSax_writebuf_skb(int id, int chan, int ack, struct sk_buff *skb);
1311void HiSax_putstatus(struct IsdnCardState *cs, char *head, char *fmt, ...);
1312void VHiSax_putstatus(struct IsdnCardState *cs, char *head, char *fmt, va_list args);
1313void HiSax_reportcard(int cardnr, int sel);
1314int QuickHex(char *txt, u_char * p, int cnt);
1315void LogFrame(struct IsdnCardState *cs, u_char * p, int size);
1316void dlogframe(struct IsdnCardState *cs, struct sk_buff *skb, int dir);
1317void iecpy(u_char * dest, u_char * iestart, int ieoffset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1318#endif /* __KERNEL__ */
1319
1320#define HZDELAY(jiffs) {int tout = jiffs; while (tout--) udelay(1000000/HZ);}
1321
1322int ll_run(struct IsdnCardState *cs, int addfeatures);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1323int CallcNew(void);
1324void CallcFree(void);
1325int CallcNewChan(struct IsdnCardState *cs);
1326void CallcFreeChan(struct IsdnCardState *cs);
1327int Isdnl1New(void);
1328void Isdnl1Free(void);
1329int Isdnl2New(void);
1330void Isdnl2Free(void);
1331int Isdnl3New(void);
1332void Isdnl3Free(void);
1333void init_tei(struct IsdnCardState *cs, int protocol);
1334void release_tei(struct IsdnCardState *cs);
1335char *HiSax_getrev(const char *revision);
1336int TeiNew(void);
1337void TeiFree(void);