Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 1 | /* |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | #ifndef _DSI_CTRL_HW_H_ |
| 15 | #define _DSI_CTRL_HW_H_ |
| 16 | |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/types.h> |
| 19 | #include <linux/bitops.h> |
| 20 | #include <linux/bitmap.h> |
| 21 | |
| 22 | #include "dsi_defs.h" |
| 23 | |
| 24 | /** |
| 25 | * Modifier flag for command transmission. If this flag is set, command |
| 26 | * information is programmed to hardware and transmission is not triggered. |
| 27 | * Caller should call the trigger_command_dma() to start the transmission. This |
| 28 | * flag is valed for kickoff_command() and kickoff_fifo_command() operations. |
| 29 | */ |
| 30 | #define DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER 0x1 |
| 31 | |
| 32 | /** |
| 33 | * enum dsi_ctrl_version - version of the dsi host controller |
| 34 | * @DSI_CTRL_VERSION_UNKNOWN: Unknown controller version |
| 35 | * @DSI_CTRL_VERSION_1_4: DSI host v1.4 controller |
| 36 | * @DSI_CTRL_VERSION_2_0: DSI host v2.0 controller |
| 37 | * @DSI_CTRL_VERSION_MAX: max version |
| 38 | */ |
| 39 | enum dsi_ctrl_version { |
| 40 | DSI_CTRL_VERSION_UNKNOWN, |
| 41 | DSI_CTRL_VERSION_1_4, |
| 42 | DSI_CTRL_VERSION_2_0, |
Shashank Babu Chinta Venkata | afef820 | 2017-04-21 13:49:56 -0700 | [diff] [blame] | 43 | DSI_CTRL_VERSION_2_2, |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 44 | DSI_CTRL_VERSION_MAX |
| 45 | }; |
| 46 | |
| 47 | /** |
| 48 | * enum dsi_ctrl_hw_features - features supported by dsi host controller |
| 49 | * @DSI_CTRL_VIDEO_TPG: Test pattern support for video mode. |
| 50 | * @DSI_CTRL_CMD_TPG: Test pattern support for command mode. |
| 51 | * @DSI_CTRL_VARIABLE_REFRESH_RATE: variable panel timing |
| 52 | * @DSI_CTRL_DYNAMIC_REFRESH: variable pixel clock rate |
| 53 | * @DSI_CTRL_NULL_PACKET_INSERTION: NULL packet insertion |
| 54 | * @DSI_CTRL_DESKEW_CALIB: Deskew calibration support |
| 55 | * @DSI_CTRL_DPHY: Controller support for DPHY |
| 56 | * @DSI_CTRL_CPHY: Controller support for CPHY |
| 57 | * @DSI_CTRL_MAX_FEATURES: |
| 58 | */ |
| 59 | enum dsi_ctrl_hw_features { |
| 60 | DSI_CTRL_VIDEO_TPG, |
| 61 | DSI_CTRL_CMD_TPG, |
| 62 | DSI_CTRL_VARIABLE_REFRESH_RATE, |
| 63 | DSI_CTRL_DYNAMIC_REFRESH, |
| 64 | DSI_CTRL_NULL_PACKET_INSERTION, |
| 65 | DSI_CTRL_DESKEW_CALIB, |
| 66 | DSI_CTRL_DPHY, |
| 67 | DSI_CTRL_CPHY, |
| 68 | DSI_CTRL_MAX_FEATURES |
| 69 | }; |
| 70 | |
| 71 | /** |
| 72 | * enum dsi_test_pattern - test pattern type |
| 73 | * @DSI_TEST_PATTERN_FIXED: Test pattern is fixed, based on init value. |
| 74 | * @DSI_TEST_PATTERN_INC: Incremental test pattern, base on init value. |
| 75 | * @DSI_TEST_PATTERN_POLY: Pattern generated from polynomial and init val. |
| 76 | * @DSI_TEST_PATTERN_MAX: |
| 77 | */ |
| 78 | enum dsi_test_pattern { |
| 79 | DSI_TEST_PATTERN_FIXED = 0, |
| 80 | DSI_TEST_PATTERN_INC, |
| 81 | DSI_TEST_PATTERN_POLY, |
| 82 | DSI_TEST_PATTERN_MAX |
| 83 | }; |
| 84 | |
| 85 | /** |
Clarence Ip | 80ada7f | 2017-05-04 09:55:21 -0700 | [diff] [blame] | 86 | * enum dsi_status_int_index - index of interrupts generated by DSI controller |
| 87 | * @DSI_SINT_CMD_MODE_DMA_DONE: Command mode DMA packets are sent out. |
| 88 | * @DSI_SINT_CMD_STREAM0_FRAME_DONE: A frame of cmd mode stream0 is sent out. |
| 89 | * @DSI_SINT_CMD_STREAM1_FRAME_DONE: A frame of cmd mode stream1 is sent out. |
| 90 | * @DSI_SINT_CMD_STREAM2_FRAME_DONE: A frame of cmd mode stream2 is sent out. |
| 91 | * @DSI_SINT_VIDEO_MODE_FRAME_DONE: A frame of video mode stream is sent out. |
| 92 | * @DSI_SINT_BTA_DONE: A BTA is completed. |
| 93 | * @DSI_SINT_CMD_FRAME_DONE: A frame of selected cmd mode stream is |
| 94 | * sent out by MDP. |
| 95 | * @DSI_SINT_DYN_REFRESH_DONE: The dynamic refresh operation completed. |
| 96 | * @DSI_SINT_DESKEW_DONE: The deskew calibration operation done. |
| 97 | * @DSI_SINT_DYN_BLANK_DMA_DONE: The dynamic blankin DMA operation has |
| 98 | * completed. |
| 99 | */ |
| 100 | enum dsi_status_int_index { |
| 101 | DSI_SINT_CMD_MODE_DMA_DONE = 0, |
| 102 | DSI_SINT_CMD_STREAM0_FRAME_DONE = 1, |
| 103 | DSI_SINT_CMD_STREAM1_FRAME_DONE = 2, |
| 104 | DSI_SINT_CMD_STREAM2_FRAME_DONE = 3, |
| 105 | DSI_SINT_VIDEO_MODE_FRAME_DONE = 4, |
| 106 | DSI_SINT_BTA_DONE = 5, |
| 107 | DSI_SINT_CMD_FRAME_DONE = 6, |
| 108 | DSI_SINT_DYN_REFRESH_DONE = 7, |
| 109 | DSI_SINT_DESKEW_DONE = 8, |
| 110 | DSI_SINT_DYN_BLANK_DMA_DONE = 9, |
| 111 | |
| 112 | DSI_STATUS_INTERRUPT_COUNT |
| 113 | }; |
| 114 | |
| 115 | /** |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 116 | * enum dsi_status_int_type - status interrupts generated by DSI controller |
| 117 | * @DSI_CMD_MODE_DMA_DONE: Command mode DMA packets are sent out. |
| 118 | * @DSI_CMD_STREAM0_FRAME_DONE: A frame of command mode stream0 is sent out. |
| 119 | * @DSI_CMD_STREAM1_FRAME_DONE: A frame of command mode stream1 is sent out. |
| 120 | * @DSI_CMD_STREAM2_FRAME_DONE: A frame of command mode stream2 is sent out. |
| 121 | * @DSI_VIDEO_MODE_FRAME_DONE: A frame of video mode stream is sent out. |
| 122 | * @DSI_BTA_DONE: A BTA is completed. |
| 123 | * @DSI_CMD_FRAME_DONE: A frame of selected command mode stream is |
| 124 | * sent out by MDP. |
| 125 | * @DSI_DYN_REFRESH_DONE: The dynamic refresh operation has completed. |
| 126 | * @DSI_DESKEW_DONE: The deskew calibration operation has completed |
| 127 | * @DSI_DYN_BLANK_DMA_DONE: The dynamic blankin DMA operation has |
| 128 | * completed. |
| 129 | */ |
| 130 | enum dsi_status_int_type { |
Clarence Ip | 80ada7f | 2017-05-04 09:55:21 -0700 | [diff] [blame] | 131 | DSI_CMD_MODE_DMA_DONE = BIT(DSI_SINT_CMD_MODE_DMA_DONE), |
| 132 | DSI_CMD_STREAM0_FRAME_DONE = BIT(DSI_SINT_CMD_STREAM0_FRAME_DONE), |
| 133 | DSI_CMD_STREAM1_FRAME_DONE = BIT(DSI_SINT_CMD_STREAM1_FRAME_DONE), |
| 134 | DSI_CMD_STREAM2_FRAME_DONE = BIT(DSI_SINT_CMD_STREAM2_FRAME_DONE), |
| 135 | DSI_VIDEO_MODE_FRAME_DONE = BIT(DSI_SINT_VIDEO_MODE_FRAME_DONE), |
| 136 | DSI_BTA_DONE = BIT(DSI_SINT_BTA_DONE), |
| 137 | DSI_CMD_FRAME_DONE = BIT(DSI_SINT_CMD_FRAME_DONE), |
| 138 | DSI_DYN_REFRESH_DONE = BIT(DSI_SINT_DYN_REFRESH_DONE), |
| 139 | DSI_DESKEW_DONE = BIT(DSI_SINT_DESKEW_DONE), |
| 140 | DSI_DYN_BLANK_DMA_DONE = BIT(DSI_SINT_DYN_BLANK_DMA_DONE) |
| 141 | }; |
| 142 | |
| 143 | /** |
| 144 | * enum dsi_error_int_index - index of error interrupts from DSI controller |
| 145 | * @DSI_EINT_RDBK_SINGLE_ECC_ERR: Single bit ECC error in read packet. |
| 146 | * @DSI_EINT_RDBK_MULTI_ECC_ERR: Multi bit ECC error in read packet. |
| 147 | * @DSI_EINT_RDBK_CRC_ERR: CRC error in read packet. |
| 148 | * @DSI_EINT_RDBK_INCOMPLETE_PKT: Incomplete read packet. |
| 149 | * @DSI_EINT_PERIPH_ERROR_PKT: Error packet returned from peripheral, |
| 150 | * @DSI_EINT_LP_RX_TIMEOUT: Low power reverse transmission timeout. |
| 151 | * @DSI_EINT_HS_TX_TIMEOUT: High speed fwd transmission timeout. |
| 152 | * @DSI_EINT_BTA_TIMEOUT: BTA timeout. |
| 153 | * @DSI_EINT_PLL_UNLOCK: PLL has unlocked. |
| 154 | * @DSI_EINT_DLN0_ESC_ENTRY_ERR: Incorrect LP Rx escape entry. |
| 155 | * @DSI_EINT_DLN0_ESC_SYNC_ERR: LP Rx data is not byte aligned. |
| 156 | * @DSI_EINT_DLN0_LP_CONTROL_ERR: Incorrect LP Rx state sequence. |
| 157 | * @DSI_EINT_PENDING_HS_TX_TIMEOUT: Pending High-speed transfer timeout. |
| 158 | * @DSI_EINT_INTERLEAVE_OP_CONTENTION: Interleave operation contention. |
| 159 | * @DSI_EINT_CMD_DMA_FIFO_UNDERFLOW: Command mode DMA FIFO underflow. |
| 160 | * @DSI_EINT_CMD_MDP_FIFO_UNDERFLOW: Command MDP FIFO underflow (failed to |
| 161 | * receive one complete line from MDP). |
| 162 | * @DSI_EINT_DLN0_HS_FIFO_OVERFLOW: High speed FIFO data lane 0 overflows. |
| 163 | * @DSI_EINT_DLN1_HS_FIFO_OVERFLOW: High speed FIFO data lane 1 overflows. |
| 164 | * @DSI_EINT_DLN2_HS_FIFO_OVERFLOW: High speed FIFO data lane 2 overflows. |
| 165 | * @DSI_EINT_DLN3_HS_FIFO_OVERFLOW: High speed FIFO data lane 3 overflows. |
| 166 | * @DSI_EINT_DLN0_HS_FIFO_UNDERFLOW: High speed FIFO data lane 0 underflows. |
| 167 | * @DSI_EINT_DLN1_HS_FIFO_UNDERFLOW: High speed FIFO data lane 1 underflows. |
| 168 | * @DSI_EINT_DLN2_HS_FIFO_UNDERFLOW: High speed FIFO data lane 2 underflows. |
| 169 | * @DSI_EINT_DLN3_HS_FIFO_UNDERFLOW: High speed FIFO data lane 3 undeflows. |
| 170 | * @DSI_EINT_DLN0_LP0_CONTENTION: PHY level contention while lane 0 low. |
| 171 | * @DSI_EINT_DLN1_LP0_CONTENTION: PHY level contention while lane 1 low. |
| 172 | * @DSI_EINT_DLN2_LP0_CONTENTION: PHY level contention while lane 2 low. |
| 173 | * @DSI_EINT_DLN3_LP0_CONTENTION: PHY level contention while lane 3 low. |
| 174 | * @DSI_EINT_DLN0_LP1_CONTENTION: PHY level contention while lane 0 high. |
| 175 | * @DSI_EINT_DLN1_LP1_CONTENTION: PHY level contention while lane 1 high. |
| 176 | * @DSI_EINT_DLN2_LP1_CONTENTION: PHY level contention while lane 2 high. |
| 177 | * @DSI_EINT_DLN3_LP1_CONTENTION: PHY level contention while lane 3 high. |
| 178 | */ |
| 179 | enum dsi_error_int_index { |
| 180 | DSI_EINT_RDBK_SINGLE_ECC_ERR = 0, |
| 181 | DSI_EINT_RDBK_MULTI_ECC_ERR = 1, |
| 182 | DSI_EINT_RDBK_CRC_ERR = 2, |
| 183 | DSI_EINT_RDBK_INCOMPLETE_PKT = 3, |
| 184 | DSI_EINT_PERIPH_ERROR_PKT = 4, |
| 185 | DSI_EINT_LP_RX_TIMEOUT = 5, |
| 186 | DSI_EINT_HS_TX_TIMEOUT = 6, |
| 187 | DSI_EINT_BTA_TIMEOUT = 7, |
| 188 | DSI_EINT_PLL_UNLOCK = 8, |
| 189 | DSI_EINT_DLN0_ESC_ENTRY_ERR = 9, |
| 190 | DSI_EINT_DLN0_ESC_SYNC_ERR = 10, |
| 191 | DSI_EINT_DLN0_LP_CONTROL_ERR = 11, |
| 192 | DSI_EINT_PENDING_HS_TX_TIMEOUT = 12, |
| 193 | DSI_EINT_INTERLEAVE_OP_CONTENTION = 13, |
| 194 | DSI_EINT_CMD_DMA_FIFO_UNDERFLOW = 14, |
| 195 | DSI_EINT_CMD_MDP_FIFO_UNDERFLOW = 15, |
| 196 | DSI_EINT_DLN0_HS_FIFO_OVERFLOW = 16, |
| 197 | DSI_EINT_DLN1_HS_FIFO_OVERFLOW = 17, |
| 198 | DSI_EINT_DLN2_HS_FIFO_OVERFLOW = 18, |
| 199 | DSI_EINT_DLN3_HS_FIFO_OVERFLOW = 19, |
| 200 | DSI_EINT_DLN0_HS_FIFO_UNDERFLOW = 20, |
| 201 | DSI_EINT_DLN1_HS_FIFO_UNDERFLOW = 21, |
| 202 | DSI_EINT_DLN2_HS_FIFO_UNDERFLOW = 22, |
| 203 | DSI_EINT_DLN3_HS_FIFO_UNDERFLOW = 23, |
| 204 | DSI_EINT_DLN0_LP0_CONTENTION = 24, |
| 205 | DSI_EINT_DLN1_LP0_CONTENTION = 25, |
| 206 | DSI_EINT_DLN2_LP0_CONTENTION = 26, |
| 207 | DSI_EINT_DLN3_LP0_CONTENTION = 27, |
| 208 | DSI_EINT_DLN0_LP1_CONTENTION = 28, |
| 209 | DSI_EINT_DLN1_LP1_CONTENTION = 29, |
| 210 | DSI_EINT_DLN2_LP1_CONTENTION = 30, |
| 211 | DSI_EINT_DLN3_LP1_CONTENTION = 31, |
| 212 | |
| 213 | DSI_ERROR_INTERRUPT_COUNT |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 214 | }; |
| 215 | |
| 216 | /** |
| 217 | * enum dsi_error_int_type - error interrupts generated by DSI controller |
| 218 | * @DSI_RDBK_SINGLE_ECC_ERR: Single bit ECC error in read packet. |
| 219 | * @DSI_RDBK_MULTI_ECC_ERR: Multi bit ECC error in read packet. |
| 220 | * @DSI_RDBK_CRC_ERR: CRC error in read packet. |
| 221 | * @DSI_RDBK_INCOMPLETE_PKT: Incomplete read packet. |
| 222 | * @DSI_PERIPH_ERROR_PKT: Error packet returned from peripheral, |
| 223 | * @DSI_LP_RX_TIMEOUT: Low power reverse transmission timeout. |
| 224 | * @DSI_HS_TX_TIMEOUT: High speed forward transmission timeout. |
| 225 | * @DSI_BTA_TIMEOUT: BTA timeout. |
| 226 | * @DSI_PLL_UNLOCK: PLL has unlocked. |
| 227 | * @DSI_DLN0_ESC_ENTRY_ERR: Incorrect LP Rx escape entry. |
| 228 | * @DSI_DLN0_ESC_SYNC_ERR: LP Rx data is not byte aligned. |
| 229 | * @DSI_DLN0_LP_CONTROL_ERR: Incorrect LP Rx state sequence. |
| 230 | * @DSI_PENDING_HS_TX_TIMEOUT: Pending High-speed transfer timeout. |
| 231 | * @DSI_INTERLEAVE_OP_CONTENTION: Interleave operation contention. |
| 232 | * @DSI_CMD_DMA_FIFO_UNDERFLOW: Command mode DMA FIFO underflow. |
| 233 | * @DSI_CMD_MDP_FIFO_UNDERFLOW: Command MDP FIFO underflow (failed to |
| 234 | * receive one complete line from MDP). |
| 235 | * @DSI_DLN0_HS_FIFO_OVERFLOW: High speed FIFO for data lane 0 overflows. |
| 236 | * @DSI_DLN1_HS_FIFO_OVERFLOW: High speed FIFO for data lane 1 overflows. |
| 237 | * @DSI_DLN2_HS_FIFO_OVERFLOW: High speed FIFO for data lane 2 overflows. |
| 238 | * @DSI_DLN3_HS_FIFO_OVERFLOW: High speed FIFO for data lane 3 overflows. |
| 239 | * @DSI_DLN0_HS_FIFO_UNDERFLOW: High speed FIFO for data lane 0 underflows. |
| 240 | * @DSI_DLN1_HS_FIFO_UNDERFLOW: High speed FIFO for data lane 1 underflows. |
| 241 | * @DSI_DLN2_HS_FIFO_UNDERFLOW: High speed FIFO for data lane 2 underflows. |
| 242 | * @DSI_DLN3_HS_FIFO_UNDERFLOW: High speed FIFO for data lane 3 undeflows. |
| 243 | * @DSI_DLN0_LP0_CONTENTION: PHY level contention while lane 0 is low. |
| 244 | * @DSI_DLN1_LP0_CONTENTION: PHY level contention while lane 1 is low. |
| 245 | * @DSI_DLN2_LP0_CONTENTION: PHY level contention while lane 2 is low. |
| 246 | * @DSI_DLN3_LP0_CONTENTION: PHY level contention while lane 3 is low. |
| 247 | * @DSI_DLN0_LP1_CONTENTION: PHY level contention while lane 0 is high. |
| 248 | * @DSI_DLN1_LP1_CONTENTION: PHY level contention while lane 1 is high. |
| 249 | * @DSI_DLN2_LP1_CONTENTION: PHY level contention while lane 2 is high. |
| 250 | * @DSI_DLN3_LP1_CONTENTION: PHY level contention while lane 3 is high. |
| 251 | */ |
| 252 | enum dsi_error_int_type { |
Clarence Ip | 80ada7f | 2017-05-04 09:55:21 -0700 | [diff] [blame] | 253 | DSI_RDBK_SINGLE_ECC_ERR = BIT(DSI_EINT_RDBK_SINGLE_ECC_ERR), |
| 254 | DSI_RDBK_MULTI_ECC_ERR = BIT(DSI_EINT_RDBK_MULTI_ECC_ERR), |
| 255 | DSI_RDBK_CRC_ERR = BIT(DSI_EINT_RDBK_CRC_ERR), |
| 256 | DSI_RDBK_INCOMPLETE_PKT = BIT(DSI_EINT_RDBK_INCOMPLETE_PKT), |
| 257 | DSI_PERIPH_ERROR_PKT = BIT(DSI_EINT_PERIPH_ERROR_PKT), |
| 258 | DSI_LP_RX_TIMEOUT = BIT(DSI_EINT_LP_RX_TIMEOUT), |
| 259 | DSI_HS_TX_TIMEOUT = BIT(DSI_EINT_HS_TX_TIMEOUT), |
| 260 | DSI_BTA_TIMEOUT = BIT(DSI_EINT_BTA_TIMEOUT), |
| 261 | DSI_PLL_UNLOCK = BIT(DSI_EINT_PLL_UNLOCK), |
| 262 | DSI_DLN0_ESC_ENTRY_ERR = BIT(DSI_EINT_DLN0_ESC_ENTRY_ERR), |
| 263 | DSI_DLN0_ESC_SYNC_ERR = BIT(DSI_EINT_DLN0_ESC_SYNC_ERR), |
| 264 | DSI_DLN0_LP_CONTROL_ERR = BIT(DSI_EINT_DLN0_LP_CONTROL_ERR), |
| 265 | DSI_PENDING_HS_TX_TIMEOUT = BIT(DSI_EINT_PENDING_HS_TX_TIMEOUT), |
| 266 | DSI_INTERLEAVE_OP_CONTENTION = BIT(DSI_EINT_INTERLEAVE_OP_CONTENTION), |
| 267 | DSI_CMD_DMA_FIFO_UNDERFLOW = BIT(DSI_EINT_CMD_DMA_FIFO_UNDERFLOW), |
| 268 | DSI_CMD_MDP_FIFO_UNDERFLOW = BIT(DSI_EINT_CMD_MDP_FIFO_UNDERFLOW), |
| 269 | DSI_DLN0_HS_FIFO_OVERFLOW = BIT(DSI_EINT_DLN0_HS_FIFO_OVERFLOW), |
| 270 | DSI_DLN1_HS_FIFO_OVERFLOW = BIT(DSI_EINT_DLN1_HS_FIFO_OVERFLOW), |
| 271 | DSI_DLN2_HS_FIFO_OVERFLOW = BIT(DSI_EINT_DLN2_HS_FIFO_OVERFLOW), |
| 272 | DSI_DLN3_HS_FIFO_OVERFLOW = BIT(DSI_EINT_DLN3_HS_FIFO_OVERFLOW), |
| 273 | DSI_DLN0_HS_FIFO_UNDERFLOW = BIT(DSI_EINT_DLN0_HS_FIFO_UNDERFLOW), |
| 274 | DSI_DLN1_HS_FIFO_UNDERFLOW = BIT(DSI_EINT_DLN1_HS_FIFO_UNDERFLOW), |
| 275 | DSI_DLN2_HS_FIFO_UNDERFLOW = BIT(DSI_EINT_DLN2_HS_FIFO_UNDERFLOW), |
| 276 | DSI_DLN3_HS_FIFO_UNDERFLOW = BIT(DSI_EINT_DLN3_HS_FIFO_UNDERFLOW), |
| 277 | DSI_DLN0_LP0_CONTENTION = BIT(DSI_EINT_DLN0_LP0_CONTENTION), |
| 278 | DSI_DLN1_LP0_CONTENTION = BIT(DSI_EINT_DLN1_LP0_CONTENTION), |
| 279 | DSI_DLN2_LP0_CONTENTION = BIT(DSI_EINT_DLN2_LP0_CONTENTION), |
| 280 | DSI_DLN3_LP0_CONTENTION = BIT(DSI_EINT_DLN3_LP0_CONTENTION), |
| 281 | DSI_DLN0_LP1_CONTENTION = BIT(DSI_EINT_DLN0_LP1_CONTENTION), |
| 282 | DSI_DLN1_LP1_CONTENTION = BIT(DSI_EINT_DLN1_LP1_CONTENTION), |
| 283 | DSI_DLN2_LP1_CONTENTION = BIT(DSI_EINT_DLN2_LP1_CONTENTION), |
| 284 | DSI_DLN3_LP1_CONTENTION = BIT(DSI_EINT_DLN3_LP1_CONTENTION), |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 285 | }; |
| 286 | |
| 287 | /** |
| 288 | * struct dsi_ctrl_cmd_dma_info - command buffer information |
| 289 | * @offset: IOMMU VA for command buffer address. |
| 290 | * @length: Length of the command buffer. |
| 291 | * @en_broadcast: Enable broadcast mode if set to true. |
| 292 | * @is_master: Is master in broadcast mode. |
| 293 | * @use_lpm: Use low power mode for command transmission. |
| 294 | */ |
| 295 | struct dsi_ctrl_cmd_dma_info { |
| 296 | u32 offset; |
| 297 | u32 length; |
| 298 | bool en_broadcast; |
| 299 | bool is_master; |
| 300 | bool use_lpm; |
| 301 | }; |
| 302 | |
| 303 | /** |
| 304 | * struct dsi_ctrl_cmd_dma_fifo_info - command payload tp be sent using FIFO |
| 305 | * @command: VA for command buffer. |
| 306 | * @size: Size of the command buffer. |
| 307 | * @en_broadcast: Enable broadcast mode if set to true. |
| 308 | * @is_master: Is master in broadcast mode. |
| 309 | * @use_lpm: Use low power mode for command transmission. |
| 310 | */ |
| 311 | struct dsi_ctrl_cmd_dma_fifo_info { |
| 312 | u32 *command; |
| 313 | u32 size; |
| 314 | bool en_broadcast; |
| 315 | bool is_master; |
| 316 | bool use_lpm; |
| 317 | }; |
| 318 | |
| 319 | struct dsi_ctrl_hw; |
| 320 | |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 321 | struct ctrl_ulps_config_ops { |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 322 | /** |
| 323 | * ulps_request() - request ulps entry for specified lanes |
| 324 | * @ctrl: Pointer to the controller host hardware. |
| 325 | * @lanes: ORed list of lanes (enum dsi_data_lanes) which need |
| 326 | * to enter ULPS. |
| 327 | * |
| 328 | * Caller should check if lanes are in ULPS mode by calling |
| 329 | * get_lanes_in_ulps() operation. |
| 330 | */ |
| 331 | void (*ulps_request)(struct dsi_ctrl_hw *ctrl, u32 lanes); |
| 332 | |
| 333 | /** |
| 334 | * ulps_exit() - exit ULPS on specified lanes |
| 335 | * @ctrl: Pointer to the controller host hardware. |
| 336 | * @lanes: ORed list of lanes (enum dsi_data_lanes) which need |
| 337 | * to exit ULPS. |
| 338 | * |
| 339 | * Caller should check if lanes are in active mode by calling |
| 340 | * get_lanes_in_ulps() operation. |
| 341 | */ |
| 342 | void (*ulps_exit)(struct dsi_ctrl_hw *ctrl, u32 lanes); |
| 343 | |
| 344 | /** |
| 345 | * get_lanes_in_ulps() - returns the list of lanes in ULPS mode |
| 346 | * @ctrl: Pointer to the controller host hardware. |
| 347 | * |
| 348 | * Returns an ORed list of lanes (enum dsi_data_lanes) that are in ULPS |
| 349 | * state. If 0 is returned, all the lanes are active. |
| 350 | * |
| 351 | * Return: List of lanes in ULPS state. |
| 352 | */ |
| 353 | u32 (*get_lanes_in_ulps)(struct dsi_ctrl_hw *ctrl); |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 354 | }; |
| 355 | |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 356 | /** |
| 357 | * struct dsi_ctrl_hw_ops - operations supported by dsi host hardware |
| 358 | */ |
| 359 | struct dsi_ctrl_hw_ops { |
| 360 | |
| 361 | /** |
| 362 | * host_setup() - Setup DSI host configuration |
| 363 | * @ctrl: Pointer to controller host hardware. |
| 364 | * @config: Configuration for DSI host controller |
| 365 | */ |
| 366 | void (*host_setup)(struct dsi_ctrl_hw *ctrl, |
| 367 | struct dsi_host_common_cfg *config); |
| 368 | |
| 369 | /** |
| 370 | * video_engine_en() - enable DSI video engine |
| 371 | * @ctrl: Pointer to controller host hardware. |
| 372 | * @on: Enable/disabel video engine. |
| 373 | */ |
| 374 | void (*video_engine_en)(struct dsi_ctrl_hw *ctrl, bool on); |
| 375 | |
| 376 | /** |
| 377 | * video_engine_setup() - Setup dsi host controller for video mode |
| 378 | * @ctrl: Pointer to controller host hardware. |
| 379 | * @common_cfg: Common configuration parameters. |
| 380 | * @cfg: Video mode configuration. |
| 381 | * |
| 382 | * Set up DSI video engine with a specific configuration. Controller and |
| 383 | * video engine are not enabled as part of this function. |
| 384 | */ |
| 385 | void (*video_engine_setup)(struct dsi_ctrl_hw *ctrl, |
| 386 | struct dsi_host_common_cfg *common_cfg, |
| 387 | struct dsi_video_engine_cfg *cfg); |
| 388 | |
| 389 | /** |
| 390 | * set_video_timing() - set up the timing for video frame |
| 391 | * @ctrl: Pointer to controller host hardware. |
| 392 | * @mode: Video mode information. |
| 393 | * |
| 394 | * Set up the video timing parameters for the DSI video mode operation. |
| 395 | */ |
| 396 | void (*set_video_timing)(struct dsi_ctrl_hw *ctrl, |
| 397 | struct dsi_mode_info *mode); |
| 398 | |
| 399 | /** |
| 400 | * cmd_engine_setup() - setup dsi host controller for command mode |
| 401 | * @ctrl: Pointer to the controller host hardware. |
| 402 | * @common_cfg: Common configuration parameters. |
| 403 | * @cfg: Command mode configuration. |
| 404 | * |
| 405 | * Setup DSI CMD engine with a specific configuration. Controller and |
| 406 | * command engine are not enabled as part of this function. |
| 407 | */ |
| 408 | void (*cmd_engine_setup)(struct dsi_ctrl_hw *ctrl, |
| 409 | struct dsi_host_common_cfg *common_cfg, |
| 410 | struct dsi_cmd_engine_cfg *cfg); |
| 411 | |
| 412 | /** |
Ajay Singh Parmar | aa9152d | 2016-05-16 18:02:07 -0700 | [diff] [blame] | 413 | * setup_cmd_stream() - set up parameters for command pixel streams |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 414 | * @ctrl: Pointer to controller host hardware. |
| 415 | * @mode: Pointer to mode information. |
Ajay Singh Parmar | aa9152d | 2016-05-16 18:02:07 -0700 | [diff] [blame] | 416 | * @h_stride: Horizontal stride in bytes. |
Ajay Singh Parmar | aa9152d | 2016-05-16 18:02:07 -0700 | [diff] [blame] | 417 | * @vc_id: stream_id. |
| 418 | * |
| 419 | * Setup parameters for command mode pixel stream size. |
| 420 | */ |
| 421 | void (*setup_cmd_stream)(struct dsi_ctrl_hw *ctrl, |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 422 | struct dsi_mode_info *mode, |
Ajay Singh Parmar | aa9152d | 2016-05-16 18:02:07 -0700 | [diff] [blame] | 423 | u32 h_stride, |
Lloyd Atkinson | 16e96de | 2017-04-19 11:18:14 -0400 | [diff] [blame] | 424 | u32 vc_id, |
| 425 | struct dsi_rect *roi); |
Ajay Singh Parmar | aa9152d | 2016-05-16 18:02:07 -0700 | [diff] [blame] | 426 | |
| 427 | /** |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 428 | * ctrl_en() - enable DSI controller engine |
| 429 | * @ctrl: Pointer to the controller host hardware. |
| 430 | * @on: turn on/off the DSI controller engine. |
| 431 | */ |
| 432 | void (*ctrl_en)(struct dsi_ctrl_hw *ctrl, bool on); |
| 433 | |
| 434 | /** |
| 435 | * cmd_engine_en() - enable DSI controller command engine |
| 436 | * @ctrl: Pointer to the controller host hardware. |
| 437 | * @on: Turn on/off the DSI command engine. |
| 438 | */ |
| 439 | void (*cmd_engine_en)(struct dsi_ctrl_hw *ctrl, bool on); |
| 440 | |
| 441 | /** |
| 442 | * phy_sw_reset() - perform a soft reset on the PHY. |
| 443 | * @ctrl: Pointer to the controller host hardware. |
| 444 | */ |
| 445 | void (*phy_sw_reset)(struct dsi_ctrl_hw *ctrl); |
| 446 | |
| 447 | /** |
| 448 | * soft_reset() - perform a soft reset on DSI controller |
| 449 | * @ctrl: Pointer to the controller host hardware. |
| 450 | * |
Lloyd Atkinson | 8c49c58 | 2016-11-18 14:23:54 -0500 | [diff] [blame] | 451 | * The video, command and controller engines will be disabled before the |
| 452 | * reset is triggered. After, the engines will be re-enabled to the same |
| 453 | * state as before the reset. |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 454 | * |
| 455 | * If the reset is done while MDP timing engine is turned on, the video |
Lloyd Atkinson | 8c49c58 | 2016-11-18 14:23:54 -0500 | [diff] [blame] | 456 | * engine should be re-enabled only during the vertical blanking time. |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 457 | */ |
| 458 | void (*soft_reset)(struct dsi_ctrl_hw *ctrl); |
| 459 | |
| 460 | /** |
| 461 | * setup_lane_map() - setup mapping between logical and physical lanes |
| 462 | * @ctrl: Pointer to the controller host hardware. |
| 463 | * @lane_map: Structure defining the mapping between DSI logical |
| 464 | * lanes and physical lanes. |
| 465 | */ |
| 466 | void (*setup_lane_map)(struct dsi_ctrl_hw *ctrl, |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 467 | struct dsi_lane_map *lane_map); |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 468 | |
| 469 | /** |
| 470 | * kickoff_command() - transmits commands stored in memory |
| 471 | * @ctrl: Pointer to the controller host hardware. |
| 472 | * @cmd: Command information. |
| 473 | * @flags: Modifiers for command transmission. |
| 474 | * |
| 475 | * The controller hardware is programmed with address and size of the |
| 476 | * command buffer. The transmission is kicked off if |
| 477 | * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag is not set. If this flag is |
| 478 | * set, caller should make a separate call to trigger_command_dma() to |
| 479 | * transmit the command. |
| 480 | */ |
| 481 | void (*kickoff_command)(struct dsi_ctrl_hw *ctrl, |
| 482 | struct dsi_ctrl_cmd_dma_info *cmd, |
| 483 | u32 flags); |
| 484 | |
| 485 | /** |
| 486 | * kickoff_fifo_command() - transmits a command using FIFO in dsi |
| 487 | * hardware. |
| 488 | * @ctrl: Pointer to the controller host hardware. |
| 489 | * @cmd: Command information. |
| 490 | * @flags: Modifiers for command transmission. |
| 491 | * |
| 492 | * The controller hardware FIFO is programmed with command header and |
| 493 | * payload. The transmission is kicked off if |
| 494 | * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag is not set. If this flag is |
| 495 | * set, caller should make a separate call to trigger_command_dma() to |
| 496 | * transmit the command. |
| 497 | */ |
| 498 | void (*kickoff_fifo_command)(struct dsi_ctrl_hw *ctrl, |
| 499 | struct dsi_ctrl_cmd_dma_fifo_info *cmd, |
| 500 | u32 flags); |
| 501 | |
| 502 | void (*reset_cmd_fifo)(struct dsi_ctrl_hw *ctrl); |
| 503 | /** |
| 504 | * trigger_command_dma() - trigger transmission of command buffer. |
| 505 | * @ctrl: Pointer to the controller host hardware. |
| 506 | * |
| 507 | * This trigger can be only used if there was a prior call to |
| 508 | * kickoff_command() of kickoff_fifo_command() with |
| 509 | * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag. |
| 510 | */ |
| 511 | void (*trigger_command_dma)(struct dsi_ctrl_hw *ctrl); |
| 512 | |
| 513 | /** |
| 514 | * get_cmd_read_data() - get data read from the peripheral |
| 515 | * @ctrl: Pointer to the controller host hardware. |
| 516 | * @rd_buf: Buffer where data will be read into. |
| 517 | * @total_read_len: Number of bytes to read. |
| 518 | */ |
| 519 | u32 (*get_cmd_read_data)(struct dsi_ctrl_hw *ctrl, |
| 520 | u8 *rd_buf, |
| 521 | u32 total_read_len); |
| 522 | |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 523 | /** |
| 524 | * wait_for_lane_idle() - wait for DSI lanes to go to idle state |
| 525 | * @ctrl: Pointer to the controller host hardware. |
| 526 | * @lanes: ORed list of lanes (enum dsi_data_lanes) which need |
| 527 | * to be checked to be in idle state. |
| 528 | */ |
| 529 | int (*wait_for_lane_idle)(struct dsi_ctrl_hw *ctrl, u32 lanes); |
| 530 | |
| 531 | struct ctrl_ulps_config_ops ulps_ops; |
| 532 | |
| 533 | /** |
| 534 | * clamp_enable() - enable DSI clamps |
| 535 | * @ctrl: Pointer to the controller host hardware. |
| 536 | * @lanes: ORed list of lanes which need to have clamps released. |
| 537 | * @enable_ulps: ulps state. |
| 538 | */ |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 539 | |
| 540 | /** |
| 541 | * clamp_enable() - enable DSI clamps to keep PHY driving a stable link |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 542 | * @ctrl: Pointer to the controller host hardware. |
| 543 | * @lanes: ORed list of lanes which need to have clamps released. |
| 544 | * @enable_ulps: TODO:?? |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 545 | */ |
| 546 | void (*clamp_enable)(struct dsi_ctrl_hw *ctrl, |
| 547 | u32 lanes, |
| 548 | bool enable_ulps); |
| 549 | |
| 550 | /** |
| 551 | * clamp_disable() - disable DSI clamps |
| 552 | * @ctrl: Pointer to the controller host hardware. |
| 553 | * @lanes: ORed list of lanes which need to have clamps released. |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 554 | * @disable_ulps: ulps state. |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 555 | */ |
| 556 | void (*clamp_disable)(struct dsi_ctrl_hw *ctrl, |
| 557 | u32 lanes, |
| 558 | bool disable_ulps); |
| 559 | |
| 560 | /** |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 561 | * phy_reset_config() - Disable/enable propagation of reset signal |
| 562 | * from ahb domain to DSI PHY |
| 563 | * @ctrl: Pointer to the controller host hardware. |
| 564 | * @enable: True to mask the reset signal, false to unmask |
| 565 | */ |
| 566 | void (*phy_reset_config)(struct dsi_ctrl_hw *ctrl, |
| 567 | bool enable); |
| 568 | |
| 569 | /** |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 570 | * get_interrupt_status() - returns the interrupt status |
| 571 | * @ctrl: Pointer to the controller host hardware. |
| 572 | * |
| 573 | * Returns the ORed list of interrupts(enum dsi_status_int_type) that |
| 574 | * are active. This list does not include any error interrupts. Caller |
| 575 | * should call get_error_status for error interrupts. |
| 576 | * |
| 577 | * Return: List of active interrupts. |
| 578 | */ |
| 579 | u32 (*get_interrupt_status)(struct dsi_ctrl_hw *ctrl); |
| 580 | |
| 581 | /** |
| 582 | * clear_interrupt_status() - clears the specified interrupts |
| 583 | * @ctrl: Pointer to the controller host hardware. |
| 584 | * @ints: List of interrupts to be cleared. |
| 585 | */ |
| 586 | void (*clear_interrupt_status)(struct dsi_ctrl_hw *ctrl, u32 ints); |
| 587 | |
| 588 | /** |
| 589 | * enable_status_interrupts() - enable the specified interrupts |
| 590 | * @ctrl: Pointer to the controller host hardware. |
| 591 | * @ints: List of interrupts to be enabled. |
| 592 | * |
| 593 | * Enables the specified interrupts. This list will override the |
| 594 | * previous interrupts enabled through this function. Caller has to |
| 595 | * maintain the state of the interrupts enabled. To disable all |
| 596 | * interrupts, set ints to 0. |
| 597 | */ |
| 598 | void (*enable_status_interrupts)(struct dsi_ctrl_hw *ctrl, u32 ints); |
| 599 | |
| 600 | /** |
| 601 | * get_error_status() - returns the error status |
| 602 | * @ctrl: Pointer to the controller host hardware. |
| 603 | * |
| 604 | * Returns the ORed list of errors(enum dsi_error_int_type) that are |
| 605 | * active. This list does not include any status interrupts. Caller |
| 606 | * should call get_interrupt_status for status interrupts. |
| 607 | * |
| 608 | * Return: List of active error interrupts. |
| 609 | */ |
| 610 | u64 (*get_error_status)(struct dsi_ctrl_hw *ctrl); |
| 611 | |
| 612 | /** |
| 613 | * clear_error_status() - clears the specified errors |
| 614 | * @ctrl: Pointer to the controller host hardware. |
| 615 | * @errors: List of errors to be cleared. |
| 616 | */ |
| 617 | void (*clear_error_status)(struct dsi_ctrl_hw *ctrl, u64 errors); |
| 618 | |
| 619 | /** |
| 620 | * enable_error_interrupts() - enable the specified interrupts |
| 621 | * @ctrl: Pointer to the controller host hardware. |
| 622 | * @errors: List of errors to be enabled. |
| 623 | * |
| 624 | * Enables the specified interrupts. This list will override the |
| 625 | * previous interrupts enabled through this function. Caller has to |
| 626 | * maintain the state of the interrupts enabled. To disable all |
| 627 | * interrupts, set errors to 0. |
| 628 | */ |
| 629 | void (*enable_error_interrupts)(struct dsi_ctrl_hw *ctrl, u64 errors); |
| 630 | |
| 631 | /** |
| 632 | * video_test_pattern_setup() - setup test pattern engine for video mode |
| 633 | * @ctrl: Pointer to the controller host hardware. |
| 634 | * @type: Type of test pattern. |
| 635 | * @init_val: Initial value to use for generating test pattern. |
| 636 | */ |
| 637 | void (*video_test_pattern_setup)(struct dsi_ctrl_hw *ctrl, |
| 638 | enum dsi_test_pattern type, |
| 639 | u32 init_val); |
| 640 | |
| 641 | /** |
| 642 | * cmd_test_pattern_setup() - setup test patttern engine for cmd mode |
| 643 | * @ctrl: Pointer to the controller host hardware. |
| 644 | * @type: Type of test pattern. |
| 645 | * @init_val: Initial value to use for generating test pattern. |
| 646 | * @stream_id: Stream Id on which packets are generated. |
| 647 | */ |
| 648 | void (*cmd_test_pattern_setup)(struct dsi_ctrl_hw *ctrl, |
| 649 | enum dsi_test_pattern type, |
| 650 | u32 init_val, |
| 651 | u32 stream_id); |
| 652 | |
| 653 | /** |
| 654 | * test_pattern_enable() - enable test pattern engine |
| 655 | * @ctrl: Pointer to the controller host hardware. |
| 656 | * @enable: Enable/Disable test pattern engine. |
| 657 | */ |
| 658 | void (*test_pattern_enable)(struct dsi_ctrl_hw *ctrl, bool enable); |
| 659 | |
| 660 | /** |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 661 | * clear_phy0_ln_err() - clear DSI PHY lane-0 errors |
| 662 | * @ctrl: Pointer to the controller host hardware. |
| 663 | */ |
| 664 | void (*clear_phy0_ln_err)(struct dsi_ctrl_hw *ctrl); |
| 665 | |
| 666 | /** |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 667 | * trigger_cmd_test_pattern() - trigger a command mode frame update with |
| 668 | * test pattern |
| 669 | * @ctrl: Pointer to the controller host hardware. |
| 670 | * @stream_id: Stream on which frame update is sent. |
| 671 | */ |
| 672 | void (*trigger_cmd_test_pattern)(struct dsi_ctrl_hw *ctrl, |
| 673 | u32 stream_id); |
Ajay Singh Parmar | 48ea427 | 2016-06-27 11:44:34 -0700 | [diff] [blame] | 674 | |
| 675 | ssize_t (*reg_dump_to_buffer)(struct dsi_ctrl_hw *ctrl, |
| 676 | char *buf, |
| 677 | u32 size); |
Rajkumar Subbiah | 01e6dd64 | 2017-07-05 14:47:47 -0400 | [diff] [blame] | 678 | |
| 679 | /** |
| 680 | * setup_misr() - Setup frame MISR |
| 681 | * @ctrl: Pointer to the controller host hardware. |
| 682 | * @panel_mode: CMD or VIDEO mode indicator |
| 683 | * @enable: Enable/disable MISR. |
| 684 | * @frame_count: Number of frames to accumulate MISR. |
| 685 | */ |
| 686 | void (*setup_misr)(struct dsi_ctrl_hw *ctrl, |
| 687 | enum dsi_op_mode panel_mode, |
| 688 | bool enable, u32 frame_count); |
| 689 | |
| 690 | /** |
| 691 | * collect_misr() - Read frame MISR |
| 692 | * @ctrl: Pointer to the controller host hardware. |
| 693 | * @panel_mode: CMD or VIDEO mode indicator |
| 694 | */ |
| 695 | u32 (*collect_misr)(struct dsi_ctrl_hw *ctrl, |
| 696 | enum dsi_op_mode panel_mode); |
| 697 | |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 698 | }; |
| 699 | |
| 700 | /* |
| 701 | * struct dsi_ctrl_hw - DSI controller hardware object specific to an instance |
Shashank Babu Chinta Venkata | afef820 | 2017-04-21 13:49:56 -0700 | [diff] [blame] | 702 | * @base: VA for the DSI controller base address. |
| 703 | * @length: Length of the DSI controller register map. |
| 704 | * @mmss_misc_base: Base address of mmss_misc register map. |
| 705 | * @mmss_misc_length: Length of mmss_misc register map. |
| 706 | * @disp_cc_base: Base address of disp_cc register map. |
| 707 | * @disp_cc_length: Length of disp_cc register map. |
| 708 | * @index: Instance ID of the controller. |
| 709 | * @feature_map: Features supported by the DSI controller. |
| 710 | * @ops: Function pointers to the operations supported by the |
| 711 | * controller. |
| 712 | * @supported_interrupts: Number of supported interrupts. |
| 713 | * @supported_errors: Number of supported errors. |
Dhaval Patel | abfaa08 | 2017-07-28 12:41:10 -0700 | [diff] [blame] | 714 | * @phy_isolation_enabled: A boolean property allows to isolate the phy from |
| 715 | * dsi controller and run only dsi controller. |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 716 | */ |
| 717 | struct dsi_ctrl_hw { |
| 718 | void __iomem *base; |
| 719 | u32 length; |
| 720 | void __iomem *mmss_misc_base; |
| 721 | u32 mmss_misc_length; |
Shashank Babu Chinta Venkata | afef820 | 2017-04-21 13:49:56 -0700 | [diff] [blame] | 722 | void __iomem *disp_cc_base; |
| 723 | u32 disp_cc_length; |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 724 | u32 index; |
| 725 | |
| 726 | /* features */ |
| 727 | DECLARE_BITMAP(feature_map, DSI_CTRL_MAX_FEATURES); |
| 728 | struct dsi_ctrl_hw_ops ops; |
| 729 | |
| 730 | /* capabilities */ |
| 731 | u32 supported_interrupts; |
| 732 | u64 supported_errors; |
Dhaval Patel | abfaa08 | 2017-07-28 12:41:10 -0700 | [diff] [blame] | 733 | |
| 734 | bool phy_isolation_enabled; |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 735 | }; |
| 736 | |
| 737 | #endif /* _DSI_CTRL_HW_H_ */ |