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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* Copyright, 1988-1992, Russell Nelson, Crynwr Software
2
3 This program is free software; you can redistribute it and/or modify
4 it under the terms of the GNU General Public License as published by
5 the Free Software Foundation, version 1.
6
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
11
12 You should have received a copy of the GNU General Public License
13 along with this program; if not, write to the Free Software
14 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
15 */
16
17#include <linux/config.h>
18
dmitry pervushin0dd3c782005-06-20 15:32:54 -070019#if defined(CONFIG_ARCH_IXDP2X01) || defined(CONFIG_ARCH_PNX0105)
Linus Torvalds1da177e2005-04-16 15:20:36 -070020/* IXDP2401/IXDP2801 uses dword-aligned register addressing */
21#define CS89x0_PORT(reg) ((reg) * 2)
22#else
23#define CS89x0_PORT(reg) (reg)
24#endif
25
26#define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
27 /* offset 2h -> Model/Product Number */
28 /* offset 3h -> Chip Revision Number */
29
30#define PP_ISAIOB 0x0020 /* IO base address */
31#define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
32#define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
33#define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
34#define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
35#define PP_ISASOF 0x0026 /* ISA DMA offset */
36#define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
37#define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
38#define PP_CS8900_ISAMemB 0x002C /* Memory base */
39#define PP_CS8920_ISAMemB 0x0348 /* */
40
41#define PP_ISABootBase 0x0030 /* Boot Prom base */
42#define PP_ISABootMask 0x0034 /* Boot Prom Mask */
43
44/* EEPROM data and command registers */
45#define PP_EECMD 0x0040 /* NVR Interface Command register */
46#define PP_EEData 0x0042 /* NVR Interface Data Register */
47#define PP_DebugReg 0x0044 /* Debug Register */
48
49#define PP_RxCFG 0x0102 /* Rx Bus config */
50#define PP_RxCTL 0x0104 /* Receive Control Register */
51#define PP_TxCFG 0x0106 /* Transmit Config Register */
52#define PP_TxCMD 0x0108 /* Transmit Command Register */
53#define PP_BufCFG 0x010A /* Bus configuration Register */
54#define PP_LineCTL 0x0112 /* Line Config Register */
55#define PP_SelfCTL 0x0114 /* Self Command Register */
56#define PP_BusCTL 0x0116 /* ISA bus control Register */
57#define PP_TestCTL 0x0118 /* Test Register */
58#define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */
59
60#define PP_ISQ 0x0120 /* Interrupt Status */
61#define PP_RxEvent 0x0124 /* Rx Event Register */
62#define PP_TxEvent 0x0128 /* Tx Event Register */
63#define PP_BufEvent 0x012C /* Bus Event Register */
64#define PP_RxMiss 0x0130 /* Receive Miss Count */
65#define PP_TxCol 0x0132 /* Transmit Collision Count */
66#define PP_LineST 0x0134 /* Line State Register */
67#define PP_SelfST 0x0136 /* Self State register */
68#define PP_BusST 0x0138 /* Bus Status */
69#define PP_TDR 0x013C /* Time Domain Reflectometry */
70#define PP_AutoNegST 0x013E /* Auto Neg Status */
71#define PP_TxCommand 0x0144 /* Tx Command */
72#define PP_TxLength 0x0146 /* Tx Length */
73#define PP_LAF 0x0150 /* Hash Table */
74#define PP_IA 0x0158 /* Physical Address Register */
75
76#define PP_RxStatus 0x0400 /* Receive start of frame */
77#define PP_RxLength 0x0402 /* Receive Length of frame */
78#define PP_RxFrame 0x0404 /* Receive frame pointer */
79#define PP_TxFrame 0x0A00 /* Transmit frame pointer */
80
81/* Primary I/O Base Address. If no I/O base is supplied by the user, then this */
82/* can be used as the default I/O base to access the PacketPage Area. */
83#define DEFAULTIOBASE 0x0300
84#define FIRST_IO 0x020C /* First I/O port to check */
85#define LAST_IO 0x037C /* Last I/O port to check (+10h) */
86#define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */
87#define ADD_SIG 0x3000 /* Expected ID signature */
88
89/* On Macs, we only need use the ISA I/O stuff until we do MEMORY_ON */
90#ifdef CONFIG_MAC
91#define LCSLOTBASE 0xfee00000
92#define MMIOBASE 0x40000
93#endif
94
95#define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */
Denis Vlasenko01bdc032005-07-31 22:34:50 -070096#define CHIP_EISA_ID_SIG_STR "0x630E"
Linus Torvalds1da177e2005-04-16 15:20:36 -070097
98#ifdef IBMEIPKT
99#define EISA_ID_SIG 0x4D24 /* IBM */
100#define PART_NO_SIG 0x1010 /* IBM */
101#define MONGOOSE_BIT 0x0000 /* IBM */
102#else
103#define EISA_ID_SIG 0x630E /* PnP Vendor ID (same as chip id for Crystal board) */
104#define PART_NO_SIG 0x4000 /* ID code CS8920 board (PnP Vendor Product code) */
105#define MONGOOSE_BIT 0x2000 /* PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */
106#endif
107
108#define PRODUCT_ID_ADD 0x0002 /* Address of product ID */
109
110/* Mask to find out the types of registers */
111#define REG_TYPE_MASK 0x001F
112
113/* Eeprom Commands */
114#define ERSE_WR_ENBL 0x00F0
115#define ERSE_WR_DISABLE 0x0000
116
117/* Defines Control/Config register quintuplet numbers */
118#define RX_BUF_CFG 0x0003
119#define RX_CONTROL 0x0005
120#define TX_CFG 0x0007
121#define TX_COMMAND 0x0009
122#define BUF_CFG 0x000B
123#define LINE_CONTROL 0x0013
124#define SELF_CONTROL 0x0015
125#define BUS_CONTROL 0x0017
126#define TEST_CONTROL 0x0019
127
128/* Defines Status/Count registers quintuplet numbers */
129#define RX_EVENT 0x0004
130#define TX_EVENT 0x0008
131#define BUF_EVENT 0x000C
132#define RX_MISS_COUNT 0x0010
133#define TX_COL_COUNT 0x0012
134#define LINE_STATUS 0x0014
135#define SELF_STATUS 0x0016
136#define BUS_STATUS 0x0018
137#define TDR 0x001C
138
139/* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */
140#define SKIP_1 0x0040
141#define RX_STREAM_ENBL 0x0080
142#define RX_OK_ENBL 0x0100
143#define RX_DMA_ONLY 0x0200
144#define AUTO_RX_DMA 0x0400
145#define BUFFER_CRC 0x0800
146#define RX_CRC_ERROR_ENBL 0x1000
147#define RX_RUNT_ENBL 0x2000
148#define RX_EXTRA_DATA_ENBL 0x4000
149
150/* PP_RxCTL - Receive Control bit definition - Read/write */
151#define RX_IA_HASH_ACCEPT 0x0040
152#define RX_PROM_ACCEPT 0x0080
153#define RX_OK_ACCEPT 0x0100
154#define RX_MULTCAST_ACCEPT 0x0200
155#define RX_IA_ACCEPT 0x0400
156#define RX_BROADCAST_ACCEPT 0x0800
157#define RX_BAD_CRC_ACCEPT 0x1000
158#define RX_RUNT_ACCEPT 0x2000
159#define RX_EXTRA_DATA_ACCEPT 0x4000
160#define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT)
161/* Default receive mode - individually addressed, broadcast, and error free */
162#define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)
163
164/* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */
165#define TX_LOST_CRS_ENBL 0x0040
166#define TX_SQE_ERROR_ENBL 0x0080
167#define TX_OK_ENBL 0x0100
168#define TX_LATE_COL_ENBL 0x0200
169#define TX_JBR_ENBL 0x0400
170#define TX_ANY_COL_ENBL 0x0800
171#define TX_16_COL_ENBL 0x8000
172
173/* PP_TxCMD - Transmit Command bit definition - Read-only */
174#define TX_START_4_BYTES 0x0000
175#define TX_START_64_BYTES 0x0040
176#define TX_START_128_BYTES 0x0080
177#define TX_START_ALL_BYTES 0x00C0
178#define TX_FORCE 0x0100
179#define TX_ONE_COL 0x0200
180#define TX_TWO_PART_DEFF_DISABLE 0x0400
181#define TX_NO_CRC 0x1000
182#define TX_RUNT 0x2000
183
184/* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */
185#define GENERATE_SW_INTERRUPT 0x0040
186#define RX_DMA_ENBL 0x0080
187#define READY_FOR_TX_ENBL 0x0100
188#define TX_UNDERRUN_ENBL 0x0200
189#define RX_MISS_ENBL 0x0400
190#define RX_128_BYTE_ENBL 0x0800
191#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
192#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
193#define RX_DEST_MATCH_ENBL 0x8000
194
195/* PP_LineCTL - Line Control bit definition - Read/write */
196#define SERIAL_RX_ON 0x0040
197#define SERIAL_TX_ON 0x0080
198#define AUI_ONLY 0x0100
199#define AUTO_AUI_10BASET 0x0200
200#define MODIFIED_BACKOFF 0x0800
201#define NO_AUTO_POLARITY 0x1000
202#define TWO_PART_DEFDIS 0x2000
203#define LOW_RX_SQUELCH 0x4000
204
205/* PP_SelfCTL - Software Self Control bit definition - Read/write */
206#define POWER_ON_RESET 0x0040
207#define SW_STOP 0x0100
208#define SLEEP_ON 0x0200
209#define AUTO_WAKEUP 0x0400
210#define HCB0_ENBL 0x1000
211#define HCB1_ENBL 0x2000
212#define HCB0 0x4000
213#define HCB1 0x8000
214
215/* PP_BusCTL - ISA Bus Control bit definition - Read/write */
216#define RESET_RX_DMA 0x0040
217#define MEMORY_ON 0x0400
218#define DMA_BURST_MODE 0x0800
219#define IO_CHANNEL_READY_ON 0x1000
220#define RX_DMA_SIZE_64K 0x2000
221#define ENABLE_IRQ 0x8000
222
223/* PP_TestCTL - Test Control bit definition - Read/write */
224#define LINK_OFF 0x0080
225#define ENDEC_LOOPBACK 0x0200
226#define AUI_LOOPBACK 0x0400
227#define BACKOFF_OFF 0x0800
228#define FDX_8900 0x4000
229#define FAST_TEST 0x8000
230
231/* PP_RxEvent - Receive Event Bit definition - Read-only */
232#define RX_IA_HASHED 0x0040
233#define RX_DRIBBLE 0x0080
234#define RX_OK 0x0100
235#define RX_HASHED 0x0200
236#define RX_IA 0x0400
237#define RX_BROADCAST 0x0800
238#define RX_CRC_ERROR 0x1000
239#define RX_RUNT 0x2000
240#define RX_EXTRA_DATA 0x4000
241
242#define HASH_INDEX_MASK 0x0FC00
243
244/* PP_TxEvent - Transmit Event Bit definition - Read-only */
245#define TX_LOST_CRS 0x0040
246#define TX_SQE_ERROR 0x0080
247#define TX_OK 0x0100
248#define TX_LATE_COL 0x0200
249#define TX_JBR 0x0400
250#define TX_16_COL 0x8000
251#define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS)
252#define TX_COL_COUNT_MASK 0x7800
253
254/* PP_BufEvent - Buffer Event Bit definition - Read-only */
255#define SW_INTERRUPT 0x0040
256#define RX_DMA 0x0080
257#define READY_FOR_TX 0x0100
258#define TX_UNDERRUN 0x0200
259#define RX_MISS 0x0400
260#define RX_128_BYTE 0x0800
261#define TX_COL_OVRFLW 0x1000
262#define RX_MISS_OVRFLW 0x2000
263#define RX_DEST_MATCH 0x8000
264
265/* PP_LineST - Ethernet Line Status bit definition - Read-only */
266#define LINK_OK 0x0080
267#define AUI_ON 0x0100
268#define TENBASET_ON 0x0200
269#define POLARITY_OK 0x1000
270#define CRS_OK 0x4000
271
272/* PP_SelfST - Chip Software Status bit definition */
273#define ACTIVE_33V 0x0040
274#define INIT_DONE 0x0080
275#define SI_BUSY 0x0100
276#define EEPROM_PRESENT 0x0200
277#define EEPROM_OK 0x0400
278#define EL_PRESENT 0x0800
279#define EE_SIZE_64 0x1000
280
281/* PP_BusST - ISA Bus Status bit definition */
282#define TX_BID_ERROR 0x0080
283#define READY_FOR_TX_NOW 0x0100
284
285/* PP_AutoNegCTL - Auto Negotiation Control bit definition */
286#define RE_NEG_NOW 0x0040
287#define ALLOW_FDX 0x0080
288#define AUTO_NEG_ENABLE 0x0100
289#define NLP_ENABLE 0x0200
290#define FORCE_FDX 0x8000
291#define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE)
292#define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW)
293
294/* PP_AutoNegST - Auto Negotiation Status bit definition */
295#define AUTO_NEG_BUSY 0x0080
296#define FLP_LINK 0x0100
297#define FLP_LINK_GOOD 0x0800
298#define LINK_FAULT 0x1000
299#define HDX_ACTIVE 0x4000
300#define FDX_ACTIVE 0x8000
301
302/* The following block defines the ISQ event types */
303#define ISQ_RECEIVER_EVENT 0x04
304#define ISQ_TRANSMITTER_EVENT 0x08
305#define ISQ_BUFFER_EVENT 0x0c
306#define ISQ_RX_MISS_EVENT 0x10
307#define ISQ_TX_COL_EVENT 0x12
308
309#define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */
310#define ISQ_HIST 16 /* small history buffer */
311#define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */
312
313#define TXRXBUFSIZE 0x0600
314#define RXDMABUFSIZE 0x8000
315#define RXDMASIZE 0x4000
316#define TXRX_LENGTH_MASK 0x07FF
317
318/* rx options bits */
319#define RCV_WITH_RXON 1 /* Set SerRx ON */
320#define RCV_COUNTS 2 /* Use Framecnt1 */
321#define RCV_PONG 4 /* Pong respondent */
322#define RCV_DONG 8 /* Dong operation */
323#define RCV_POLLING 0x10 /* Poll RxEvent */
324#define RCV_ISQ 0x20 /* Use ISQ, int */
325#define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */
326#define RCV_DMA 0x200 /* Set RxDMA only */
327#define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */
328#define RCV_FIXED_DATA 0x800 /* Every frame same */
329#define RCV_IO 0x1000 /* Use ISA IO only */
330#define RCV_MEMORY 0x2000 /* Use ISA Memory */
331
332#define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */
333#define PKT_START PP_TxFrame /* Start of packet RAM */
334
335#define RX_FRAME_PORT CS89x0_PORT(0x0000)
336#define TX_FRAME_PORT RX_FRAME_PORT
337#define TX_CMD_PORT CS89x0_PORT(0x0004)
338#define TX_NOW 0x0000 /* Tx packet after 5 bytes copied */
339#define TX_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */
340#define TX_AFTER_ALL 0x00c0 /* Tx packet after all bytes copied */
341#define TX_LEN_PORT CS89x0_PORT(0x0006)
342#define ISQ_PORT CS89x0_PORT(0x0008)
343#define ADD_PORT CS89x0_PORT(0x000A)
344#define DATA_PORT CS89x0_PORT(0x000C)
345
346#define EEPROM_WRITE_EN 0x00F0
347#define EEPROM_WRITE_DIS 0x0000
348#define EEPROM_WRITE_CMD 0x0100
349#define EEPROM_READ_CMD 0x0200
350
351/* Receive Header */
352/* Description of header of each packet in receive area of memory */
353#define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */
354#define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */
355#define RBUF_LEN_LOW 2 /* Length of received data - low byte */
356#define RBUF_LEN_HI 3 /* Length of received data - high byte */
357#define RBUF_HEAD_LEN 4 /* Length of this header */
358
359#define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */
360#define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */
361
362/* for bios scan */
363/* */
364#ifdef CSDEBUG
365/* use these values for debugging bios scan */
366#define BIOS_START_SEG 0x00000
367#define BIOS_OFFSET_INC 0x0010
368#else
369#define BIOS_START_SEG 0x0c000
370#define BIOS_OFFSET_INC 0x0200
371#endif
372
373#define BIOS_LAST_OFFSET 0x0fc00
374
375/* Byte offsets into the EEPROM configuration buffer */
376#define ISA_CNF_OFFSET 0x6
377#define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */
378#define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */
379
380 /* the assumption here is that the bits in the eeprom are generally */
381 /* in the same position as those in the autonegctl register. */
382 /* Of course the IMM bit is not in that register so it must be */
383 /* masked out */
384#define EE_FORCE_FDX 0x8000
385#define EE_NLP_ENABLE 0x0200
386#define EE_AUTO_NEG_ENABLE 0x0100
387#define EE_ALLOW_FDX 0x0080
388#define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX)
389
390#define IMM_BIT 0x0040 /* ignore missing media */
391
392#define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2)
393#define A_CNF_10B_T 0x0001
394#define A_CNF_AUI 0x0002
395#define A_CNF_10B_2 0x0004
396#define A_CNF_MEDIA_TYPE 0x0070
397#define A_CNF_MEDIA_AUTO 0x0070
398#define A_CNF_MEDIA_10B_T 0x0020
399#define A_CNF_MEDIA_AUI 0x0040
400#define A_CNF_MEDIA_10B_2 0x0010
401#define A_CNF_DC_DC_POLARITY 0x0080
402#define A_CNF_NO_AUTO_POLARITY 0x2000
403#define A_CNF_LOW_RX_SQUELCH 0x4000
404#define A_CNF_EXTND_10B_2 0x8000
405
406#define PACKET_PAGE_OFFSET 0x8
407
408/* Bit definitions for the ISA configuration word from the EEPROM */
409#define INT_NO_MASK 0x000F
410#define DMA_NO_MASK 0x0070
411#define ISA_DMA_SIZE 0x0200
412#define ISA_AUTO_RxDMA 0x0400
413#define ISA_RxDMA 0x0800
414#define DMA_BURST 0x1000
415#define STREAM_TRANSFER 0x2000
416#define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)
417
418/* DMA controller registers */
419#define DMA_BASE 0x00 /* DMA controller base */
420#define DMA_BASE_2 0x0C0 /* DMA controller base */
421
422#define DMA_STAT 0x0D0 /* DMA controller status register */
423#define DMA_MASK 0x0D4 /* DMA controller mask register */
424#define DMA_MODE 0x0D6 /* DMA controller mode register */
425#define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */
426
427/* DMA data */
428#define DMA_DISABLE 0x04 /* Disable channel n */
429#define DMA_ENABLE 0x00 /* Enable channel n */
430/* Demand transfers, incr. address, auto init, writes, ch. n */
431#define DMA_RX_MODE 0x14
432/* Demand transfers, incr. address, auto init, reads, ch. n */
433#define DMA_TX_MODE 0x18
434
435#define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */
436
437#define CS8900 0x0000
438#define CS8920 0x4000
439#define CS8920M 0x6000
440#define REVISON_BITS 0x1F00
441#define EEVER_NUMBER 0x12
442#define CHKSUM_LEN 0x14
443#define CHKSUM_VAL 0x0000
444#define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */
445#define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */
446#define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */
447#define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */
448#ifdef CONFIG_SH_HICOSH4
449#define CS8900_IRQ_MAP 0x0002 /* HiCO-SH4 board has its IRQ on #1 */
450#else
451#define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */
452#endif
453
454#define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */
455
456#define PNP_ADD_PORT 0x0279
457#define PNP_WRITE_PORT 0x0A79
458
459#define GET_PNP_ISA_STRUCT 0x40
460#define PNP_ISA_STRUCT_LEN 0x06
461#define PNP_CSN_CNT_OFF 0x01
462#define PNP_RD_PORT_OFF 0x02
463#define PNP_FUNCTION_OK 0x00
464#define PNP_WAKE 0x03
465#define PNP_RSRC_DATA 0x04
466#define PNP_RSRC_READY 0x01
467#define PNP_STATUS 0x05
468#define PNP_ACTIVATE 0x30
469#define PNP_CNF_IO_H 0x60
470#define PNP_CNF_IO_L 0x61
471#define PNP_CNF_INT 0x70
472#define PNP_CNF_DMA 0x74
473#define PNP_CNF_MEM 0x48
474
475#define BIT0 1
476#define BIT15 0x8000
477