Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2013 NVIDIA Corporation |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | #include <linux/clk.h> |
| 10 | #include <linux/io.h> |
| 11 | #include <linux/platform_device.h> |
| 12 | #include <linux/reset.h> |
| 13 | #include <linux/tegra-powergate.h> |
| 14 | |
| 15 | #include <drm/drm_dp_helper.h> |
| 16 | |
| 17 | #include "dc.h" |
| 18 | #include "drm.h" |
| 19 | #include "sor.h" |
| 20 | |
| 21 | struct tegra_sor { |
| 22 | struct host1x_client client; |
| 23 | struct tegra_output output; |
| 24 | struct device *dev; |
| 25 | |
| 26 | void __iomem *regs; |
| 27 | |
| 28 | struct reset_control *rst; |
| 29 | struct clk *clk_parent; |
| 30 | struct clk *clk_safe; |
| 31 | struct clk *clk_dp; |
| 32 | struct clk *clk; |
| 33 | |
| 34 | struct tegra_dpaux *dpaux; |
| 35 | |
| 36 | bool enabled; |
| 37 | }; |
| 38 | |
| 39 | static inline struct tegra_sor * |
| 40 | host1x_client_to_sor(struct host1x_client *client) |
| 41 | { |
| 42 | return container_of(client, struct tegra_sor, client); |
| 43 | } |
| 44 | |
| 45 | static inline struct tegra_sor *to_sor(struct tegra_output *output) |
| 46 | { |
| 47 | return container_of(output, struct tegra_sor, output); |
| 48 | } |
| 49 | |
| 50 | static inline unsigned long tegra_sor_readl(struct tegra_sor *sor, |
| 51 | unsigned long offset) |
| 52 | { |
| 53 | return readl(sor->regs + (offset << 2)); |
| 54 | } |
| 55 | |
| 56 | static inline void tegra_sor_writel(struct tegra_sor *sor, unsigned long value, |
| 57 | unsigned long offset) |
| 58 | { |
| 59 | writel(value, sor->regs + (offset << 2)); |
| 60 | } |
| 61 | |
| 62 | static int tegra_sor_dp_train_fast(struct tegra_sor *sor, |
| 63 | struct drm_dp_link *link) |
| 64 | { |
| 65 | unsigned long value; |
| 66 | unsigned int i; |
| 67 | u8 pattern; |
| 68 | int err; |
| 69 | |
| 70 | /* setup lane parameters */ |
| 71 | value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | |
| 72 | SOR_LANE_DRIVE_CURRENT_LANE2(0x40) | |
| 73 | SOR_LANE_DRIVE_CURRENT_LANE1(0x40) | |
| 74 | SOR_LANE_DRIVE_CURRENT_LANE0(0x40); |
| 75 | tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0); |
| 76 | |
| 77 | value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | |
| 78 | SOR_LANE_PREEMPHASIS_LANE2(0x0f) | |
| 79 | SOR_LANE_PREEMPHASIS_LANE1(0x0f) | |
| 80 | SOR_LANE_PREEMPHASIS_LANE0(0x0f); |
| 81 | tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0); |
| 82 | |
| 83 | value = SOR_LANE_POST_CURSOR_LANE3(0x00) | |
| 84 | SOR_LANE_POST_CURSOR_LANE2(0x00) | |
| 85 | SOR_LANE_POST_CURSOR_LANE1(0x00) | |
| 86 | SOR_LANE_POST_CURSOR_LANE0(0x00); |
| 87 | tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0); |
| 88 | |
| 89 | /* disable LVDS mode */ |
| 90 | tegra_sor_writel(sor, 0, SOR_LVDS); |
| 91 | |
| 92 | value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); |
| 93 | value |= SOR_DP_PADCTL_TX_PU_ENABLE; |
| 94 | value &= ~SOR_DP_PADCTL_TX_PU_MASK; |
| 95 | value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ |
| 96 | tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); |
| 97 | |
| 98 | value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); |
| 99 | value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | |
| 100 | SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; |
| 101 | tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); |
| 102 | |
| 103 | usleep_range(10, 100); |
| 104 | |
| 105 | value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); |
| 106 | value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | |
| 107 | SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); |
| 108 | tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); |
| 109 | |
| 110 | err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B); |
| 111 | if (err < 0) |
| 112 | return err; |
| 113 | |
| 114 | for (i = 0, value = 0; i < link->num_lanes; i++) { |
| 115 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | |
| 116 | SOR_DP_TPG_SCRAMBLER_NONE | |
| 117 | SOR_DP_TPG_PATTERN_TRAIN1; |
| 118 | value = (value << 8) | lane; |
| 119 | } |
| 120 | |
| 121 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
| 122 | |
| 123 | pattern = DP_TRAINING_PATTERN_1; |
| 124 | |
| 125 | err = tegra_dpaux_train(sor->dpaux, link, pattern); |
| 126 | if (err < 0) |
| 127 | return err; |
| 128 | |
| 129 | value = tegra_sor_readl(sor, SOR_DP_SPARE_0); |
| 130 | value |= SOR_DP_SPARE_SEQ_ENABLE; |
| 131 | value &= ~SOR_DP_SPARE_PANEL_INTERNAL; |
| 132 | value |= SOR_DP_SPARE_MACRO_SOR_CLK; |
| 133 | tegra_sor_writel(sor, value, SOR_DP_SPARE_0); |
| 134 | |
| 135 | for (i = 0, value = 0; i < link->num_lanes; i++) { |
| 136 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | |
| 137 | SOR_DP_TPG_SCRAMBLER_NONE | |
| 138 | SOR_DP_TPG_PATTERN_TRAIN2; |
| 139 | value = (value << 8) | lane; |
| 140 | } |
| 141 | |
| 142 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
| 143 | |
| 144 | pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2; |
| 145 | |
| 146 | err = tegra_dpaux_train(sor->dpaux, link, pattern); |
| 147 | if (err < 0) |
| 148 | return err; |
| 149 | |
| 150 | for (i = 0, value = 0; i < link->num_lanes; i++) { |
| 151 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | |
| 152 | SOR_DP_TPG_SCRAMBLER_GALIOS | |
| 153 | SOR_DP_TPG_PATTERN_NONE; |
| 154 | value = (value << 8) | lane; |
| 155 | } |
| 156 | |
| 157 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
| 158 | |
| 159 | pattern = DP_TRAINING_PATTERN_DISABLE; |
| 160 | |
| 161 | err = tegra_dpaux_train(sor->dpaux, link, pattern); |
| 162 | if (err < 0) |
| 163 | return err; |
| 164 | |
| 165 | return 0; |
| 166 | } |
| 167 | |
| 168 | static void tegra_sor_super_update(struct tegra_sor *sor) |
| 169 | { |
| 170 | tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0); |
| 171 | tegra_sor_writel(sor, 1, SOR_SUPER_STATE_0); |
| 172 | tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0); |
| 173 | } |
| 174 | |
| 175 | static void tegra_sor_update(struct tegra_sor *sor) |
| 176 | { |
| 177 | tegra_sor_writel(sor, 0, SOR_STATE_0); |
| 178 | tegra_sor_writel(sor, 1, SOR_STATE_0); |
| 179 | tegra_sor_writel(sor, 0, SOR_STATE_0); |
| 180 | } |
| 181 | |
| 182 | static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) |
| 183 | { |
| 184 | unsigned long value; |
| 185 | |
| 186 | value = tegra_sor_readl(sor, SOR_PWM_DIV); |
| 187 | value &= ~SOR_PWM_DIV_MASK; |
| 188 | value |= 0x400; /* period */ |
| 189 | tegra_sor_writel(sor, value, SOR_PWM_DIV); |
| 190 | |
| 191 | value = tegra_sor_readl(sor, SOR_PWM_CTL); |
| 192 | value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; |
| 193 | value |= 0x400; /* duty cycle */ |
| 194 | value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ |
| 195 | value |= SOR_PWM_CTL_TRIGGER; |
| 196 | tegra_sor_writel(sor, value, SOR_PWM_CTL); |
| 197 | |
| 198 | timeout = jiffies + msecs_to_jiffies(timeout); |
| 199 | |
| 200 | while (time_before(jiffies, timeout)) { |
| 201 | value = tegra_sor_readl(sor, SOR_PWM_CTL); |
| 202 | if ((value & SOR_PWM_CTL_TRIGGER) == 0) |
| 203 | return 0; |
| 204 | |
| 205 | usleep_range(25, 100); |
| 206 | } |
| 207 | |
| 208 | return -ETIMEDOUT; |
| 209 | } |
| 210 | |
| 211 | static int tegra_sor_attach(struct tegra_sor *sor) |
| 212 | { |
| 213 | unsigned long value, timeout; |
| 214 | |
| 215 | /* wake up in normal mode */ |
| 216 | value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); |
| 217 | value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; |
| 218 | value |= SOR_SUPER_STATE_MODE_NORMAL; |
| 219 | tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); |
| 220 | tegra_sor_super_update(sor); |
| 221 | |
| 222 | /* attach */ |
| 223 | value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); |
| 224 | value |= SOR_SUPER_STATE_ATTACHED; |
| 225 | tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); |
| 226 | tegra_sor_super_update(sor); |
| 227 | |
| 228 | timeout = jiffies + msecs_to_jiffies(250); |
| 229 | |
| 230 | while (time_before(jiffies, timeout)) { |
| 231 | value = tegra_sor_readl(sor, SOR_TEST); |
| 232 | if ((value & SOR_TEST_ATTACHED) != 0) |
| 233 | return 0; |
| 234 | |
| 235 | usleep_range(25, 100); |
| 236 | } |
| 237 | |
| 238 | return -ETIMEDOUT; |
| 239 | } |
| 240 | |
| 241 | static int tegra_sor_wakeup(struct tegra_sor *sor) |
| 242 | { |
| 243 | struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); |
| 244 | unsigned long value, timeout; |
| 245 | |
| 246 | /* enable display controller outputs */ |
| 247 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); |
| 248 | value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | |
| 249 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; |
| 250 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); |
| 251 | |
| 252 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); |
| 253 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); |
| 254 | |
| 255 | timeout = jiffies + msecs_to_jiffies(250); |
| 256 | |
| 257 | /* wait for head to wake up */ |
| 258 | while (time_before(jiffies, timeout)) { |
| 259 | value = tegra_sor_readl(sor, SOR_TEST); |
| 260 | value &= SOR_TEST_HEAD_MODE_MASK; |
| 261 | |
| 262 | if (value == SOR_TEST_HEAD_MODE_AWAKE) |
| 263 | return 0; |
| 264 | |
| 265 | usleep_range(25, 100); |
| 266 | } |
| 267 | |
| 268 | return -ETIMEDOUT; |
| 269 | } |
| 270 | |
| 271 | static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) |
| 272 | { |
| 273 | unsigned long value; |
| 274 | |
| 275 | value = tegra_sor_readl(sor, SOR_PWR); |
| 276 | value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; |
| 277 | tegra_sor_writel(sor, value, SOR_PWR); |
| 278 | |
| 279 | timeout = jiffies + msecs_to_jiffies(timeout); |
| 280 | |
| 281 | while (time_before(jiffies, timeout)) { |
| 282 | value = tegra_sor_readl(sor, SOR_PWR); |
| 283 | if ((value & SOR_PWR_TRIGGER) == 0) |
| 284 | return 0; |
| 285 | |
| 286 | usleep_range(25, 100); |
| 287 | } |
| 288 | |
| 289 | return -ETIMEDOUT; |
| 290 | } |
| 291 | |
| 292 | static int tegra_output_sor_enable(struct tegra_output *output) |
| 293 | { |
| 294 | struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); |
| 295 | struct drm_display_mode *mode = &dc->base.mode; |
| 296 | unsigned int vbe, vse, hbe, hse, vbs, hbs, i; |
| 297 | struct tegra_sor *sor = to_sor(output); |
| 298 | unsigned long value; |
| 299 | int err; |
| 300 | |
| 301 | if (sor->enabled) |
| 302 | return 0; |
| 303 | |
| 304 | err = clk_prepare_enable(sor->clk); |
| 305 | if (err < 0) |
| 306 | return err; |
| 307 | |
| 308 | reset_control_deassert(sor->rst); |
| 309 | |
| 310 | if (sor->dpaux) { |
| 311 | err = tegra_dpaux_enable(sor->dpaux); |
| 312 | if (err < 0) |
| 313 | dev_err(sor->dev, "failed to enable DP: %d\n", err); |
| 314 | } |
| 315 | |
| 316 | err = clk_set_parent(sor->clk, sor->clk_safe); |
| 317 | if (err < 0) |
| 318 | dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); |
| 319 | |
| 320 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
| 321 | value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; |
| 322 | value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; |
| 323 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
| 324 | |
| 325 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 326 | value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; |
| 327 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 328 | usleep_range(20, 100); |
| 329 | |
| 330 | value = tegra_sor_readl(sor, SOR_PLL_3); |
| 331 | value |= SOR_PLL_3_PLL_VDD_MODE_V3_3; |
| 332 | tegra_sor_writel(sor, value, SOR_PLL_3); |
| 333 | |
| 334 | value = SOR_PLL_0_ICHPMP(0xf) | SOR_PLL_0_VCOCAP_RST | |
| 335 | SOR_PLL_0_PLLREG_LEVEL_V45 | SOR_PLL_0_RESISTOR_EXT; |
| 336 | tegra_sor_writel(sor, value, SOR_PLL_0); |
| 337 | |
| 338 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 339 | value |= SOR_PLL_2_SEQ_PLLCAPPD; |
| 340 | value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; |
| 341 | value |= SOR_PLL_2_LVDS_ENABLE; |
| 342 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 343 | |
| 344 | value = SOR_PLL_1_TERM_COMPOUT | SOR_PLL_1_TMDS_TERM; |
| 345 | tegra_sor_writel(sor, value, SOR_PLL_1); |
| 346 | |
| 347 | while (true) { |
| 348 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 349 | if ((value & SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE) == 0) |
| 350 | break; |
| 351 | |
| 352 | usleep_range(250, 1000); |
| 353 | } |
| 354 | |
| 355 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 356 | value &= ~SOR_PLL_2_POWERDOWN_OVERRIDE; |
| 357 | value &= ~SOR_PLL_2_PORT_POWERDOWN; |
| 358 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 359 | |
| 360 | /* |
| 361 | * power up |
| 362 | */ |
| 363 | |
| 364 | /* set safe link bandwidth (1.62 Gbps) */ |
| 365 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
| 366 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; |
| 367 | value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; |
| 368 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
| 369 | |
| 370 | /* step 1 */ |
| 371 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 372 | value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL_2_PORT_POWERDOWN | |
| 373 | SOR_PLL_2_BANDGAP_POWERDOWN; |
| 374 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 375 | |
| 376 | value = tegra_sor_readl(sor, SOR_PLL_0); |
| 377 | value |= SOR_PLL_0_VCOPD | SOR_PLL_0_POWER_OFF; |
| 378 | tegra_sor_writel(sor, value, SOR_PLL_0); |
| 379 | |
| 380 | value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); |
| 381 | value &= ~SOR_DP_PADCTL_PAD_CAL_PD; |
| 382 | tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); |
| 383 | |
| 384 | /* step 2 */ |
| 385 | err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); |
| 386 | if (err < 0) { |
| 387 | dev_err(sor->dev, "failed to power on I/O rail: %d\n", err); |
| 388 | return err; |
| 389 | } |
| 390 | |
| 391 | usleep_range(5, 100); |
| 392 | |
| 393 | /* step 3 */ |
| 394 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 395 | value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; |
| 396 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 397 | |
| 398 | usleep_range(20, 100); |
| 399 | |
| 400 | /* step 4 */ |
| 401 | value = tegra_sor_readl(sor, SOR_PLL_0); |
| 402 | value &= ~SOR_PLL_0_POWER_OFF; |
| 403 | value &= ~SOR_PLL_0_VCOPD; |
| 404 | tegra_sor_writel(sor, value, SOR_PLL_0); |
| 405 | |
| 406 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 407 | value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; |
| 408 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 409 | |
| 410 | usleep_range(200, 1000); |
| 411 | |
| 412 | /* step 5 */ |
| 413 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 414 | value &= ~SOR_PLL_2_PORT_POWERDOWN; |
| 415 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 416 | |
| 417 | /* switch to DP clock */ |
| 418 | err = clk_set_parent(sor->clk, sor->clk_dp); |
| 419 | if (err < 0) |
| 420 | dev_err(sor->dev, "failed to set DP parent clock: %d\n", err); |
| 421 | |
| 422 | /* power dplanes (XXX parameterize based on link?) */ |
| 423 | value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); |
| 424 | value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | |
| 425 | SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; |
| 426 | tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); |
| 427 | |
| 428 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); |
| 429 | value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; |
| 430 | value |= SOR_DP_LINKCTL_LANE_COUNT(4); |
| 431 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); |
| 432 | |
| 433 | /* start lane sequencer */ |
| 434 | value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | |
| 435 | SOR_LANE_SEQ_CTL_POWER_STATE_UP; |
| 436 | tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); |
| 437 | |
| 438 | while (true) { |
| 439 | value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); |
| 440 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) |
| 441 | break; |
| 442 | |
| 443 | usleep_range(250, 1000); |
| 444 | } |
| 445 | |
| 446 | /* set link bandwidth (2.7 GHz, XXX: parameterize based on link?) */ |
| 447 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
| 448 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; |
| 449 | value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; |
| 450 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
| 451 | |
| 452 | /* set linkctl */ |
| 453 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); |
| 454 | value |= SOR_DP_LINKCTL_ENABLE; |
| 455 | |
| 456 | value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; |
| 457 | value |= SOR_DP_LINKCTL_TU_SIZE(59); /* XXX: don't hardcode? */ |
| 458 | |
| 459 | value |= SOR_DP_LINKCTL_ENHANCED_FRAME; |
| 460 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); |
| 461 | |
| 462 | for (i = 0, value = 0; i < 4; i++) { |
| 463 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | |
| 464 | SOR_DP_TPG_SCRAMBLER_GALIOS | |
| 465 | SOR_DP_TPG_PATTERN_NONE; |
| 466 | value = (value << 8) | lane; |
| 467 | } |
| 468 | |
| 469 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
| 470 | |
| 471 | value = tegra_sor_readl(sor, SOR_DP_CONFIG_0); |
| 472 | value &= ~SOR_DP_CONFIG_WATERMARK_MASK; |
| 473 | value |= SOR_DP_CONFIG_WATERMARK(14); /* XXX: don't hardcode? */ |
| 474 | |
| 475 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; |
| 476 | value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(47); /* XXX: don't hardcode? */ |
| 477 | |
| 478 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; |
| 479 | value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(9); /* XXX: don't hardcode? */ |
| 480 | |
| 481 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; /* XXX: don't hardcode? */ |
| 482 | |
| 483 | value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; |
| 484 | value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; /* XXX: don't hardcode? */ |
| 485 | tegra_sor_writel(sor, value, SOR_DP_CONFIG_0); |
| 486 | |
| 487 | value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); |
| 488 | value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; |
| 489 | value |= 137; /* XXX: don't hardcode? */ |
| 490 | tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); |
| 491 | |
| 492 | value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); |
| 493 | value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; |
| 494 | value |= 2368; /* XXX: don't hardcode? */ |
| 495 | tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); |
| 496 | |
| 497 | /* enable pad calibration logic */ |
| 498 | value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); |
| 499 | value |= SOR_DP_PADCTL_PAD_CAL_PD; |
| 500 | tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); |
| 501 | |
| 502 | if (sor->dpaux) { |
| 503 | /* FIXME: properly convert to struct drm_dp_aux */ |
| 504 | struct drm_dp_aux *aux = (struct drm_dp_aux *)sor->dpaux; |
| 505 | struct drm_dp_link link; |
| 506 | u8 rate, lanes; |
| 507 | |
| 508 | err = drm_dp_link_probe(aux, &link); |
| 509 | if (err < 0) { |
| 510 | dev_err(sor->dev, "failed to probe eDP link: %d\n", |
| 511 | err); |
| 512 | return err; |
| 513 | } |
| 514 | |
| 515 | err = drm_dp_link_power_up(aux, &link); |
| 516 | if (err < 0) { |
| 517 | dev_err(sor->dev, "failed to power up eDP link: %d\n", |
| 518 | err); |
| 519 | return err; |
| 520 | } |
| 521 | |
| 522 | err = drm_dp_link_configure(aux, &link); |
| 523 | if (err < 0) { |
| 524 | dev_err(sor->dev, "failed to configure eDP link: %d\n", |
| 525 | err); |
| 526 | return err; |
| 527 | } |
| 528 | |
| 529 | rate = drm_dp_link_rate_to_bw_code(link.rate); |
| 530 | lanes = link.num_lanes; |
| 531 | |
| 532 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
| 533 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; |
| 534 | value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); |
| 535 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
| 536 | |
| 537 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); |
| 538 | value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; |
| 539 | value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); |
| 540 | |
| 541 | if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) |
| 542 | value |= SOR_DP_LINKCTL_ENHANCED_FRAME; |
| 543 | |
| 544 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); |
| 545 | |
| 546 | /* disable training pattern generator */ |
| 547 | |
| 548 | for (i = 0; i < link.num_lanes; i++) { |
| 549 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | |
| 550 | SOR_DP_TPG_SCRAMBLER_GALIOS | |
| 551 | SOR_DP_TPG_PATTERN_NONE; |
| 552 | value = (value << 8) | lane; |
| 553 | } |
| 554 | |
| 555 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
| 556 | |
| 557 | err = tegra_sor_dp_train_fast(sor, &link); |
| 558 | if (err < 0) { |
| 559 | dev_err(sor->dev, "DP fast link training failed: %d\n", |
| 560 | err); |
| 561 | return err; |
| 562 | } |
| 563 | |
| 564 | dev_dbg(sor->dev, "fast link training succeeded\n"); |
| 565 | } |
| 566 | |
| 567 | err = tegra_sor_power_up(sor, 250); |
| 568 | if (err < 0) { |
| 569 | dev_err(sor->dev, "failed to power up SOR: %d\n", err); |
| 570 | return err; |
| 571 | } |
| 572 | |
| 573 | /* start display controller in continuous mode */ |
| 574 | value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS); |
| 575 | value |= WRITE_MUX; |
| 576 | tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS); |
| 577 | |
| 578 | tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS); |
| 579 | tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND); |
| 580 | |
| 581 | value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS); |
| 582 | value &= ~WRITE_MUX; |
| 583 | tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS); |
| 584 | |
| 585 | /* |
| 586 | * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete |
| 587 | * raster, associate with display controller) |
| 588 | */ |
| 589 | value = SOR_STATE_ASY_PIXELDEPTH_BPP_24_444 | |
| 590 | SOR_STATE_ASY_VSYNCPOL | |
| 591 | SOR_STATE_ASY_HSYNCPOL | |
| 592 | SOR_STATE_ASY_PROTOCOL_DP_A | |
| 593 | SOR_STATE_ASY_CRC_MODE_COMPLETE | |
| 594 | SOR_STATE_ASY_OWNER(dc->pipe + 1); |
| 595 | tegra_sor_writel(sor, value, SOR_STATE_1); |
| 596 | |
| 597 | /* |
| 598 | * TODO: The video timing programming below doesn't seem to match the |
| 599 | * register definitions. |
| 600 | */ |
| 601 | |
| 602 | value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); |
| 603 | tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0)); |
| 604 | |
| 605 | vse = mode->vsync_end - mode->vsync_start - 1; |
| 606 | hse = mode->hsync_end - mode->hsync_start - 1; |
| 607 | |
| 608 | value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); |
| 609 | tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0)); |
| 610 | |
| 611 | vbe = vse + (mode->vsync_start - mode->vdisplay); |
| 612 | hbe = hse + (mode->hsync_start - mode->hdisplay); |
| 613 | |
| 614 | value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); |
| 615 | tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0)); |
| 616 | |
| 617 | vbs = vbe + mode->vdisplay; |
| 618 | hbs = hbe + mode->hdisplay; |
| 619 | |
| 620 | value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); |
| 621 | tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0)); |
| 622 | |
| 623 | /* XXX interlaced mode */ |
| 624 | tegra_sor_writel(sor, 0x00000001, SOR_HEAD_STATE_5(0)); |
| 625 | |
| 626 | /* CSTM (LVDS, link A/B, upper) */ |
| 627 | value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_B | SOR_CSTM_LINK_ACT_B | |
| 628 | SOR_CSTM_UPPER; |
| 629 | tegra_sor_writel(sor, value, SOR_CSTM); |
| 630 | |
| 631 | /* PWM setup */ |
| 632 | err = tegra_sor_setup_pwm(sor, 250); |
| 633 | if (err < 0) { |
| 634 | dev_err(sor->dev, "failed to setup PWM: %d\n", err); |
| 635 | return err; |
| 636 | } |
| 637 | |
| 638 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 639 | value |= SOR_ENABLE; |
| 640 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
| 641 | |
| 642 | tegra_sor_update(sor); |
| 643 | |
| 644 | err = tegra_sor_attach(sor); |
| 645 | if (err < 0) { |
| 646 | dev_err(sor->dev, "failed to attach SOR: %d\n", err); |
| 647 | return err; |
| 648 | } |
| 649 | |
| 650 | err = tegra_sor_wakeup(sor); |
| 651 | if (err < 0) { |
| 652 | dev_err(sor->dev, "failed to enable DC: %d\n", err); |
| 653 | return err; |
| 654 | } |
| 655 | |
| 656 | sor->enabled = true; |
| 657 | |
| 658 | return 0; |
| 659 | } |
| 660 | |
| 661 | static int tegra_sor_detach(struct tegra_sor *sor) |
| 662 | { |
| 663 | unsigned long value, timeout; |
| 664 | |
| 665 | /* switch to safe mode */ |
| 666 | value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); |
| 667 | value &= ~SOR_SUPER_STATE_MODE_NORMAL; |
| 668 | tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); |
| 669 | tegra_sor_super_update(sor); |
| 670 | |
| 671 | timeout = jiffies + msecs_to_jiffies(250); |
| 672 | |
| 673 | while (time_before(jiffies, timeout)) { |
| 674 | value = tegra_sor_readl(sor, SOR_PWR); |
| 675 | if (value & SOR_PWR_MODE_SAFE) |
| 676 | break; |
| 677 | } |
| 678 | |
| 679 | if ((value & SOR_PWR_MODE_SAFE) == 0) |
| 680 | return -ETIMEDOUT; |
| 681 | |
| 682 | /* go to sleep */ |
| 683 | value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); |
| 684 | value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; |
| 685 | tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); |
| 686 | tegra_sor_super_update(sor); |
| 687 | |
| 688 | /* detach */ |
| 689 | value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); |
| 690 | value &= ~SOR_SUPER_STATE_ATTACHED; |
| 691 | tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); |
| 692 | tegra_sor_super_update(sor); |
| 693 | |
| 694 | timeout = jiffies + msecs_to_jiffies(250); |
| 695 | |
| 696 | while (time_before(jiffies, timeout)) { |
| 697 | value = tegra_sor_readl(sor, SOR_TEST); |
| 698 | if ((value & SOR_TEST_ATTACHED) == 0) |
| 699 | break; |
| 700 | |
| 701 | usleep_range(25, 100); |
| 702 | } |
| 703 | |
| 704 | if ((value & SOR_TEST_ATTACHED) != 0) |
| 705 | return -ETIMEDOUT; |
| 706 | |
| 707 | return 0; |
| 708 | } |
| 709 | |
| 710 | static int tegra_sor_power_down(struct tegra_sor *sor) |
| 711 | { |
| 712 | unsigned long value, timeout; |
| 713 | int err; |
| 714 | |
| 715 | value = tegra_sor_readl(sor, SOR_PWR); |
| 716 | value &= ~SOR_PWR_NORMAL_STATE_PU; |
| 717 | value |= SOR_PWR_TRIGGER; |
| 718 | tegra_sor_writel(sor, value, SOR_PWR); |
| 719 | |
| 720 | timeout = jiffies + msecs_to_jiffies(250); |
| 721 | |
| 722 | while (time_before(jiffies, timeout)) { |
| 723 | value = tegra_sor_readl(sor, SOR_PWR); |
| 724 | if ((value & SOR_PWR_TRIGGER) == 0) |
| 725 | return 0; |
| 726 | |
| 727 | usleep_range(25, 100); |
| 728 | } |
| 729 | |
| 730 | if ((value & SOR_PWR_TRIGGER) != 0) |
| 731 | return -ETIMEDOUT; |
| 732 | |
| 733 | err = clk_set_parent(sor->clk, sor->clk_safe); |
| 734 | if (err < 0) |
| 735 | dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); |
| 736 | |
| 737 | value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); |
| 738 | value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | |
| 739 | SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); |
| 740 | tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); |
| 741 | |
| 742 | /* stop lane sequencer */ |
| 743 | value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | |
| 744 | SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; |
| 745 | tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); |
| 746 | |
| 747 | timeout = jiffies + msecs_to_jiffies(250); |
| 748 | |
| 749 | while (time_before(jiffies, timeout)) { |
| 750 | value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); |
| 751 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) |
| 752 | break; |
| 753 | |
| 754 | usleep_range(25, 100); |
| 755 | } |
| 756 | |
| 757 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) |
| 758 | return -ETIMEDOUT; |
| 759 | |
| 760 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 761 | value |= SOR_PLL_2_PORT_POWERDOWN; |
| 762 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 763 | |
| 764 | usleep_range(20, 100); |
| 765 | |
| 766 | value = tegra_sor_readl(sor, SOR_PLL_0); |
| 767 | value |= SOR_PLL_0_POWER_OFF; |
| 768 | value |= SOR_PLL_0_VCOPD; |
| 769 | tegra_sor_writel(sor, value, SOR_PLL_0); |
| 770 | |
| 771 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 772 | value |= SOR_PLL_2_SEQ_PLLCAPPD; |
| 773 | value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; |
| 774 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 775 | |
| 776 | usleep_range(20, 100); |
| 777 | |
| 778 | return 0; |
| 779 | } |
| 780 | |
| 781 | static int tegra_output_sor_disable(struct tegra_output *output) |
| 782 | { |
| 783 | struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); |
| 784 | struct tegra_sor *sor = to_sor(output); |
| 785 | unsigned long value; |
| 786 | int err; |
| 787 | |
| 788 | if (!sor->enabled) |
| 789 | return 0; |
| 790 | |
| 791 | err = tegra_sor_detach(sor); |
| 792 | if (err < 0) { |
| 793 | dev_err(sor->dev, "failed to detach SOR: %d\n", err); |
| 794 | return err; |
| 795 | } |
| 796 | |
| 797 | tegra_sor_writel(sor, 0, SOR_STATE_1); |
| 798 | tegra_sor_update(sor); |
| 799 | |
| 800 | /* |
| 801 | * The following accesses registers of the display controller, so make |
| 802 | * sure it's only executed when the output is attached to one. |
| 803 | */ |
| 804 | if (dc) { |
| 805 | /* |
| 806 | * XXX: We can't do this here because it causes the SOR to go |
| 807 | * into an erroneous state and the output will look scrambled |
| 808 | * the next time it is enabled. Presumably this is because we |
| 809 | * should be doing this only on the next VBLANK. A possible |
| 810 | * solution would be to queue a "power-off" event to trigger |
| 811 | * this code to be run during the next VBLANK. |
| 812 | */ |
| 813 | /* |
| 814 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); |
| 815 | value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | |
| 816 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); |
| 817 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); |
| 818 | */ |
| 819 | |
| 820 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); |
| 821 | value &= ~DISP_CTRL_MODE_MASK; |
| 822 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); |
| 823 | |
| 824 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 825 | value &= ~SOR_ENABLE; |
| 826 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
| 827 | |
| 828 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); |
| 829 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); |
| 830 | } |
| 831 | |
| 832 | err = tegra_sor_power_down(sor); |
| 833 | if (err < 0) { |
| 834 | dev_err(sor->dev, "failed to power down SOR: %d\n", err); |
| 835 | return err; |
| 836 | } |
| 837 | |
| 838 | if (sor->dpaux) { |
| 839 | err = tegra_dpaux_disable(sor->dpaux); |
| 840 | if (err < 0) { |
| 841 | dev_err(sor->dev, "failed to disable DP: %d\n", err); |
| 842 | return err; |
| 843 | } |
| 844 | } |
| 845 | |
| 846 | err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS); |
| 847 | if (err < 0) { |
| 848 | dev_err(sor->dev, "failed to power off I/O rail: %d\n", err); |
| 849 | return err; |
| 850 | } |
| 851 | |
| 852 | reset_control_assert(sor->rst); |
| 853 | clk_disable_unprepare(sor->clk); |
| 854 | |
| 855 | sor->enabled = false; |
| 856 | |
| 857 | return 0; |
| 858 | } |
| 859 | |
| 860 | static int tegra_output_sor_setup_clock(struct tegra_output *output, |
| 861 | struct clk *clk, unsigned long pclk) |
| 862 | { |
| 863 | struct tegra_sor *sor = to_sor(output); |
| 864 | int err; |
| 865 | |
| 866 | /* round to next MHz */ |
| 867 | pclk = DIV_ROUND_UP(pclk / 2, 1000000) * 1000000; |
| 868 | |
| 869 | err = clk_set_parent(clk, sor->clk_parent); |
| 870 | if (err < 0) { |
| 871 | dev_err(sor->dev, "failed to set parent clock: %d\n", err); |
| 872 | return err; |
| 873 | } |
| 874 | |
| 875 | err = clk_set_rate(sor->clk_parent, pclk); |
| 876 | if (err < 0) { |
| 877 | dev_err(sor->dev, "failed to set base clock rate to %lu Hz\n", |
| 878 | pclk * 2); |
| 879 | return err; |
| 880 | } |
| 881 | |
| 882 | return 0; |
| 883 | } |
| 884 | |
| 885 | static int tegra_output_sor_check_mode(struct tegra_output *output, |
| 886 | struct drm_display_mode *mode, |
| 887 | enum drm_mode_status *status) |
| 888 | { |
| 889 | /* |
| 890 | * FIXME: For now, always assume that the mode is okay. |
| 891 | */ |
| 892 | |
| 893 | *status = MODE_OK; |
| 894 | |
| 895 | return 0; |
| 896 | } |
| 897 | |
| 898 | static enum drm_connector_status |
| 899 | tegra_output_sor_detect(struct tegra_output *output) |
| 900 | { |
| 901 | struct tegra_sor *sor = to_sor(output); |
| 902 | |
| 903 | if (sor->dpaux) |
| 904 | return tegra_dpaux_detect(sor->dpaux); |
| 905 | |
| 906 | return connector_status_unknown; |
| 907 | } |
| 908 | |
| 909 | static const struct tegra_output_ops sor_ops = { |
| 910 | .enable = tegra_output_sor_enable, |
| 911 | .disable = tegra_output_sor_disable, |
| 912 | .setup_clock = tegra_output_sor_setup_clock, |
| 913 | .check_mode = tegra_output_sor_check_mode, |
| 914 | .detect = tegra_output_sor_detect, |
| 915 | }; |
| 916 | |
| 917 | static int tegra_sor_init(struct host1x_client *client) |
| 918 | { |
| 919 | struct tegra_drm *tegra = dev_get_drvdata(client->parent); |
| 920 | struct tegra_sor *sor = host1x_client_to_sor(client); |
| 921 | int err; |
| 922 | |
| 923 | if (!sor->dpaux) |
| 924 | return -ENODEV; |
| 925 | |
| 926 | sor->output.type = TEGRA_OUTPUT_EDP; |
| 927 | |
| 928 | sor->output.dev = sor->dev; |
| 929 | sor->output.ops = &sor_ops; |
| 930 | |
| 931 | err = tegra_output_init(tegra->drm, &sor->output); |
| 932 | if (err < 0) { |
| 933 | dev_err(sor->dev, "output setup failed: %d\n", err); |
| 934 | return err; |
| 935 | } |
| 936 | |
| 937 | if (sor->dpaux) { |
| 938 | err = tegra_dpaux_attach(sor->dpaux, &sor->output); |
| 939 | if (err < 0) { |
| 940 | dev_err(sor->dev, "failed to attach DP: %d\n", err); |
| 941 | return err; |
| 942 | } |
| 943 | } |
| 944 | |
| 945 | return 0; |
| 946 | } |
| 947 | |
| 948 | static int tegra_sor_exit(struct host1x_client *client) |
| 949 | { |
| 950 | struct tegra_sor *sor = host1x_client_to_sor(client); |
| 951 | int err; |
| 952 | |
| 953 | err = tegra_output_disable(&sor->output); |
| 954 | if (err < 0) { |
| 955 | dev_err(sor->dev, "output failed to disable: %d\n", err); |
| 956 | return err; |
| 957 | } |
| 958 | |
| 959 | if (sor->dpaux) { |
| 960 | err = tegra_dpaux_detach(sor->dpaux); |
| 961 | if (err < 0) { |
| 962 | dev_err(sor->dev, "failed to detach DP: %d\n", err); |
| 963 | return err; |
| 964 | } |
| 965 | } |
| 966 | |
| 967 | err = tegra_output_exit(&sor->output); |
| 968 | if (err < 0) { |
| 969 | dev_err(sor->dev, "output cleanup failed: %d\n", err); |
| 970 | return err; |
| 971 | } |
| 972 | |
| 973 | return 0; |
| 974 | } |
| 975 | |
| 976 | static const struct host1x_client_ops sor_client_ops = { |
| 977 | .init = tegra_sor_init, |
| 978 | .exit = tegra_sor_exit, |
| 979 | }; |
| 980 | |
| 981 | static int tegra_sor_probe(struct platform_device *pdev) |
| 982 | { |
| 983 | struct device_node *np; |
| 984 | struct tegra_sor *sor; |
| 985 | struct resource *regs; |
| 986 | int err; |
| 987 | |
| 988 | sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); |
| 989 | if (!sor) |
| 990 | return -ENOMEM; |
| 991 | |
| 992 | sor->output.dev = sor->dev = &pdev->dev; |
| 993 | |
| 994 | np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); |
| 995 | if (np) { |
| 996 | sor->dpaux = tegra_dpaux_find_by_of_node(np); |
| 997 | of_node_put(np); |
| 998 | |
| 999 | if (!sor->dpaux) |
| 1000 | return -EPROBE_DEFER; |
| 1001 | } |
| 1002 | |
| 1003 | err = tegra_output_probe(&sor->output); |
| 1004 | if (err < 0) |
| 1005 | return err; |
| 1006 | |
| 1007 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1008 | sor->regs = devm_ioremap_resource(&pdev->dev, regs); |
| 1009 | if (IS_ERR(sor->regs)) |
| 1010 | return PTR_ERR(sor->regs); |
| 1011 | |
| 1012 | sor->rst = devm_reset_control_get(&pdev->dev, "sor"); |
| 1013 | if (IS_ERR(sor->rst)) |
| 1014 | return PTR_ERR(sor->rst); |
| 1015 | |
| 1016 | sor->clk = devm_clk_get(&pdev->dev, NULL); |
| 1017 | if (IS_ERR(sor->clk)) |
| 1018 | return PTR_ERR(sor->clk); |
| 1019 | |
| 1020 | sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); |
| 1021 | if (IS_ERR(sor->clk_parent)) |
| 1022 | return PTR_ERR(sor->clk_parent); |
| 1023 | |
| 1024 | err = clk_prepare_enable(sor->clk_parent); |
| 1025 | if (err < 0) |
| 1026 | return err; |
| 1027 | |
| 1028 | sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); |
| 1029 | if (IS_ERR(sor->clk_safe)) |
| 1030 | return PTR_ERR(sor->clk_safe); |
| 1031 | |
| 1032 | err = clk_prepare_enable(sor->clk_safe); |
| 1033 | if (err < 0) |
| 1034 | return err; |
| 1035 | |
| 1036 | sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); |
| 1037 | if (IS_ERR(sor->clk_dp)) |
| 1038 | return PTR_ERR(sor->clk_dp); |
| 1039 | |
| 1040 | err = clk_prepare_enable(sor->clk_dp); |
| 1041 | if (err < 0) |
| 1042 | return err; |
| 1043 | |
| 1044 | INIT_LIST_HEAD(&sor->client.list); |
| 1045 | sor->client.ops = &sor_client_ops; |
| 1046 | sor->client.dev = &pdev->dev; |
| 1047 | |
| 1048 | err = host1x_client_register(&sor->client); |
| 1049 | if (err < 0) { |
| 1050 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", |
| 1051 | err); |
| 1052 | return err; |
| 1053 | } |
| 1054 | |
| 1055 | platform_set_drvdata(pdev, sor); |
| 1056 | |
| 1057 | return 0; |
| 1058 | } |
| 1059 | |
| 1060 | static int tegra_sor_remove(struct platform_device *pdev) |
| 1061 | { |
| 1062 | struct tegra_sor *sor = platform_get_drvdata(pdev); |
| 1063 | int err; |
| 1064 | |
| 1065 | err = host1x_client_unregister(&sor->client); |
| 1066 | if (err < 0) { |
| 1067 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", |
| 1068 | err); |
| 1069 | return err; |
| 1070 | } |
| 1071 | |
| 1072 | clk_disable_unprepare(sor->clk_parent); |
| 1073 | clk_disable_unprepare(sor->clk_safe); |
| 1074 | clk_disable_unprepare(sor->clk_dp); |
| 1075 | clk_disable_unprepare(sor->clk); |
| 1076 | |
| 1077 | return 0; |
| 1078 | } |
| 1079 | |
| 1080 | static const struct of_device_id tegra_sor_of_match[] = { |
| 1081 | { .compatible = "nvidia,tegra124-sor", }, |
| 1082 | { }, |
| 1083 | }; |
| 1084 | |
| 1085 | struct platform_driver tegra_sor_driver = { |
| 1086 | .driver = { |
| 1087 | .name = "tegra-sor", |
| 1088 | .of_match_table = tegra_sor_of_match, |
| 1089 | }, |
| 1090 | .probe = tegra_sor_probe, |
| 1091 | .remove = tegra_sor_remove, |
| 1092 | }; |