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gerrit-public.fairphone.software / kernel / msm-4.9 / 6b7bc0618ff1a333d2265131b124e966335d5dee / . / drivers / pinctrl / sirf / pinctrl-atlas7.c
blob: 9df0c5f25824a2cbac9d3284f27a688345e83687 [file] [log] [blame]
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]1/*
2 * pinctrl pads, groups, functions for CSR SiRFatlasVII
3 *
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
5 * company.
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/io.h>
13#include <linux/bitops.h>
14#include <linux/irq.h>
15#include <linux/slab.h>
16#include <linux/clk.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_device.h>
20#include <linux/of_platform.h>
21#include <linux/of_irq.h>
22#include <linux/of_gpio.h>
23#include <linux/pinctrl/machine.h>
24#include <linux/pinctrl/pinconf.h>
25#include <linux/pinctrl/pinctrl.h>
26#include <linux/pinctrl/pinmux.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/pinctrl/pinconf-generic.h>
29#include <linux/gpio.h>
30
31/* Definition of Pad&Mux Properties */
32#define N 0
33
34/* The Bank contains input-disable regisgers */
35#define BANK_DS 0
36
37/* Clear Register offset */
38#define CLR_REG(r) ((r) + 0x04)
39
40/* Definition of multiple function select register */
41#define FUNC_CLEAR_MASK 0x7
42#define FUNC_GPIO 0
43#define FUNC_ANALOGUE 0x8
44#define ANA_CLEAR_MASK 0x1
45
46/* The Atlas7's Pad Type List */
47enum altas7_pad_type {
48 PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */
49 PAD_T_4WE_PU, /* ZIO_PAD3V_4WE_PD */
50 PAD_T_16ST, /* ZIO_PAD3V_SDCLK_PD */
51 PAD_T_M31_0204_PD, /* PRDW0204SDGZ_M311311_PD */
52 PAD_T_M31_0204_PU, /* PRDW0204SDGZ_M311311_PU */
53 PAD_T_M31_0610_PD, /* PRUW0610SDGZ_M311311_PD */
54 PAD_T_M31_0610_PU, /* PRUW0610SDGZ_M311311_PU */
55 PAD_T_AD, /* PRDWUWHW08SCDG_HZ */
56};
57
58/* Raw value of Driver-Strength Bits */
59#define DS3 BIT(3)
60#define DS2 BIT(2)
61#define DS1 BIT(1)
62#define DS0 BIT(0)
63#define DSZ 0
64
65/* Drive-Strength Intermediate Values */
66#define DS_NULL -1
67#define DS_1BIT_IM_VAL DS0
68#define DS_1BIT_MASK 0x1
69#define DS_2BIT_IM_VAL (DS1 | DS0)
70#define DS_2BIT_MASK 0x3
71#define DS_4BIT_IM_VAL (DS3 | DS2 | DS1 | DS0)
72#define DS_4BIT_MASK 0xf
73
74/* The Drive-Strength of 4WE Pad DS1 0 CO */
75#define DS_4WE_3 (DS1 | DS0) /* 1 1 3 */
76#define DS_4WE_2 (DS1) /* 1 0 2 */
77#define DS_4WE_1 (DS0) /* 0 1 1 */
78#define DS_4WE_0 (DSZ) /* 0 0 0 */
79
80/* The Drive-Strength of 16st Pad DS3 2 1 0 CO */
81#define DS_16ST_15 (DS3 | DS2 | DS1 | DS0) /* 1 1 1 1 15 */
82#define DS_16ST_14 (DS3 | DS2 | DS0) /* 1 1 0 1 13 */
83#define DS_16ST_13 (DS3 | DS2 | DS1) /* 1 1 1 0 14 */
84#define DS_16ST_12 (DS2 | DS1 | DS0) /* 0 1 1 1 7 */
85#define DS_16ST_11 (DS2 | DS0) /* 0 1 0 1 5 */
86#define DS_16ST_10 (DS3 | DS1 | DS0) /* 1 0 1 1 11 */
87#define DS_16ST_9 (DS3 | DS0) /* 1 0 0 1 9 */
88#define DS_16ST_8 (DS1 | DS0) /* 0 0 1 1 3 */
89#define DS_16ST_7 (DS2 | DS1) /* 0 1 1 0 6 */
90#define DS_16ST_6 (DS3 | DS2) /* 1 1 0 0 12 */
91#define DS_16ST_5 (DS2) /* 0 1 0 0 4 */
92#define DS_16ST_4 (DS3 | DS1) /* 1 0 1 0 10 */
93#define DS_16ST_3 (DS1) /* 0 0 1 0 2 */
94#define DS_16ST_2 (DS0) /* 0 0 0 1 1 */
95#define DS_16ST_1 (DSZ) /* 0 0 0 0 0 */
96#define DS_16ST_0 (DS3) /* 1 0 0 0 8 */
97
98/* The Drive-Strength of M31 Pad DS0 CO */
99#define DS_M31_0 (DSZ) /* 0 0 */
100#define DS_M31_1 (DS0) /* 1 1 */
101
102/* Raw values of Pull Option Bits */
103#define PUN BIT(1)
104#define PD BIT(0)
105#define PE BIT(0)
106#define PZ 0
107
108/* Definition of Pull Types */
109#define PULL_UP 0
110#define HIGH_HYSTERESIS 1
111#define HIGH_Z 2
112#define PULL_DOWN 3
113#define PULL_DISABLE 4
114#define PULL_ENABLE 5
115#define PULL_UNKNOWN -1
116
117/* Pull Options for 4WE Pad PUN PD CO */
118#define P4WE_PULL_MASK 0x3
119#define P4WE_PULL_DOWN (PUN | PD) /* 1 1 3 */
120#define P4WE_HIGH_Z (PUN) /* 1 0 2 */
121#define P4WE_HIGH_HYSTERESIS (PD) /* 0 1 1 */
122#define P4WE_PULL_UP (PZ) /* 0 0 0 */
123
124/* Pull Options for 16ST Pad PUN PD CO */
125#define P16ST_PULL_MASK 0x3
126#define P16ST_PULL_DOWN (PUN | PD) /* 1 1 3 */
127#define P16ST_HIGH_Z (PUN) /* 1 0 2 */
128#define P16ST_PULL_UP (PZ) /* 0 0 0 */
129
130/* Pull Options for M31 Pad PE */
131#define PM31_PULL_MASK 0x1
132#define PM31_PULL_ENABLED (PE) /* 1 */
133#define PM31_PULL_DISABLED (PZ) /* 0 */
134
135/* Pull Options for A/D Pad PUN PD CO */
136#define PANGD_PULL_MASK 0x3
137#define PANGD_PULL_DOWN (PUN | PD) /* 1 1 3 */
138#define PANGD_HIGH_Z (PUN) /* 1 0 2 */
139#define PANGD_PULL_UP (PZ) /* 0 0 0 */
140
141/* Definition of Input Disable */
142#define DI_MASK 0x1
143#define DI_DISABLE 0x1
144#define DI_ENABLE 0x0
145
146/* Definition of Input Disable Value */
147#define DIV_MASK 0x1
148#define DIV_DISABLE 0x1
149#define DIV_ENABLE 0x0
150
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]151/* Number of Function input disable registers */
152#define NUM_OF_IN_DISABLE_REG 0x2
153
154/* Offset of Function input disable registers */
155#define IN_DISABLE_0_REG_SET 0x0A00
156#define IN_DISABLE_0_REG_CLR 0x0A04
157#define IN_DISABLE_1_REG_SET 0x0A08
158#define IN_DISABLE_1_REG_CLR 0x0A0C
159#define IN_DISABLE_VAL_0_REG_SET 0x0A80
160#define IN_DISABLE_VAL_0_REG_CLR 0x0A84
161#define IN_DISABLE_VAL_1_REG_SET 0x0A88
162#define IN_DISABLE_VAL_1_REG_CLR 0x0A8C
163
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]164struct dt_params {
165 const char *property;
166 int value;
167};
168
169/**
170 * struct atlas7_pad_conf - Atlas7 Pad Configuration
171 * @id The ID of this Pad.
172 * @type: The type of this Pad.
173 * @mux_reg: The mux register offset.
174 * This register contains the mux.
175 * @pupd_reg: The pull-up/down register offset.
176 * @drvstr_reg: The drive-strength register offset.
177 * @ad_ctrl_reg: The Analogue/Digital Control register.
178 *
179 * @mux_bit: The start bit of mux register.
180 * @pupd_bit: The start bit of pull-up/down register.
181 * @drvstr_bit: The start bit of drive-strength register.
182 * @ad_ctrl_bit: The start bit of analogue/digital register.
183 */
184struct atlas7_pad_config {
185 const u32 id;
186 u32 type;
187 u32 mux_reg;
188 u32 pupd_reg;
189 u32 drvstr_reg;
190 u32 ad_ctrl_reg;
191 /* bits in register */
192 u8 mux_bit;
193 u8 pupd_bit;
194 u8 drvstr_bit;
195 u8 ad_ctrl_bit;
196};
197
198#define PADCONF(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb) \
199 { \
200 .id = pad, \
201 .type = t, \
202 .mux_reg = mr, \
203 .pupd_reg = pr, \
204 .drvstr_reg = dsr, \
205 .ad_ctrl_reg = adr, \
206 .mux_bit = mb, \
207 .pupd_bit = pb, \
208 .drvstr_bit = dsb, \
209 .ad_ctrl_bit = adb, \
210 }
211
212/**
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]213 * struct atlas7_pad_status - Atlas7 Pad status
214 */
215struct atlas7_pad_status {
216 u8 func;
217 u8 pull;
218 u8 dstr;
219 u8 reserved;
220};
221
222/**
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]223 * struct atlas7_pad_mux - Atlas7 mux
224 * @bank: The bank of this pad's registers on.
225 * @pin : The ID of this Pad.
226 * @func: The mux func on this Pad.
227 * @dinput_reg: The Input-Disable register offset.
228 * @dinput_bit: The start bit of Input-Disable register.
229 * @dinput_val_reg: The Input-Disable-value register offset.
230 * This register is used to set the value of this pad
231 * if this pad was disabled.
232 * @dinput_val_bit: The start bit of Input-Disable Value register.
233 */
234struct atlas7_pad_mux {
235 u32 bank;
236 u32 pin;
237 u32 func;
238 u32 dinput_reg;
239 u32 dinput_bit;
240 u32 dinput_val_reg;
241 u32 dinput_val_bit;
242};
243
244#define MUX(b, pad, f, dr, db, dvr, dvb) \
245 { \
246 .bank = b, \
247 .pin = pad, \
248 .func = f, \
249 .dinput_reg = dr, \
250 .dinput_bit = db, \
251 .dinput_val_reg = dvr, \
252 .dinput_val_bit = dvb, \
253 }
254
255struct atlas7_grp_mux {
256 unsigned int group;
257 unsigned int pad_mux_count;
258 const struct atlas7_pad_mux *pad_mux_list;
259};
260
261 /**
262 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
263 * @name: the name of this specific pin group
264 * @pins: an array of discrete physical pins used in this group, taken
265 * from the driver-local pin enumeration space
266 * @num_pins: the number of pins in this group array, i.e. the number of
267 * elements in .pins so we can iterate over that array
268 */
269struct atlas7_pin_group {
270 const char *name;
271 const unsigned int *pins;
272 const unsigned num_pins;
273};
274
275#define GROUP(n, p) \
276 { \
277 .name = n, \
278 .pins = p, \
279 .num_pins = ARRAY_SIZE(p), \
280 }
281
282struct atlas7_pmx_func {
283 const char *name;
284 const char * const *groups;
285 const unsigned num_groups;
286 const struct atlas7_grp_mux *grpmux;
287};
288
289#define FUNCTION(n, g, m) \
290 { \
291 .name = n, \
292 .groups = g, \
293 .num_groups = ARRAY_SIZE(g), \
294 .grpmux = m, \
295 }
296
297struct atlas7_pinctrl_data {
298 struct pinctrl_pin_desc *pads;
299 int pads_cnt;
300 struct atlas7_pin_group *grps;
301 int grps_cnt;
302 struct atlas7_pmx_func *funcs;
303 int funcs_cnt;
304 struct atlas7_pad_config *confs;
305 int confs_cnt;
306};
307
308/* Platform info of atlas7 pinctrl */
309#define ATLAS7_PINCTRL_REG_BANKS 2
310#define ATLAS7_PINCTRL_BANK_0_PINS 18
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]311#define ATLAS7_PINCTRL_BANK_1_PINS 141
312#define ATLAS7_PINCTRL_TOTAL_PINS \
313 (ATLAS7_PINCTRL_BANK_0_PINS + ATLAS7_PINCTRL_BANK_1_PINS)
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]314
315/**
316 * Atlas7 GPIO Chip
317 */
318
319#define NGPIO_OF_BANK 32
320#define GPIO_TO_BANK(gpio) ((gpio) / NGPIO_OF_BANK)
321
322/* Registers of GPIO Controllers */
323#define ATLAS7_GPIO_BASE(g, b) ((g)->reg + 0x100 * (b))
324#define ATLAS7_GPIO_CTRL(b, i) ((b)->base + 4 * (i))
325#define ATLAS7_GPIO_INT_STATUS(b) ((b)->base + 0x8C)
326
327/* Definition bits of GPIO Control Registers */
328#define ATLAS7_GPIO_CTL_INTR_LOW_MASK BIT(0)
329#define ATLAS7_GPIO_CTL_INTR_HIGH_MASK BIT(1)
330#define ATLAS7_GPIO_CTL_INTR_TYPE_MASK BIT(2)
331#define ATLAS7_GPIO_CTL_INTR_EN_MASK BIT(3)
332#define ATLAS7_GPIO_CTL_INTR_STATUS_MASK BIT(4)
333#define ATLAS7_GPIO_CTL_OUT_EN_MASK BIT(5)
334#define ATLAS7_GPIO_CTL_DATAOUT_MASK BIT(6)
335#define ATLAS7_GPIO_CTL_DATAIN_MASK BIT(7)
336
337struct atlas7_gpio_bank {
338 struct pinctrl_dev *pctldev;
339 int id;
340 int irq;
341 void __iomem *base;
342 unsigned int gpio_offset;
343 unsigned int ngpio;
344 const unsigned int *gpio_pins;
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]345 u32 sleep_data[NGPIO_OF_BANK];
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]346};
347
348struct atlas7_gpio_chip {
349 const char *name;
350 void __iomem *reg;
351 struct clk *clk;
352 int nbank;
353 spinlock_t lock;
354 struct gpio_chip chip;
355 struct atlas7_gpio_bank banks[0];
356};
357
358static inline struct atlas7_gpio_chip *to_atlas7_gpio(struct gpio_chip *gc)
359{
360 return container_of(gc, struct atlas7_gpio_chip, chip);
361}
362
363/**
364 * @dev: a pointer back to containing device
365 * @virtbase: the offset to the controller in virtual memory
366 */
367struct atlas7_pmx {
368 struct device *dev;
369 struct pinctrl_dev *pctl;
370 struct pinctrl_desc pctl_desc;
371 struct atlas7_pinctrl_data *pctl_data;
372 void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS];
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]373 u32 status_ds[NUM_OF_IN_DISABLE_REG];
374 u32 status_dsv[NUM_OF_IN_DISABLE_REG];
375 struct atlas7_pad_status sleep_data[ATLAS7_PINCTRL_TOTAL_PINS];
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]376};
377
378/*
379 * Pad list for the pinmux subsystem
380 * refer to A7DA IO Summary - CS-314158-DD-4E.xls
381 */
382
383/*Pads in IOC RTC & TOP */
384static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
385 /* RTC PADs */
386 PINCTRL_PIN(0, "rtc_gpio_0"),
387 PINCTRL_PIN(1, "rtc_gpio_1"),
388 PINCTRL_PIN(2, "rtc_gpio_2"),
389 PINCTRL_PIN(3, "rtc_gpio_3"),
390 PINCTRL_PIN(4, "low_bat_ind_b"),
391 PINCTRL_PIN(5, "on_key_b"),
392 PINCTRL_PIN(6, "ext_on"),
393 PINCTRL_PIN(7, "mem_on"),
394 PINCTRL_PIN(8, "core_on"),
395 PINCTRL_PIN(9, "io_on"),
396 PINCTRL_PIN(10, "can0_tx"),
397 PINCTRL_PIN(11, "can0_rx"),
398 PINCTRL_PIN(12, "spi0_clk"),
399 PINCTRL_PIN(13, "spi0_cs_b"),
400 PINCTRL_PIN(14, "spi0_io_0"),
401 PINCTRL_PIN(15, "spi0_io_1"),
402 PINCTRL_PIN(16, "spi0_io_2"),
403 PINCTRL_PIN(17, "spi0_io_3"),
404
405 /* TOP PADs */
406 PINCTRL_PIN(18, "spi1_en"),
407 PINCTRL_PIN(19, "spi1_clk"),
408 PINCTRL_PIN(20, "spi1_din"),
409 PINCTRL_PIN(21, "spi1_dout"),
410 PINCTRL_PIN(22, "trg_spi_clk"),
411 PINCTRL_PIN(23, "trg_spi_di"),
412 PINCTRL_PIN(24, "trg_spi_do"),
413 PINCTRL_PIN(25, "trg_spi_cs_b"),
414 PINCTRL_PIN(26, "trg_acq_d1"),
415 PINCTRL_PIN(27, "trg_irq_b"),
416 PINCTRL_PIN(28, "trg_acq_d0"),
417 PINCTRL_PIN(29, "trg_acq_clk"),
418 PINCTRL_PIN(30, "trg_shutdown_b_out"),
419 PINCTRL_PIN(31, "sdio2_clk"),
420 PINCTRL_PIN(32, "sdio2_cmd"),
421 PINCTRL_PIN(33, "sdio2_dat_0"),
422 PINCTRL_PIN(34, "sdio2_dat_1"),
423 PINCTRL_PIN(35, "sdio2_dat_2"),
424 PINCTRL_PIN(36, "sdio2_dat_3"),
425 PINCTRL_PIN(37, "df_ad_7"),
426 PINCTRL_PIN(38, "df_ad_6"),
427 PINCTRL_PIN(39, "df_ad_5"),
428 PINCTRL_PIN(40, "df_ad_4"),
429 PINCTRL_PIN(41, "df_ad_3"),
430 PINCTRL_PIN(42, "df_ad_2"),
431 PINCTRL_PIN(43, "df_ad_1"),
432 PINCTRL_PIN(44, "df_ad_0"),
433 PINCTRL_PIN(45, "df_dqs"),
434 PINCTRL_PIN(46, "df_cle"),
435 PINCTRL_PIN(47, "df_ale"),
436 PINCTRL_PIN(48, "df_we_b"),
437 PINCTRL_PIN(49, "df_re_b"),
438 PINCTRL_PIN(50, "df_ry_by"),
439 PINCTRL_PIN(51, "df_cs_b_1"),
440 PINCTRL_PIN(52, "df_cs_b_0"),
441 PINCTRL_PIN(53, "l_pclk"),
442 PINCTRL_PIN(54, "l_lck"),
443 PINCTRL_PIN(55, "l_fck"),
444 PINCTRL_PIN(56, "l_de"),
445 PINCTRL_PIN(57, "ldd_0"),
446 PINCTRL_PIN(58, "ldd_1"),
447 PINCTRL_PIN(59, "ldd_2"),
448 PINCTRL_PIN(60, "ldd_3"),
449 PINCTRL_PIN(61, "ldd_4"),
450 PINCTRL_PIN(62, "ldd_5"),
451 PINCTRL_PIN(63, "ldd_6"),
452 PINCTRL_PIN(64, "ldd_7"),
453 PINCTRL_PIN(65, "ldd_8"),
454 PINCTRL_PIN(66, "ldd_9"),
455 PINCTRL_PIN(67, "ldd_10"),
456 PINCTRL_PIN(68, "ldd_11"),
457 PINCTRL_PIN(69, "ldd_12"),
458 PINCTRL_PIN(70, "ldd_13"),
459 PINCTRL_PIN(71, "ldd_14"),
460 PINCTRL_PIN(72, "ldd_15"),
461 PINCTRL_PIN(73, "lcd_gpio_20"),
462 PINCTRL_PIN(74, "vip_0"),
463 PINCTRL_PIN(75, "vip_1"),
464 PINCTRL_PIN(76, "vip_2"),
465 PINCTRL_PIN(77, "vip_3"),
466 PINCTRL_PIN(78, "vip_4"),
467 PINCTRL_PIN(79, "vip_5"),
468 PINCTRL_PIN(80, "vip_6"),
469 PINCTRL_PIN(81, "vip_7"),
470 PINCTRL_PIN(82, "vip_pxclk"),
471 PINCTRL_PIN(83, "vip_hsync"),
472 PINCTRL_PIN(84, "vip_vsync"),
473 PINCTRL_PIN(85, "sdio3_clk"),
474 PINCTRL_PIN(86, "sdio3_cmd"),
475 PINCTRL_PIN(87, "sdio3_dat_0"),
476 PINCTRL_PIN(88, "sdio3_dat_1"),
477 PINCTRL_PIN(89, "sdio3_dat_2"),
478 PINCTRL_PIN(90, "sdio3_dat_3"),
479 PINCTRL_PIN(91, "sdio5_clk"),
480 PINCTRL_PIN(92, "sdio5_cmd"),
481 PINCTRL_PIN(93, "sdio5_dat_0"),
482 PINCTRL_PIN(94, "sdio5_dat_1"),
483 PINCTRL_PIN(95, "sdio5_dat_2"),
484 PINCTRL_PIN(96, "sdio5_dat_3"),
485 PINCTRL_PIN(97, "rgmii_txd_0"),
486 PINCTRL_PIN(98, "rgmii_txd_1"),
487 PINCTRL_PIN(99, "rgmii_txd_2"),
488 PINCTRL_PIN(100, "rgmii_txd_3"),
489 PINCTRL_PIN(101, "rgmii_txclk"),
490 PINCTRL_PIN(102, "rgmii_tx_ctl"),
491 PINCTRL_PIN(103, "rgmii_rxd_0"),
492 PINCTRL_PIN(104, "rgmii_rxd_1"),
493 PINCTRL_PIN(105, "rgmii_rxd_2"),
494 PINCTRL_PIN(106, "rgmii_rxd_3"),
495 PINCTRL_PIN(107, "rgmii_rx_clk"),
496 PINCTRL_PIN(108, "rgmii_rxc_ctl"),
497 PINCTRL_PIN(109, "rgmii_mdio"),
498 PINCTRL_PIN(110, "rgmii_mdc"),
499 PINCTRL_PIN(111, "rgmii_intr_n"),
500 PINCTRL_PIN(112, "i2s_mclk"),
501 PINCTRL_PIN(113, "i2s_bclk"),
502 PINCTRL_PIN(114, "i2s_ws"),
503 PINCTRL_PIN(115, "i2s_dout0"),
504 PINCTRL_PIN(116, "i2s_dout1"),
505 PINCTRL_PIN(117, "i2s_dout2"),
506 PINCTRL_PIN(118, "i2s_din"),
507 PINCTRL_PIN(119, "gpio_0"),
508 PINCTRL_PIN(120, "gpio_1"),
509 PINCTRL_PIN(121, "gpio_2"),
510 PINCTRL_PIN(122, "gpio_3"),
511 PINCTRL_PIN(123, "gpio_4"),
512 PINCTRL_PIN(124, "gpio_5"),
513 PINCTRL_PIN(125, "gpio_6"),
514 PINCTRL_PIN(126, "gpio_7"),
515 PINCTRL_PIN(127, "sda_0"),
516 PINCTRL_PIN(128, "scl_0"),
517 PINCTRL_PIN(129, "coex_pio_0"),
518 PINCTRL_PIN(130, "coex_pio_1"),
519 PINCTRL_PIN(131, "coex_pio_2"),
520 PINCTRL_PIN(132, "coex_pio_3"),
521 PINCTRL_PIN(133, "uart0_tx"),
522 PINCTRL_PIN(134, "uart0_rx"),
523 PINCTRL_PIN(135, "uart1_tx"),
524 PINCTRL_PIN(136, "uart1_rx"),
525 PINCTRL_PIN(137, "uart3_tx"),
526 PINCTRL_PIN(138, "uart3_rx"),
527 PINCTRL_PIN(139, "uart4_tx"),
528 PINCTRL_PIN(140, "uart4_rx"),
529 PINCTRL_PIN(141, "usp0_clk"),
530 PINCTRL_PIN(142, "usp0_tx"),
531 PINCTRL_PIN(143, "usp0_rx"),
532 PINCTRL_PIN(144, "usp0_fs"),
533 PINCTRL_PIN(145, "usp1_clk"),
534 PINCTRL_PIN(146, "usp1_tx"),
535 PINCTRL_PIN(147, "usp1_rx"),
536 PINCTRL_PIN(148, "usp1_fs"),
537 PINCTRL_PIN(149, "lvds_tx0d4p"),
538 PINCTRL_PIN(150, "lvds_tx0d4n"),
539 PINCTRL_PIN(151, "lvds_tx0d3p"),
540 PINCTRL_PIN(152, "lvds_tx0d3n"),
541 PINCTRL_PIN(153, "lvds_tx0d2p"),
542 PINCTRL_PIN(154, "lvds_tx0d2n"),
543 PINCTRL_PIN(155, "lvds_tx0d1p"),
544 PINCTRL_PIN(156, "lvds_tx0d1n"),
545 PINCTRL_PIN(157, "lvds_tx0d0p"),
546 PINCTRL_PIN(158, "lvds_tx0d0n"),
547};
548
549struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
550 /* The Configuration of IOC_RTC Pads */
551 PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
552 PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
553 PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0),
554 PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0),
555 PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0),
556 PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0),
557 PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0),
558 PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0),
559 PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0),
560 PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0),
561 PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0),
562 PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0),
563 PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0),
564 PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0),
565 PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0),
566 PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0),
567 PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0),
568 PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0),
569 /* The Configuration of IOC_TOP Pads */
570 PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0),
571 PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0),
572 PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0),
573 PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0),
574 PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0),
575 PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0),
576 PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0),
577 PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0),
578 PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0),
579 PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0),
580 PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0),
581 PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0),
582 PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0),
583 PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0),
584 PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0),
585 PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0),
586 PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0),
587 PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0),
588 PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0),
589 PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0),
590 PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0),
591 PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0),
592 PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0),
593 PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0),
594 PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0),
595 PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0),
596 PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0),
597 PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0),
598 PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0),
599 PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0),
600 PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0),
601 PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0),
602 PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0),
603 PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0),
604 PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0),
605 PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0),
606 PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0),
607 PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0),
608 PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0),
609 PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0),
610 PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0),
611 PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0),
612 PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0),
613 PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0),
614 PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0),
615 PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0),
616 PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0),
617 PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0),
618 PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0),
619 PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0),
620 PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0),
621 PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0),
622 PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0),
623 PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0),
624 PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0),
625 PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0),
626 PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0),
627 PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0),
628 PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0),
629 PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0),
630 PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0),
631 PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0),
632 PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0),
633 PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0),
634 PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0),
635 PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0),
636 PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0),
637 PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0),
638 PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0),
639 PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0),
640 PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0),
641 PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0),
642 PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0),
643 PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0),
644 PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0),
645 PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0),
646 PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0),
647 PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0),
648 PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0),
649 PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0),
650 PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0),
651 PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0),
652 PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0),
653 PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0),
654 PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0),
655 PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0),
656 PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0),
657 PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0),
658 PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0),
659 PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0),
660 PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0),
661 PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0),
662 PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0),
663 PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0),
664 PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0),
665 PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0),
666 PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0),
667 PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0),
668 PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0),
669 PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0),
670 PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0),
671 PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0),
672 PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0),
673 PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0),
674 PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0),
675 PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0),
676 PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0),
677 PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0),
678 PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0),
679 PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0),
680 PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0),
681 PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0),
682 PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0),
683 PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0),
684 PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0),
685 PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0),
686 PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0),
687 PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0),
688 PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0),
689 PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0),
690 PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0),
691 PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0),
692 PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0),
693 PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0),
694 PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0),
695 PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0),
696 PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0),
697 PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0),
698 PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0),
699 PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0),
700 PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0),
701 PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0),
702 PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1),
703 PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2),
704 PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3),
705 PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4),
706 PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5),
707 PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6),
708 PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7),
709 PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8),
710 PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9),
711};
712
713/* pin list of each pin group */
714static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124,
715 125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, };
716static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80,
717 81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
718 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, };
719static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36,
720 85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94,
721 95, 96, 112, 113, 114, 115, 116, 117, 118, };
722static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102,
723 103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21,
724 141, 142, 143, 144, 145, 146, 147, 148, };
725static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154,
726 151, 152, 149, 150, };
727static const unsigned int uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40, 39,
728 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135, 136,
729 137, 138, 139, 140, };
730static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13,
731 14, 15, 16, 17, };
732static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, };
733static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41,
734 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118,
735 115, 49, 50, 142, 143, 80, };
736static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113,
737 114, };
738static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, };
739static const unsigned int audio_i2s_extclk_pins[] = { 112, };
740static const unsigned int audio_uart0_pins[] = { 143, 142, 141, 144, };
741static const unsigned int audio_uart1_pins[] = { 147, 146, 145, 148, };
742static const unsigned int audio_uart2_pins0[] = { 20, 21, 19, 18, };
743static const unsigned int audio_uart2_pins1[] = { 109, 110, 101, 111, };
744static const unsigned int c_can_trnsvr_pins[] = { 1, };
745static const unsigned int c0_can_pins0[] = { 11, 10, };
746static const unsigned int c0_can_pins1[] = { 2, 3, };
747static const unsigned int c1_can_pins0[] = { 138, 137, };
748static const unsigned int c1_can_pins1[] = { 147, 146, };
749static const unsigned int c1_can_pins2[] = { 2, 3, };
750static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68,
751 69, 70, 71, };
752static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, };
753static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, };
754static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, };
755static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, };
756static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47,
757 49, 50, 54, 55, 56, };
758static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, };
759static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, };
760static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75,
761 76, 77, };
762static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, };
763static const unsigned int clkc_pins0[] = { 30, 47, };
764static const unsigned int clkc_pins1[] = { 78, 54, };
765static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, };
766static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, };
767static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, };
768static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, };
769static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, };
770static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78,
771 79, 80, 81, 83, 84, 73, 55, 56, };
772static const unsigned int cvbs_dbg_test_pins0[] = { 57, };
773static const unsigned int cvbs_dbg_test_pins1[] = { 58, };
774static const unsigned int cvbs_dbg_test_pins2[] = { 59, };
775static const unsigned int cvbs_dbg_test_pins3[] = { 60, };
776static const unsigned int cvbs_dbg_test_pins4[] = { 61, };
777static const unsigned int cvbs_dbg_test_pins5[] = { 62, };
778static const unsigned int cvbs_dbg_test_pins6[] = { 63, };
779static const unsigned int cvbs_dbg_test_pins7[] = { 64, };
780static const unsigned int cvbs_dbg_test_pins8[] = { 65, };
781static const unsigned int cvbs_dbg_test_pins9[] = { 66, };
782static const unsigned int cvbs_dbg_test_pins10[] = { 67, };
783static const unsigned int cvbs_dbg_test_pins11[] = { 68, };
784static const unsigned int cvbs_dbg_test_pins12[] = { 69, };
785static const unsigned int cvbs_dbg_test_pins13[] = { 70, };
786static const unsigned int cvbs_dbg_test_pins14[] = { 71, };
787static const unsigned int cvbs_dbg_test_pins15[] = { 72, };
788static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125,
789 120, };
790static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61,
791 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, };
792static const unsigned int gn_gnss_eclk_pins[] = { 113, };
793static const unsigned int gn_gnss_irq1_pins0[] = { 112, };
794static const unsigned int gn_gnss_irq2_pins0[] = { 118, };
795static const unsigned int gn_gnss_tm_pins[] = { 115, };
796static const unsigned int gn_gnss_tsync_pins[] = { 114, };
797static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40,
798 39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, };
799static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, };
800static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, };
801static const unsigned int gn_trg_shutdown_pins0[] = { 30, };
802static const unsigned int gn_trg_shutdown_pins1[] = { 83, };
803static const unsigned int gn_trg_shutdown_pins2[] = { 117, };
804static const unsigned int gn_trg_shutdown_pins3[] = { 123, };
805static const unsigned int i2c0_pins[] = { 128, 127, };
806static const unsigned int i2c1_pins[] = { 126, 125, };
807static const unsigned int jtag_pins0[] = { 125, 4, 2, 0, 1, 3, };
808static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, };
809static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64,
810 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80,
811 81, 56, 53, };
812static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63,
813 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, };
814static const unsigned int ld_ldd_fck_pins[] = { 55, };
815static const unsigned int ld_ldd_lck_pins[] = { 54, };
816static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61,
817 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, };
818static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154,
819 155, 156, 157, 158, };
820static const unsigned int nd_df_pins[] = { 44, 43, 42, 41, 40, 39, 38, 37,
821 47, 46, 52, 51, 45, 49, 50, 48, 124, };
822static const unsigned int nd_df_nowp_pins[] = { 44, 43, 42, 41, 40, 39, 38,
823 37, 47, 46, 52, 51, 45, 49, 50, 48, };
824static const unsigned int ps_pins[] = { 120, 119, };
825static const unsigned int pwc_core_on_pins[] = { 8, };
826static const unsigned int pwc_ext_on_pins[] = { 6, };
827static const unsigned int pwc_gpio3_clk_pins[] = { 3, };
828static const unsigned int pwc_io_on_pins[] = { 9, };
829static const unsigned int pwc_lowbatt_b_pins0[] = { 4, };
830static const unsigned int pwc_mem_on_pins[] = { 7, };
831static const unsigned int pwc_on_key_b_pins0[] = { 5, };
832static const unsigned int pwc_wakeup_src0_pins[] = { 0, };
833static const unsigned int pwc_wakeup_src1_pins[] = { 1, };
834static const unsigned int pwc_wakeup_src2_pins[] = { 2, };
835static const unsigned int pwc_wakeup_src3_pins[] = { 3, };
836static const unsigned int pw_cko0_pins0[] = { 123, };
837static const unsigned int pw_cko0_pins1[] = { 101, };
838static const unsigned int pw_cko0_pins2[] = { 82, };
839static const unsigned int pw_cko1_pins0[] = { 124, };
840static const unsigned int pw_cko1_pins1[] = { 110, };
841static const unsigned int pw_i2s01_clk_pins0[] = { 125, };
842static const unsigned int pw_i2s01_clk_pins1[] = { 117, };
843static const unsigned int pw_pwm0_pins[] = { 119, };
844static const unsigned int pw_pwm1_pins[] = { 120, };
845static const unsigned int pw_pwm2_pins0[] = { 121, };
846static const unsigned int pw_pwm2_pins1[] = { 98, };
847static const unsigned int pw_pwm3_pins0[] = { 122, };
848static const unsigned int pw_pwm3_pins1[] = { 73, };
849static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, };
850static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, };
851static const unsigned int pw_backlight_pins0[] = { 122, };
852static const unsigned int pw_backlight_pins1[] = { 73, };
853static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107,
854 102, 97, 98, 99, 100, 101, };
855static const unsigned int rg_gmac_phy_intr_n_pins[] = { 111, };
856static const unsigned int rg_rgmii_mac_pins[] = { 109, 110, };
857static const unsigned int rg_rgmii_phy_ref_clk_pins0[] = { 111, };
858static const unsigned int rg_rgmii_phy_ref_clk_pins1[] = { 53, };
859static const unsigned int sd0_pins[] = { 46, 47, 44, 43, 42, 41, 40, 39, 38,
860 37, };
861static const unsigned int sd0_4bit_pins[] = { 46, 47, 44, 43, 42, 41, };
862static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38,
863 37, };
864static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, };
865static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, };
866static const unsigned int sd2_pins0[] = { 124, 31, 32, 33, 34, 35, 36, 123, };
867static const unsigned int sd2_no_cdb_pins0[] = { 31, 32, 33, 34, 35, 36, 123, };
868static const unsigned int sd3_pins[] = { 85, 86, 87, 88, 89, 90, };
869static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, };
870static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, };
871static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, };
872static const unsigned int sp0_ext_ldo_on_pins[] = { 4, };
873static const unsigned int sp0_qspi_pins[] = { 12, 13, 14, 15, 16, 17, };
874static const unsigned int sp1_spi_pins[] = { 19, 20, 21, 18, };
875static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61,
876 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, };
877static const unsigned int uart0_pins[] = { 121, 120, 134, 133, };
878static const unsigned int uart0_nopause_pins[] = { 134, 133, };
879static const unsigned int uart1_pins[] = { 136, 135, };
880static const unsigned int uart2_pins[] = { 11, 10, };
881static const unsigned int uart3_pins0[] = { 125, 126, 138, 137, };
882static const unsigned int uart3_pins1[] = { 111, 109, 84, 83, };
883static const unsigned int uart3_pins2[] = { 140, 139, 138, 137, };
884static const unsigned int uart3_pins3[] = { 139, 140, 84, 83, };
885static const unsigned int uart3_nopause_pins0[] = { 138, 137, };
886static const unsigned int uart3_nopause_pins1[] = { 84, 83, };
887static const unsigned int uart4_pins0[] = { 122, 123, 140, 139, };
888static const unsigned int uart4_pins1[] = { 100, 99, 140, 139, };
889static const unsigned int uart4_pins2[] = { 117, 116, 140, 139, };
890static const unsigned int uart4_nopause_pins[] = { 140, 139, };
891static const unsigned int usb0_drvvbus_pins[] = { 51, };
892static const unsigned int usb1_drvvbus_pins[] = { 134, };
893static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63,
894 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86,
895 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, };
896static const unsigned int vi_vip1_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81,
897 82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, };
898static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80,
899 81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98,
900 99, 100, };
901static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79,
902 80, 81, };
903static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 108, 103,
904 104, 105, 106, };
905
906/* definition of pin group table */
907struct atlas7_pin_group altas7_pin_groups[] = {
908 GROUP("gnss_gpio_grp", gnss_gpio_pins),
909 GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins),
910 GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
911 GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins),
912 GROUP("lvds_gpio_grp", lvds_gpio_pins),
913 GROUP("uart_nand_gpio_grp", uart_nand_gpio_pins),
914 GROUP("rtc_gpio_grp", rtc_gpio_pins),
915 GROUP("audio_ac97_grp", audio_ac97_pins),
916 GROUP("audio_func_dbg_grp", audio_func_dbg_pins),
917 GROUP("audio_i2s_grp", audio_i2s_pins),
918 GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins),
919 GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins),
920 GROUP("audio_uart0_grp", audio_uart0_pins),
921 GROUP("audio_uart1_grp", audio_uart1_pins),
922 GROUP("audio_uart2_grp0", audio_uart2_pins0),
923 GROUP("audio_uart2_grp1", audio_uart2_pins1),
924 GROUP("c_can_trnsvr_grp", c_can_trnsvr_pins),
925 GROUP("c0_can_grp0", c0_can_pins0),
926 GROUP("c0_can_grp1", c0_can_pins1),
927 GROUP("c1_can_grp0", c1_can_pins0),
928 GROUP("c1_can_grp1", c1_can_pins1),
929 GROUP("c1_can_grp2", c1_can_pins2),
930 GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins),
931 GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins),
932 GROUP("ca_coex_grp", ca_coex_pins),
933 GROUP("ca_curator_lpc_grp", ca_curator_lpc_pins),
934 GROUP("ca_pcm_debug_grp", ca_pcm_debug_pins),
935 GROUP("ca_pio_grp", ca_pio_pins),
936 GROUP("ca_sdio_debug_grp", ca_sdio_debug_pins),
937 GROUP("ca_spi_grp", ca_spi_pins),
938 GROUP("ca_trb_grp", ca_trb_pins),
939 GROUP("ca_uart_debug_grp", ca_uart_debug_pins),
940 GROUP("clkc_grp0", clkc_pins0),
941 GROUP("clkc_grp1", clkc_pins1),
942 GROUP("gn_gnss_i2c_grp", gn_gnss_i2c_pins),
943 GROUP("gn_gnss_uart_nopause_grp", gn_gnss_uart_nopause_pins),
944 GROUP("gn_gnss_uart_grp", gn_gnss_uart_pins),
945 GROUP("gn_trg_spi_grp0", gn_trg_spi_pins0),
946 GROUP("gn_trg_spi_grp1", gn_trg_spi_pins1),
947 GROUP("cvbs_dbg_grp", cvbs_dbg_pins),
948 GROUP("cvbs_dbg_test_grp0", cvbs_dbg_test_pins0),
949 GROUP("cvbs_dbg_test_grp1", cvbs_dbg_test_pins1),
950 GROUP("cvbs_dbg_test_grp2", cvbs_dbg_test_pins2),
951 GROUP("cvbs_dbg_test_grp3", cvbs_dbg_test_pins3),
952 GROUP("cvbs_dbg_test_grp4", cvbs_dbg_test_pins4),
953 GROUP("cvbs_dbg_test_grp5", cvbs_dbg_test_pins5),
954 GROUP("cvbs_dbg_test_grp6", cvbs_dbg_test_pins6),
955 GROUP("cvbs_dbg_test_grp7", cvbs_dbg_test_pins7),
956 GROUP("cvbs_dbg_test_grp8", cvbs_dbg_test_pins8),
957 GROUP("cvbs_dbg_test_grp9", cvbs_dbg_test_pins9),
958 GROUP("cvbs_dbg_test_grp10", cvbs_dbg_test_pins10),
959 GROUP("cvbs_dbg_test_grp11", cvbs_dbg_test_pins11),
960 GROUP("cvbs_dbg_test_grp12", cvbs_dbg_test_pins12),
961 GROUP("cvbs_dbg_test_grp13", cvbs_dbg_test_pins13),
962 GROUP("cvbs_dbg_test_grp14", cvbs_dbg_test_pins14),
963 GROUP("cvbs_dbg_test_grp15", cvbs_dbg_test_pins15),
964 GROUP("gn_gnss_power_grp", gn_gnss_power_pins),
965 GROUP("gn_gnss_sw_status_grp", gn_gnss_sw_status_pins),
966 GROUP("gn_gnss_eclk_grp", gn_gnss_eclk_pins),
967 GROUP("gn_gnss_irq1_grp0", gn_gnss_irq1_pins0),
968 GROUP("gn_gnss_irq2_grp0", gn_gnss_irq2_pins0),
969 GROUP("gn_gnss_tm_grp", gn_gnss_tm_pins),
970 GROUP("gn_gnss_tsync_grp", gn_gnss_tsync_pins),
971 GROUP("gn_io_gnsssys_sw_cfg_grp", gn_io_gnsssys_sw_cfg_pins),
972 GROUP("gn_trg_grp0", gn_trg_pins0),
973 GROUP("gn_trg_grp1", gn_trg_pins1),
974 GROUP("gn_trg_shutdown_grp0", gn_trg_shutdown_pins0),
975 GROUP("gn_trg_shutdown_grp1", gn_trg_shutdown_pins1),
976 GROUP("gn_trg_shutdown_grp2", gn_trg_shutdown_pins2),
977 GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3),
978 GROUP("i2c0_grp", i2c0_pins),
979 GROUP("i2c1_grp", i2c1_pins),
980 GROUP("jtag_grp0", jtag_pins0),
981 GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0),
982 GROUP("ld_ldd_grp", ld_ldd_pins),
983 GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins),
984 GROUP("ld_ldd_fck_grp", ld_ldd_fck_pins),
985 GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins),
986 GROUP("lr_lcdrom_grp", lr_lcdrom_pins),
987 GROUP("lvds_analog_grp", lvds_analog_pins),
988 GROUP("nd_df_grp", nd_df_pins),
989 GROUP("nd_df_nowp_grp", nd_df_nowp_pins),
990 GROUP("ps_grp", ps_pins),
991 GROUP("pwc_core_on_grp", pwc_core_on_pins),
992 GROUP("pwc_ext_on_grp", pwc_ext_on_pins),
993 GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins),
994 GROUP("pwc_io_on_grp", pwc_io_on_pins),
995 GROUP("pwc_lowbatt_b_grp0", pwc_lowbatt_b_pins0),
996 GROUP("pwc_mem_on_grp", pwc_mem_on_pins),
997 GROUP("pwc_on_key_b_grp0", pwc_on_key_b_pins0),
998 GROUP("pwc_wakeup_src0_grp", pwc_wakeup_src0_pins),
999 GROUP("pwc_wakeup_src1_grp", pwc_wakeup_src1_pins),
1000 GROUP("pwc_wakeup_src2_grp", pwc_wakeup_src2_pins),
1001 GROUP("pwc_wakeup_src3_grp", pwc_wakeup_src3_pins),
1002 GROUP("pw_cko0_grp0", pw_cko0_pins0),
1003 GROUP("pw_cko0_grp1", pw_cko0_pins1),
1004 GROUP("pw_cko0_grp2", pw_cko0_pins2),
1005 GROUP("pw_cko1_grp0", pw_cko1_pins0),
1006 GROUP("pw_cko1_grp1", pw_cko1_pins1),
1007 GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0),
1008 GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1),
1009 GROUP("pw_pwm0_grp", pw_pwm0_pins),
1010 GROUP("pw_pwm1_grp", pw_pwm1_pins),
1011 GROUP("pw_pwm2_grp0", pw_pwm2_pins0),
1012 GROUP("pw_pwm2_grp1", pw_pwm2_pins1),
1013 GROUP("pw_pwm3_grp0", pw_pwm3_pins0),
1014 GROUP("pw_pwm3_grp1", pw_pwm3_pins1),
1015 GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0),
1016 GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1),
1017 GROUP("pw_backlight_grp0", pw_backlight_pins0),
1018 GROUP("pw_backlight_grp1", pw_backlight_pins1),
1019 GROUP("rg_eth_mac_grp", rg_eth_mac_pins),
1020 GROUP("rg_gmac_phy_intr_n_grp", rg_gmac_phy_intr_n_pins),
1021 GROUP("rg_rgmii_mac_grp", rg_rgmii_mac_pins),
1022 GROUP("rg_rgmii_phy_ref_clk_grp0", rg_rgmii_phy_ref_clk_pins0),
1023 GROUP("rg_rgmii_phy_ref_clk_grp1", rg_rgmii_phy_ref_clk_pins1),
1024 GROUP("sd0_grp", sd0_pins),
1025 GROUP("sd0_4bit_grp", sd0_4bit_pins),
1026 GROUP("sd1_grp", sd1_pins),
1027 GROUP("sd1_4bit_grp0", sd1_4bit_pins0),
1028 GROUP("sd1_4bit_grp1", sd1_4bit_pins1),
1029 GROUP("sd2_grp0", sd2_pins0),
1030 GROUP("sd2_no_cdb_grp0", sd2_no_cdb_pins0),
1031 GROUP("sd3_grp", sd3_pins),
1032 GROUP("sd5_grp", sd5_pins),
1033 GROUP("sd6_grp0", sd6_pins0),
1034 GROUP("sd6_grp1", sd6_pins1),
1035 GROUP("sp0_ext_ldo_on_grp", sp0_ext_ldo_on_pins),
1036 GROUP("sp0_qspi_grp", sp0_qspi_pins),
1037 GROUP("sp1_spi_grp", sp1_spi_pins),
1038 GROUP("tpiu_trace_grp", tpiu_trace_pins),
1039 GROUP("uart0_grp", uart0_pins),
1040 GROUP("uart0_nopause_grp", uart0_nopause_pins),
1041 GROUP("uart1_grp", uart1_pins),
1042 GROUP("uart2_grp", uart2_pins),
1043 GROUP("uart3_grp0", uart3_pins0),
1044 GROUP("uart3_grp1", uart3_pins1),
1045 GROUP("uart3_grp2", uart3_pins2),
1046 GROUP("uart3_grp3", uart3_pins3),
1047 GROUP("uart3_nopause_grp0", uart3_nopause_pins0),
1048 GROUP("uart3_nopause_grp1", uart3_nopause_pins1),
1049 GROUP("uart4_grp0", uart4_pins0),
1050 GROUP("uart4_grp1", uart4_pins1),
1051 GROUP("uart4_grp2", uart4_pins2),
1052 GROUP("uart4_nopause_grp", uart4_nopause_pins),
1053 GROUP("usb0_drvvbus_grp", usb0_drvvbus_pins),
1054 GROUP("usb1_drvvbus_grp", usb1_drvvbus_pins),
1055 GROUP("visbus_dout_grp", visbus_dout_pins),
1056 GROUP("vi_vip1_grp", vi_vip1_pins),
1057 GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins),
1058 GROUP("vi_vip1_low8bit_grp", vi_vip1_low8bit_pins),
1059 GROUP("vi_vip1_high8bit_grp", vi_vip1_high8bit_pins),
1060};
1061
1062/* How many groups that a function can use */
1063static const char * const gnss_gpio_grp[] = { "gnss_gpio_grp", };
1064static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", };
1065static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", };
1066static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", };
1067static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", };
1068static const char * const uart_nand_gpio_grp[] = { "uart_nand_gpio_grp", };
1069static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", };
1070static const char * const audio_ac97_grp[] = { "audio_ac97_grp", };
1071static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", };
1072static const char * const audio_i2s_grp[] = { "audio_i2s_grp", };
1073static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", };
1074static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", };
1075static const char * const audio_uart0_grp[] = { "audio_uart0_grp", };
1076static const char * const audio_uart1_grp[] = { "audio_uart1_grp", };
1077static const char * const audio_uart2_grp0[] = { "audio_uart2_grp0", };
1078static const char * const audio_uart2_grp1[] = { "audio_uart2_grp1", };
1079static const char * const c_can_trnsvr_grp[] = { "c_can_trnsvr_grp", };
1080static const char * const c0_can_grp0[] = { "c0_can_grp0", };
1081static const char * const c0_can_grp1[] = { "c0_can_grp1", };
1082static const char * const c1_can_grp0[] = { "c1_can_grp0", };
1083static const char * const c1_can_grp1[] = { "c1_can_grp1", };
1084static const char * const c1_can_grp2[] = { "c1_can_grp2", };
1085static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", };
1086static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", };
1087static const char * const ca_coex_grp[] = { "ca_coex_grp", };
1088static const char * const ca_curator_lpc_grp[] = { "ca_curator_lpc_grp", };
1089static const char * const ca_pcm_debug_grp[] = { "ca_pcm_debug_grp", };
1090static const char * const ca_pio_grp[] = { "ca_pio_grp", };
1091static const char * const ca_sdio_debug_grp[] = { "ca_sdio_debug_grp", };
1092static const char * const ca_spi_grp[] = { "ca_spi_grp", };
1093static const char * const ca_trb_grp[] = { "ca_trb_grp", };
1094static const char * const ca_uart_debug_grp[] = { "ca_uart_debug_grp", };
1095static const char * const clkc_grp0[] = { "clkc_grp0", };
1096static const char * const clkc_grp1[] = { "clkc_grp1", };
1097static const char * const gn_gnss_i2c_grp[] = { "gn_gnss_i2c_grp", };
1098static const char * const gn_gnss_uart_nopause_grp[] = {
1099 "gn_gnss_uart_nopause_grp", };
1100static const char * const gn_gnss_uart_grp[] = { "gn_gnss_uart_grp", };
1101static const char * const gn_trg_spi_grp0[] = { "gn_trg_spi_grp0", };
1102static const char * const gn_trg_spi_grp1[] = { "gn_trg_spi_grp1", };
1103static const char * const cvbs_dbg_grp[] = { "cvbs_dbg_grp", };
1104static const char * const cvbs_dbg_test_grp0[] = { "cvbs_dbg_test_grp0", };
1105static const char * const cvbs_dbg_test_grp1[] = { "cvbs_dbg_test_grp1", };
1106static const char * const cvbs_dbg_test_grp2[] = { "cvbs_dbg_test_grp2", };
1107static const char * const cvbs_dbg_test_grp3[] = { "cvbs_dbg_test_grp3", };
1108static const char * const cvbs_dbg_test_grp4[] = { "cvbs_dbg_test_grp4", };
1109static const char * const cvbs_dbg_test_grp5[] = { "cvbs_dbg_test_grp5", };
1110static const char * const cvbs_dbg_test_grp6[] = { "cvbs_dbg_test_grp6", };
1111static const char * const cvbs_dbg_test_grp7[] = { "cvbs_dbg_test_grp7", };
1112static const char * const cvbs_dbg_test_grp8[] = { "cvbs_dbg_test_grp8", };
1113static const char * const cvbs_dbg_test_grp9[] = { "cvbs_dbg_test_grp9", };
1114static const char * const cvbs_dbg_test_grp10[] = { "cvbs_dbg_test_grp10", };
1115static const char * const cvbs_dbg_test_grp11[] = { "cvbs_dbg_test_grp11", };
1116static const char * const cvbs_dbg_test_grp12[] = { "cvbs_dbg_test_grp12", };
1117static const char * const cvbs_dbg_test_grp13[] = { "cvbs_dbg_test_grp13", };
1118static const char * const cvbs_dbg_test_grp14[] = { "cvbs_dbg_test_grp14", };
1119static const char * const cvbs_dbg_test_grp15[] = { "cvbs_dbg_test_grp15", };
1120static const char * const gn_gnss_power_grp[] = { "gn_gnss_power_grp", };
1121static const char * const gn_gnss_sw_status_grp[] = {
1122 "gn_gnss_sw_status_grp", };
1123static const char * const gn_gnss_eclk_grp[] = { "gn_gnss_eclk_grp", };
1124static const char * const gn_gnss_irq1_grp0[] = { "gn_gnss_irq1_grp0", };
1125static const char * const gn_gnss_irq2_grp0[] = { "gn_gnss_irq2_grp0", };
1126static const char * const gn_gnss_tm_grp[] = { "gn_gnss_tm_grp", };
1127static const char * const gn_gnss_tsync_grp[] = { "gn_gnss_tsync_grp", };
1128static const char * const gn_io_gnsssys_sw_cfg_grp[] = {
1129 "gn_io_gnsssys_sw_cfg_grp", };
1130static const char * const gn_trg_grp0[] = { "gn_trg_grp0", };
1131static const char * const gn_trg_grp1[] = { "gn_trg_grp1", };
1132static const char * const gn_trg_shutdown_grp0[] = { "gn_trg_shutdown_grp0", };
1133static const char * const gn_trg_shutdown_grp1[] = { "gn_trg_shutdown_grp1", };
1134static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", };
1135static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", };
1136static const char * const i2c0_grp[] = { "i2c0_grp", };
1137static const char * const i2c1_grp[] = { "i2c1_grp", };
1138static const char * const jtag_grp0[] = { "jtag_grp0", };
1139static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", };
1140static const char * const ld_ldd_grp[] = { "ld_ldd_grp", };
1141static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", };
1142static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", };
1143static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", };
1144static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", };
1145static const char * const lvds_analog_grp[] = { "lvds_analog_grp", };
1146static const char * const nd_df_grp[] = { "nd_df_grp", };
1147static const char * const nd_df_nowp_grp[] = { "nd_df_nowp_grp", };
1148static const char * const ps_grp[] = { "ps_grp", };
1149static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", };
1150static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", };
1151static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", };
1152static const char * const pwc_io_on_grp[] = { "pwc_io_on_grp", };
1153static const char * const pwc_lowbatt_b_grp0[] = { "pwc_lowbatt_b_grp0", };
1154static const char * const pwc_mem_on_grp[] = { "pwc_mem_on_grp", };
1155static const char * const pwc_on_key_b_grp0[] = { "pwc_on_key_b_grp0", };
1156static const char * const pwc_wakeup_src0_grp[] = { "pwc_wakeup_src0_grp", };
1157static const char * const pwc_wakeup_src1_grp[] = { "pwc_wakeup_src1_grp", };
1158static const char * const pwc_wakeup_src2_grp[] = { "pwc_wakeup_src2_grp", };
1159static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", };
1160static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", };
1161static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", };
1162static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", };
1163static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", };
1164static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", };
1165static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", };
1166static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", };
1167static const char * const pw_pwm0_grp[] = { "pw_pwm0_grp", };
1168static const char * const pw_pwm1_grp[] = { "pw_pwm1_grp", };
1169static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", };
1170static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", };
1171static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", };
1172static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", };
1173static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", };
1174static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", };
1175static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", };
1176static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", };
1177static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", };
1178static const char * const rg_gmac_phy_intr_n_grp[] = {
1179 "rg_gmac_phy_intr_n_grp", };
1180static const char * const rg_rgmii_mac_grp[] = { "rg_rgmii_mac_grp", };
1181static const char * const rg_rgmii_phy_ref_clk_grp0[] = {
1182 "rg_rgmii_phy_ref_clk_grp0", };
1183static const char * const rg_rgmii_phy_ref_clk_grp1[] = {
1184 "rg_rgmii_phy_ref_clk_grp1", };
1185static const char * const sd0_grp[] = { "sd0_grp", };
1186static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", };
1187static const char * const sd1_grp[] = { "sd1_grp", };
1188static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", };
1189static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", };
1190static const char * const sd2_grp0[] = { "sd2_grp0", };
1191static const char * const sd2_no_cdb_grp0[] = { "sd2_no_cdb_grp0", };
1192static const char * const sd3_grp[] = { "sd3_grp", };
1193static const char * const sd5_grp[] = { "sd5_grp", };
1194static const char * const sd6_grp0[] = { "sd6_grp0", };
1195static const char * const sd6_grp1[] = { "sd6_grp1", };
1196static const char * const sp0_ext_ldo_on_grp[] = { "sp0_ext_ldo_on_grp", };
1197static const char * const sp0_qspi_grp[] = { "sp0_qspi_grp", };
1198static const char * const sp1_spi_grp[] = { "sp1_spi_grp", };
1199static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", };
1200static const char * const uart0_grp[] = { "uart0_grp", };
1201static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", };
1202static const char * const uart1_grp[] = { "uart1_grp", };
1203static const char * const uart2_grp[] = { "uart2_grp", };
1204static const char * const uart3_grp0[] = { "uart3_grp0", };
1205static const char * const uart3_grp1[] = { "uart3_grp1", };
1206static const char * const uart3_grp2[] = { "uart3_grp2", };
1207static const char * const uart3_grp3[] = { "uart3_grp3", };
1208static const char * const uart3_nopause_grp0[] = { "uart3_nopause_grp0", };
1209static const char * const uart3_nopause_grp1[] = { "uart3_nopause_grp1", };
1210static const char * const uart4_grp0[] = { "uart4_grp0", };
1211static const char * const uart4_grp1[] = { "uart4_grp1", };
1212static const char * const uart4_grp2[] = { "uart4_grp2", };
1213static const char * const uart4_nopause_grp[] = { "uart4_nopause_grp", };
1214static const char * const usb0_drvvbus_grp[] = { "usb0_drvvbus_grp", };
1215static const char * const usb1_drvvbus_grp[] = { "usb1_drvvbus_grp", };
1216static const char * const visbus_dout_grp[] = { "visbus_dout_grp", };
1217static const char * const vi_vip1_grp[] = { "vi_vip1_grp", };
1218static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", };
1219static const char * const vi_vip1_low8bit_grp[] = { "vi_vip1_low8bit_grp", };
1220static const char * const vi_vip1_high8bit_grp[] = { "vi_vip1_high8bit_grp", };
1221
1222static struct atlas7_pad_mux gnss_gpio_grp_pad_mux[] = {
1223 MUX(1, 119, 0, N, N, N, N),
1224 MUX(1, 120, 0, N, N, N, N),
1225 MUX(1, 121, 0, N, N, N, N),
1226 MUX(1, 122, 0, N, N, N, N),
1227 MUX(1, 123, 0, N, N, N, N),
1228 MUX(1, 124, 0, N, N, N, N),
1229 MUX(1, 125, 0, N, N, N, N),
1230 MUX(1, 126, 0, N, N, N, N),
1231 MUX(1, 127, 0, N, N, N, N),
1232 MUX(1, 128, 0, N, N, N, N),
1233 MUX(1, 22, 0, N, N, N, N),
1234 MUX(1, 23, 0, N, N, N, N),
1235 MUX(1, 24, 0, N, N, N, N),
1236 MUX(1, 25, 0, N, N, N, N),
1237 MUX(1, 26, 0, N, N, N, N),
1238 MUX(1, 27, 0, N, N, N, N),
1239 MUX(1, 28, 0, N, N, N, N),
1240 MUX(1, 29, 0, N, N, N, N),
1241 MUX(1, 30, 0, N, N, N, N),
1242};
1243
1244static struct atlas7_grp_mux gnss_gpio_grp_mux = {
1245 .pad_mux_count = ARRAY_SIZE(gnss_gpio_grp_pad_mux),
1246 .pad_mux_list = gnss_gpio_grp_pad_mux,
1247};
1248
1249static struct atlas7_pad_mux lcd_vip_gpio_grp_pad_mux[] = {
1250 MUX(1, 74, 0, N, N, N, N),
1251 MUX(1, 75, 0, N, N, N, N),
1252 MUX(1, 76, 0, N, N, N, N),
1253 MUX(1, 77, 0, N, N, N, N),
1254 MUX(1, 78, 0, N, N, N, N),
1255 MUX(1, 79, 0, N, N, N, N),
1256 MUX(1, 80, 0, N, N, N, N),
1257 MUX(1, 81, 0, N, N, N, N),
1258 MUX(1, 82, 0, N, N, N, N),
1259 MUX(1, 83, 0, N, N, N, N),
1260 MUX(1, 84, 0, N, N, N, N),
1261 MUX(1, 53, 0, N, N, N, N),
1262 MUX(1, 54, 0, N, N, N, N),
1263 MUX(1, 55, 0, N, N, N, N),
1264 MUX(1, 56, 0, N, N, N, N),
1265 MUX(1, 57, 0, N, N, N, N),
1266 MUX(1, 58, 0, N, N, N, N),
1267 MUX(1, 59, 0, N, N, N, N),
1268 MUX(1, 60, 0, N, N, N, N),
1269 MUX(1, 61, 0, N, N, N, N),
1270 MUX(1, 62, 0, N, N, N, N),
1271 MUX(1, 63, 0, N, N, N, N),
1272 MUX(1, 64, 0, N, N, N, N),
1273 MUX(1, 65, 0, N, N, N, N),
1274 MUX(1, 66, 0, N, N, N, N),
1275 MUX(1, 67, 0, N, N, N, N),
1276 MUX(1, 68, 0, N, N, N, N),
1277 MUX(1, 69, 0, N, N, N, N),
1278 MUX(1, 70, 0, N, N, N, N),
1279 MUX(1, 71, 0, N, N, N, N),
1280 MUX(1, 72, 0, N, N, N, N),
1281 MUX(1, 73, 0, N, N, N, N),
1282};
1283
1284static struct atlas7_grp_mux lcd_vip_gpio_grp_mux = {
1285 .pad_mux_count = ARRAY_SIZE(lcd_vip_gpio_grp_pad_mux),
1286 .pad_mux_list = lcd_vip_gpio_grp_pad_mux,
1287};
1288
1289static struct atlas7_pad_mux sdio_i2s_gpio_grp_pad_mux[] = {
1290 MUX(1, 31, 0, N, N, N, N),
1291 MUX(1, 32, 0, N, N, N, N),
1292 MUX(1, 33, 0, N, N, N, N),
1293 MUX(1, 34, 0, N, N, N, N),
1294 MUX(1, 35, 0, N, N, N, N),
1295 MUX(1, 36, 0, N, N, N, N),
1296 MUX(1, 85, 0, N, N, N, N),
1297 MUX(1, 86, 0, N, N, N, N),
1298 MUX(1, 87, 0, N, N, N, N),
1299 MUX(1, 88, 0, N, N, N, N),
1300 MUX(1, 89, 0, N, N, N, N),
1301 MUX(1, 90, 0, N, N, N, N),
1302 MUX(1, 129, 0, N, N, N, N),
1303 MUX(1, 130, 0, N, N, N, N),
1304 MUX(1, 131, 0, N, N, N, N),
1305 MUX(1, 132, 0, N, N, N, N),
1306 MUX(1, 91, 0, N, N, N, N),
1307 MUX(1, 92, 0, N, N, N, N),
1308 MUX(1, 93, 0, N, N, N, N),
1309 MUX(1, 94, 0, N, N, N, N),
1310 MUX(1, 95, 0, N, N, N, N),
1311 MUX(1, 96, 0, N, N, N, N),
1312 MUX(1, 112, 0, N, N, N, N),
1313 MUX(1, 113, 0, N, N, N, N),
1314 MUX(1, 114, 0, N, N, N, N),
1315 MUX(1, 115, 0, N, N, N, N),
1316 MUX(1, 116, 0, N, N, N, N),
1317 MUX(1, 117, 0, N, N, N, N),
1318 MUX(1, 118, 0, N, N, N, N),
1319};
1320
1321static struct atlas7_grp_mux sdio_i2s_gpio_grp_mux = {
1322 .pad_mux_count = ARRAY_SIZE(sdio_i2s_gpio_grp_pad_mux),
1323 .pad_mux_list = sdio_i2s_gpio_grp_pad_mux,
1324};
1325
1326static struct atlas7_pad_mux sp_rgmii_gpio_grp_pad_mux[] = {
1327 MUX(1, 97, 0, N, N, N, N),
1328 MUX(1, 98, 0, N, N, N, N),
1329 MUX(1, 99, 0, N, N, N, N),
1330 MUX(1, 100, 0, N, N, N, N),
1331 MUX(1, 101, 0, N, N, N, N),
1332 MUX(1, 102, 0, N, N, N, N),
1333 MUX(1, 103, 0, N, N, N, N),
1334 MUX(1, 104, 0, N, N, N, N),
1335 MUX(1, 105, 0, N, N, N, N),
1336 MUX(1, 106, 0, N, N, N, N),
1337 MUX(1, 107, 0, N, N, N, N),
1338 MUX(1, 108, 0, N, N, N, N),
1339 MUX(1, 109, 0, N, N, N, N),
1340 MUX(1, 110, 0, N, N, N, N),
1341 MUX(1, 111, 0, N, N, N, N),
1342 MUX(1, 18, 0, N, N, N, N),
1343 MUX(1, 19, 0, N, N, N, N),
1344 MUX(1, 20, 0, N, N, N, N),
1345 MUX(1, 21, 0, N, N, N, N),
1346 MUX(1, 141, 0, N, N, N, N),
1347 MUX(1, 142, 0, N, N, N, N),
1348 MUX(1, 143, 0, N, N, N, N),
1349 MUX(1, 144, 0, N, N, N, N),
1350 MUX(1, 145, 0, N, N, N, N),
1351 MUX(1, 146, 0, N, N, N, N),
1352 MUX(1, 147, 0, N, N, N, N),
1353 MUX(1, 148, 0, N, N, N, N),
1354};
1355
1356static struct atlas7_grp_mux sp_rgmii_gpio_grp_mux = {
1357 .pad_mux_count = ARRAY_SIZE(sp_rgmii_gpio_grp_pad_mux),
1358 .pad_mux_list = sp_rgmii_gpio_grp_pad_mux,
1359};
1360
1361static struct atlas7_pad_mux lvds_gpio_grp_pad_mux[] = {
1362 MUX(1, 157, 0, N, N, N, N),
1363 MUX(1, 158, 0, N, N, N, N),
1364 MUX(1, 155, 0, N, N, N, N),
1365 MUX(1, 156, 0, N, N, N, N),
1366 MUX(1, 153, 0, N, N, N, N),
1367 MUX(1, 154, 0, N, N, N, N),
1368 MUX(1, 151, 0, N, N, N, N),
1369 MUX(1, 152, 0, N, N, N, N),
1370 MUX(1, 149, 0, N, N, N, N),
1371 MUX(1, 150, 0, N, N, N, N),
1372};
1373
1374static struct atlas7_grp_mux lvds_gpio_grp_mux = {
1375 .pad_mux_count = ARRAY_SIZE(lvds_gpio_grp_pad_mux),
1376 .pad_mux_list = lvds_gpio_grp_pad_mux,
1377};
1378
1379static struct atlas7_pad_mux uart_nand_gpio_grp_pad_mux[] = {
1380 MUX(1, 44, 0, N, N, N, N),
1381 MUX(1, 43, 0, N, N, N, N),
1382 MUX(1, 42, 0, N, N, N, N),
1383 MUX(1, 41, 0, N, N, N, N),
1384 MUX(1, 40, 0, N, N, N, N),
1385 MUX(1, 39, 0, N, N, N, N),
1386 MUX(1, 38, 0, N, N, N, N),
1387 MUX(1, 37, 0, N, N, N, N),
1388 MUX(1, 46, 0, N, N, N, N),
1389 MUX(1, 47, 0, N, N, N, N),
1390 MUX(1, 48, 0, N, N, N, N),
1391 MUX(1, 49, 0, N, N, N, N),
1392 MUX(1, 50, 0, N, N, N, N),
1393 MUX(1, 52, 0, N, N, N, N),
1394 MUX(1, 51, 0, N, N, N, N),
1395 MUX(1, 45, 0, N, N, N, N),
1396 MUX(1, 133, 0, N, N, N, N),
1397 MUX(1, 134, 0, N, N, N, N),
1398 MUX(1, 135, 0, N, N, N, N),
1399 MUX(1, 136, 0, N, N, N, N),
1400 MUX(1, 137, 0, N, N, N, N),
1401 MUX(1, 138, 0, N, N, N, N),
1402 MUX(1, 139, 0, N, N, N, N),
1403 MUX(1, 140, 0, N, N, N, N),
1404};
1405
1406static struct atlas7_grp_mux uart_nand_gpio_grp_mux = {
1407 .pad_mux_count = ARRAY_SIZE(uart_nand_gpio_grp_pad_mux),
1408 .pad_mux_list = uart_nand_gpio_grp_pad_mux,
1409};
1410
1411static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = {
1412 MUX(0, 0, 0, N, N, N, N),
1413 MUX(0, 1, 0, N, N, N, N),
1414 MUX(0, 2, 0, N, N, N, N),
1415 MUX(0, 3, 0, N, N, N, N),
1416 MUX(0, 4, 0, N, N, N, N),
1417 MUX(0, 10, 0, N, N, N, N),
1418 MUX(0, 11, 0, N, N, N, N),
1419 MUX(0, 12, 0, N, N, N, N),
1420 MUX(0, 13, 0, N, N, N, N),
1421 MUX(0, 14, 0, N, N, N, N),
1422 MUX(0, 15, 0, N, N, N, N),
1423 MUX(0, 16, 0, N, N, N, N),
1424 MUX(0, 17, 0, N, N, N, N),
1425};
1426
1427static struct atlas7_grp_mux rtc_gpio_grp_mux = {
1428 .pad_mux_count = ARRAY_SIZE(rtc_gpio_grp_pad_mux),
1429 .pad_mux_list = rtc_gpio_grp_pad_mux,
1430};
1431
1432static struct atlas7_pad_mux audio_ac97_grp_pad_mux[] = {
1433 MUX(1, 113, 2, N, N, N, N),
1434 MUX(1, 118, 2, N, N, N, N),
1435 MUX(1, 115, 2, N, N, N, N),
1436 MUX(1, 114, 2, N, N, N, N),
1437};
1438
1439static struct atlas7_grp_mux audio_ac97_grp_mux = {
1440 .pad_mux_count = ARRAY_SIZE(audio_ac97_grp_pad_mux),
1441 .pad_mux_list = audio_ac97_grp_pad_mux,
1442};
1443
1444static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = {
1445 MUX(1, 141, 4, N, N, N, N),
1446 MUX(1, 144, 4, N, N, N, N),
1447 MUX(1, 44, 6, N, N, N, N),
1448 MUX(1, 43, 6, N, N, N, N),
1449 MUX(1, 42, 6, N, N, N, N),
1450 MUX(1, 41, 6, N, N, N, N),
1451 MUX(1, 40, 6, N, N, N, N),
1452 MUX(1, 39, 6, N, N, N, N),
1453 MUX(1, 38, 6, N, N, N, N),
1454 MUX(1, 37, 6, N, N, N, N),
1455 MUX(1, 74, 6, N, N, N, N),
1456 MUX(1, 75, 6, N, N, N, N),
1457 MUX(1, 76, 6, N, N, N, N),
1458 MUX(1, 77, 6, N, N, N, N),
1459 MUX(1, 78, 6, N, N, N, N),
1460 MUX(1, 79, 6, N, N, N, N),
1461 MUX(1, 81, 6, N, N, N, N),
1462 MUX(1, 113, 6, N, N, N, N),
1463 MUX(1, 114, 6, N, N, N, N),
1464 MUX(1, 118, 6, N, N, N, N),
1465 MUX(1, 115, 6, N, N, N, N),
1466 MUX(1, 49, 6, N, N, N, N),
1467 MUX(1, 50, 6, N, N, N, N),
1468 MUX(1, 142, 4, N, N, N, N),
1469 MUX(1, 143, 4, N, N, N, N),
1470 MUX(1, 80, 6, N, N, N, N),
1471};
1472
1473static struct atlas7_grp_mux audio_func_dbg_grp_mux = {
1474 .pad_mux_count = ARRAY_SIZE(audio_func_dbg_grp_pad_mux),
1475 .pad_mux_list = audio_func_dbg_grp_pad_mux,
1476};
1477
1478static struct atlas7_pad_mux audio_i2s_grp_pad_mux[] = {
1479 MUX(1, 118, 1, N, N, N, N),
1480 MUX(1, 115, 1, N, N, N, N),
1481 MUX(1, 116, 1, N, N, N, N),
1482 MUX(1, 117, 1, N, N, N, N),
1483 MUX(1, 112, 1, N, N, N, N),
1484 MUX(1, 113, 1, N, N, N, N),
1485 MUX(1, 114, 1, N, N, N, N),
1486};
1487
1488static struct atlas7_grp_mux audio_i2s_grp_mux = {
1489 .pad_mux_count = ARRAY_SIZE(audio_i2s_grp_pad_mux),
1490 .pad_mux_list = audio_i2s_grp_pad_mux,
1491};
1492
1493static struct atlas7_pad_mux audio_i2s_2ch_grp_pad_mux[] = {
1494 MUX(1, 118, 1, N, N, N, N),
1495 MUX(1, 115, 1, N, N, N, N),
1496 MUX(1, 112, 1, N, N, N, N),
1497 MUX(1, 113, 1, N, N, N, N),
1498 MUX(1, 114, 1, N, N, N, N),
1499};
1500
1501static struct atlas7_grp_mux audio_i2s_2ch_grp_mux = {
1502 .pad_mux_count = ARRAY_SIZE(audio_i2s_2ch_grp_pad_mux),
1503 .pad_mux_list = audio_i2s_2ch_grp_pad_mux,
1504};
1505
1506static struct atlas7_pad_mux audio_i2s_extclk_grp_pad_mux[] = {
1507 MUX(1, 112, 2, N, N, N, N),
1508};
1509
1510static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = {
1511 .pad_mux_count = ARRAY_SIZE(audio_i2s_extclk_grp_pad_mux),
1512 .pad_mux_list = audio_i2s_extclk_grp_pad_mux,
1513};
1514
1515static struct atlas7_pad_mux audio_uart0_grp_pad_mux[] = {
1516 MUX(1, 143, 1, N, N, N, N),
1517 MUX(1, 142, 1, N, N, N, N),
1518 MUX(1, 141, 1, N, N, N, N),
1519 MUX(1, 144, 1, N, N, N, N),
1520};
1521
1522static struct atlas7_grp_mux audio_uart0_grp_mux = {
1523 .pad_mux_count = ARRAY_SIZE(audio_uart0_grp_pad_mux),
1524 .pad_mux_list = audio_uart0_grp_pad_mux,
1525};
1526
1527static struct atlas7_pad_mux audio_uart1_grp_pad_mux[] = {
1528 MUX(1, 147, 1, N, N, N, N),
1529 MUX(1, 146, 1, N, N, N, N),
1530 MUX(1, 145, 1, N, N, N, N),
1531 MUX(1, 148, 1, N, N, N, N),
1532};
1533
1534static struct atlas7_grp_mux audio_uart1_grp_mux = {
1535 .pad_mux_count = ARRAY_SIZE(audio_uart1_grp_pad_mux),
1536 .pad_mux_list = audio_uart1_grp_pad_mux,
1537};
1538
1539static struct atlas7_pad_mux audio_uart2_grp0_pad_mux[] = {
1540 MUX(1, 20, 2, 0xa00, 24, 0xa80, 24),
1541 MUX(1, 21, 2, 0xa00, 25, 0xa80, 25),
1542 MUX(1, 19, 2, 0xa00, 23, 0xa80, 23),
1543 MUX(1, 18, 2, 0xa00, 22, 0xa80, 22),
1544};
1545
1546static struct atlas7_grp_mux audio_uart2_grp0_mux = {
1547 .pad_mux_count = ARRAY_SIZE(audio_uart2_grp0_pad_mux),
1548 .pad_mux_list = audio_uart2_grp0_pad_mux,
1549};
1550
1551static struct atlas7_pad_mux audio_uart2_grp1_pad_mux[] = {
1552 MUX(1, 109, 2, 0xa00, 24, 0xa80, 24),
1553 MUX(1, 110, 2, 0xa00, 25, 0xa80, 25),
1554 MUX(1, 101, 2, 0xa00, 23, 0xa80, 23),
1555 MUX(1, 111, 2, 0xa00, 22, 0xa80, 22),
1556};
1557
1558static struct atlas7_grp_mux audio_uart2_grp1_mux = {
1559 .pad_mux_count = ARRAY_SIZE(audio_uart2_grp1_pad_mux),
1560 .pad_mux_list = audio_uart2_grp1_pad_mux,
1561};
1562
1563static struct atlas7_pad_mux c_can_trnsvr_grp_pad_mux[] = {
1564 MUX(0, 1, 2, N, N, N, N),
1565};
1566
1567static struct atlas7_grp_mux c_can_trnsvr_grp_mux = {
1568 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_grp_pad_mux),
1569 .pad_mux_list = c_can_trnsvr_grp_pad_mux,
1570};
1571
1572static struct atlas7_pad_mux c0_can_grp0_pad_mux[] = {
1573 MUX(0, 11, 1, 0xa08, 9, 0xa88, 9),
1574 MUX(0, 10, 1, N, N, N, N),
1575};
1576
1577static struct atlas7_grp_mux c0_can_grp0_mux = {
1578 .pad_mux_count = ARRAY_SIZE(c0_can_grp0_pad_mux),
1579 .pad_mux_list = c0_can_grp0_pad_mux,
1580};
1581
1582static struct atlas7_pad_mux c0_can_grp1_pad_mux[] = {
1583 MUX(0, 2, 5, 0xa08, 9, 0xa88, 9),
1584 MUX(0, 3, 5, N, N, N, N),
1585};
1586
1587static struct atlas7_grp_mux c0_can_grp1_mux = {
1588 .pad_mux_count = ARRAY_SIZE(c0_can_grp1_pad_mux),
1589 .pad_mux_list = c0_can_grp1_pad_mux,
1590};
1591
1592static struct atlas7_pad_mux c1_can_grp0_pad_mux[] = {
1593 MUX(1, 138, 2, 0xa00, 4, 0xa80, 4),
1594 MUX(1, 137, 2, N, N, N, N),
1595};
1596
1597static struct atlas7_grp_mux c1_can_grp0_mux = {
1598 .pad_mux_count = ARRAY_SIZE(c1_can_grp0_pad_mux),
1599 .pad_mux_list = c1_can_grp0_pad_mux,
1600};
1601
1602static struct atlas7_pad_mux c1_can_grp1_pad_mux[] = {
1603 MUX(1, 147, 2, 0xa00, 4, 0xa80, 4),
1604 MUX(1, 146, 2, N, N, N, N),
1605};
1606
1607static struct atlas7_grp_mux c1_can_grp1_mux = {
1608 .pad_mux_count = ARRAY_SIZE(c1_can_grp1_pad_mux),
1609 .pad_mux_list = c1_can_grp1_pad_mux,
1610};
1611
1612static struct atlas7_pad_mux c1_can_grp2_pad_mux[] = {
1613 MUX(0, 2, 2, 0xa00, 4, 0xa80, 4),
1614 MUX(0, 3, 2, N, N, N, N),
1615};
1616
1617static struct atlas7_grp_mux c1_can_grp2_mux = {
1618 .pad_mux_count = ARRAY_SIZE(c1_can_grp2_pad_mux),
1619 .pad_mux_list = c1_can_grp2_pad_mux,
1620};
1621
1622static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = {
1623 MUX(1, 62, 4, N, N, N, N),
1624 MUX(1, 63, 4, N, N, N, N),
1625 MUX(1, 64, 4, N, N, N, N),
1626 MUX(1, 65, 4, N, N, N, N),
1627 MUX(1, 66, 4, N, N, N, N),
1628 MUX(1, 67, 4, N, N, N, N),
1629 MUX(1, 68, 4, N, N, N, N),
1630 MUX(1, 69, 4, N, N, N, N),
1631 MUX(1, 70, 4, N, N, N, N),
1632 MUX(1, 71, 4, N, N, N, N),
1633};
1634
1635static struct atlas7_grp_mux ca_audio_lpc_grp_mux = {
1636 .pad_mux_count = ARRAY_SIZE(ca_audio_lpc_grp_pad_mux),
1637 .pad_mux_list = ca_audio_lpc_grp_pad_mux,
1638};
1639
1640static struct atlas7_pad_mux ca_bt_lpc_grp_pad_mux[] = {
1641 MUX(1, 85, 5, N, N, N, N),
1642 MUX(1, 86, 5, N, N, N, N),
1643 MUX(1, 87, 5, N, N, N, N),
1644 MUX(1, 88, 5, N, N, N, N),
1645 MUX(1, 89, 5, N, N, N, N),
1646 MUX(1, 90, 5, N, N, N, N),
1647};
1648
1649static struct atlas7_grp_mux ca_bt_lpc_grp_mux = {
1650 .pad_mux_count = ARRAY_SIZE(ca_bt_lpc_grp_pad_mux),
1651 .pad_mux_list = ca_bt_lpc_grp_pad_mux,
1652};
1653
1654static struct atlas7_pad_mux ca_coex_grp_pad_mux[] = {
1655 MUX(1, 129, 1, N, N, N, N),
1656 MUX(1, 130, 1, N, N, N, N),
1657 MUX(1, 131, 1, N, N, N, N),
1658 MUX(1, 132, 1, N, N, N, N),
1659};
1660
1661static struct atlas7_grp_mux ca_coex_grp_mux = {
1662 .pad_mux_count = ARRAY_SIZE(ca_coex_grp_pad_mux),
1663 .pad_mux_list = ca_coex_grp_pad_mux,
1664};
1665
1666static struct atlas7_pad_mux ca_curator_lpc_grp_pad_mux[] = {
1667 MUX(1, 57, 4, N, N, N, N),
1668 MUX(1, 58, 4, N, N, N, N),
1669 MUX(1, 59, 4, N, N, N, N),
1670 MUX(1, 60, 4, N, N, N, N),
1671};
1672
1673static struct atlas7_grp_mux ca_curator_lpc_grp_mux = {
1674 .pad_mux_count = ARRAY_SIZE(ca_curator_lpc_grp_pad_mux),
1675 .pad_mux_list = ca_curator_lpc_grp_pad_mux,
1676};
1677
1678static struct atlas7_pad_mux ca_pcm_debug_grp_pad_mux[] = {
1679 MUX(1, 91, 5, N, N, N, N),
1680 MUX(1, 93, 5, N, N, N, N),
1681 MUX(1, 94, 5, N, N, N, N),
1682 MUX(1, 92, 5, N, N, N, N),
1683};
1684
1685static struct atlas7_grp_mux ca_pcm_debug_grp_mux = {
1686 .pad_mux_count = ARRAY_SIZE(ca_pcm_debug_grp_pad_mux),
1687 .pad_mux_list = ca_pcm_debug_grp_pad_mux,
1688};
1689
1690static struct atlas7_pad_mux ca_pio_grp_pad_mux[] = {
1691 MUX(1, 121, 2, N, N, N, N),
1692 MUX(1, 122, 2, N, N, N, N),
1693 MUX(1, 125, 6, N, N, N, N),
1694 MUX(1, 126, 6, N, N, N, N),
1695 MUX(1, 38, 5, N, N, N, N),
1696 MUX(1, 37, 5, N, N, N, N),
1697 MUX(1, 47, 5, N, N, N, N),
1698 MUX(1, 49, 5, N, N, N, N),
1699 MUX(1, 50, 5, N, N, N, N),
1700 MUX(1, 54, 4, N, N, N, N),
1701 MUX(1, 55, 4, N, N, N, N),
1702 MUX(1, 56, 4, N, N, N, N),
1703};
1704
1705static struct atlas7_grp_mux ca_pio_grp_mux = {
1706 .pad_mux_count = ARRAY_SIZE(ca_pio_grp_pad_mux),
1707 .pad_mux_list = ca_pio_grp_pad_mux,
1708};
1709
1710static struct atlas7_pad_mux ca_sdio_debug_grp_pad_mux[] = {
1711 MUX(1, 40, 5, N, N, N, N),
1712 MUX(1, 39, 5, N, N, N, N),
1713 MUX(1, 44, 5, N, N, N, N),
1714 MUX(1, 43, 5, N, N, N, N),
1715 MUX(1, 42, 5, N, N, N, N),
1716 MUX(1, 41, 5, N, N, N, N),
1717};
1718
1719static struct atlas7_grp_mux ca_sdio_debug_grp_mux = {
1720 .pad_mux_count = ARRAY_SIZE(ca_sdio_debug_grp_pad_mux),
1721 .pad_mux_list = ca_sdio_debug_grp_pad_mux,
1722};
1723
1724static struct atlas7_pad_mux ca_spi_grp_pad_mux[] = {
1725 MUX(1, 82, 5, N, N, N, N),
1726 MUX(1, 79, 5, 0xa08, 6, 0xa88, 6),
1727 MUX(1, 80, 5, N, N, N, N),
1728 MUX(1, 81, 5, N, N, N, N),
1729};
1730
1731static struct atlas7_grp_mux ca_spi_grp_mux = {
1732 .pad_mux_count = ARRAY_SIZE(ca_spi_grp_pad_mux),
1733 .pad_mux_list = ca_spi_grp_pad_mux,
1734};
1735
1736static struct atlas7_pad_mux ca_trb_grp_pad_mux[] = {
1737 MUX(1, 91, 4, N, N, N, N),
1738 MUX(1, 93, 4, N, N, N, N),
1739 MUX(1, 94, 4, N, N, N, N),
1740 MUX(1, 95, 4, N, N, N, N),
1741 MUX(1, 96, 4, N, N, N, N),
1742 MUX(1, 78, 5, N, N, N, N),
1743 MUX(1, 74, 5, N, N, N, N),
1744 MUX(1, 75, 5, N, N, N, N),
1745 MUX(1, 76, 5, N, N, N, N),
1746 MUX(1, 77, 5, N, N, N, N),
1747};
1748
1749static struct atlas7_grp_mux ca_trb_grp_mux = {
1750 .pad_mux_count = ARRAY_SIZE(ca_trb_grp_pad_mux),
1751 .pad_mux_list = ca_trb_grp_pad_mux,
1752};
1753
1754static struct atlas7_pad_mux ca_uart_debug_grp_pad_mux[] = {
1755 MUX(1, 136, 3, N, N, N, N),
1756 MUX(1, 135, 3, N, N, N, N),
1757 MUX(1, 134, 3, N, N, N, N),
1758 MUX(1, 133, 3, N, N, N, N),
1759};
1760
1761static struct atlas7_grp_mux ca_uart_debug_grp_mux = {
1762 .pad_mux_count = ARRAY_SIZE(ca_uart_debug_grp_pad_mux),
1763 .pad_mux_list = ca_uart_debug_grp_pad_mux,
1764};
1765
1766static struct atlas7_pad_mux clkc_grp0_pad_mux[] = {
1767 MUX(1, 30, 2, 0xa08, 14, 0xa88, 14),
1768 MUX(1, 47, 6, N, N, N, N),
1769};
1770
1771static struct atlas7_grp_mux clkc_grp0_mux = {
1772 .pad_mux_count = ARRAY_SIZE(clkc_grp0_pad_mux),
1773 .pad_mux_list = clkc_grp0_pad_mux,
1774};
1775
1776static struct atlas7_pad_mux clkc_grp1_pad_mux[] = {
1777 MUX(1, 78, 3, 0xa08, 14, 0xa88, 14),
1778 MUX(1, 54, 5, N, N, N, N),
1779};
1780
1781static struct atlas7_grp_mux clkc_grp1_mux = {
1782 .pad_mux_count = ARRAY_SIZE(clkc_grp1_pad_mux),
1783 .pad_mux_list = clkc_grp1_pad_mux,
1784};
1785
1786static struct atlas7_pad_mux gn_gnss_i2c_grp_pad_mux[] = {
1787 MUX(1, 128, 2, N, N, N, N),
1788 MUX(1, 127, 2, N, N, N, N),
1789};
1790
1791static struct atlas7_grp_mux gn_gnss_i2c_grp_mux = {
1792 .pad_mux_count = ARRAY_SIZE(gn_gnss_i2c_grp_pad_mux),
1793 .pad_mux_list = gn_gnss_i2c_grp_pad_mux,
1794};
1795
1796static struct atlas7_pad_mux gn_gnss_uart_nopause_grp_pad_mux[] = {
1797 MUX(1, 134, 4, N, N, N, N),
1798 MUX(1, 133, 4, N, N, N, N),
1799};
1800
1801static struct atlas7_grp_mux gn_gnss_uart_nopause_grp_mux = {
1802 .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_nopause_grp_pad_mux),
1803 .pad_mux_list = gn_gnss_uart_nopause_grp_pad_mux,
1804};
1805
1806static struct atlas7_pad_mux gn_gnss_uart_grp_pad_mux[] = {
1807 MUX(1, 134, 4, N, N, N, N),
1808 MUX(1, 133, 4, N, N, N, N),
1809 MUX(1, 136, 4, N, N, N, N),
1810 MUX(1, 135, 4, N, N, N, N),
1811};
1812
1813static struct atlas7_grp_mux gn_gnss_uart_grp_mux = {
1814 .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_grp_pad_mux),
1815 .pad_mux_list = gn_gnss_uart_grp_pad_mux,
1816};
1817
1818static struct atlas7_pad_mux gn_trg_spi_grp0_pad_mux[] = {
1819 MUX(1, 22, 1, N, N, N, N),
1820 MUX(1, 25, 1, N, N, N, N),
1821 MUX(1, 23, 1, 0xa00, 10, 0xa80, 10),
1822 MUX(1, 24, 1, N, N, N, N),
1823};
1824
1825static struct atlas7_grp_mux gn_trg_spi_grp0_mux = {
1826 .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp0_pad_mux),
1827 .pad_mux_list = gn_trg_spi_grp0_pad_mux,
1828};
1829
1830static struct atlas7_pad_mux gn_trg_spi_grp1_pad_mux[] = {
1831 MUX(1, 82, 3, N, N, N, N),
1832 MUX(1, 79, 3, N, N, N, N),
1833 MUX(1, 80, 3, 0xa00, 10, 0xa80, 10),
1834 MUX(1, 81, 3, N, N, N, N),
1835};
1836
1837static struct atlas7_grp_mux gn_trg_spi_grp1_mux = {
1838 .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp1_pad_mux),
1839 .pad_mux_list = gn_trg_spi_grp1_pad_mux,
1840};
1841
1842static struct atlas7_pad_mux cvbs_dbg_grp_pad_mux[] = {
1843 MUX(1, 54, 3, N, N, N, N),
1844 MUX(1, 53, 3, N, N, N, N),
1845 MUX(1, 82, 7, N, N, N, N),
1846 MUX(1, 74, 7, N, N, N, N),
1847 MUX(1, 75, 7, N, N, N, N),
1848 MUX(1, 76, 7, N, N, N, N),
1849 MUX(1, 77, 7, N, N, N, N),
1850 MUX(1, 78, 7, N, N, N, N),
1851 MUX(1, 79, 7, N, N, N, N),
1852 MUX(1, 80, 7, N, N, N, N),
1853 MUX(1, 81, 7, N, N, N, N),
1854 MUX(1, 83, 7, N, N, N, N),
1855 MUX(1, 84, 7, N, N, N, N),
1856 MUX(1, 73, 3, N, N, N, N),
1857 MUX(1, 55, 3, N, N, N, N),
1858 MUX(1, 56, 3, N, N, N, N),
1859};
1860
1861static struct atlas7_grp_mux cvbs_dbg_grp_mux = {
1862 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_grp_pad_mux),
1863 .pad_mux_list = cvbs_dbg_grp_pad_mux,
1864};
1865
1866static struct atlas7_pad_mux cvbs_dbg_test_grp0_pad_mux[] = {
1867 MUX(1, 57, 3, N, N, N, N),
1868};
1869
1870static struct atlas7_grp_mux cvbs_dbg_test_grp0_mux = {
1871 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp0_pad_mux),
1872 .pad_mux_list = cvbs_dbg_test_grp0_pad_mux,
1873};
1874
1875static struct atlas7_pad_mux cvbs_dbg_test_grp1_pad_mux[] = {
1876 MUX(1, 58, 3, N, N, N, N),
1877};
1878
1879static struct atlas7_grp_mux cvbs_dbg_test_grp1_mux = {
1880 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp1_pad_mux),
1881 .pad_mux_list = cvbs_dbg_test_grp1_pad_mux,
1882};
1883
1884static struct atlas7_pad_mux cvbs_dbg_test_grp2_pad_mux[] = {
1885 MUX(1, 59, 3, N, N, N, N),
1886};
1887
1888static struct atlas7_grp_mux cvbs_dbg_test_grp2_mux = {
1889 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp2_pad_mux),
1890 .pad_mux_list = cvbs_dbg_test_grp2_pad_mux,
1891};
1892
1893static struct atlas7_pad_mux cvbs_dbg_test_grp3_pad_mux[] = {
1894 MUX(1, 60, 3, N, N, N, N),
1895};
1896
1897static struct atlas7_grp_mux cvbs_dbg_test_grp3_mux = {
1898 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp3_pad_mux),
1899 .pad_mux_list = cvbs_dbg_test_grp3_pad_mux,
1900};
1901
1902static struct atlas7_pad_mux cvbs_dbg_test_grp4_pad_mux[] = {
1903 MUX(1, 61, 3, N, N, N, N),
1904};
1905
1906static struct atlas7_grp_mux cvbs_dbg_test_grp4_mux = {
1907 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp4_pad_mux),
1908 .pad_mux_list = cvbs_dbg_test_grp4_pad_mux,
1909};
1910
1911static struct atlas7_pad_mux cvbs_dbg_test_grp5_pad_mux[] = {
1912 MUX(1, 62, 3, N, N, N, N),
1913};
1914
1915static struct atlas7_grp_mux cvbs_dbg_test_grp5_mux = {
1916 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp5_pad_mux),
1917 .pad_mux_list = cvbs_dbg_test_grp5_pad_mux,
1918};
1919
1920static struct atlas7_pad_mux cvbs_dbg_test_grp6_pad_mux[] = {
1921 MUX(1, 63, 3, N, N, N, N),
1922};
1923
1924static struct atlas7_grp_mux cvbs_dbg_test_grp6_mux = {
1925 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp6_pad_mux),
1926 .pad_mux_list = cvbs_dbg_test_grp6_pad_mux,
1927};
1928
1929static struct atlas7_pad_mux cvbs_dbg_test_grp7_pad_mux[] = {
1930 MUX(1, 64, 3, N, N, N, N),
1931};
1932
1933static struct atlas7_grp_mux cvbs_dbg_test_grp7_mux = {
1934 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp7_pad_mux),
1935 .pad_mux_list = cvbs_dbg_test_grp7_pad_mux,
1936};
1937
1938static struct atlas7_pad_mux cvbs_dbg_test_grp8_pad_mux[] = {
1939 MUX(1, 65, 3, N, N, N, N),
1940};
1941
1942static struct atlas7_grp_mux cvbs_dbg_test_grp8_mux = {
1943 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp8_pad_mux),
1944 .pad_mux_list = cvbs_dbg_test_grp8_pad_mux,
1945};
1946
1947static struct atlas7_pad_mux cvbs_dbg_test_grp9_pad_mux[] = {
1948 MUX(1, 66, 3, N, N, N, N),
1949};
1950
1951static struct atlas7_grp_mux cvbs_dbg_test_grp9_mux = {
1952 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp9_pad_mux),
1953 .pad_mux_list = cvbs_dbg_test_grp9_pad_mux,
1954};
1955
1956static struct atlas7_pad_mux cvbs_dbg_test_grp10_pad_mux[] = {
1957 MUX(1, 67, 3, N, N, N, N),
1958};
1959
1960static struct atlas7_grp_mux cvbs_dbg_test_grp10_mux = {
1961 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp10_pad_mux),
1962 .pad_mux_list = cvbs_dbg_test_grp10_pad_mux,
1963};
1964
1965static struct atlas7_pad_mux cvbs_dbg_test_grp11_pad_mux[] = {
1966 MUX(1, 68, 3, N, N, N, N),
1967};
1968
1969static struct atlas7_grp_mux cvbs_dbg_test_grp11_mux = {
1970 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp11_pad_mux),
1971 .pad_mux_list = cvbs_dbg_test_grp11_pad_mux,
1972};
1973
1974static struct atlas7_pad_mux cvbs_dbg_test_grp12_pad_mux[] = {
1975 MUX(1, 69, 3, N, N, N, N),
1976};
1977
1978static struct atlas7_grp_mux cvbs_dbg_test_grp12_mux = {
1979 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp12_pad_mux),
1980 .pad_mux_list = cvbs_dbg_test_grp12_pad_mux,
1981};
1982
1983static struct atlas7_pad_mux cvbs_dbg_test_grp13_pad_mux[] = {
1984 MUX(1, 70, 3, N, N, N, N),
1985};
1986
1987static struct atlas7_grp_mux cvbs_dbg_test_grp13_mux = {
1988 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp13_pad_mux),
1989 .pad_mux_list = cvbs_dbg_test_grp13_pad_mux,
1990};
1991
1992static struct atlas7_pad_mux cvbs_dbg_test_grp14_pad_mux[] = {
1993 MUX(1, 71, 3, N, N, N, N),
1994};
1995
1996static struct atlas7_grp_mux cvbs_dbg_test_grp14_mux = {
1997 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp14_pad_mux),
1998 .pad_mux_list = cvbs_dbg_test_grp14_pad_mux,
1999};
2000
2001static struct atlas7_pad_mux cvbs_dbg_test_grp15_pad_mux[] = {
2002 MUX(1, 72, 3, N, N, N, N),
2003};
2004
2005static struct atlas7_grp_mux cvbs_dbg_test_grp15_mux = {
2006 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp15_pad_mux),
2007 .pad_mux_list = cvbs_dbg_test_grp15_pad_mux,
2008};
2009
2010static struct atlas7_pad_mux gn_gnss_power_grp_pad_mux[] = {
2011 MUX(1, 123, 7, N, N, N, N),
2012 MUX(1, 124, 7, N, N, N, N),
2013 MUX(1, 121, 7, N, N, N, N),
2014 MUX(1, 122, 7, N, N, N, N),
2015 MUX(1, 125, 7, N, N, N, N),
2016 MUX(1, 120, 7, N, N, N, N),
2017};
2018
2019static struct atlas7_grp_mux gn_gnss_power_grp_mux = {
2020 .pad_mux_count = ARRAY_SIZE(gn_gnss_power_grp_pad_mux),
2021 .pad_mux_list = gn_gnss_power_grp_pad_mux,
2022};
2023
2024static struct atlas7_pad_mux gn_gnss_sw_status_grp_pad_mux[] = {
2025 MUX(1, 57, 7, N, N, N, N),
2026 MUX(1, 58, 7, N, N, N, N),
2027 MUX(1, 59, 7, N, N, N, N),
2028 MUX(1, 60, 7, N, N, N, N),
2029 MUX(1, 61, 7, N, N, N, N),
2030 MUX(1, 62, 7, N, N, N, N),
2031 MUX(1, 63, 7, N, N, N, N),
2032 MUX(1, 64, 7, N, N, N, N),
2033 MUX(1, 65, 7, N, N, N, N),
2034 MUX(1, 66, 7, N, N, N, N),
2035 MUX(1, 67, 7, N, N, N, N),
2036 MUX(1, 68, 7, N, N, N, N),
2037 MUX(1, 69, 7, N, N, N, N),
2038 MUX(1, 70, 7, N, N, N, N),
2039 MUX(1, 71, 7, N, N, N, N),
2040 MUX(1, 72, 7, N, N, N, N),
2041 MUX(1, 53, 7, N, N, N, N),
2042 MUX(1, 55, 7, N, N, N, N),
2043 MUX(1, 56, 7, 0xa08, 12, 0xa88, 12),
2044 MUX(1, 54, 7, N, N, N, N),
2045};
2046
2047static struct atlas7_grp_mux gn_gnss_sw_status_grp_mux = {
2048 .pad_mux_count = ARRAY_SIZE(gn_gnss_sw_status_grp_pad_mux),
2049 .pad_mux_list = gn_gnss_sw_status_grp_pad_mux,
2050};
2051
2052static struct atlas7_pad_mux gn_gnss_eclk_grp_pad_mux[] = {
2053 MUX(1, 113, 4, N, N, N, N),
2054};
2055
2056static struct atlas7_grp_mux gn_gnss_eclk_grp_mux = {
2057 .pad_mux_count = ARRAY_SIZE(gn_gnss_eclk_grp_pad_mux),
2058 .pad_mux_list = gn_gnss_eclk_grp_pad_mux,
2059};
2060
2061static struct atlas7_pad_mux gn_gnss_irq1_grp0_pad_mux[] = {
2062 MUX(1, 112, 4, 0xa08, 10, 0xa88, 10),
2063};
2064
2065static struct atlas7_grp_mux gn_gnss_irq1_grp0_mux = {
2066 .pad_mux_count = ARRAY_SIZE(gn_gnss_irq1_grp0_pad_mux),
2067 .pad_mux_list = gn_gnss_irq1_grp0_pad_mux,
2068};
2069
2070static struct atlas7_pad_mux gn_gnss_irq2_grp0_pad_mux[] = {
2071 MUX(1, 118, 4, 0xa08, 11, 0xa88, 11),
2072};
2073
2074static struct atlas7_grp_mux gn_gnss_irq2_grp0_mux = {
2075 .pad_mux_count = ARRAY_SIZE(gn_gnss_irq2_grp0_pad_mux),
2076 .pad_mux_list = gn_gnss_irq2_grp0_pad_mux,
2077};
2078
2079static struct atlas7_pad_mux gn_gnss_tm_grp_pad_mux[] = {
2080 MUX(1, 115, 4, N, N, N, N),
2081};
2082
2083static struct atlas7_grp_mux gn_gnss_tm_grp_mux = {
2084 .pad_mux_count = ARRAY_SIZE(gn_gnss_tm_grp_pad_mux),
2085 .pad_mux_list = gn_gnss_tm_grp_pad_mux,
2086};
2087
2088static struct atlas7_pad_mux gn_gnss_tsync_grp_pad_mux[] = {
2089 MUX(1, 114, 4, N, N, N, N),
2090};
2091
2092static struct atlas7_grp_mux gn_gnss_tsync_grp_mux = {
2093 .pad_mux_count = ARRAY_SIZE(gn_gnss_tsync_grp_pad_mux),
2094 .pad_mux_list = gn_gnss_tsync_grp_pad_mux,
2095};
2096
2097static struct atlas7_pad_mux gn_io_gnsssys_sw_cfg_grp_pad_mux[] = {
2098 MUX(1, 44, 7, N, N, N, N),
2099 MUX(1, 43, 7, N, N, N, N),
2100 MUX(1, 42, 7, N, N, N, N),
2101 MUX(1, 41, 7, N, N, N, N),
2102 MUX(1, 40, 7, N, N, N, N),
2103 MUX(1, 39, 7, N, N, N, N),
2104 MUX(1, 38, 7, N, N, N, N),
2105 MUX(1, 37, 7, N, N, N, N),
2106 MUX(1, 49, 7, N, N, N, N),
2107 MUX(1, 50, 7, N, N, N, N),
2108 MUX(1, 91, 7, N, N, N, N),
2109 MUX(1, 92, 7, N, N, N, N),
2110 MUX(1, 93, 7, N, N, N, N),
2111 MUX(1, 94, 7, N, N, N, N),
2112 MUX(1, 95, 7, N, N, N, N),
2113 MUX(1, 96, 7, N, N, N, N),
2114};
2115
2116static struct atlas7_grp_mux gn_io_gnsssys_sw_cfg_grp_mux = {
2117 .pad_mux_count = ARRAY_SIZE(gn_io_gnsssys_sw_cfg_grp_pad_mux),
2118 .pad_mux_list = gn_io_gnsssys_sw_cfg_grp_pad_mux,
2119};
2120
2121static struct atlas7_pad_mux gn_trg_grp0_pad_mux[] = {
2122 MUX(1, 29, 1, 0xa00, 6, 0xa80, 6),
2123 MUX(1, 28, 1, 0xa00, 7, 0xa80, 7),
2124 MUX(1, 26, 1, 0xa00, 8, 0xa80, 8),
2125 MUX(1, 27, 1, 0xa00, 9, 0xa80, 9),
2126};
2127
2128static struct atlas7_grp_mux gn_trg_grp0_mux = {
2129 .pad_mux_count = ARRAY_SIZE(gn_trg_grp0_pad_mux),
2130 .pad_mux_list = gn_trg_grp0_pad_mux,
2131};
2132
2133static struct atlas7_pad_mux gn_trg_grp1_pad_mux[] = {
2134 MUX(1, 77, 3, 0xa00, 6, 0xa80, 6),
2135 MUX(1, 76, 3, 0xa00, 7, 0xa80, 7),
2136 MUX(1, 74, 3, 0xa00, 8, 0xa80, 8),
2137 MUX(1, 75, 3, 0xa00, 9, 0xa80, 9),
2138};
2139
2140static struct atlas7_grp_mux gn_trg_grp1_mux = {
2141 .pad_mux_count = ARRAY_SIZE(gn_trg_grp1_pad_mux),
2142 .pad_mux_list = gn_trg_grp1_pad_mux,
2143};
2144
2145static struct atlas7_pad_mux gn_trg_shutdown_grp0_pad_mux[] = {
2146 MUX(1, 30, 1, N, N, N, N),
2147};
2148
2149static struct atlas7_grp_mux gn_trg_shutdown_grp0_mux = {
2150 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp0_pad_mux),
2151 .pad_mux_list = gn_trg_shutdown_grp0_pad_mux,
2152};
2153
2154static struct atlas7_pad_mux gn_trg_shutdown_grp1_pad_mux[] = {
2155 MUX(1, 83, 3, N, N, N, N),
2156};
2157
2158static struct atlas7_grp_mux gn_trg_shutdown_grp1_mux = {
2159 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp1_pad_mux),
2160 .pad_mux_list = gn_trg_shutdown_grp1_pad_mux,
2161};
2162
2163static struct atlas7_pad_mux gn_trg_shutdown_grp2_pad_mux[] = {
2164 MUX(1, 117, 4, N, N, N, N),
2165};
2166
2167static struct atlas7_grp_mux gn_trg_shutdown_grp2_mux = {
2168 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp2_pad_mux),
2169 .pad_mux_list = gn_trg_shutdown_grp2_pad_mux,
2170};
2171
2172static struct atlas7_pad_mux gn_trg_shutdown_grp3_pad_mux[] = {
2173 MUX(1, 123, 5, N, N, N, N),
2174};
2175
2176static struct atlas7_grp_mux gn_trg_shutdown_grp3_mux = {
2177 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp3_pad_mux),
2178 .pad_mux_list = gn_trg_shutdown_grp3_pad_mux,
2179};
2180
2181static struct atlas7_pad_mux i2c0_grp_pad_mux[] = {
2182 MUX(1, 128, 1, N, N, N, N),
2183 MUX(1, 127, 1, N, N, N, N),
2184};
2185
2186static struct atlas7_grp_mux i2c0_grp_mux = {
2187 .pad_mux_count = ARRAY_SIZE(i2c0_grp_pad_mux),
2188 .pad_mux_list = i2c0_grp_pad_mux,
2189};
2190
2191static struct atlas7_pad_mux i2c1_grp_pad_mux[] = {
2192 MUX(1, 126, 4, N, N, N, N),
2193 MUX(1, 125, 4, N, N, N, N),
2194};
2195
2196static struct atlas7_grp_mux i2c1_grp_mux = {
2197 .pad_mux_count = ARRAY_SIZE(i2c1_grp_pad_mux),
2198 .pad_mux_list = i2c1_grp_pad_mux,
2199};
2200
2201static struct atlas7_pad_mux jtag_grp0_pad_mux[] = {
2202 MUX(1, 125, 5, 0xa08, 2, 0xa88, 2),
2203 MUX(0, 4, 3, 0xa08, 3, 0xa88, 3),
2204 MUX(0, 2, 3, N, N, N, N),
2205 MUX(0, 0, 3, N, N, N, N),
2206 MUX(0, 1, 3, N, N, N, N),
2207 MUX(0, 3, 3, N, N, N, N),
2208};
2209
2210static struct atlas7_grp_mux jtag_grp0_mux = {
2211 .pad_mux_count = ARRAY_SIZE(jtag_grp0_pad_mux),
2212 .pad_mux_list = jtag_grp0_pad_mux,
2213};
2214
2215static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = {
2216 MUX(1, 141, 2, N, N, N, N),
2217 MUX(1, 144, 2, 0xa08, 8, 0xa88, 8),
2218 MUX(1, 143, 2, N, N, N, N),
2219 MUX(1, 142, 2, N, N, N, N),
2220};
2221
2222static struct atlas7_grp_mux ks_kas_spi_grp0_mux = {
2223 .pad_mux_count = ARRAY_SIZE(ks_kas_spi_grp0_pad_mux),
2224 .pad_mux_list = ks_kas_spi_grp0_pad_mux,
2225};
2226
2227static struct atlas7_pad_mux ld_ldd_grp_pad_mux[] = {
2228 MUX(1, 57, 1, N, N, N, N),
2229 MUX(1, 58, 1, N, N, N, N),
2230 MUX(1, 59, 1, N, N, N, N),
2231 MUX(1, 60, 1, N, N, N, N),
2232 MUX(1, 61, 1, N, N, N, N),
2233 MUX(1, 62, 1, N, N, N, N),
2234 MUX(1, 63, 1, N, N, N, N),
2235 MUX(1, 64, 1, N, N, N, N),
2236 MUX(1, 65, 1, N, N, N, N),
2237 MUX(1, 66, 1, N, N, N, N),
2238 MUX(1, 67, 1, N, N, N, N),
2239 MUX(1, 68, 1, N, N, N, N),
2240 MUX(1, 69, 1, N, N, N, N),
2241 MUX(1, 70, 1, N, N, N, N),
2242 MUX(1, 71, 1, N, N, N, N),
2243 MUX(1, 72, 1, N, N, N, N),
2244 MUX(1, 74, 2, N, N, N, N),
2245 MUX(1, 75, 2, N, N, N, N),
2246 MUX(1, 76, 2, N, N, N, N),
2247 MUX(1, 77, 2, N, N, N, N),
2248 MUX(1, 78, 2, N, N, N, N),
2249 MUX(1, 79, 2, N, N, N, N),
2250 MUX(1, 80, 2, N, N, N, N),
2251 MUX(1, 81, 2, N, N, N, N),
2252 MUX(1, 56, 1, N, N, N, N),
2253 MUX(1, 53, 1, N, N, N, N),
2254};
2255
2256static struct atlas7_grp_mux ld_ldd_grp_mux = {
2257 .pad_mux_count = ARRAY_SIZE(ld_ldd_grp_pad_mux),
2258 .pad_mux_list = ld_ldd_grp_pad_mux,
2259};
2260
2261static struct atlas7_pad_mux ld_ldd_16bit_grp_pad_mux[] = {
2262 MUX(1, 57, 1, N, N, N, N),
2263 MUX(1, 58, 1, N, N, N, N),
2264 MUX(1, 59, 1, N, N, N, N),
2265 MUX(1, 60, 1, N, N, N, N),
2266 MUX(1, 61, 1, N, N, N, N),
2267 MUX(1, 62, 1, N, N, N, N),
2268 MUX(1, 63, 1, N, N, N, N),
2269 MUX(1, 64, 1, N, N, N, N),
2270 MUX(1, 65, 1, N, N, N, N),
2271 MUX(1, 66, 1, N, N, N, N),
2272 MUX(1, 67, 1, N, N, N, N),
2273 MUX(1, 68, 1, N, N, N, N),
2274 MUX(1, 69, 1, N, N, N, N),
2275 MUX(1, 70, 1, N, N, N, N),
2276 MUX(1, 71, 1, N, N, N, N),
2277 MUX(1, 72, 1, N, N, N, N),
2278 MUX(1, 56, 1, N, N, N, N),
2279 MUX(1, 53, 1, N, N, N, N),
2280};
2281
2282static struct atlas7_grp_mux ld_ldd_16bit_grp_mux = {
2283 .pad_mux_count = ARRAY_SIZE(ld_ldd_16bit_grp_pad_mux),
2284 .pad_mux_list = ld_ldd_16bit_grp_pad_mux,
2285};
2286
2287static struct atlas7_pad_mux ld_ldd_fck_grp_pad_mux[] = {
2288 MUX(1, 55, 1, N, N, N, N),
2289};
2290
2291static struct atlas7_grp_mux ld_ldd_fck_grp_mux = {
2292 .pad_mux_count = ARRAY_SIZE(ld_ldd_fck_grp_pad_mux),
2293 .pad_mux_list = ld_ldd_fck_grp_pad_mux,
2294};
2295
2296static struct atlas7_pad_mux ld_ldd_lck_grp_pad_mux[] = {
2297 MUX(1, 54, 1, N, N, N, N),
2298};
2299
2300static struct atlas7_grp_mux ld_ldd_lck_grp_mux = {
2301 .pad_mux_count = ARRAY_SIZE(ld_ldd_lck_grp_pad_mux),
2302 .pad_mux_list = ld_ldd_lck_grp_pad_mux,
2303};
2304
2305static struct atlas7_pad_mux lr_lcdrom_grp_pad_mux[] = {
2306 MUX(1, 73, 2, N, N, N, N),
2307 MUX(1, 54, 2, N, N, N, N),
2308 MUX(1, 57, 2, N, N, N, N),
2309 MUX(1, 58, 2, N, N, N, N),
2310 MUX(1, 59, 2, N, N, N, N),
2311 MUX(1, 60, 2, N, N, N, N),
2312 MUX(1, 61, 2, N, N, N, N),
2313 MUX(1, 62, 2, N, N, N, N),
2314 MUX(1, 63, 2, N, N, N, N),
2315 MUX(1, 64, 2, N, N, N, N),
2316 MUX(1, 65, 2, N, N, N, N),
2317 MUX(1, 66, 2, N, N, N, N),
2318 MUX(1, 67, 2, N, N, N, N),
2319 MUX(1, 68, 2, N, N, N, N),
2320 MUX(1, 69, 2, N, N, N, N),
2321 MUX(1, 70, 2, N, N, N, N),
2322 MUX(1, 71, 2, N, N, N, N),
2323 MUX(1, 72, 2, N, N, N, N),
2324 MUX(1, 56, 2, N, N, N, N),
2325 MUX(1, 53, 2, N, N, N, N),
2326 MUX(1, 55, 2, N, N, N, N),
2327};
2328
2329static struct atlas7_grp_mux lr_lcdrom_grp_mux = {
2330 .pad_mux_count = ARRAY_SIZE(lr_lcdrom_grp_pad_mux),
2331 .pad_mux_list = lr_lcdrom_grp_pad_mux,
2332};
2333
2334static struct atlas7_pad_mux lvds_analog_grp_pad_mux[] = {
2335 MUX(1, 149, 8, N, N, N, N),
2336 MUX(1, 150, 8, N, N, N, N),
2337 MUX(1, 151, 8, N, N, N, N),
2338 MUX(1, 152, 8, N, N, N, N),
2339 MUX(1, 153, 8, N, N, N, N),
2340 MUX(1, 154, 8, N, N, N, N),
2341 MUX(1, 155, 8, N, N, N, N),
2342 MUX(1, 156, 8, N, N, N, N),
2343 MUX(1, 157, 8, N, N, N, N),
2344 MUX(1, 158, 8, N, N, N, N),
2345};
2346
2347static struct atlas7_grp_mux lvds_analog_grp_mux = {
2348 .pad_mux_count = ARRAY_SIZE(lvds_analog_grp_pad_mux),
2349 .pad_mux_list = lvds_analog_grp_pad_mux,
2350};
2351
2352static struct atlas7_pad_mux nd_df_grp_pad_mux[] = {
2353 MUX(1, 44, 1, N, N, N, N),
2354 MUX(1, 43, 1, N, N, N, N),
2355 MUX(1, 42, 1, N, N, N, N),
2356 MUX(1, 41, 1, N, N, N, N),
2357 MUX(1, 40, 1, N, N, N, N),
2358 MUX(1, 39, 1, N, N, N, N),
2359 MUX(1, 38, 1, N, N, N, N),
2360 MUX(1, 37, 1, N, N, N, N),
2361 MUX(1, 47, 1, N, N, N, N),
2362 MUX(1, 46, 1, N, N, N, N),
2363 MUX(1, 52, 1, N, N, N, N),
2364 MUX(1, 51, 1, N, N, N, N),
2365 MUX(1, 45, 1, N, N, N, N),
2366 MUX(1, 49, 1, N, N, N, N),
2367 MUX(1, 50, 1, N, N, N, N),
2368 MUX(1, 48, 1, N, N, N, N),
2369 MUX(1, 124, 4, N, N, N, N),
2370};
2371
2372static struct atlas7_grp_mux nd_df_grp_mux = {
2373 .pad_mux_count = ARRAY_SIZE(nd_df_grp_pad_mux),
2374 .pad_mux_list = nd_df_grp_pad_mux,
2375};
2376
2377static struct atlas7_pad_mux nd_df_nowp_grp_pad_mux[] = {
2378 MUX(1, 44, 1, N, N, N, N),
2379 MUX(1, 43, 1, N, N, N, N),
2380 MUX(1, 42, 1, N, N, N, N),
2381 MUX(1, 41, 1, N, N, N, N),
2382 MUX(1, 40, 1, N, N, N, N),
2383 MUX(1, 39, 1, N, N, N, N),
2384 MUX(1, 38, 1, N, N, N, N),
2385 MUX(1, 37, 1, N, N, N, N),
2386 MUX(1, 47, 1, N, N, N, N),
2387 MUX(1, 46, 1, N, N, N, N),
2388 MUX(1, 52, 1, N, N, N, N),
2389 MUX(1, 51, 1, N, N, N, N),
2390 MUX(1, 45, 1, N, N, N, N),
2391 MUX(1, 49, 1, N, N, N, N),
2392 MUX(1, 50, 1, N, N, N, N),
2393 MUX(1, 48, 1, N, N, N, N),
2394};
2395
2396static struct atlas7_grp_mux nd_df_nowp_grp_mux = {
2397 .pad_mux_count = ARRAY_SIZE(nd_df_nowp_grp_pad_mux),
2398 .pad_mux_list = nd_df_nowp_grp_pad_mux,
2399};
2400
2401static struct atlas7_pad_mux ps_grp_pad_mux[] = {
2402 MUX(1, 120, 2, N, N, N, N),
2403 MUX(1, 119, 2, N, N, N, N),
2404};
2405
2406static struct atlas7_grp_mux ps_grp_mux = {
2407 .pad_mux_count = ARRAY_SIZE(ps_grp_pad_mux),
2408 .pad_mux_list = ps_grp_pad_mux,
2409};
2410
2411static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = {
2412 MUX(0, 8, 1, N, N, N, N),
2413};
2414
2415static struct atlas7_grp_mux pwc_core_on_grp_mux = {
2416 .pad_mux_count = ARRAY_SIZE(pwc_core_on_grp_pad_mux),
2417 .pad_mux_list = pwc_core_on_grp_pad_mux,
2418};
2419
2420static struct atlas7_pad_mux pwc_ext_on_grp_pad_mux[] = {
2421 MUX(0, 6, 1, N, N, N, N),
2422};
2423
2424static struct atlas7_grp_mux pwc_ext_on_grp_mux = {
2425 .pad_mux_count = ARRAY_SIZE(pwc_ext_on_grp_pad_mux),
2426 .pad_mux_list = pwc_ext_on_grp_pad_mux,
2427};
2428
2429static struct atlas7_pad_mux pwc_gpio3_clk_grp_pad_mux[] = {
2430 MUX(0, 3, 4, N, N, N, N),
2431};
2432
2433static struct atlas7_grp_mux pwc_gpio3_clk_grp_mux = {
2434 .pad_mux_count = ARRAY_SIZE(pwc_gpio3_clk_grp_pad_mux),
2435 .pad_mux_list = pwc_gpio3_clk_grp_pad_mux,
2436};
2437
2438static struct atlas7_pad_mux pwc_io_on_grp_pad_mux[] = {
2439 MUX(0, 9, 1, N, N, N, N),
2440};
2441
2442static struct atlas7_grp_mux pwc_io_on_grp_mux = {
2443 .pad_mux_count = ARRAY_SIZE(pwc_io_on_grp_pad_mux),
2444 .pad_mux_list = pwc_io_on_grp_pad_mux,
2445};
2446
2447static struct atlas7_pad_mux pwc_lowbatt_b_grp0_pad_mux[] = {
2448 MUX(0, 4, 1, 0xa08, 4, 0xa88, 4),
2449};
2450
2451static struct atlas7_grp_mux pwc_lowbatt_b_grp0_mux = {
2452 .pad_mux_count = ARRAY_SIZE(pwc_lowbatt_b_grp0_pad_mux),
2453 .pad_mux_list = pwc_lowbatt_b_grp0_pad_mux,
2454};
2455
2456static struct atlas7_pad_mux pwc_mem_on_grp_pad_mux[] = {
2457 MUX(0, 7, 1, N, N, N, N),
2458};
2459
2460static struct atlas7_grp_mux pwc_mem_on_grp_mux = {
2461 .pad_mux_count = ARRAY_SIZE(pwc_mem_on_grp_pad_mux),
2462 .pad_mux_list = pwc_mem_on_grp_pad_mux,
2463};
2464
2465static struct atlas7_pad_mux pwc_on_key_b_grp0_pad_mux[] = {
2466 MUX(0, 5, 1, 0xa08, 5, 0xa88, 5),
2467};
2468
2469static struct atlas7_grp_mux pwc_on_key_b_grp0_mux = {
2470 .pad_mux_count = ARRAY_SIZE(pwc_on_key_b_grp0_pad_mux),
2471 .pad_mux_list = pwc_on_key_b_grp0_pad_mux,
2472};
2473
2474static struct atlas7_pad_mux pwc_wakeup_src0_grp_pad_mux[] = {
2475 MUX(0, 0, 1, N, N, N, N),
2476};
2477
2478static struct atlas7_grp_mux pwc_wakeup_src0_grp_mux = {
2479 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src0_grp_pad_mux),
2480 .pad_mux_list = pwc_wakeup_src0_grp_pad_mux,
2481};
2482
2483static struct atlas7_pad_mux pwc_wakeup_src1_grp_pad_mux[] = {
2484 MUX(0, 1, 1, N, N, N, N),
2485};
2486
2487static struct atlas7_grp_mux pwc_wakeup_src1_grp_mux = {
2488 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src1_grp_pad_mux),
2489 .pad_mux_list = pwc_wakeup_src1_grp_pad_mux,
2490};
2491
2492static struct atlas7_pad_mux pwc_wakeup_src2_grp_pad_mux[] = {
2493 MUX(0, 2, 1, N, N, N, N),
2494};
2495
2496static struct atlas7_grp_mux pwc_wakeup_src2_grp_mux = {
2497 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src2_grp_pad_mux),
2498 .pad_mux_list = pwc_wakeup_src2_grp_pad_mux,
2499};
2500
2501static struct atlas7_pad_mux pwc_wakeup_src3_grp_pad_mux[] = {
2502 MUX(0, 3, 1, N, N, N, N),
2503};
2504
2505static struct atlas7_grp_mux pwc_wakeup_src3_grp_mux = {
2506 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src3_grp_pad_mux),
2507 .pad_mux_list = pwc_wakeup_src3_grp_pad_mux,
2508};
2509
2510static struct atlas7_pad_mux pw_cko0_grp0_pad_mux[] = {
2511 MUX(1, 123, 3, N, N, N, N),
2512};
2513
2514static struct atlas7_grp_mux pw_cko0_grp0_mux = {
2515 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp0_pad_mux),
2516 .pad_mux_list = pw_cko0_grp0_pad_mux,
2517};
2518
2519static struct atlas7_pad_mux pw_cko0_grp1_pad_mux[] = {
2520 MUX(1, 101, 4, N, N, N, N),
2521};
2522
2523static struct atlas7_grp_mux pw_cko0_grp1_mux = {
2524 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp1_pad_mux),
2525 .pad_mux_list = pw_cko0_grp1_pad_mux,
2526};
2527
2528static struct atlas7_pad_mux pw_cko0_grp2_pad_mux[] = {
2529 MUX(1, 82, 2, N, N, N, N),
2530};
2531
2532static struct atlas7_grp_mux pw_cko0_grp2_mux = {
2533 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp2_pad_mux),
2534 .pad_mux_list = pw_cko0_grp2_pad_mux,
2535};
2536
2537static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = {
2538 MUX(1, 124, 3, N, N, N, N),
2539};
2540
2541static struct atlas7_grp_mux pw_cko1_grp0_mux = {
2542 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp0_pad_mux),
2543 .pad_mux_list = pw_cko1_grp0_pad_mux,
2544};
2545
2546static struct atlas7_pad_mux pw_cko1_grp1_pad_mux[] = {
2547 MUX(1, 110, 4, N, N, N, N),
2548};
2549
2550static struct atlas7_grp_mux pw_cko1_grp1_mux = {
2551 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp1_pad_mux),
2552 .pad_mux_list = pw_cko1_grp1_pad_mux,
2553};
2554
2555static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = {
2556 MUX(1, 125, 3, N, N, N, N),
2557};
2558
2559static struct atlas7_grp_mux pw_i2s01_clk_grp0_mux = {
2560 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp0_pad_mux),
2561 .pad_mux_list = pw_i2s01_clk_grp0_pad_mux,
2562};
2563
2564static struct atlas7_pad_mux pw_i2s01_clk_grp1_pad_mux[] = {
2565 MUX(1, 117, 3, N, N, N, N),
2566};
2567
2568static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = {
2569 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp1_pad_mux),
2570 .pad_mux_list = pw_i2s01_clk_grp1_pad_mux,
2571};
2572
2573static struct atlas7_pad_mux pw_pwm0_grp_pad_mux[] = {
2574 MUX(1, 119, 3, N, N, N, N),
2575};
2576
2577static struct atlas7_grp_mux pw_pwm0_grp_mux = {
2578 .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp_pad_mux),
2579 .pad_mux_list = pw_pwm0_grp_pad_mux,
2580};
2581
2582static struct atlas7_pad_mux pw_pwm1_grp_pad_mux[] = {
2583 MUX(1, 120, 3, N, N, N, N),
2584};
2585
2586static struct atlas7_grp_mux pw_pwm1_grp_mux = {
2587 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp_pad_mux),
2588 .pad_mux_list = pw_pwm1_grp_pad_mux,
2589};
2590
2591static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = {
2592 MUX(1, 121, 3, N, N, N, N),
2593};
2594
2595static struct atlas7_grp_mux pw_pwm2_grp0_mux = {
2596 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp0_pad_mux),
2597 .pad_mux_list = pw_pwm2_grp0_pad_mux,
2598};
2599
2600static struct atlas7_pad_mux pw_pwm2_grp1_pad_mux[] = {
2601 MUX(1, 98, 3, N, N, N, N),
2602};
2603
2604static struct atlas7_grp_mux pw_pwm2_grp1_mux = {
2605 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp1_pad_mux),
2606 .pad_mux_list = pw_pwm2_grp1_pad_mux,
2607};
2608
2609static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = {
2610 MUX(1, 122, 3, N, N, N, N),
2611};
2612
2613static struct atlas7_grp_mux pw_pwm3_grp0_mux = {
2614 .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp0_pad_mux),
2615 .pad_mux_list = pw_pwm3_grp0_pad_mux,
2616};
2617
2618static struct atlas7_pad_mux pw_pwm3_grp1_pad_mux[] = {
2619 MUX(1, 73, 4, N, N, N, N),
2620};
2621
2622static struct atlas7_grp_mux pw_pwm3_grp1_mux = {
2623 .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp1_pad_mux),
2624 .pad_mux_list = pw_pwm3_grp1_pad_mux,
2625};
2626
2627static struct atlas7_pad_mux pw_pwm_cpu_vol_grp0_pad_mux[] = {
2628 MUX(1, 121, 3, N, N, N, N),
2629};
2630
2631static struct atlas7_grp_mux pw_pwm_cpu_vol_grp0_mux = {
2632 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp0_pad_mux),
2633 .pad_mux_list = pw_pwm_cpu_vol_grp0_pad_mux,
2634};
2635
2636static struct atlas7_pad_mux pw_pwm_cpu_vol_grp1_pad_mux[] = {
2637 MUX(1, 98, 3, N, N, N, N),
2638};
2639
2640static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = {
2641 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp1_pad_mux),
2642 .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux,
2643};
2644
2645static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = {
2646 MUX(1, 122, 3, N, N, N, N),
2647};
2648
2649static struct atlas7_grp_mux pw_backlight_grp0_mux = {
2650 .pad_mux_count = ARRAY_SIZE(pw_backlight_grp0_pad_mux),
2651 .pad_mux_list = pw_backlight_grp0_pad_mux,
2652};
2653
2654static struct atlas7_pad_mux pw_backlight_grp1_pad_mux[] = {
2655 MUX(1, 73, 4, N, N, N, N),
2656};
2657
2658static struct atlas7_grp_mux pw_backlight_grp1_mux = {
2659 .pad_mux_count = ARRAY_SIZE(pw_backlight_grp1_pad_mux),
2660 .pad_mux_list = pw_backlight_grp1_pad_mux,
2661};
2662
2663static struct atlas7_pad_mux rg_eth_mac_grp_pad_mux[] = {
2664 MUX(1, 108, 1, N, N, N, N),
2665 MUX(1, 103, 1, N, N, N, N),
2666 MUX(1, 104, 1, N, N, N, N),
2667 MUX(1, 105, 1, N, N, N, N),
2668 MUX(1, 106, 1, N, N, N, N),
2669 MUX(1, 107, 1, N, N, N, N),
2670 MUX(1, 102, 1, N, N, N, N),
2671 MUX(1, 97, 1, N, N, N, N),
2672 MUX(1, 98, 1, N, N, N, N),
2673 MUX(1, 99, 1, N, N, N, N),
2674 MUX(1, 100, 1, N, N, N, N),
2675 MUX(1, 101, 1, N, N, N, N),
2676};
2677
2678static struct atlas7_grp_mux rg_eth_mac_grp_mux = {
2679 .pad_mux_count = ARRAY_SIZE(rg_eth_mac_grp_pad_mux),
2680 .pad_mux_list = rg_eth_mac_grp_pad_mux,
2681};
2682
2683static struct atlas7_pad_mux rg_gmac_phy_intr_n_grp_pad_mux[] = {
2684 MUX(1, 111, 1, 0xa08, 13, 0xa88, 13),
2685};
2686
2687static struct atlas7_grp_mux rg_gmac_phy_intr_n_grp_mux = {
2688 .pad_mux_count = ARRAY_SIZE(rg_gmac_phy_intr_n_grp_pad_mux),
2689 .pad_mux_list = rg_gmac_phy_intr_n_grp_pad_mux,
2690};
2691
2692static struct atlas7_pad_mux rg_rgmii_mac_grp_pad_mux[] = {
2693 MUX(1, 109, 1, N, N, N, N),
2694 MUX(1, 110, 1, N, N, N, N),
2695};
2696
2697static struct atlas7_grp_mux rg_rgmii_mac_grp_mux = {
2698 .pad_mux_count = ARRAY_SIZE(rg_rgmii_mac_grp_pad_mux),
2699 .pad_mux_list = rg_rgmii_mac_grp_pad_mux,
2700};
2701
2702static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp0_pad_mux[] = {
2703 MUX(1, 111, 5, N, N, N, N),
2704};
2705
2706static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp0_mux = {
2707 .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp0_pad_mux),
2708 .pad_mux_list = rg_rgmii_phy_ref_clk_grp0_pad_mux,
2709};
2710
2711static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp1_pad_mux[] = {
2712 MUX(1, 53, 4, N, N, N, N),
2713};
2714
2715static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp1_mux = {
2716 .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp1_pad_mux),
2717 .pad_mux_list = rg_rgmii_phy_ref_clk_grp1_pad_mux,
2718};
2719
2720static struct atlas7_pad_mux sd0_grp_pad_mux[] = {
2721 MUX(1, 46, 2, N, N, N, N),
2722 MUX(1, 47, 2, N, N, N, N),
2723 MUX(1, 44, 2, N, N, N, N),
2724 MUX(1, 43, 2, N, N, N, N),
2725 MUX(1, 42, 2, N, N, N, N),
2726 MUX(1, 41, 2, N, N, N, N),
2727 MUX(1, 40, 2, N, N, N, N),
2728 MUX(1, 39, 2, N, N, N, N),
2729 MUX(1, 38, 2, N, N, N, N),
2730 MUX(1, 37, 2, N, N, N, N),
2731};
2732
2733static struct atlas7_grp_mux sd0_grp_mux = {
2734 .pad_mux_count = ARRAY_SIZE(sd0_grp_pad_mux),
2735 .pad_mux_list = sd0_grp_pad_mux,
2736};
2737
2738static struct atlas7_pad_mux sd0_4bit_grp_pad_mux[] = {
2739 MUX(1, 46, 2, N, N, N, N),
2740 MUX(1, 47, 2, N, N, N, N),
2741 MUX(1, 44, 2, N, N, N, N),
2742 MUX(1, 43, 2, N, N, N, N),
2743 MUX(1, 42, 2, N, N, N, N),
2744 MUX(1, 41, 2, N, N, N, N),
2745};
2746
2747static struct atlas7_grp_mux sd0_4bit_grp_mux = {
2748 .pad_mux_count = ARRAY_SIZE(sd0_4bit_grp_pad_mux),
2749 .pad_mux_list = sd0_4bit_grp_pad_mux,
2750};
2751
2752static struct atlas7_pad_mux sd1_grp_pad_mux[] = {
2753 MUX(1, 48, 3, N, N, N, N),
2754 MUX(1, 49, 3, N, N, N, N),
2755 MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
2756 MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
2757 MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
2758 MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
2759 MUX(1, 40, 3, N, N, N, N),
2760 MUX(1, 39, 3, N, N, N, N),
2761 MUX(1, 38, 3, N, N, N, N),
2762 MUX(1, 37, 3, N, N, N, N),
2763};
2764
2765static struct atlas7_grp_mux sd1_grp_mux = {
2766 .pad_mux_count = ARRAY_SIZE(sd1_grp_pad_mux),
2767 .pad_mux_list = sd1_grp_pad_mux,
2768};
2769
2770static struct atlas7_pad_mux sd1_4bit_grp0_pad_mux[] = {
2771 MUX(1, 48, 3, N, N, N, N),
2772 MUX(1, 49, 3, N, N, N, N),
2773 MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
2774 MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
2775 MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
2776 MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
2777};
2778
2779static struct atlas7_grp_mux sd1_4bit_grp0_mux = {
2780 .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp0_pad_mux),
2781 .pad_mux_list = sd1_4bit_grp0_pad_mux,
2782};
2783
2784static struct atlas7_pad_mux sd1_4bit_grp1_pad_mux[] = {
2785 MUX(1, 48, 3, N, N, N, N),
2786 MUX(1, 49, 3, N, N, N, N),
2787 MUX(1, 40, 4, 0xa00, 0, 0xa80, 0),
2788 MUX(1, 39, 4, 0xa00, 1, 0xa80, 1),
2789 MUX(1, 38, 4, 0xa00, 2, 0xa80, 2),
2790 MUX(1, 37, 4, 0xa00, 3, 0xa80, 3),
2791};
2792
2793static struct atlas7_grp_mux sd1_4bit_grp1_mux = {
2794 .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp1_pad_mux),
2795 .pad_mux_list = sd1_4bit_grp1_pad_mux,
2796};
2797
2798static struct atlas7_pad_mux sd2_grp0_pad_mux[] = {
2799 MUX(1, 124, 2, 0xa08, 7, 0xa88, 7),
2800 MUX(1, 31, 1, N, N, N, N),
2801 MUX(1, 32, 1, N, N, N, N),
2802 MUX(1, 33, 1, N, N, N, N),
2803 MUX(1, 34, 1, N, N, N, N),
2804 MUX(1, 35, 1, N, N, N, N),
2805 MUX(1, 36, 1, N, N, N, N),
2806 MUX(1, 123, 2, N, N, N, N),
2807};
2808
2809static struct atlas7_grp_mux sd2_grp0_mux = {
2810 .pad_mux_count = ARRAY_SIZE(sd2_grp0_pad_mux),
2811 .pad_mux_list = sd2_grp0_pad_mux,
2812};
2813
2814static struct atlas7_pad_mux sd2_no_cdb_grp0_pad_mux[] = {
2815 MUX(1, 31, 1, N, N, N, N),
2816 MUX(1, 32, 1, N, N, N, N),
2817 MUX(1, 33, 1, N, N, N, N),
2818 MUX(1, 34, 1, N, N, N, N),
2819 MUX(1, 35, 1, N, N, N, N),
2820 MUX(1, 36, 1, N, N, N, N),
2821 MUX(1, 123, 2, N, N, N, N),
2822};
2823
2824static struct atlas7_grp_mux sd2_no_cdb_grp0_mux = {
2825 .pad_mux_count = ARRAY_SIZE(sd2_no_cdb_grp0_pad_mux),
2826 .pad_mux_list = sd2_no_cdb_grp0_pad_mux,
2827};
2828
2829static struct atlas7_pad_mux sd3_grp_pad_mux[] = {
2830 MUX(1, 85, 1, N, N, N, N),
2831 MUX(1, 86, 1, N, N, N, N),
2832 MUX(1, 87, 1, N, N, N, N),
2833 MUX(1, 88, 1, N, N, N, N),
2834 MUX(1, 89, 1, N, N, N, N),
2835 MUX(1, 90, 1, N, N, N, N),
2836};
2837
2838static struct atlas7_grp_mux sd3_grp_mux = {
2839 .pad_mux_count = ARRAY_SIZE(sd3_grp_pad_mux),
2840 .pad_mux_list = sd3_grp_pad_mux,
2841};
2842
2843static struct atlas7_pad_mux sd5_grp_pad_mux[] = {
2844 MUX(1, 91, 1, N, N, N, N),
2845 MUX(1, 92, 1, N, N, N, N),
2846 MUX(1, 93, 1, N, N, N, N),
2847 MUX(1, 94, 1, N, N, N, N),
2848 MUX(1, 95, 1, N, N, N, N),
2849 MUX(1, 96, 1, N, N, N, N),
2850};
2851
2852static struct atlas7_grp_mux sd5_grp_mux = {
2853 .pad_mux_count = ARRAY_SIZE(sd5_grp_pad_mux),
2854 .pad_mux_list = sd5_grp_pad_mux,
2855};
2856
2857static struct atlas7_pad_mux sd6_grp0_pad_mux[] = {
2858 MUX(1, 79, 4, 0xa00, 27, 0xa80, 27),
2859 MUX(1, 78, 4, 0xa00, 26, 0xa80, 26),
2860 MUX(1, 74, 4, 0xa00, 28, 0xa80, 28),
2861 MUX(1, 75, 4, 0xa00, 29, 0xa80, 29),
2862 MUX(1, 76, 4, 0xa00, 30, 0xa80, 30),
2863 MUX(1, 77, 4, 0xa00, 31, 0xa80, 31),
2864};
2865
2866static struct atlas7_grp_mux sd6_grp0_mux = {
2867 .pad_mux_count = ARRAY_SIZE(sd6_grp0_pad_mux),
2868 .pad_mux_list = sd6_grp0_pad_mux,
2869};
2870
2871static struct atlas7_pad_mux sd6_grp1_pad_mux[] = {
2872 MUX(1, 101, 3, 0xa00, 27, 0xa80, 27),
2873 MUX(1, 99, 3, 0xa00, 26, 0xa80, 26),
2874 MUX(1, 100, 3, 0xa00, 28, 0xa80, 28),
2875 MUX(1, 110, 3, 0xa00, 29, 0xa80, 29),
2876 MUX(1, 109, 3, 0xa00, 30, 0xa80, 30),
2877 MUX(1, 111, 3, 0xa00, 31, 0xa80, 31),
2878};
2879
2880static struct atlas7_grp_mux sd6_grp1_mux = {
2881 .pad_mux_count = ARRAY_SIZE(sd6_grp1_pad_mux),
2882 .pad_mux_list = sd6_grp1_pad_mux,
2883};
2884
2885static struct atlas7_pad_mux sp0_ext_ldo_on_grp_pad_mux[] = {
2886 MUX(0, 4, 2, N, N, N, N),
2887};
2888
2889static struct atlas7_grp_mux sp0_ext_ldo_on_grp_mux = {
2890 .pad_mux_count = ARRAY_SIZE(sp0_ext_ldo_on_grp_pad_mux),
2891 .pad_mux_list = sp0_ext_ldo_on_grp_pad_mux,
2892};
2893
2894static struct atlas7_pad_mux sp0_qspi_grp_pad_mux[] = {
2895 MUX(0, 12, 1, N, N, N, N),
2896 MUX(0, 13, 1, N, N, N, N),
2897 MUX(0, 14, 1, N, N, N, N),
2898 MUX(0, 15, 1, N, N, N, N),
2899 MUX(0, 16, 1, N, N, N, N),
2900 MUX(0, 17, 1, N, N, N, N),
2901};
2902
2903static struct atlas7_grp_mux sp0_qspi_grp_mux = {
2904 .pad_mux_count = ARRAY_SIZE(sp0_qspi_grp_pad_mux),
2905 .pad_mux_list = sp0_qspi_grp_pad_mux,
2906};
2907
2908static struct atlas7_pad_mux sp1_spi_grp_pad_mux[] = {
2909 MUX(1, 19, 1, N, N, N, N),
2910 MUX(1, 20, 1, N, N, N, N),
2911 MUX(1, 21, 1, N, N, N, N),
2912 MUX(1, 18, 1, N, N, N, N),
2913};
2914
2915static struct atlas7_grp_mux sp1_spi_grp_mux = {
2916 .pad_mux_count = ARRAY_SIZE(sp1_spi_grp_pad_mux),
2917 .pad_mux_list = sp1_spi_grp_pad_mux,
2918};
2919
2920static struct atlas7_pad_mux tpiu_trace_grp_pad_mux[] = {
2921 MUX(1, 53, 5, N, N, N, N),
2922 MUX(1, 56, 5, N, N, N, N),
2923 MUX(1, 57, 5, N, N, N, N),
2924 MUX(1, 58, 5, N, N, N, N),
2925 MUX(1, 59, 5, N, N, N, N),
2926 MUX(1, 60, 5, N, N, N, N),
2927 MUX(1, 61, 5, N, N, N, N),
2928 MUX(1, 62, 5, N, N, N, N),
2929 MUX(1, 63, 5, N, N, N, N),
2930 MUX(1, 64, 5, N, N, N, N),
2931 MUX(1, 65, 5, N, N, N, N),
2932 MUX(1, 66, 5, N, N, N, N),
2933 MUX(1, 67, 5, N, N, N, N),
2934 MUX(1, 68, 5, N, N, N, N),
2935 MUX(1, 69, 5, N, N, N, N),
2936 MUX(1, 70, 5, N, N, N, N),
2937 MUX(1, 71, 5, N, N, N, N),
2938 MUX(1, 72, 5, N, N, N, N),
2939};
2940
2941static struct atlas7_grp_mux tpiu_trace_grp_mux = {
2942 .pad_mux_count = ARRAY_SIZE(tpiu_trace_grp_pad_mux),
2943 .pad_mux_list = tpiu_trace_grp_pad_mux,
2944};
2945
2946static struct atlas7_pad_mux uart0_grp_pad_mux[] = {
2947 MUX(1, 121, 4, N, N, N, N),
2948 MUX(1, 120, 4, N, N, N, N),
2949 MUX(1, 134, 1, N, N, N, N),
2950 MUX(1, 133, 1, N, N, N, N),
2951};
2952
2953static struct atlas7_grp_mux uart0_grp_mux = {
2954 .pad_mux_count = ARRAY_SIZE(uart0_grp_pad_mux),
2955 .pad_mux_list = uart0_grp_pad_mux,
2956};
2957
2958static struct atlas7_pad_mux uart0_nopause_grp_pad_mux[] = {
2959 MUX(1, 134, 1, N, N, N, N),
2960 MUX(1, 133, 1, N, N, N, N),
2961};
2962
2963static struct atlas7_grp_mux uart0_nopause_grp_mux = {
2964 .pad_mux_count = ARRAY_SIZE(uart0_nopause_grp_pad_mux),
2965 .pad_mux_list = uart0_nopause_grp_pad_mux,
2966};
2967
2968static struct atlas7_pad_mux uart1_grp_pad_mux[] = {
2969 MUX(1, 136, 1, N, N, N, N),
2970 MUX(1, 135, 1, N, N, N, N),
2971};
2972
2973static struct atlas7_grp_mux uart1_grp_mux = {
2974 .pad_mux_count = ARRAY_SIZE(uart1_grp_pad_mux),
2975 .pad_mux_list = uart1_grp_pad_mux,
2976};
2977
2978static struct atlas7_pad_mux uart2_grp_pad_mux[] = {
2979 MUX(0, 11, 2, N, N, N, N),
2980 MUX(0, 10, 2, N, N, N, N),
2981};
2982
2983static struct atlas7_grp_mux uart2_grp_mux = {
2984 .pad_mux_count = ARRAY_SIZE(uart2_grp_pad_mux),
2985 .pad_mux_list = uart2_grp_pad_mux,
2986};
2987
2988static struct atlas7_pad_mux uart3_grp0_pad_mux[] = {
2989 MUX(1, 125, 2, 0xa08, 0, 0xa88, 0),
2990 MUX(1, 126, 2, N, N, N, N),
2991 MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
2992 MUX(1, 137, 1, N, N, N, N),
2993};
2994
2995static struct atlas7_grp_mux uart3_grp0_mux = {
2996 .pad_mux_count = ARRAY_SIZE(uart3_grp0_pad_mux),
2997 .pad_mux_list = uart3_grp0_pad_mux,
2998};
2999
3000static struct atlas7_pad_mux uart3_grp1_pad_mux[] = {
3001 MUX(1, 111, 4, 0xa08, 0, 0xa88, 0),
3002 MUX(1, 109, 4, N, N, N, N),
3003 MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
3004 MUX(1, 83, 2, N, N, N, N),
3005};
3006
3007static struct atlas7_grp_mux uart3_grp1_mux = {
3008 .pad_mux_count = ARRAY_SIZE(uart3_grp1_pad_mux),
3009 .pad_mux_list = uart3_grp1_pad_mux,
3010};
3011
3012static struct atlas7_pad_mux uart3_grp2_pad_mux[] = {
3013 MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
3014 MUX(1, 139, 2, N, N, N, N),
3015 MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
3016 MUX(1, 137, 1, N, N, N, N),
3017};
3018
3019static struct atlas7_grp_mux uart3_grp2_mux = {
3020 .pad_mux_count = ARRAY_SIZE(uart3_grp2_pad_mux),
3021 .pad_mux_list = uart3_grp2_pad_mux,
3022};
3023
3024static struct atlas7_pad_mux uart3_grp3_pad_mux[] = {
3025 MUX(1, 139, 2, N, N, N, N),
3026 MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
3027 MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
3028 MUX(1, 83, 2, N, N, N, N),
3029};
3030
3031static struct atlas7_grp_mux uart3_grp3_mux = {
3032 .pad_mux_count = ARRAY_SIZE(uart3_grp3_pad_mux),
3033 .pad_mux_list = uart3_grp3_pad_mux,
3034};
3035
3036static struct atlas7_pad_mux uart3_nopause_grp0_pad_mux[] = {
3037 MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
3038 MUX(1, 137, 1, N, N, N, N),
3039};
3040
3041static struct atlas7_grp_mux uart3_nopause_grp0_mux = {
3042 .pad_mux_count = ARRAY_SIZE(uart3_nopause_grp0_pad_mux),
3043 .pad_mux_list = uart3_nopause_grp0_pad_mux,
3044};
3045
3046static struct atlas7_pad_mux uart3_nopause_grp1_pad_mux[] = {
3047 MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
3048 MUX(1, 83, 2, N, N, N, N),
3049};
3050
3051static struct atlas7_grp_mux uart3_nopause_grp1_mux = {
3052 .pad_mux_count = ARRAY_SIZE(uart3_nopause_grp1_pad_mux),
3053 .pad_mux_list = uart3_nopause_grp1_pad_mux,
3054};
3055
3056static struct atlas7_pad_mux uart4_grp0_pad_mux[] = {
3057 MUX(1, 122, 4, 0xa08, 1, 0xa88, 1),
3058 MUX(1, 123, 4, N, N, N, N),
3059 MUX(1, 140, 1, N, N, N, N),
3060 MUX(1, 139, 1, N, N, N, N),
3061};
3062
3063static struct atlas7_grp_mux uart4_grp0_mux = {
3064 .pad_mux_count = ARRAY_SIZE(uart4_grp0_pad_mux),
3065 .pad_mux_list = uart4_grp0_pad_mux,
3066};
3067
3068static struct atlas7_pad_mux uart4_grp1_pad_mux[] = {
3069 MUX(1, 100, 4, 0xa08, 1, 0xa88, 1),
3070 MUX(1, 99, 4, N, N, N, N),
3071 MUX(1, 140, 1, N, N, N, N),
3072 MUX(1, 139, 1, N, N, N, N),
3073};
3074
3075static struct atlas7_grp_mux uart4_grp1_mux = {
3076 .pad_mux_count = ARRAY_SIZE(uart4_grp1_pad_mux),
3077 .pad_mux_list = uart4_grp1_pad_mux,
3078};
3079
3080static struct atlas7_pad_mux uart4_grp2_pad_mux[] = {
3081 MUX(1, 117, 2, 0xa08, 1, 0xa88, 1),
3082 MUX(1, 116, 2, N, N, N, N),
3083 MUX(1, 140, 1, N, N, N, N),
3084 MUX(1, 139, 1, N, N, N, N),
3085};
3086
3087static struct atlas7_grp_mux uart4_grp2_mux = {
3088 .pad_mux_count = ARRAY_SIZE(uart4_grp2_pad_mux),
3089 .pad_mux_list = uart4_grp2_pad_mux,
3090};
3091
3092static struct atlas7_pad_mux uart4_nopause_grp_pad_mux[] = {
3093 MUX(1, 140, 1, N, N, N, N),
3094 MUX(1, 139, 1, N, N, N, N),
3095};
3096
3097static struct atlas7_grp_mux uart4_nopause_grp_mux = {
3098 .pad_mux_count = ARRAY_SIZE(uart4_nopause_grp_pad_mux),
3099 .pad_mux_list = uart4_nopause_grp_pad_mux,
3100};
3101
3102static struct atlas7_pad_mux usb0_drvvbus_grp_pad_mux[] = {
3103 MUX(1, 51, 2, N, N, N, N),
3104};
3105
3106static struct atlas7_grp_mux usb0_drvvbus_grp_mux = {
3107 .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp_pad_mux),
3108 .pad_mux_list = usb0_drvvbus_grp_pad_mux,
3109};
3110
3111static struct atlas7_pad_mux usb1_drvvbus_grp_pad_mux[] = {
3112 MUX(1, 134, 2, N, N, N, N),
3113};
3114
3115static struct atlas7_grp_mux usb1_drvvbus_grp_mux = {
3116 .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp_pad_mux),
3117 .pad_mux_list = usb1_drvvbus_grp_pad_mux,
3118};
3119
3120static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = {
3121 MUX(1, 57, 6, N, N, N, N),
3122 MUX(1, 58, 6, N, N, N, N),
3123 MUX(1, 59, 6, N, N, N, N),
3124 MUX(1, 60, 6, N, N, N, N),
3125 MUX(1, 61, 6, N, N, N, N),
3126 MUX(1, 62, 6, N, N, N, N),
3127 MUX(1, 63, 6, N, N, N, N),
3128 MUX(1, 64, 6, N, N, N, N),
3129 MUX(1, 65, 6, N, N, N, N),
3130 MUX(1, 66, 6, N, N, N, N),
3131 MUX(1, 67, 6, N, N, N, N),
3132 MUX(1, 68, 6, N, N, N, N),
3133 MUX(1, 69, 6, N, N, N, N),
3134 MUX(1, 70, 6, N, N, N, N),
3135 MUX(1, 71, 6, N, N, N, N),
3136 MUX(1, 72, 6, N, N, N, N),
3137 MUX(1, 53, 6, N, N, N, N),
3138 MUX(1, 54, 6, N, N, N, N),
3139 MUX(1, 55, 6, N, N, N, N),
3140 MUX(1, 56, 6, N, N, N, N),
3141 MUX(1, 85, 6, N, N, N, N),
3142 MUX(1, 86, 6, N, N, N, N),
3143 MUX(1, 87, 6, N, N, N, N),
3144 MUX(1, 88, 6, N, N, N, N),
3145 MUX(1, 89, 6, N, N, N, N),
3146 MUX(1, 90, 6, N, N, N, N),
3147 MUX(1, 91, 6, N, N, N, N),
3148 MUX(1, 92, 6, N, N, N, N),
3149 MUX(1, 93, 6, N, N, N, N),
3150 MUX(1, 94, 6, N, N, N, N),
3151 MUX(1, 95, 6, N, N, N, N),
3152 MUX(1, 96, 6, N, N, N, N),
3153};
3154
3155static struct atlas7_grp_mux visbus_dout_grp_mux = {
3156 .pad_mux_count = ARRAY_SIZE(visbus_dout_grp_pad_mux),
3157 .pad_mux_list = visbus_dout_grp_pad_mux,
3158};
3159
3160static struct atlas7_pad_mux vi_vip1_grp_pad_mux[] = {
3161 MUX(1, 74, 1, N, N, N, N),
3162 MUX(1, 75, 1, N, N, N, N),
3163 MUX(1, 76, 1, N, N, N, N),
3164 MUX(1, 77, 1, N, N, N, N),
3165 MUX(1, 78, 1, N, N, N, N),
3166 MUX(1, 79, 1, N, N, N, N),
3167 MUX(1, 80, 1, N, N, N, N),
3168 MUX(1, 81, 1, N, N, N, N),
3169 MUX(1, 82, 1, N, N, N, N),
3170 MUX(1, 83, 1, N, N, N, N),
3171 MUX(1, 84, 1, N, N, N, N),
3172 MUX(1, 103, 2, N, N, N, N),
3173 MUX(1, 104, 2, N, N, N, N),
3174 MUX(1, 105, 2, N, N, N, N),
3175 MUX(1, 106, 2, N, N, N, N),
3176 MUX(1, 107, 2, N, N, N, N),
3177 MUX(1, 102, 2, N, N, N, N),
3178 MUX(1, 97, 2, N, N, N, N),
3179 MUX(1, 98, 2, N, N, N, N),
3180};
3181
3182static struct atlas7_grp_mux vi_vip1_grp_mux = {
3183 .pad_mux_count = ARRAY_SIZE(vi_vip1_grp_pad_mux),
3184 .pad_mux_list = vi_vip1_grp_pad_mux,
3185};
3186
3187static struct atlas7_pad_mux vi_vip1_ext_grp_pad_mux[] = {
3188 MUX(1, 74, 1, N, N, N, N),
3189 MUX(1, 75, 1, N, N, N, N),
3190 MUX(1, 76, 1, N, N, N, N),
3191 MUX(1, 77, 1, N, N, N, N),
3192 MUX(1, 78, 1, N, N, N, N),
3193 MUX(1, 79, 1, N, N, N, N),
3194 MUX(1, 80, 1, N, N, N, N),
3195 MUX(1, 81, 1, N, N, N, N),
3196 MUX(1, 82, 1, N, N, N, N),
3197 MUX(1, 83, 1, N, N, N, N),
3198 MUX(1, 84, 1, N, N, N, N),
3199 MUX(1, 108, 2, N, N, N, N),
3200 MUX(1, 103, 2, N, N, N, N),
3201 MUX(1, 104, 2, N, N, N, N),
3202 MUX(1, 105, 2, N, N, N, N),
3203 MUX(1, 106, 2, N, N, N, N),
3204 MUX(1, 107, 2, N, N, N, N),
3205 MUX(1, 102, 2, N, N, N, N),
3206 MUX(1, 97, 2, N, N, N, N),
3207 MUX(1, 98, 2, N, N, N, N),
3208 MUX(1, 99, 2, N, N, N, N),
3209 MUX(1, 100, 2, N, N, N, N),
3210};
3211
3212static struct atlas7_grp_mux vi_vip1_ext_grp_mux = {
3213 .pad_mux_count = ARRAY_SIZE(vi_vip1_ext_grp_pad_mux),
3214 .pad_mux_list = vi_vip1_ext_grp_pad_mux,
3215};
3216
3217static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = {
3218 MUX(1, 74, 1, N, N, N, N),
3219 MUX(1, 75, 1, N, N, N, N),
3220 MUX(1, 76, 1, N, N, N, N),
3221 MUX(1, 77, 1, N, N, N, N),
3222 MUX(1, 78, 1, N, N, N, N),
3223 MUX(1, 79, 1, N, N, N, N),
3224 MUX(1, 80, 1, N, N, N, N),
3225 MUX(1, 81, 1, N, N, N, N),
3226};
3227
3228static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = {
3229 .pad_mux_count = ARRAY_SIZE(vi_vip1_low8bit_grp_pad_mux),
3230 .pad_mux_list = vi_vip1_low8bit_grp_pad_mux,
3231};
3232
3233static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = {
3234 MUX(1, 82, 1, N, N, N, N),
3235 MUX(1, 83, 1, N, N, N, N),
3236 MUX(1, 84, 1, N, N, N, N),
3237 MUX(1, 108, 2, N, N, N, N),
3238 MUX(1, 103, 2, N, N, N, N),
3239 MUX(1, 104, 2, N, N, N, N),
3240 MUX(1, 105, 2, N, N, N, N),
3241 MUX(1, 106, 2, N, N, N, N),
3242};
3243
3244static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = {
3245 .pad_mux_count = ARRAY_SIZE(vi_vip1_high8bit_grp_pad_mux),
3246 .pad_mux_list = vi_vip1_high8bit_grp_pad_mux,
3247};
3248
3249static struct atlas7_pmx_func atlas7_pmx_functions[] = {
3250 FUNCTION("gnss_gpio", gnss_gpio_grp, &gnss_gpio_grp_mux),
3251 FUNCTION("lcd_vip_gpio", lcd_vip_gpio_grp, &lcd_vip_gpio_grp_mux),
3252 FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux),
3253 FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux),
3254 FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux),
3255 FUNCTION("uart_nand_gpio",
3256 uart_nand_gpio_grp,
3257 &uart_nand_gpio_grp_mux),
3258 FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux),
3259 FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux),
3260 FUNCTION("audio_func_dbg",
3261 audio_func_dbg_grp,
3262 &audio_func_dbg_grp_mux),
3263 FUNCTION("audio_i2s", audio_i2s_grp, &audio_i2s_grp_mux),
3264 FUNCTION("audio_i2s_2ch", audio_i2s_2ch_grp, &audio_i2s_2ch_grp_mux),
3265 FUNCTION("audio_i2s_extclk",
3266 audio_i2s_extclk_grp,
3267 &audio_i2s_extclk_grp_mux),
3268 FUNCTION("audio_uart0", audio_uart0_grp, &audio_uart0_grp_mux),
3269 FUNCTION("audio_uart1", audio_uart1_grp, &audio_uart1_grp_mux),
3270 FUNCTION("audio_uart2_m0", audio_uart2_grp0, &audio_uart2_grp0_mux),
3271 FUNCTION("audio_uart2_m1", audio_uart2_grp1, &audio_uart2_grp1_mux),
3272 FUNCTION("c_can_trnsvr", c_can_trnsvr_grp, &c_can_trnsvr_grp_mux),
3273 FUNCTION("c0_can_m0", c0_can_grp0, &c0_can_grp0_mux),
3274 FUNCTION("c0_can_m1", c0_can_grp1, &c0_can_grp1_mux),
3275 FUNCTION("c1_can_m0", c1_can_grp0, &c1_can_grp0_mux),
3276 FUNCTION("c1_can_m1", c1_can_grp1, &c1_can_grp1_mux),
3277 FUNCTION("c1_can_m2", c1_can_grp2, &c1_can_grp2_mux),
3278 FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux),
3279 FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux),
3280 FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux),
3281 FUNCTION("ca_curator_lpc",
3282 ca_curator_lpc_grp,
3283 &ca_curator_lpc_grp_mux),
3284 FUNCTION("ca_pcm_debug", ca_pcm_debug_grp, &ca_pcm_debug_grp_mux),
3285 FUNCTION("ca_pio", ca_pio_grp, &ca_pio_grp_mux),
3286 FUNCTION("ca_sdio_debug", ca_sdio_debug_grp, &ca_sdio_debug_grp_mux),
3287 FUNCTION("ca_spi", ca_spi_grp, &ca_spi_grp_mux),
3288 FUNCTION("ca_trb", ca_trb_grp, &ca_trb_grp_mux),
3289 FUNCTION("ca_uart_debug", ca_uart_debug_grp, &ca_uart_debug_grp_mux),
3290 FUNCTION("clkc_m0", clkc_grp0, &clkc_grp0_mux),
3291 FUNCTION("clkc_m1", clkc_grp1, &clkc_grp1_mux),
3292 FUNCTION("gn_gnss_i2c", gn_gnss_i2c_grp, &gn_gnss_i2c_grp_mux),
3293 FUNCTION("gn_gnss_uart_nopause",
3294 gn_gnss_uart_nopause_grp,
3295 &gn_gnss_uart_nopause_grp_mux),
3296 FUNCTION("gn_gnss_uart", gn_gnss_uart_grp, &gn_gnss_uart_grp_mux),
3297 FUNCTION("gn_trg_spi_m0", gn_trg_spi_grp0, &gn_trg_spi_grp0_mux),
3298 FUNCTION("gn_trg_spi_m1", gn_trg_spi_grp1, &gn_trg_spi_grp1_mux),
3299 FUNCTION("cvbs_dbg", cvbs_dbg_grp, &cvbs_dbg_grp_mux),
3300 FUNCTION("cvbs_dbg_test_m0",
3301 cvbs_dbg_test_grp0,
3302 &cvbs_dbg_test_grp0_mux),
3303 FUNCTION("cvbs_dbg_test_m1",
3304 cvbs_dbg_test_grp1,
3305 &cvbs_dbg_test_grp1_mux),
3306 FUNCTION("cvbs_dbg_test_m2",
3307 cvbs_dbg_test_grp2,
3308 &cvbs_dbg_test_grp2_mux),
3309 FUNCTION("cvbs_dbg_test_m3",
3310 cvbs_dbg_test_grp3,
3311 &cvbs_dbg_test_grp3_mux),
3312 FUNCTION("cvbs_dbg_test_m4",
3313 cvbs_dbg_test_grp4,
3314 &cvbs_dbg_test_grp4_mux),
3315 FUNCTION("cvbs_dbg_test_m5",
3316 cvbs_dbg_test_grp5,
3317 &cvbs_dbg_test_grp5_mux),
3318 FUNCTION("cvbs_dbg_test_m6",
3319 cvbs_dbg_test_grp6,
3320 &cvbs_dbg_test_grp6_mux),
3321 FUNCTION("cvbs_dbg_test_m7",
3322 cvbs_dbg_test_grp7,
3323 &cvbs_dbg_test_grp7_mux),
3324 FUNCTION("cvbs_dbg_test_m8",
3325 cvbs_dbg_test_grp8,
3326 &cvbs_dbg_test_grp8_mux),
3327 FUNCTION("cvbs_dbg_test_m9",
3328 cvbs_dbg_test_grp9,
3329 &cvbs_dbg_test_grp9_mux),
3330 FUNCTION("cvbs_dbg_test_m10",
3331 cvbs_dbg_test_grp10,
3332 &cvbs_dbg_test_grp10_mux),
3333 FUNCTION("cvbs_dbg_test_m11",
3334 cvbs_dbg_test_grp11,
3335 &cvbs_dbg_test_grp11_mux),
3336 FUNCTION("cvbs_dbg_test_m12",
3337 cvbs_dbg_test_grp12,
3338 &cvbs_dbg_test_grp12_mux),
3339 FUNCTION("cvbs_dbg_test_m13",
3340 cvbs_dbg_test_grp13,
3341 &cvbs_dbg_test_grp13_mux),
3342 FUNCTION("cvbs_dbg_test_m14",
3343 cvbs_dbg_test_grp14,
3344 &cvbs_dbg_test_grp14_mux),
3345 FUNCTION("cvbs_dbg_test_m15",
3346 cvbs_dbg_test_grp15,
3347 &cvbs_dbg_test_grp15_mux),
3348 FUNCTION("gn_gnss_power", gn_gnss_power_grp, &gn_gnss_power_grp_mux),
3349 FUNCTION("gn_gnss_sw_status",
3350 gn_gnss_sw_status_grp,
3351 &gn_gnss_sw_status_grp_mux),
3352 FUNCTION("gn_gnss_eclk", gn_gnss_eclk_grp, &gn_gnss_eclk_grp_mux),
3353 FUNCTION("gn_gnss_irq1_m0",
3354 gn_gnss_irq1_grp0,
3355 &gn_gnss_irq1_grp0_mux),
3356 FUNCTION("gn_gnss_irq2_m0",
3357 gn_gnss_irq2_grp0,
3358 &gn_gnss_irq2_grp0_mux),
3359 FUNCTION("gn_gnss_tm", gn_gnss_tm_grp, &gn_gnss_tm_grp_mux),
3360 FUNCTION("gn_gnss_tsync", gn_gnss_tsync_grp, &gn_gnss_tsync_grp_mux),
3361 FUNCTION("gn_io_gnsssys_sw_cfg",
3362 gn_io_gnsssys_sw_cfg_grp,
3363 &gn_io_gnsssys_sw_cfg_grp_mux),
3364 FUNCTION("gn_trg_m0", gn_trg_grp0, &gn_trg_grp0_mux),
3365 FUNCTION("gn_trg_m1", gn_trg_grp1, &gn_trg_grp1_mux),
3366 FUNCTION("gn_trg_shutdown_m0",
3367 gn_trg_shutdown_grp0,
3368 &gn_trg_shutdown_grp0_mux),
3369 FUNCTION("gn_trg_shutdown_m1",
3370 gn_trg_shutdown_grp1,
3371 &gn_trg_shutdown_grp1_mux),
3372 FUNCTION("gn_trg_shutdown_m2",
3373 gn_trg_shutdown_grp2,
3374 &gn_trg_shutdown_grp2_mux),
3375 FUNCTION("gn_trg_shutdown_m3",
3376 gn_trg_shutdown_grp3,
3377 &gn_trg_shutdown_grp3_mux),
3378 FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux),
3379 FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux),
3380 FUNCTION("jtag_m0", jtag_grp0, &jtag_grp0_mux),
3381 FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux),
3382 FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux),
3383 FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux),
3384 FUNCTION("ld_ldd_fck", ld_ldd_fck_grp, &ld_ldd_fck_grp_mux),
3385 FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux),
3386 FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux),
3387 FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux),
3388 FUNCTION("nd_df", nd_df_grp, &nd_df_grp_mux),
3389 FUNCTION("nd_df_nowp", nd_df_nowp_grp, &nd_df_nowp_grp_mux),
3390 FUNCTION("ps", ps_grp, &ps_grp_mux),
3391 FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux),
3392 FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux),
3393 FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux),
3394 FUNCTION("pwc_io_on", pwc_io_on_grp, &pwc_io_on_grp_mux),
3395 FUNCTION("pwc_lowbatt_b_m0",
3396 pwc_lowbatt_b_grp0,
3397 &pwc_lowbatt_b_grp0_mux),
3398 FUNCTION("pwc_mem_on", pwc_mem_on_grp, &pwc_mem_on_grp_mux),
3399 FUNCTION("pwc_on_key_b_m0",
3400 pwc_on_key_b_grp0,
3401 &pwc_on_key_b_grp0_mux),
3402 FUNCTION("pwc_wakeup_src0",
3403 pwc_wakeup_src0_grp,
3404 &pwc_wakeup_src0_grp_mux),
3405 FUNCTION("pwc_wakeup_src1",
3406 pwc_wakeup_src1_grp,
3407 &pwc_wakeup_src1_grp_mux),
3408 FUNCTION("pwc_wakeup_src2",
3409 pwc_wakeup_src2_grp,
3410 &pwc_wakeup_src2_grp_mux),
3411 FUNCTION("pwc_wakeup_src3",
3412 pwc_wakeup_src3_grp,
3413 &pwc_wakeup_src3_grp_mux),
3414 FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux),
3415 FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux),
3416 FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux),
3417 FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux),
3418 FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux),
3419 FUNCTION("pw_i2s01_clk_m0",
3420 pw_i2s01_clk_grp0,
3421 &pw_i2s01_clk_grp0_mux),
3422 FUNCTION("pw_i2s01_clk_m1",
3423 pw_i2s01_clk_grp1,
3424 &pw_i2s01_clk_grp1_mux),
3425 FUNCTION("pw_pwm0", pw_pwm0_grp, &pw_pwm0_grp_mux),
3426 FUNCTION("pw_pwm1", pw_pwm1_grp, &pw_pwm1_grp_mux),
3427 FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux),
3428 FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux),
3429 FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux),
3430 FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux),
3431 FUNCTION("pw_pwm_cpu_vol_m0",
3432 pw_pwm_cpu_vol_grp0,
3433 &pw_pwm_cpu_vol_grp0_mux),
3434 FUNCTION("pw_pwm_cpu_vol_m1",
3435 pw_pwm_cpu_vol_grp1,
3436 &pw_pwm_cpu_vol_grp1_mux),
3437 FUNCTION("pw_backlight_m0",
3438 pw_backlight_grp0,
3439 &pw_backlight_grp0_mux),
3440 FUNCTION("pw_backlight_m1",
3441 pw_backlight_grp1,
3442 &pw_backlight_grp1_mux),
3443 FUNCTION("rg_eth_mac", rg_eth_mac_grp, &rg_eth_mac_grp_mux),
3444 FUNCTION("rg_gmac_phy_intr_n",
3445 rg_gmac_phy_intr_n_grp,
3446 &rg_gmac_phy_intr_n_grp_mux),
3447 FUNCTION("rg_rgmii_mac", rg_rgmii_mac_grp, &rg_rgmii_mac_grp_mux),
3448 FUNCTION("rg_rgmii_phy_ref_clk_m0",
3449 rg_rgmii_phy_ref_clk_grp0,
3450 &rg_rgmii_phy_ref_clk_grp0_mux),
3451 FUNCTION("rg_rgmii_phy_ref_clk_m1",
3452 rg_rgmii_phy_ref_clk_grp1,
3453 &rg_rgmii_phy_ref_clk_grp1_mux),
3454 FUNCTION("sd0", sd0_grp, &sd0_grp_mux),
3455 FUNCTION("sd0_4bit", sd0_4bit_grp, &sd0_4bit_grp_mux),
3456 FUNCTION("sd1", sd1_grp, &sd1_grp_mux),
3457 FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux),
3458 FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux),
3459 FUNCTION("sd2_m0", sd2_grp0, &sd2_grp0_mux),
3460 FUNCTION("sd2_no_cdb_m0", sd2_no_cdb_grp0, &sd2_no_cdb_grp0_mux),
3461 FUNCTION("sd3", sd3_grp, &sd3_grp_mux),
3462 FUNCTION("sd5", sd5_grp, &sd5_grp_mux),
3463 FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux),
3464 FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux),
3465 FUNCTION("sp0_ext_ldo_on",
3466 sp0_ext_ldo_on_grp,
3467 &sp0_ext_ldo_on_grp_mux),
3468 FUNCTION("sp0_qspi", sp0_qspi_grp, &sp0_qspi_grp_mux),
3469 FUNCTION("sp1_spi", sp1_spi_grp, &sp1_spi_grp_mux),
3470 FUNCTION("tpiu_trace", tpiu_trace_grp, &tpiu_trace_grp_mux),
3471 FUNCTION("uart0", uart0_grp, &uart0_grp_mux),
3472 FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux),
3473 FUNCTION("uart1", uart1_grp, &uart1_grp_mux),
3474 FUNCTION("uart2", uart2_grp, &uart2_grp_mux),
3475 FUNCTION("uart3_m0", uart3_grp0, &uart3_grp0_mux),
3476 FUNCTION("uart3_m1", uart3_grp1, &uart3_grp1_mux),
3477 FUNCTION("uart3_m2", uart3_grp2, &uart3_grp2_mux),
3478 FUNCTION("uart3_m3", uart3_grp3, &uart3_grp3_mux),
3479 FUNCTION("uart3_nopause_m0",
3480 uart3_nopause_grp0,
3481 &uart3_nopause_grp0_mux),
3482 FUNCTION("uart3_nopause_m1",
3483 uart3_nopause_grp1,
3484 &uart3_nopause_grp1_mux),
3485 FUNCTION("uart4_m0", uart4_grp0, &uart4_grp0_mux),
3486 FUNCTION("uart4_m1", uart4_grp1, &uart4_grp1_mux),
3487 FUNCTION("uart4_m2", uart4_grp2, &uart4_grp2_mux),
3488 FUNCTION("uart4_nopause", uart4_nopause_grp, &uart4_nopause_grp_mux),
3489 FUNCTION("usb0_drvvbus", usb0_drvvbus_grp, &usb0_drvvbus_grp_mux),
3490 FUNCTION("usb1_drvvbus", usb1_drvvbus_grp, &usb1_drvvbus_grp_mux),
3491 FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux),
3492 FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux),
3493 FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux),
3494 FUNCTION("vi_vip1_low8bit",
3495 vi_vip1_low8bit_grp,
3496 &vi_vip1_low8bit_grp_mux),
3497 FUNCTION("vi_vip1_high8bit",
3498 vi_vip1_high8bit_grp,
3499 &vi_vip1_high8bit_grp_mux),
3500};
3501
3502struct atlas7_pinctrl_data atlas7_ioc_data = {
3503 .pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads,
3504 .pads_cnt = ARRAY_SIZE(atlas7_ioc_pads),
3505 .grps = (struct atlas7_pin_group *)altas7_pin_groups,
3506 .grps_cnt = ARRAY_SIZE(altas7_pin_groups),
3507 .funcs = (struct atlas7_pmx_func *)atlas7_pmx_functions,
3508 .funcs_cnt = ARRAY_SIZE(atlas7_pmx_functions),
3509 .confs = (struct atlas7_pad_config *)atlas7_ioc_pad_confs,
3510 .confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs),
3511};
3512
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]3513/* Simple map data structure */
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]3514struct map_data {
3515 u8 idx;
3516 u8 data;
3517};
3518
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]3519/**
3520 * struct atlas7_pull_info - Atlas7 Pad pull info
3521 * @type:The type of this Pad.
3522 * @mask:The mas value of this pin's pull bits.
3523 * @v2s: The map of pull register value to pull status.
3524 * @s2v: The map of pull status to pull register value.
3525 */
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]3526struct atlas7_pull_info {
3527 u8 pad_type;
3528 u8 mask;
3529 const struct map_data *v2s;
3530 const struct map_data *s2v;
3531};
3532
3533/* Pull Register value map to status */
3534static const struct map_data p4we_pull_v2s[] = {
3535 { P4WE_PULL_UP, PULL_UP },
3536 { P4WE_HIGH_HYSTERESIS, HIGH_HYSTERESIS },
3537 { P4WE_HIGH_Z, HIGH_Z },
3538 { P4WE_PULL_DOWN, PULL_DOWN },
3539};
3540
3541static const struct map_data p16st_pull_v2s[] = {
3542 { P16ST_PULL_UP, PULL_UP },
3543 { PD, PULL_UNKNOWN },
3544 { P16ST_HIGH_Z, HIGH_Z },
3545 { P16ST_PULL_DOWN, PULL_DOWN },
3546};
3547
3548static const struct map_data pm31_pull_v2s[] = {
3549 { PM31_PULL_DISABLED, PULL_DOWN },
3550 { PM31_PULL_ENABLED, PULL_UP },
3551};
3552
3553static const struct map_data pangd_pull_v2s[] = {
3554 { PANGD_PULL_UP, PULL_UP },
3555 { PD, PULL_UNKNOWN },
3556 { PANGD_HIGH_Z, HIGH_Z },
3557 { PANGD_PULL_DOWN, PULL_DOWN },
3558};
3559
3560/* Pull status map to register value */
3561static const struct map_data p4we_pull_s2v[] = {
3562 { PULL_UP, P4WE_PULL_UP },
3563 { HIGH_HYSTERESIS, P4WE_HIGH_HYSTERESIS },
3564 { HIGH_Z, P4WE_HIGH_Z },
3565 { PULL_DOWN, P4WE_PULL_DOWN },
3566 { PULL_DISABLE, -1 },
3567 { PULL_ENABLE, -1 },
3568};
3569
3570static const struct map_data p16st_pull_s2v[] = {
3571 { PULL_UP, P16ST_PULL_UP },
3572 { HIGH_HYSTERESIS, -1 },
3573 { HIGH_Z, P16ST_HIGH_Z },
3574 { PULL_DOWN, P16ST_PULL_DOWN },
3575 { PULL_DISABLE, -1 },
3576 { PULL_ENABLE, -1 },
3577};
3578
3579static const struct map_data pm31_pull_s2v[] = {
3580 { PULL_UP, PM31_PULL_ENABLED },
3581 { HIGH_HYSTERESIS, -1 },
3582 { HIGH_Z, -1 },
3583 { PULL_DOWN, PM31_PULL_DISABLED },
3584 { PULL_DISABLE, -1 },
3585 { PULL_ENABLE, -1 },
3586};
3587
3588static const struct map_data pangd_pull_s2v[] = {
3589 { PULL_UP, PANGD_PULL_UP },
3590 { HIGH_HYSTERESIS, -1 },
3591 { HIGH_Z, PANGD_HIGH_Z },
3592 { PULL_DOWN, PANGD_PULL_DOWN },
3593 { PULL_DISABLE, -1 },
3594 { PULL_ENABLE, -1 },
3595};
3596
3597static const struct atlas7_pull_info atlas7_pull_map[] = {
3598 { PAD_T_4WE_PD, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
3599 { PAD_T_4WE_PU, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
3600 { PAD_T_16ST, P16ST_PULL_MASK, p16st_pull_v2s, p16st_pull_s2v },
3601 { PAD_T_M31_0204_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
3602 { PAD_T_M31_0204_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
3603 { PAD_T_M31_0610_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
3604 { PAD_T_M31_0610_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
3605 { PAD_T_AD, PANGD_PULL_MASK, pangd_pull_v2s, pangd_pull_s2v },
3606};
3607
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]3608/**
3609 * struct atlas7_ds_ma_info - Atlas7 Pad DriveStrength & currents info
3610 * @ma: The Drive Strength in current value .
3611 * @ds_16st: The correspond raw value of 16st pad.
3612 * @ds_4we: The correspond raw value of 4we pad.
3613 * @ds_0204m31: The correspond raw value of 0204m31 pad.
3614 * @ds_0610m31: The correspond raw value of 0610m31 pad.
3615 */
3616struct atlas7_ds_ma_info {
3617 u32 ma;
3618 u32 ds_16st;
3619 u32 ds_4we;
3620 u32 ds_0204m31;
3621 u32 ds_0610m31;
3622};
3623
3624static const struct atlas7_ds_ma_info atlas7_ma2ds_map[] = {
3625 { 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL },
3626 { 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL },
3627 { 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0 },
3628 { 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL },
3629 { 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1 },
3630 { 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL },
3631 { 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL },
3632 { 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL },
3633 { 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL },
3634 { 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL },
3635 { 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL },
3636 { 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL },
3637 { 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL },
3638 { 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL },
3639 { 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL },
3640 { 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL },
3641};
3642
3643/**
3644 * struct atlas7_ds_info - Atlas7 Pad DriveStrength info
3645 * @type: The type of this Pad.
3646 * @mask: The mask value of this pin's pull bits.
3647 * @imval: The immediate value of drives trength register.
3648 */
3649struct atlas7_ds_info {
3650 u8 type;
3651 u8 mask;
3652 u8 imval;
3653 u8 reserved;
3654};
3655
3656static const struct atlas7_ds_info atlas7_ds_map[] = {
3657 { PAD_T_4WE_PD, DS_2BIT_MASK, DS_2BIT_IM_VAL },
3658 { PAD_T_4WE_PU, DS_2BIT_MASK, DS_2BIT_IM_VAL },
3659 { PAD_T_16ST, DS_4BIT_MASK, DS_4BIT_IM_VAL },
3660 { PAD_T_M31_0204_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
3661 { PAD_T_M31_0204_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
3662 { PAD_T_M31_0610_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
3663 { PAD_T_M31_0610_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
3664 { PAD_T_AD, DS_NULL, DS_NULL },
3665};
3666
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3667static inline u32 atlas7_pin_to_bank(u32 pin)
3668{
3669 return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0;
3670}
3671
3672static int atlas7_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
3673{
3674 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3675
3676 return pmx->pctl_data->funcs_cnt;
3677}
3678
3679static const char *atlas7_pmx_get_func_name(struct pinctrl_dev *pctldev,
3680 u32 selector)
3681{
3682 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3683
3684 return pmx->pctl_data->funcs[selector].name;
3685}
3686
3687static int atlas7_pmx_get_func_groups(struct pinctrl_dev *pctldev,
3688 u32 selector, const char * const **groups,
3689 u32 * const num_groups)
3690{
3691 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3692
3693 *groups = pmx->pctl_data->funcs[selector].groups;
3694 *num_groups = pmx->pctl_data->funcs[selector].num_groups;
3695
3696 return 0;
3697}
3698
3699static void __atlas7_pmx_pin_input_disable_set(struct atlas7_pmx *pmx,
3700 const struct atlas7_pad_mux *mux)
3701{
3702 /* Set Input Disable to avoid input glitches
3703 *
3704 * All Input-Disable Control registers are located on IOCRTC.
3705 * So the regs bank is always 0.
3706 *
3707 */
3708 if (mux->dinput_reg && mux->dinput_val_reg) {
3709 writel(DI_MASK << mux->dinput_bit,
3710 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
3711 writel(DI_DISABLE << mux->dinput_bit,
3712 pmx->regs[BANK_DS] + mux->dinput_reg);
3713
3714
3715 writel(DIV_MASK << mux->dinput_val_bit,
3716 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
3717 writel(DIV_DISABLE << mux->dinput_val_bit,
3718 pmx->regs[BANK_DS] + mux->dinput_val_reg);
3719 }
3720}
3721
3722static void __atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx *pmx,
3723 const struct atlas7_pad_mux *mux)
3724{
3725 /* Clear Input Disable to avoid input glitches */
3726 if (mux->dinput_reg && mux->dinput_val_reg) {
3727 writel(DI_MASK << mux->dinput_bit,
3728 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
3729 writel(DI_ENABLE << mux->dinput_bit,
3730 pmx->regs[BANK_DS] + mux->dinput_reg);
3731
3732 writel(DIV_MASK << mux->dinput_val_bit,
3733 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
3734 writel(DIV_ENABLE << mux->dinput_val_bit,
3735 pmx->regs[BANK_DS] + mux->dinput_val_reg);
3736 }
3737}
3738
3739static int __atlas7_pmx_pin_ad_sel(struct atlas7_pmx *pmx,
3740 struct atlas7_pad_config *conf,
3741 u32 bank, u32 ad_sel)
3742{
3743 unsigned long regv;
3744
3745 /* Write to clear register to clear A/D selector */
3746 writel(ANA_CLEAR_MASK << conf->ad_ctrl_bit,
3747 pmx->regs[bank] + CLR_REG(conf->ad_ctrl_reg));
3748
3749 /* Set target pad A/D selector */
3750 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
3751 regv &= ~(ANA_CLEAR_MASK << conf->ad_ctrl_bit);
3752 writel(regv | (ad_sel << conf->ad_ctrl_bit),
3753 pmx->regs[bank] + conf->ad_ctrl_reg);
3754
3755 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
3756 pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
3757 bank, conf->ad_ctrl_reg, regv);
3758 return 0;
3759}
3760
3761static int __atlas7_pmx_pin_analog_enable(struct atlas7_pmx *pmx,
3762 struct atlas7_pad_config *conf, u32 bank)
3763{
3764 /* Only PAD_T_AD pins can change between Analogue&Digital */
3765 if (conf->type != PAD_T_AD)
3766 return -EINVAL;
3767
3768 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0);
3769}
3770
3771static int __atlas7_pmx_pin_digital_enable(struct atlas7_pmx *pmx,
3772 struct atlas7_pad_config *conf, u32 bank)
3773{
3774 /* Other type pads are always digital */
3775 if (conf->type != PAD_T_AD)
3776 return 0;
3777
3778 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1);
3779}
3780
3781static int __atlas7_pmx_pin_enable(struct atlas7_pmx *pmx,
3782 u32 pin, u32 func)
3783{
3784 struct atlas7_pad_config *conf;
3785 u32 bank;
3786 int ret;
3787 unsigned long regv;
3788
3789 pr_debug("PMX DUMP ### pin#%d func:%d #### START >>>\n",
3790 pin, func);
3791
3792 /* Get this Pad's descriptor from PINCTRL */
3793 conf = &pmx->pctl_data->confs[pin];
3794 bank = atlas7_pin_to_bank(pin);
3795
3796 /* Just enable the analog function of this pad */
3797 if (FUNC_ANALOGUE == func) {
3798 ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank);
3799 if (ret)
3800 dev_err(pmx->dev,
3801 "Convert pad#%d to analog failed, ret=%d\n",
3802 pin, ret);
3803 return ret;
3804 }
3805
3806 /* Set Pads from analog to digital */
3807 ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank);
3808 if (ret) {
3809 dev_err(pmx->dev,
3810 "Convert pad#%d to digital failed, ret=%d\n",
3811 pin, ret);
3812 return ret;
3813 }
3814
3815 /* Write to clear register to clear current function */
3816 writel(FUNC_CLEAR_MASK << conf->mux_bit,
3817 pmx->regs[bank] + CLR_REG(conf->mux_reg));
3818
3819 /* Set target pad mux function */
3820 regv = readl(pmx->regs[bank] + conf->mux_reg);
3821 regv &= ~(FUNC_CLEAR_MASK << conf->mux_bit);
3822 writel(regv | (func << conf->mux_bit),
3823 pmx->regs[bank] + conf->mux_reg);
3824
3825 regv = readl(pmx->regs[bank] + conf->mux_reg);
3826 pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
3827 bank, conf->mux_reg, regv);
3828
3829 return 0;
3830}
3831
3832static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev,
3833 u32 func_selector, u32 group_selector)
3834{
3835 int idx, ret;
3836 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3837 struct atlas7_pmx_func *pmx_func;
3838 struct atlas7_pin_group *pin_grp;
3839 const struct atlas7_grp_mux *grp_mux;
3840 const struct atlas7_pad_mux *mux;
3841
3842 pmx_func = &pmx->pctl_data->funcs[func_selector];
3843 pin_grp = &pmx->pctl_data->grps[group_selector];
3844
3845 pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### START >>>\n",
3846 pmx_func->name, pin_grp->name);
3847
3848 grp_mux = pmx_func->grpmux;
3849
3850 for (idx = 0; idx < grp_mux->pad_mux_count; idx++) {
3851 mux = &grp_mux->pad_mux_list[idx];
3852 __atlas7_pmx_pin_input_disable_set(pmx, mux);
3853 ret = __atlas7_pmx_pin_enable(pmx, mux->pin, mux->func);
3854 if (ret) {
3855 dev_err(pmx->dev,
3856 "FUNC:%s GRP:%s PIN#%d.%d failed, ret=%d\n",
3857 pmx_func->name, pin_grp->name,
3858 mux->pin, mux->func, ret);
3859 BUG_ON(1);
3860 }
3861 __atlas7_pmx_pin_input_disable_clr(pmx, mux);
3862 }
3863 pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### END <<<\n",
3864 pmx_func->name, pin_grp->name);
3865
3866 return 0;
3867}
3868
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3869static u32 convert_current_to_drive_strength(u32 type, u32 ma)
3870{
3871 int idx;
3872
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]3873 for (idx = 0; idx < ARRAY_SIZE(atlas7_ma2ds_map); idx++) {
3874 if (atlas7_ma2ds_map[idx].ma != ma)
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3875 continue;
3876
3877 if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU)
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]3878 return atlas7_ma2ds_map[idx].ds_4we;
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3879 else if (type == PAD_T_16ST)
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]3880 return atlas7_ma2ds_map[idx].ds_16st;
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3881 else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU)
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]3882 return atlas7_ma2ds_map[idx].ds_0204m31;
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3883 else if (type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU)
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]3884 return atlas7_ma2ds_map[idx].ds_0610m31;
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3885 }
3886
3887 return DS_NULL;
3888}
3889
3890static int altas7_pinctrl_set_pull_sel(struct pinctrl_dev *pctldev,
3891 u32 pin, u32 sel)
3892{
3893 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3894 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]3895 const struct atlas7_pull_info *pull_info;
3896 u32 bank;
3897 unsigned long regv;
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]3898 void __iomem *pull_sel_reg;
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3899
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]3900 bank = atlas7_pin_to_bank(pin);
3901 pull_info = &atlas7_pull_map[conf->type];
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3902 pull_sel_reg = pmx->regs[bank] + conf->pupd_reg;
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3903
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]3904 /* Retrieve correspond register value from table by sel */
3905 regv = pull_info->s2v[sel].data & pull_info->mask;
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3906
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]3907 /* Clear & Set new value to pull register */
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]3908 writel(pull_info->mask << conf->pupd_bit, CLR_REG(pull_sel_reg));
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]3909 writel(regv << conf->pupd_bit, pull_sel_reg);
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3910
3911 pr_debug("PIN_CFG ### SET PIN#%d PULL SELECTOR:%d == OK ####\n",
3912 pin, sel);
3913 return 0;
3914}
3915
3916static int __altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
3917 u32 pin, u32 sel)
3918{
3919 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3920 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]3921 const struct atlas7_ds_info *ds_info;
3922 u32 bank;
3923 void __iomem *ds_sel_reg;
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3924
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]3925 ds_info = &atlas7_ds_map[conf->type];
3926 if (sel & (~(ds_info->mask)))
3927 goto unsupport;
3928
3929 bank = atlas7_pin_to_bank(pin);
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3930 ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg;
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3931
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]3932 writel(ds_info->imval << conf->drvstr_bit, CLR_REG(ds_sel_reg));
3933 writel(sel << conf->drvstr_bit, ds_sel_reg);
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3934
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]3935 return 0;
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3936
3937unsupport:
3938 pr_err("Pad#%d type[%d] doesn't support ds code[%d]!\n",
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]3939 pin, conf->type, sel);
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]3940 return -ENOTSUPP;
3941}
3942
3943static int altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
3944 u32 pin, u32 ma)
3945{
3946 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3947 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
3948 u32 type = conf->type;
3949 u32 sel;
3950 int ret;
3951
3952 sel = convert_current_to_drive_strength(conf->type, ma);
3953 if (DS_NULL == sel) {
3954 pr_err("Pad#%d type[%d] doesn't support ds current[%d]!\n",
3955 pin, type, ma);
3956 return -ENOTSUPP;
3957 }
3958
3959 ret = __altas7_pinctrl_set_drive_strength_sel(pctldev,
3960 pin, sel);
3961 pr_debug("PIN_CFG ### SET PIN#%d DS:%d MA:%d == %s ####\n",
3962 pin, sel, ma, ret?"FAILED":"OK");
3963 return ret;
3964}
3965
3966static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
3967 struct pinctrl_gpio_range *range, u32 pin)
3968{
3969 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3970 u32 idx;
3971
3972 dev_dbg(pmx->dev,
3973 "atlas7_pmx_gpio_request_enable: pin=%d\n", pin);
3974 for (idx = 0; idx < range->npins; idx++) {
3975 if (pin == range->pins[idx])
3976 break;
3977 }
3978
3979 if (idx >= range->npins) {
3980 dev_err(pmx->dev,
3981 "The pin#%d could not be requested as GPIO!!\n",
3982 pin);
3983 return -EPERM;
3984 }
3985
3986 __atlas7_pmx_pin_enable(pmx, pin, FUNC_GPIO);
3987
3988 return 0;
3989}
3990
3991static struct pinmux_ops atlas7_pinmux_ops = {
3992 .get_functions_count = atlas7_pmx_get_funcs_count,
3993 .get_function_name = atlas7_pmx_get_func_name,
3994 .get_function_groups = atlas7_pmx_get_func_groups,
3995 .set_mux = atlas7_pmx_set_mux,
3996 .gpio_request_enable = atlas7_pmx_gpio_request_enable,
3997};
3998
3999static int atlas7_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
4000{
4001 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4002
4003 return pmx->pctl_data->grps_cnt;
4004}
4005
4006static const char *atlas7_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
4007 u32 group)
4008{
4009 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4010
4011 return pmx->pctl_data->grps[group].name;
4012}
4013
4014static int atlas7_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
4015 u32 group, const u32 **pins, u32 *num_pins)
4016{
4017 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4018
4019 *num_pins = pmx->pctl_data->grps[group].num_pins;
4020 *pins = pmx->pctl_data->grps[group].pins;
4021
4022 return 0;
4023}
4024
4025static int atlas7_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
4026 struct device_node *np_config,
4027 struct pinctrl_map **map,
4028 u32 *num_maps)
4029{
4030 return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
4031 num_maps, PIN_MAP_TYPE_INVALID);
4032}
4033
4034static void atlas7_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
4035 struct pinctrl_map *map, u32 num_maps)
4036{
4037 kfree(map);
4038}
4039
4040static const struct pinctrl_ops atlas7_pinctrl_ops = {
4041 .get_groups_count = atlas7_pinctrl_get_groups_count,
4042 .get_group_name = atlas7_pinctrl_get_group_name,
4043 .get_group_pins = atlas7_pinctrl_get_group_pins,
4044 .dt_node_to_map = atlas7_pinctrl_dt_node_to_map,
4045 .dt_free_map = atlas7_pinctrl_dt_free_map,
4046};
4047
4048static int atlas7_pin_config_set(struct pinctrl_dev *pctldev,
4049 unsigned pin, unsigned long *configs,
4050 unsigned num_configs)
4051{
4052 u16 param, arg;
4053 int idx, err;
4054
4055 for (idx = 0; idx < num_configs; idx++) {
4056 param = pinconf_to_config_param(configs[idx]);
4057 arg = pinconf_to_config_argument(configs[idx]);
4058
4059 pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d >>>>>\n",
4060 pin, atlas7_ioc_pads[pin].name, param, arg);
4061 switch (param) {
4062 case PIN_CONFIG_BIAS_PULL_UP:
4063 err = altas7_pinctrl_set_pull_sel(pctldev,
4064 pin, PULL_UP);
4065 if (err)
4066 return err;
4067 break;
4068
4069 case PIN_CONFIG_BIAS_PULL_DOWN:
4070 err = altas7_pinctrl_set_pull_sel(pctldev,
4071 pin, PULL_DOWN);
4072 if (err)
4073 return err;
4074 break;
4075
4076 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
4077 err = altas7_pinctrl_set_pull_sel(pctldev,
4078 pin, HIGH_HYSTERESIS);
4079 if (err)
4080 return err;
4081 break;
4082 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
4083 err = altas7_pinctrl_set_pull_sel(pctldev,
4084 pin, HIGH_Z);
4085 if (err)
4086 return err;
4087 break;
4088
4089 case PIN_CONFIG_DRIVE_STRENGTH:
4090 err = altas7_pinctrl_set_drive_strength_sel(pctldev,
4091 pin, arg);
4092 if (err)
4093 return err;
4094 break;
4095 default:
4096 return -ENOTSUPP;
4097 }
4098 pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d <<<<\n",
4099 pin, atlas7_ioc_pads[pin].name, param, arg);
4100 }
4101
4102 return 0;
4103}
4104
4105static int atlas7_pin_config_group_set(struct pinctrl_dev *pctldev,
4106 unsigned group, unsigned long *configs,
4107 unsigned num_configs)
4108{
4109 const unsigned *pins;
4110 unsigned npins;
4111 int i, ret;
4112
4113 ret = atlas7_pinctrl_get_group_pins(pctldev, group, &pins, &npins);
4114 if (ret)
4115 return ret;
4116 for (i = 0; i < npins; i++) {
4117 if (atlas7_pin_config_set(pctldev, pins[i],
4118 configs, num_configs))
4119 return -ENOTSUPP;
4120 }
4121 return 0;
4122}
4123
4124static const struct pinconf_ops atlas7_pinconf_ops = {
4125 .pin_config_set = atlas7_pin_config_set,
4126 .pin_config_group_set = atlas7_pin_config_group_set,
4127 .is_generic = true,
4128};
4129
4130static int atlas7_pinmux_probe(struct platform_device *pdev)
4131{
4132 int ret, idx;
4133 struct atlas7_pmx *pmx;
4134 struct device_node *np = pdev->dev.of_node;
4135 u32 banks = ATLAS7_PINCTRL_REG_BANKS;
4136
4137 /* Create state holders etc for this driver */
4138 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
4139 if (!pmx)
4140 return -ENOMEM;
4141
4142 pmx->dev = &pdev->dev;
4143
4144 pmx->pctl_data = &atlas7_ioc_data;
4145 pmx->pctl_desc.name = "pinctrl-atlas7";
4146 pmx->pctl_desc.pins = pmx->pctl_data->pads;
4147 pmx->pctl_desc.npins = pmx->pctl_data->pads_cnt;
4148 pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops;
4149 pmx->pctl_desc.pmxops = &atlas7_pinmux_ops;
4150 pmx->pctl_desc.confops = &atlas7_pinconf_ops;
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]4151
4152 for (idx = 0; idx < banks; idx++) {
4153 pmx->regs[idx] = of_iomap(np, idx);
4154 if (!pmx->regs[idx]) {
4155 dev_err(&pdev->dev,
4156 "can't map ioc bank#%d registers\n", idx);
4157 ret = -ENOMEM;
4158 goto unmap_io;
4159 }
4160 }
4161
4162 /* Now register the pin controller and all pins it handles */
4163 pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx);
Masahiro Yamada323de9e2015-06-09 13:01:16 +0900[diff] [blame]4164 if (IS_ERR(pmx->pctl)) {
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]4165 dev_err(&pdev->dev, "could not register atlas7 pinmux driver\n");
Masahiro Yamada323de9e2015-06-09 13:01:16 +0900[diff] [blame]4166 ret = PTR_ERR(pmx->pctl);
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]4167 goto unmap_io;
4168 }
4169
4170 platform_set_drvdata(pdev, pmx);
4171
4172 dev_info(&pdev->dev, "initialized atlas7 pinmux driver\n");
4173
4174 return 0;
4175
4176unmap_io:
4177 for (idx = 0; idx < banks; idx++) {
4178 if (!pmx->regs[idx])
4179 break;
4180 iounmap(pmx->regs[idx]);
4181 }
4182
4183 return ret;
4184}
4185
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]4186#ifdef CONFIG_PM_SLEEP
4187static int atlas7_pinmux_suspend_noirq(struct device *dev)
4188{
4189 struct atlas7_pmx *pmx = dev_get_drvdata(dev);
4190 struct atlas7_pad_status *status;
4191 struct atlas7_pad_config *conf;
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]4192 const struct atlas7_ds_info *ds_info;
4193 const struct atlas7_pull_info *pull_info;
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]4194 int idx;
4195 u32 bank;
4196 unsigned long regv;
4197
4198 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
4199 /* Get this Pad's descriptor from PINCTRL */
4200 conf = &pmx->pctl_data->confs[idx];
4201 bank = atlas7_pin_to_bank(idx);
4202 status = &pmx->sleep_data[idx];
4203
4204 /* Save Function selector */
4205 regv = readl(pmx->regs[bank] + conf->mux_reg);
4206 status->func = (regv >> conf->mux_bit) & FUNC_CLEAR_MASK;
4207
4208 /* Check if Pad is in Analogue selector */
4209 if (conf->ad_ctrl_reg == -1)
4210 goto save_ds_sel;
4211
4212 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
4213 if (!(regv & (conf->ad_ctrl_bit << ANA_CLEAR_MASK)))
4214 status->func = FUNC_ANALOGUE;
4215
4216save_ds_sel:
4217 if (conf->drvstr_reg == -1)
4218 goto save_pull_sel;
4219
4220 /* Save Drive Strength selector */
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]4221 ds_info = &atlas7_ds_map[conf->type];
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]4222 regv = readl(pmx->regs[bank] + conf->drvstr_reg);
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]4223 status->dstr = (regv >> conf->drvstr_bit) & ds_info->mask;
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]4224
4225save_pull_sel:
4226 /* Save Pull selector */
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]4227 pull_info = &atlas7_pull_map[conf->type];
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]4228 regv = readl(pmx->regs[bank] + conf->pupd_reg);
Wei Chen627b1512015-08-05 03:22:14 +0000[diff] [blame]4229 regv = (regv >> conf->pupd_bit) & pull_info->mask;
4230 status->pull = pull_info->v2s[regv].data;
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]4231 }
4232
4233 /*
4234 * Save disable input selector, this selector is not for Pin,
4235 * but for Mux function.
4236 */
4237 for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
4238 pmx->status_ds[idx] = readl(pmx->regs[BANK_DS] +
4239 IN_DISABLE_0_REG_SET + 0x8 * idx);
4240 pmx->status_dsv[idx] = readl(pmx->regs[BANK_DS] +
4241 IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
4242 }
4243
4244 return 0;
4245}
4246
4247static int atlas7_pinmux_resume_noirq(struct device *dev)
4248{
4249 struct atlas7_pmx *pmx = dev_get_drvdata(dev);
4250 struct atlas7_pad_status *status;
4251 struct atlas7_pad_config *conf;
4252 int idx;
4253 u32 bank;
4254
4255 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
4256 /* Get this Pad's descriptor from PINCTRL */
4257 conf = &pmx->pctl_data->confs[idx];
4258 bank = atlas7_pin_to_bank(idx);
4259 status = &pmx->sleep_data[idx];
4260
4261 /* Restore Function selector */
4262 __atlas7_pmx_pin_enable(pmx, idx, (u32)status->func & 0xff);
4263
4264 if (FUNC_ANALOGUE == status->func)
4265 goto restore_pull_sel;
4266
4267 /* Restore Drive Strength selector */
4268 __altas7_pinctrl_set_drive_strength_sel(pmx->pctl, idx,
4269 (u32)status->dstr & 0xff);
4270
4271restore_pull_sel:
4272 /* Restore Pull selector */
4273 altas7_pinctrl_set_pull_sel(pmx->pctl, idx,
4274 (u32)status->pull & 0xff);
4275 }
4276
4277 /*
4278 * Restore disable input selector, this selector is not for Pin,
4279 * but for Mux function
4280 */
4281 for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
4282 writel(~0, pmx->regs[BANK_DS] +
4283 IN_DISABLE_0_REG_CLR + 0x8 * idx);
4284 writel(pmx->status_ds[idx], pmx->regs[BANK_DS] +
4285 IN_DISABLE_0_REG_SET + 0x8 * idx);
4286 writel(~0, pmx->regs[BANK_DS] +
4287 IN_DISABLE_VAL_0_REG_CLR + 0x8 * idx);
4288 writel(pmx->status_dsv[idx], pmx->regs[BANK_DS] +
4289 IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
4290 }
4291
4292 return 0;
4293}
4294
4295static const struct dev_pm_ops atlas7_pinmux_pm_ops = {
4296 .suspend_noirq = atlas7_pinmux_suspend_noirq,
4297 .resume_noirq = atlas7_pinmux_resume_noirq,
4298 .freeze_noirq = atlas7_pinmux_suspend_noirq,
4299 .restore_noirq = atlas7_pinmux_resume_noirq,
4300};
4301#endif
4302
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]4303static const struct of_device_id atlas7_pinmux_ids[] = {
4304 { .compatible = "sirf,atlas7-ioc",},
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]4305 {},
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]4306};
4307
4308static struct platform_driver atlas7_pinmux_driver = {
4309 .driver = {
4310 .name = "atlas7-ioc",
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]4311 .of_match_table = atlas7_pinmux_ids,
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]4312#ifdef CONFIG_PM_SLEEP
4313 .pm = &atlas7_pinmux_pm_ops,
4314#endif
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]4315 },
4316 .probe = atlas7_pinmux_probe,
4317};
4318
4319static int __init atlas7_pinmux_init(void)
4320{
4321 return platform_driver_register(&atlas7_pinmux_driver);
4322}
4323arch_initcall(atlas7_pinmux_init);
4324
4325
4326/**
4327 * The Following is GPIO Code
4328 */
4329static inline struct
4330atlas7_gpio_bank *atlas7_gpio_to_bank(struct atlas7_gpio_chip *a7gc, u32 gpio)
4331{
4332 return &a7gc->banks[GPIO_TO_BANK(gpio)];
4333}
4334
4335static int __atlas7_gpio_to_pin(struct atlas7_gpio_chip *a7gc, u32 gpio)
4336{
4337 struct atlas7_gpio_bank *bank;
4338 u32 ofs;
4339
4340 bank = atlas7_gpio_to_bank(a7gc, gpio);
4341 ofs = gpio - bank->gpio_offset;
4342 if (ofs >= bank->ngpio)
4343 return -ENODEV;
4344
4345 return bank->gpio_pins[ofs];
4346}
4347
4348static void atlas7_gpio_irq_ack(struct irq_data *d)
4349{
4350 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
4351 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
4352 struct atlas7_gpio_bank *bank;
4353 void __iomem *ctrl_reg;
4354 u32 val, pin_in_bank;
4355 unsigned long flags;
4356
4357 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
4358 pin_in_bank = d->hwirq - bank->gpio_offset;
4359 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
4360
4361 spin_lock_irqsave(&a7gc->lock, flags);
4362
4363 val = readl(ctrl_reg);
4364 /* clear interrupt status */
4365 writel(val, ctrl_reg);
4366
4367 spin_unlock_irqrestore(&a7gc->lock, flags);
4368}
4369
4370static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx)
4371{
4372 struct atlas7_gpio_bank *bank;
4373 void __iomem *ctrl_reg;
4374 u32 val, pin_in_bank;
4375
4376 bank = atlas7_gpio_to_bank(a7gc, idx);
4377 pin_in_bank = idx - bank->gpio_offset;
4378 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
4379
4380 val = readl(ctrl_reg);
4381 val &= ~(ATLAS7_GPIO_CTL_INTR_EN_MASK |
4382 ATLAS7_GPIO_CTL_INTR_STATUS_MASK);
4383 writel(val, ctrl_reg);
4384}
4385
4386static void atlas7_gpio_irq_mask(struct irq_data *d)
4387{
4388 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
4389 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
4390 unsigned long flags;
4391
4392 spin_lock_irqsave(&a7gc->lock, flags);
4393
4394 __atlas7_gpio_irq_mask(a7gc, d->hwirq);
4395
4396 spin_unlock_irqrestore(&a7gc->lock, flags);
4397}
4398
4399static void atlas7_gpio_irq_unmask(struct irq_data *d)
4400{
4401 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
4402 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
4403 struct atlas7_gpio_bank *bank;
4404 void __iomem *ctrl_reg;
4405 u32 val, pin_in_bank;
4406 unsigned long flags;
4407
4408 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
4409 pin_in_bank = d->hwirq - bank->gpio_offset;
4410 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
4411
4412 spin_lock_irqsave(&a7gc->lock, flags);
4413
4414 val = readl(ctrl_reg);
4415 val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK;
4416 val |= ATLAS7_GPIO_CTL_INTR_EN_MASK;
4417 writel(val, ctrl_reg);
4418
4419 spin_unlock_irqrestore(&a7gc->lock, flags);
4420}
4421
4422static int atlas7_gpio_irq_type(struct irq_data *d,
4423 unsigned int type)
4424{
4425 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
4426 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
4427 struct atlas7_gpio_bank *bank;
4428 void __iomem *ctrl_reg;
4429 u32 val, pin_in_bank;
4430 unsigned long flags;
4431
4432 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
4433 pin_in_bank = d->hwirq - bank->gpio_offset;
4434 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
4435
4436 spin_lock_irqsave(&a7gc->lock, flags);
4437
4438 val = readl(ctrl_reg);
4439 val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK |
4440 ATLAS7_GPIO_CTL_INTR_EN_MASK);
4441
4442 switch (type) {
4443 case IRQ_TYPE_NONE:
4444 break;
4445
4446 case IRQ_TYPE_EDGE_RISING:
4447 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
4448 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
4449 val &= ~ATLAS7_GPIO_CTL_INTR_LOW_MASK;
4450 break;
4451
4452 case IRQ_TYPE_EDGE_FALLING:
4453 val &= ~ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
4454 val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK |
4455 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
4456 break;
4457
4458 case IRQ_TYPE_EDGE_BOTH:
4459 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
4460 ATLAS7_GPIO_CTL_INTR_LOW_MASK |
4461 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
4462 break;
4463
4464 case IRQ_TYPE_LEVEL_LOW:
4465 val &= ~(ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
4466 ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
4467 val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK;
4468 break;
4469
4470 case IRQ_TYPE_LEVEL_HIGH:
4471 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
4472 val &= ~(ATLAS7_GPIO_CTL_INTR_LOW_MASK |
4473 ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
4474 break;
4475 }
4476
4477 writel(val, ctrl_reg);
4478
4479 spin_unlock_irqrestore(&a7gc->lock, flags);
4480
4481 return 0;
4482}
4483
4484static struct irq_chip atlas7_gpio_irq_chip = {
4485 .name = "atlas7-gpio-irq",
4486 .irq_ack = atlas7_gpio_irq_ack,
4487 .irq_mask = atlas7_gpio_irq_mask,
4488 .irq_unmask = atlas7_gpio_irq_unmask,
4489 .irq_set_type = atlas7_gpio_irq_type,
4490};
4491
Thomas Gleixner3b0d1562015-07-13 01:54:35 +0200[diff] [blame]4492static void atlas7_gpio_handle_irq(unsigned int __irq, struct irq_desc *desc)
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]4493{
4494 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
4495 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
4496 struct atlas7_gpio_bank *bank = NULL;
4497 u32 status, ctrl;
4498 int pin_in_bank = 0, idx;
Thomas Gleixner3b0d1562015-07-13 01:54:35 +0200[diff] [blame]4499 struct irq_chip *chip = irq_desc_get_chip(desc);
4500 unsigned int irq = irq_desc_get_irq(desc);
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]4501
4502 for (idx = 0; idx < a7gc->nbank; idx++) {
4503 bank = &a7gc->banks[idx];
4504 if (bank->irq == irq)
4505 break;
4506 }
4507 BUG_ON(idx == a7gc->nbank);
4508
4509 chained_irq_enter(chip, desc);
4510
4511 status = readl(ATLAS7_GPIO_INT_STATUS(bank));
4512 if (!status) {
4513 pr_warn("%s: gpio [%s] status %#x no interrupt is flaged\n",
4514 __func__, gc->label, status);
4515 handle_bad_irq(irq, desc);
4516 return;
4517 }
4518
4519 while (status) {
4520 ctrl = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
4521
4522 /*
4523 * Here we must check whether the corresponding GPIO's
4524 * interrupt has been enabled, otherwise just skip it
4525 */
4526 if ((status & 0x1) && (ctrl & ATLAS7_GPIO_CTL_INTR_EN_MASK)) {
4527 pr_debug("%s: chip[%s] gpio:%d happens\n",
4528 __func__, gc->label,
4529 bank->gpio_offset + pin_in_bank);
4530 generic_handle_irq(
4531 irq_find_mapping(gc->irqdomain,
4532 bank->gpio_offset + pin_in_bank));
4533 }
4534
4535 if (++pin_in_bank >= bank->ngpio)
4536 break;
4537
4538 status = status >> 1;
4539 }
4540
4541 chained_irq_exit(chip, desc);
4542}
4543
4544static void __atlas7_gpio_set_input(struct atlas7_gpio_chip *a7gc,
4545 unsigned int gpio)
4546{
4547 struct atlas7_gpio_bank *bank;
4548 void __iomem *ctrl_reg;
4549 u32 val, pin_in_bank;
4550
4551 bank = atlas7_gpio_to_bank(a7gc, gpio);
4552 pin_in_bank = gpio - bank->gpio_offset;
4553 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
4554
4555 val = readl(ctrl_reg);
4556 val &= ~ATLAS7_GPIO_CTL_OUT_EN_MASK;
4557 writel(val, ctrl_reg);
4558}
4559
4560static int atlas7_gpio_request(struct gpio_chip *chip,
4561 unsigned int gpio)
4562{
4563 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
4564 int ret;
4565 unsigned long flags;
4566
4567 ret = __atlas7_gpio_to_pin(a7gc, gpio);
4568 if (ret < 0)
4569 return ret;
4570
4571 if (pinctrl_request_gpio(chip->base + gpio))
4572 return -ENODEV;
4573
4574 spin_lock_irqsave(&a7gc->lock, flags);
4575
4576 /*
4577 * default status:
4578 * set direction as input and mask irq
4579 */
4580 __atlas7_gpio_set_input(a7gc, gpio);
4581 __atlas7_gpio_irq_mask(a7gc, gpio);
4582
4583 spin_unlock_irqrestore(&a7gc->lock, flags);
4584
4585 return 0;
4586}
4587
4588static void atlas7_gpio_free(struct gpio_chip *chip,
4589 unsigned int gpio)
4590{
4591 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
4592 unsigned long flags;
4593
4594 spin_lock_irqsave(&a7gc->lock, flags);
4595
4596 __atlas7_gpio_irq_mask(a7gc, gpio);
4597 __atlas7_gpio_set_input(a7gc, gpio);
4598
4599 spin_unlock_irqrestore(&a7gc->lock, flags);
4600
4601 pinctrl_free_gpio(chip->base + gpio);
4602}
4603
4604static int atlas7_gpio_direction_input(struct gpio_chip *chip,
4605 unsigned int gpio)
4606{
4607 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
4608 unsigned long flags;
4609
4610 spin_lock_irqsave(&a7gc->lock, flags);
4611
4612 __atlas7_gpio_set_input(a7gc, gpio);
4613
4614 spin_unlock_irqrestore(&a7gc->lock, flags);
4615
4616 return 0;
4617}
4618
4619static void __atlas7_gpio_set_output(struct atlas7_gpio_chip *a7gc,
4620 unsigned int gpio, int value)
4621{
4622 struct atlas7_gpio_bank *bank;
4623 void __iomem *ctrl_reg;
4624 u32 out_ctrl, pin_in_bank;
4625
4626 bank = atlas7_gpio_to_bank(a7gc, gpio);
4627 pin_in_bank = gpio - bank->gpio_offset;
4628 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
4629
4630 out_ctrl = readl(ctrl_reg);
4631 if (value)
4632 out_ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
4633 else
4634 out_ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
4635
4636 out_ctrl &= ~ATLAS7_GPIO_CTL_INTR_EN_MASK;
4637 out_ctrl |= ATLAS7_GPIO_CTL_OUT_EN_MASK;
4638 writel(out_ctrl, ctrl_reg);
4639}
4640
4641static int atlas7_gpio_direction_output(struct gpio_chip *chip,
4642 unsigned int gpio, int value)
4643{
4644 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
4645 unsigned long flags;
4646
4647 spin_lock_irqsave(&a7gc->lock, flags);
4648
4649 __atlas7_gpio_set_output(a7gc, gpio, value);
4650
4651 spin_unlock_irqrestore(&a7gc->lock, flags);
4652
4653 return 0;
4654}
4655
4656static int atlas7_gpio_get_value(struct gpio_chip *chip,
4657 unsigned int gpio)
4658{
4659 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
4660 struct atlas7_gpio_bank *bank;
4661 u32 val, pin_in_bank;
4662 unsigned long flags;
4663
4664 bank = atlas7_gpio_to_bank(a7gc, gpio);
4665 pin_in_bank = gpio - bank->gpio_offset;
4666
4667 spin_lock_irqsave(&a7gc->lock, flags);
4668
4669 val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
4670
4671 spin_unlock_irqrestore(&a7gc->lock, flags);
4672
4673 return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK);
4674}
4675
4676static void atlas7_gpio_set_value(struct gpio_chip *chip,
4677 unsigned int gpio, int value)
4678{
4679 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
4680 struct atlas7_gpio_bank *bank;
4681 void __iomem *ctrl_reg;
4682 u32 ctrl, pin_in_bank;
4683 unsigned long flags;
4684
4685 bank = atlas7_gpio_to_bank(a7gc, gpio);
4686 pin_in_bank = gpio - bank->gpio_offset;
4687 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
4688
4689 spin_lock_irqsave(&a7gc->lock, flags);
4690
4691 ctrl = readl(ctrl_reg);
4692 if (value)
4693 ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
4694 else
4695 ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
4696 writel(ctrl, ctrl_reg);
4697
4698 spin_unlock_irqrestore(&a7gc->lock, flags);
4699}
4700
4701static const struct of_device_id atlas7_gpio_ids[] = {
4702 { .compatible = "sirf,atlas7-gpio", },
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]4703 {},
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]4704};
4705
4706static int atlas7_gpio_probe(struct platform_device *pdev)
4707{
4708 struct device_node *np = pdev->dev.of_node;
4709 struct atlas7_gpio_chip *a7gc;
4710 struct gpio_chip *chip;
4711 u32 nbank;
4712 int ret, idx;
4713
4714 ret = of_property_read_u32(np, "gpio-banks", &nbank);
4715 if (ret) {
4716 dev_err(&pdev->dev,
4717 "Could not find GPIO bank info,ret=%d!\n",
4718 ret);
4719 return ret;
4720 }
4721
4722 /* retrieve gpio descriptor data */
4723 a7gc = devm_kzalloc(&pdev->dev, sizeof(*a7gc) +
4724 sizeof(struct atlas7_gpio_bank) * nbank, GFP_KERNEL);
4725 if (!a7gc)
4726 return -ENOMEM;
4727
4728 /* Get Gpio clk */
4729 a7gc->clk = of_clk_get(np, 0);
4730 if (!IS_ERR(a7gc->clk)) {
4731 ret = clk_prepare_enable(a7gc->clk);
4732 if (ret) {
4733 dev_err(&pdev->dev,
4734 "Could not enable clock!\n");
4735 return ret;
4736 }
4737 }
4738
4739 /* Get Gpio Registers */
4740 a7gc->reg = of_iomap(np, 0);
4741 if (!a7gc->reg) {
4742 dev_err(&pdev->dev, "Could not map GPIO Registers!\n");
4743 return -ENOMEM;
4744 }
4745
4746 a7gc->nbank = nbank;
4747 spin_lock_init(&a7gc->lock);
4748
4749 /* Setup GPIO Chip */
4750 chip = &a7gc->chip;
4751 chip->request = atlas7_gpio_request;
4752 chip->free = atlas7_gpio_free;
4753 chip->direction_input = atlas7_gpio_direction_input;
4754 chip->get = atlas7_gpio_get_value;
4755 chip->direction_output = atlas7_gpio_direction_output;
4756 chip->set = atlas7_gpio_set_value;
4757 chip->base = -1;
4758 /* Each chip can support 32 pins at one bank */
4759 chip->ngpio = NGPIO_OF_BANK * nbank;
4760 chip->label = kstrdup(np->name, GFP_KERNEL);
4761 chip->of_node = np;
4762 chip->of_gpio_n_cells = 2;
4763 chip->dev = &pdev->dev;
4764
4765 /* Add gpio chip to system */
4766 ret = gpiochip_add(chip);
4767 if (ret) {
4768 dev_err(&pdev->dev,
4769 "%s: error in probe function with status %d\n",
4770 np->name, ret);
4771 goto failed;
4772 }
4773
4774 /* Add gpio chip to irq subsystem */
4775 ret = gpiochip_irqchip_add(chip, &atlas7_gpio_irq_chip,
4776 0, handle_level_irq, IRQ_TYPE_NONE);
4777 if (ret) {
4778 dev_err(&pdev->dev,
4779 "could not connect irqchip to gpiochip\n");
4780 goto failed;
4781 }
4782
4783 for (idx = 0; idx < nbank; idx++) {
4784 struct gpio_pin_range *pin_range;
4785 struct atlas7_gpio_bank *bank;
4786
4787 bank = &a7gc->banks[idx];
4788 /* Set ctrl registers' base of this bank */
4789 bank->base = ATLAS7_GPIO_BASE(a7gc, idx);
4790
4791 /* Get interrupt number from DTS */
4792 ret = of_irq_get(np, idx);
4793 if (ret == -EPROBE_DEFER) {
4794 dev_err(&pdev->dev,
4795 "Unable to find IRQ number. ret=%d\n", ret);
4796 goto failed;
4797 }
4798 bank->irq = ret;
4799
4800 gpiochip_set_chained_irqchip(chip, &atlas7_gpio_irq_chip,
4801 bank->irq, atlas7_gpio_handle_irq);
4802
4803 /* Records gpio_pin_range to a7gc */
4804 list_for_each_entry(pin_range, &chip->pin_ranges, node) {
4805 struct pinctrl_gpio_range *range;
4806
4807 range = &pin_range->range;
4808 if (range->id == NGPIO_OF_BANK * idx) {
4809 bank->gpio_offset = range->id;
4810 bank->ngpio = range->npins;
4811 bank->gpio_pins = range->pins;
4812 bank->pctldev = pin_range->pctldev;
4813 break;
4814 }
4815 }
4816
4817 BUG_ON(!bank->pctldev);
4818 }
4819
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]4820 platform_set_drvdata(pdev, a7gc);
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]4821 dev_info(&pdev->dev, "add to system.\n");
4822 return 0;
4823failed:
4824 return ret;
4825}
4826
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]4827#ifdef CONFIG_PM_SLEEP
4828static int atlas7_gpio_suspend_noirq(struct device *dev)
4829{
4830 struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
4831 struct atlas7_gpio_bank *bank;
4832 void __iomem *ctrl_reg;
4833 u32 idx, pin;
4834
4835 for (idx = 0; idx < a7gc->nbank; idx++) {
4836 bank = &a7gc->banks[idx];
4837 for (pin = 0; pin < bank->ngpio; pin++) {
4838 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
4839 bank->sleep_data[pin] = readl(ctrl_reg);
4840 }
4841 }
4842
4843 return 0;
4844}
4845
4846static int atlas7_gpio_resume_noirq(struct device *dev)
4847{
4848 struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
4849 struct atlas7_gpio_bank *bank;
4850 void __iomem *ctrl_reg;
4851 u32 idx, pin;
4852
4853 for (idx = 0; idx < a7gc->nbank; idx++) {
4854 bank = &a7gc->banks[idx];
4855 for (pin = 0; pin < bank->ngpio; pin++) {
4856 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
4857 writel(bank->sleep_data[pin], ctrl_reg);
4858 }
4859 }
4860
4861 return 0;
4862}
4863
4864static const struct dev_pm_ops atlas7_gpio_pm_ops = {
4865 .suspend_noirq = atlas7_gpio_suspend_noirq,
4866 .resume_noirq = atlas7_gpio_resume_noirq,
4867 .freeze_noirq = atlas7_gpio_suspend_noirq,
4868 .restore_noirq = atlas7_gpio_resume_noirq,
4869};
4870#endif
4871
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]4872static struct platform_driver atlas7_gpio_driver = {
4873 .driver = {
4874 .name = "atlas7-gpio",
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]4875 .of_match_table = atlas7_gpio_ids,
Wei Chen48356aa2015-07-27 11:57:25 +0000[diff] [blame]4876#ifdef CONFIG_PM_SLEEP
4877 .pm = &atlas7_gpio_pm_ops,
4878#endif
Wei Chenf9367792015-05-18 07:28:32 +0000[diff] [blame]4879 },
4880 .probe = atlas7_gpio_probe,
4881};
4882
4883static int __init atlas7_gpio_init(void)
4884{
4885 return platform_driver_register(&atlas7_gpio_driver);
4886}
4887subsys_initcall(atlas7_gpio_init);
4888
4889MODULE_DESCRIPTION("SIRFSOC Atlas7 pin control driver");
4890MODULE_LICENSE("GPL");