blob: 46b4f5eab421badbec1ae38cab4afac88fb7c731 [file] [log] [blame]
Max Filippov5584b4d2012-11-03 12:57:52 +04001/ {
Baruch Siach42beb762013-12-01 10:13:33 +02002 compatible = "cdns,xtensa-xtfpga";
Max Filippov5584b4d2012-11-03 12:57:52 +04003 #address-cells = <1>;
4 #size-cells = <1>;
5 interrupt-parent = <&pic>;
6
7 chosen {
8 bootargs = "earlycon=uart8250,mmio32,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
9 };
10
11 memory@0 {
12 device_type = "memory";
13 reg = <0x00000000 0x06000000>;
14 };
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19 cpu@0 {
Baruch Siach42beb762013-12-01 10:13:33 +020020 compatible = "cdns,xtensa-cpu";
Max Filippov5584b4d2012-11-03 12:57:52 +040021 reg = <0>;
22 /* Filled in by platform_setup from FPGA register
23 * clock-frequency = <100000000>;
24 */
25 };
26 };
27
28 pic: pic {
Max Filippovcbd1de22013-12-01 12:59:49 +040029 compatible = "cdns,xtensa-pic";
Max Filippov5584b4d2012-11-03 12:57:52 +040030 /* one cell: internal irq number,
31 * two cells: second cell == 0: internal irq number
32 * second cell == 1: external irq number
33 */
34 #interrupt-cells = <2>;
35 interrupt-controller;
36 };
37
38 serial0: serial@fd050020 {
39 device_type = "serial";
40 compatible = "ns16550a";
41 no-loopback-test;
42 reg = <0xfd050020 0x20>;
43 reg-shift = <2>;
44 interrupts = <0 1>; /* external irq 0 */
45 /* Filled in by platform_setup from FPGA register
46 * clock-frequency = <100000000>;
47 */
48 };
49
50 enet0: ethoc@fd030000 {
51 compatible = "opencores,ethoc";
52 reg = <0xfd030000 0x4000 0xfd800000 0x4000>;
53 interrupts = <1 1>; /* external irq 1 */
54 local-mac-address = [00 50 c2 13 6f 00];
55 };
56};