blob: 36ec171698b833ddbebb6c9e51e9f18d4c53f278 [file] [log] [blame]
Johannes Weinere5083a62009-03-04 16:21:31 +01001/*
2 * xtensa mmu stuff
3 *
4 * Extracted from init.c
5 */
6#include <linux/percpu.h>
7#include <linux/init.h>
8#include <linux/string.h>
9#include <linux/slab.h>
10#include <linux/cache.h>
11
12#include <asm/tlb.h>
13#include <asm/tlbflush.h>
14#include <asm/mmu_context.h>
15#include <asm/page.h>
Baruch Siach6cb97112013-12-29 11:03:30 +020016#include <asm/initialize_mmu.h>
17#include <asm/io.h>
Johannes Weinere5083a62009-03-04 16:21:31 +010018
Johannes Weinere5083a62009-03-04 16:21:31 +010019void __init paging_init(void)
20{
21 memset(swapper_pg_dir, 0, PAGE_SIZE);
22}
23
24/*
25 * Flush the mmu and reset associated register to default values.
26 */
Max Filippovf6151362013-10-17 02:42:26 +040027void init_mmu(void)
Johannes Weinere5083a62009-03-04 16:21:31 +010028{
Max Filippove85e3352012-12-03 15:01:43 +040029#if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
30 /*
31 * Writing zeros to the instruction and data TLBCFG special
32 * registers ensure that valid values exist in the register.
33 *
34 * For existing PGSZID<w> fields, zero selects the first element
35 * of the page-size array. For nonexistent PGSZID<w> fields,
36 * zero is the best value to write. Also, when changing PGSZID<w>
Johannes Weinere5083a62009-03-04 16:21:31 +010037 * fields, the corresponding TLB must be flushed.
38 */
39 set_itlbcfg_register(0);
40 set_dtlbcfg_register(0);
Max Filippove85e3352012-12-03 15:01:43 +040041#endif
Baruch Siach6cb97112013-12-29 11:03:30 +020042#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && CONFIG_OF
43 /*
44 * Update the IO area mapping in case xtensa_kio_paddr has changed
45 */
46 write_dtlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
47 XCHAL_KIO_CACHED_VADDR + 6);
48 write_itlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
49 XCHAL_KIO_CACHED_VADDR + 6);
50 write_dtlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
51 XCHAL_KIO_BYPASS_VADDR + 6);
52 write_itlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
53 XCHAL_KIO_BYPASS_VADDR + 6);
54#endif
55
Max Filippovf6151362013-10-17 02:42:26 +040056 local_flush_tlb_all();
Johannes Weinere5083a62009-03-04 16:21:31 +010057
58 /* Set rasid register to a known value. */
59
Max Filippovec747b22012-12-11 01:26:24 +040060 set_rasid_register(ASID_INSERT(ASID_USER_FIRST));
Johannes Weinere5083a62009-03-04 16:21:31 +010061
62 /* Set PTEVADDR special register to the start of the page
63 * table, which is in kernel mappable space (ie. not
64 * statically mapped). This register's value is undefined on
65 * reset.
66 */
67 set_ptevaddr_register(PGTABLE_START);
68}