Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1 | /* |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 2 | * Copyright 2012 Red Hat Inc. |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 3 | * |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 10 | * |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 13 | * |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 21 | * |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 22 | * Authors: Ben Skeggs |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 23 | */ |
| 24 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 25 | #include <core/os.h> |
| 26 | #include <core/class.h> |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 27 | #include <core/client.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 28 | #include <core/handle.h> |
| 29 | #include <core/engctx.h> |
| 30 | #include <core/enum.h> |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 31 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 32 | #include <subdev/fb.h> |
| 33 | #include <subdev/vm.h> |
| 34 | #include <subdev/timer.h> |
| 35 | |
Ben Skeggs | 72a1482 | 2012-08-13 16:26:07 +1000 | [diff] [blame] | 36 | #include <engine/fifo.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 37 | #include <engine/graph.h> |
| 38 | |
| 39 | #include "nv50.h" |
| 40 | |
| 41 | struct nv50_graph_priv { |
| 42 | struct nouveau_graph base; |
| 43 | spinlock_t lock; |
| 44 | u32 size; |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 45 | }; |
| 46 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 47 | struct nv50_graph_chan { |
| 48 | struct nouveau_graph_chan base; |
| 49 | }; |
Marcin KoĆcielnicki | 304424e | 2010-03-01 00:18:39 +0000 | [diff] [blame] | 50 | |
Christoph Bumiller | 7e22e71 | 2013-03-27 22:16:54 +0100 | [diff] [blame] | 51 | static u64 |
| 52 | nv50_graph_units(struct nouveau_graph *graph) |
| 53 | { |
| 54 | struct nv50_graph_priv *priv = (void *)graph; |
| 55 | |
| 56 | return nv_rd32(priv, 0x1540); |
| 57 | } |
| 58 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 59 | /******************************************************************************* |
| 60 | * Graphics object classes |
| 61 | ******************************************************************************/ |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 62 | |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 63 | static int |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 64 | nv50_graph_object_ctor(struct nouveau_object *parent, |
| 65 | struct nouveau_object *engine, |
| 66 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 67 | struct nouveau_object **pobject) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 68 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 69 | struct nouveau_gpuobj *obj; |
Ben Skeggs | 4ea52f8 | 2011-03-31 13:44:16 +1000 | [diff] [blame] | 70 | int ret; |
| 71 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 72 | ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, |
| 73 | 16, 16, 0, &obj); |
| 74 | *pobject = nv_object(obj); |
Ben Skeggs | 4ea52f8 | 2011-03-31 13:44:16 +1000 | [diff] [blame] | 75 | if (ret) |
| 76 | return ret; |
Ben Skeggs | 4ea52f8 | 2011-03-31 13:44:16 +1000 | [diff] [blame] | 77 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 78 | nv_wo32(obj, 0x00, nv_mclass(obj)); |
Ben Skeggs | 4ea52f8 | 2011-03-31 13:44:16 +1000 | [diff] [blame] | 79 | nv_wo32(obj, 0x04, 0x00000000); |
| 80 | nv_wo32(obj, 0x08, 0x00000000); |
| 81 | nv_wo32(obj, 0x0c, 0x00000000); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 82 | return 0; |
Ben Skeggs | 4ea52f8 | 2011-03-31 13:44:16 +1000 | [diff] [blame] | 83 | } |
| 84 | |
Marcin Slusarz | 5b8a43a | 2012-08-19 23:00:00 +0200 | [diff] [blame] | 85 | static struct nouveau_ofuncs |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 86 | nv50_graph_ofuncs = { |
| 87 | .ctor = nv50_graph_object_ctor, |
| 88 | .dtor = _nouveau_gpuobj_dtor, |
| 89 | .init = _nouveau_gpuobj_init, |
| 90 | .fini = _nouveau_gpuobj_fini, |
| 91 | .rd32 = _nouveau_gpuobj_rd32, |
| 92 | .wr32 = _nouveau_gpuobj_wr32, |
| 93 | }; |
| 94 | |
| 95 | static struct nouveau_oclass |
| 96 | nv50_graph_sclass[] = { |
| 97 | { 0x0030, &nv50_graph_ofuncs }, |
| 98 | { 0x502d, &nv50_graph_ofuncs }, |
| 99 | { 0x5039, &nv50_graph_ofuncs }, |
| 100 | { 0x5097, &nv50_graph_ofuncs }, |
| 101 | { 0x50c0, &nv50_graph_ofuncs }, |
| 102 | {} |
| 103 | }; |
| 104 | |
| 105 | static struct nouveau_oclass |
| 106 | nv84_graph_sclass[] = { |
| 107 | { 0x0030, &nv50_graph_ofuncs }, |
| 108 | { 0x502d, &nv50_graph_ofuncs }, |
| 109 | { 0x5039, &nv50_graph_ofuncs }, |
| 110 | { 0x50c0, &nv50_graph_ofuncs }, |
| 111 | { 0x8297, &nv50_graph_ofuncs }, |
| 112 | {} |
| 113 | }; |
| 114 | |
| 115 | static struct nouveau_oclass |
| 116 | nva0_graph_sclass[] = { |
| 117 | { 0x0030, &nv50_graph_ofuncs }, |
| 118 | { 0x502d, &nv50_graph_ofuncs }, |
| 119 | { 0x5039, &nv50_graph_ofuncs }, |
| 120 | { 0x50c0, &nv50_graph_ofuncs }, |
| 121 | { 0x8397, &nv50_graph_ofuncs }, |
| 122 | {} |
| 123 | }; |
| 124 | |
| 125 | static struct nouveau_oclass |
| 126 | nva3_graph_sclass[] = { |
| 127 | { 0x0030, &nv50_graph_ofuncs }, |
| 128 | { 0x502d, &nv50_graph_ofuncs }, |
| 129 | { 0x5039, &nv50_graph_ofuncs }, |
| 130 | { 0x50c0, &nv50_graph_ofuncs }, |
| 131 | { 0x8597, &nv50_graph_ofuncs }, |
| 132 | { 0x85c0, &nv50_graph_ofuncs }, |
| 133 | {} |
| 134 | }; |
| 135 | |
| 136 | static struct nouveau_oclass |
| 137 | nvaf_graph_sclass[] = { |
| 138 | { 0x0030, &nv50_graph_ofuncs }, |
| 139 | { 0x502d, &nv50_graph_ofuncs }, |
| 140 | { 0x5039, &nv50_graph_ofuncs }, |
| 141 | { 0x50c0, &nv50_graph_ofuncs }, |
| 142 | { 0x85c0, &nv50_graph_ofuncs }, |
| 143 | { 0x8697, &nv50_graph_ofuncs }, |
| 144 | {} |
| 145 | }; |
| 146 | |
| 147 | /******************************************************************************* |
| 148 | * PGRAPH context |
| 149 | ******************************************************************************/ |
| 150 | |
| 151 | static int |
| 152 | nv50_graph_context_ctor(struct nouveau_object *parent, |
| 153 | struct nouveau_object *engine, |
| 154 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 155 | struct nouveau_object **pobject) |
Ben Skeggs | 56ac747 | 2010-10-22 10:26:24 +1000 | [diff] [blame] | 156 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 157 | struct nv50_graph_priv *priv = (void *)engine; |
| 158 | struct nv50_graph_chan *chan; |
| 159 | int ret; |
| 160 | |
| 161 | ret = nouveau_graph_context_create(parent, engine, oclass, NULL, |
| 162 | priv->size, 0, |
| 163 | NVOBJ_FLAG_ZERO_ALLOC, &chan); |
| 164 | *pobject = nv_object(chan); |
| 165 | if (ret) |
| 166 | return ret; |
| 167 | |
| 168 | nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan)); |
| 169 | return 0; |
Ben Skeggs | 56ac747 | 2010-10-22 10:26:24 +1000 | [diff] [blame] | 170 | } |
| 171 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 172 | static struct nouveau_oclass |
| 173 | nv50_graph_cclass = { |
| 174 | .handle = NV_ENGCTX(GR, 0x50), |
| 175 | .ofuncs = &(struct nouveau_ofuncs) { |
| 176 | .ctor = nv50_graph_context_ctor, |
| 177 | .dtor = _nouveau_graph_context_dtor, |
| 178 | .init = _nouveau_graph_context_init, |
| 179 | .fini = _nouveau_graph_context_fini, |
| 180 | .rd32 = _nouveau_graph_context_rd32, |
| 181 | .wr32 = _nouveau_graph_context_wr32, |
| 182 | }, |
| 183 | }; |
| 184 | |
| 185 | /******************************************************************************* |
| 186 | * PGRAPH engine/subdev functions |
| 187 | ******************************************************************************/ |
| 188 | |
Marcin Slusarz | d432a2d | 2012-11-11 19:52:59 +0100 | [diff] [blame] | 189 | static const struct nouveau_bitfield nv50_pgraph_status[] = { |
| 190 | { 0x00000001, "BUSY" }, /* set when any bit is set */ |
| 191 | { 0x00000002, "DISPATCH" }, |
| 192 | { 0x00000004, "UNK2" }, |
| 193 | { 0x00000008, "UNK3" }, |
| 194 | { 0x00000010, "UNK4" }, |
| 195 | { 0x00000020, "UNK5" }, |
| 196 | { 0x00000040, "M2MF" }, |
| 197 | { 0x00000080, "UNK7" }, |
| 198 | { 0x00000100, "CTXPROG" }, |
| 199 | { 0x00000200, "VFETCH" }, |
| 200 | { 0x00000400, "CCACHE_UNK4" }, |
| 201 | { 0x00000800, "STRMOUT_GSCHED_UNK5" }, |
| 202 | { 0x00001000, "UNK14XX" }, |
| 203 | { 0x00002000, "UNK24XX_CSCHED" }, |
| 204 | { 0x00004000, "UNK1CXX" }, |
| 205 | { 0x00008000, "CLIPID" }, |
| 206 | { 0x00010000, "ZCULL" }, |
| 207 | { 0x00020000, "ENG2D" }, |
| 208 | { 0x00040000, "UNK34XX" }, |
| 209 | { 0x00080000, "TPRAST" }, |
| 210 | { 0x00100000, "TPROP" }, |
| 211 | { 0x00200000, "TEX" }, |
| 212 | { 0x00400000, "TPVP" }, |
| 213 | { 0x00800000, "MP" }, |
| 214 | { 0x01000000, "ROP" }, |
| 215 | {} |
| 216 | }; |
| 217 | |
| 218 | static const char *const nv50_pgraph_vstatus_0[] = { |
| 219 | "VFETCH", "CCACHE", "UNK4", "UNK5", "GSCHED", "STRMOUT", "UNK14XX", NULL |
| 220 | }; |
| 221 | |
| 222 | static const char *const nv50_pgraph_vstatus_1[] = { |
| 223 | "TPRAST", "TPROP", "TEXTURE", "TPVP", "MP", NULL |
| 224 | }; |
| 225 | |
| 226 | static const char *const nv50_pgraph_vstatus_2[] = { |
| 227 | "UNK24XX", "CSCHED", "UNK1CXX", "CLIPID", "ZCULL", "ENG2D", "UNK34XX", |
| 228 | "ROP", NULL |
| 229 | }; |
| 230 | |
| 231 | static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r, |
| 232 | const char *const units[], u32 status) |
| 233 | { |
| 234 | int i; |
| 235 | |
| 236 | nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status); |
| 237 | |
| 238 | for (i = 0; units[i] && status; i++) { |
| 239 | if ((status & 7) == 1) |
| 240 | pr_cont(" %s", units[i]); |
| 241 | status >>= 3; |
| 242 | } |
| 243 | if (status) |
| 244 | pr_cont(" (invalid: 0x%x)", status); |
| 245 | pr_cont("\n"); |
| 246 | } |
| 247 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 248 | static int |
| 249 | nv84_graph_tlb_flush(struct nouveau_engine *engine) |
| 250 | { |
| 251 | struct nouveau_timer *ptimer = nouveau_timer(engine); |
| 252 | struct nv50_graph_priv *priv = (void *)engine; |
Ben Skeggs | 56ac747 | 2010-10-22 10:26:24 +1000 | [diff] [blame] | 253 | bool idle, timeout = false; |
| 254 | unsigned long flags; |
| 255 | u64 start; |
| 256 | u32 tmp; |
| 257 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 258 | spin_lock_irqsave(&priv->lock, flags); |
| 259 | nv_mask(priv, 0x400500, 0x00000001, 0x00000000); |
Ben Skeggs | 56ac747 | 2010-10-22 10:26:24 +1000 | [diff] [blame] | 260 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 261 | start = ptimer->read(ptimer); |
Ben Skeggs | 56ac747 | 2010-10-22 10:26:24 +1000 | [diff] [blame] | 262 | do { |
| 263 | idle = true; |
| 264 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 265 | for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) { |
Ben Skeggs | 56ac747 | 2010-10-22 10:26:24 +1000 | [diff] [blame] | 266 | if ((tmp & 7) == 1) |
| 267 | idle = false; |
| 268 | } |
| 269 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 270 | for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) { |
Ben Skeggs | 56ac747 | 2010-10-22 10:26:24 +1000 | [diff] [blame] | 271 | if ((tmp & 7) == 1) |
| 272 | idle = false; |
| 273 | } |
| 274 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 275 | for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) { |
Ben Skeggs | 56ac747 | 2010-10-22 10:26:24 +1000 | [diff] [blame] | 276 | if ((tmp & 7) == 1) |
| 277 | idle = false; |
| 278 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 279 | } while (!idle && |
| 280 | !(timeout = ptimer->read(ptimer) - start > 2000000000)); |
Ben Skeggs | 56ac747 | 2010-10-22 10:26:24 +1000 | [diff] [blame] | 281 | |
| 282 | if (timeout) { |
Marcin Slusarz | d432a2d | 2012-11-11 19:52:59 +0100 | [diff] [blame] | 283 | nv_error(priv, "PGRAPH TLB flush idle timeout fail\n"); |
| 284 | |
| 285 | tmp = nv_rd32(priv, 0x400700); |
| 286 | nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp); |
| 287 | nouveau_bitfield_print(nv50_pgraph_status, tmp); |
| 288 | pr_cont("\n"); |
| 289 | |
| 290 | nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0, |
| 291 | nv_rd32(priv, 0x400380)); |
| 292 | nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1, |
| 293 | nv_rd32(priv, 0x400384)); |
| 294 | nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2, |
| 295 | nv_rd32(priv, 0x400388)); |
Ben Skeggs | 56ac747 | 2010-10-22 10:26:24 +1000 | [diff] [blame] | 296 | } |
| 297 | |
Ben Skeggs | 56ac747 | 2010-10-22 10:26:24 +1000 | [diff] [blame] | 298 | |
Ben Skeggs | 464d636 | 2013-05-13 20:55:46 +1000 | [diff] [blame] | 299 | nv_wr32(priv, 0x100c80, 0x00000001); |
| 300 | if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) |
| 301 | nv_error(priv, "vm flush timeout\n"); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 302 | nv_mask(priv, 0x400500, 0x00000001, 0x00000001); |
| 303 | spin_unlock_irqrestore(&priv->lock, flags); |
| 304 | return timeout ? -EBUSY : 0; |
Ben Skeggs | 56ac747 | 2010-10-22 10:26:24 +1000 | [diff] [blame] | 305 | } |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 306 | |
Ilia Mirkin | f750ecc | 2014-01-17 06:19:46 -0500 | [diff] [blame] | 307 | static const struct nouveau_bitfield nv50_mp_exec_errors[] = { |
| 308 | { 0x01, "STACK_UNDERFLOW" }, |
| 309 | { 0x02, "STACK_MISMATCH" }, |
| 310 | { 0x04, "QUADON_ACTIVE" }, |
| 311 | { 0x08, "TIMEOUT" }, |
| 312 | { 0x10, "INVALID_OPCODE" }, |
| 313 | { 0x20, "PM_OVERFLOW" }, |
| 314 | { 0x40, "BREAKPOINT" }, |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 315 | {} |
| 316 | }; |
| 317 | |
Ilia Mirkin | ea7dce9 | 2014-01-17 00:13:05 -0500 | [diff] [blame] | 318 | static const struct nouveau_bitfield nv50_mpc_traps[] = { |
| 319 | { 0x0000001, "LOCAL_LIMIT_READ" }, |
| 320 | { 0x0000010, "LOCAL_LIMIT_WRITE" }, |
| 321 | { 0x0000040, "STACK_LIMIT" }, |
| 322 | { 0x0000100, "GLOBAL_LIMIT_READ" }, |
| 323 | { 0x0001000, "GLOBAL_LIMIT_WRITE" }, |
| 324 | { 0x0010000, "MP0" }, |
| 325 | { 0x0020000, "MP1" }, |
| 326 | { 0x0040000, "GLOBAL_LIMIT_RED" }, |
| 327 | { 0x0400000, "GLOBAL_LIMIT_ATOM" }, |
| 328 | { 0x4000000, "MP2" }, |
| 329 | {} |
| 330 | }; |
| 331 | |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 332 | static const struct nouveau_bitfield nv50_graph_trap_m2mf[] = { |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 333 | { 0x00000001, "NOTIFY" }, |
| 334 | { 0x00000002, "IN" }, |
| 335 | { 0x00000004, "OUT" }, |
| 336 | {} |
| 337 | }; |
| 338 | |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 339 | static const struct nouveau_bitfield nv50_graph_trap_vfetch[] = { |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 340 | { 0x00000001, "FAULT" }, |
| 341 | {} |
| 342 | }; |
| 343 | |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 344 | static const struct nouveau_bitfield nv50_graph_trap_strmout[] = { |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 345 | { 0x00000001, "FAULT" }, |
| 346 | {} |
| 347 | }; |
| 348 | |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 349 | static const struct nouveau_bitfield nv50_graph_trap_ccache[] = { |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 350 | { 0x00000001, "FAULT" }, |
| 351 | {} |
| 352 | }; |
| 353 | |
| 354 | /* There must be a *lot* of these. Will take some time to gather them up. */ |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 355 | const struct nouveau_enum nv50_data_error_names[] = { |
Marcin Slusarz | 887cd78 | 2012-06-14 23:58:08 +0200 | [diff] [blame] | 356 | { 0x00000003, "INVALID_OPERATION", NULL }, |
Ben Skeggs | bb9b18a | 2011-03-08 08:39:43 +1000 | [diff] [blame] | 357 | { 0x00000004, "INVALID_VALUE", NULL }, |
| 358 | { 0x00000005, "INVALID_ENUM", NULL }, |
| 359 | { 0x00000008, "INVALID_OBJECT", NULL }, |
| 360 | { 0x00000009, "READ_ONLY_OBJECT", NULL }, |
| 361 | { 0x0000000a, "SUPERVISOR_OBJECT", NULL }, |
| 362 | { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL }, |
| 363 | { 0x0000000c, "INVALID_BITFIELD", NULL }, |
| 364 | { 0x0000000d, "BEGIN_END_ACTIVE", NULL }, |
| 365 | { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL }, |
| 366 | { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL }, |
| 367 | { 0x00000010, "RT_DOUBLE_BIND", NULL }, |
| 368 | { 0x00000011, "RT_TYPES_MISMATCH", NULL }, |
| 369 | { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL }, |
| 370 | { 0x00000015, "FP_TOO_FEW_REGS", NULL }, |
| 371 | { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL }, |
| 372 | { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL }, |
| 373 | { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL }, |
| 374 | { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL }, |
| 375 | { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL }, |
| 376 | { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL }, |
| 377 | { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL }, |
| 378 | { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL }, |
| 379 | { 0x0000001f, "RT_BPP128_WITH_MS8", NULL }, |
| 380 | { 0x00000021, "Z_OUT_OF_BOUNDS", NULL }, |
| 381 | { 0x00000023, "XY_OUT_OF_BOUNDS", NULL }, |
Marcin Slusarz | 547e6c7 | 2012-05-06 23:08:55 +0200 | [diff] [blame] | 382 | { 0x00000024, "VP_ZERO_INPUTS", NULL }, |
Ben Skeggs | bb9b18a | 2011-03-08 08:39:43 +1000 | [diff] [blame] | 383 | { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL }, |
| 384 | { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL }, |
| 385 | { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL }, |
| 386 | { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL }, |
| 387 | { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL }, |
| 388 | { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL }, |
| 389 | { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL }, |
| 390 | { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL }, |
| 391 | { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL }, |
| 392 | { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL }, |
| 393 | { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL }, |
| 394 | { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL }, |
| 395 | { 0x00000046, "LAYER_ID_NEEDS_GP", NULL }, |
| 396 | { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL }, |
| 397 | { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL }, |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 398 | {} |
| 399 | }; |
| 400 | |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 401 | static const struct nouveau_bitfield nv50_graph_intr_name[] = { |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 402 | { 0x00000001, "NOTIFY" }, |
| 403 | { 0x00000002, "COMPUTE_QUERY" }, |
| 404 | { 0x00000010, "ILLEGAL_MTHD" }, |
| 405 | { 0x00000020, "ILLEGAL_CLASS" }, |
| 406 | { 0x00000040, "DOUBLE_NOTIFY" }, |
| 407 | { 0x00001000, "CONTEXT_SWITCH" }, |
| 408 | { 0x00010000, "BUFFER_NOTIFY" }, |
| 409 | { 0x00100000, "DATA_ERROR" }, |
| 410 | { 0x00200000, "TRAP" }, |
| 411 | { 0x01000000, "SINGLE_STEP" }, |
| 412 | {} |
| 413 | }; |
| 414 | |
Ilia Mirkin | e2dd003 | 2014-01-16 02:47:11 -0500 | [diff] [blame] | 415 | static const struct nouveau_bitfield nv50_graph_trap_prop[] = { |
| 416 | { 0x00000004, "SURF_WIDTH_OVERRUN" }, |
| 417 | { 0x00000008, "SURF_HEIGHT_OVERRUN" }, |
| 418 | { 0x00000010, "DST2D_FAULT" }, |
| 419 | { 0x00000020, "ZETA_FAULT" }, |
| 420 | { 0x00000040, "RT_FAULT" }, |
| 421 | { 0x00000080, "CUDA_FAULT" }, |
| 422 | { 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" }, |
| 423 | { 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" }, |
| 424 | { 0x00000400, "RT_STORAGE_TYPE_MISMATCH" }, |
| 425 | { 0x00000800, "DST2D_LINEAR_MISMATCH" }, |
| 426 | { 0x00001000, "RT_LINEAR_MISMATCH" }, |
| 427 | {} |
| 428 | }; |
| 429 | |
| 430 | static void |
| 431 | nv50_priv_prop_trap(struct nv50_graph_priv *priv, |
| 432 | u32 ustatus_addr, u32 ustatus, u32 tp) |
| 433 | { |
| 434 | u32 e0c = nv_rd32(priv, ustatus_addr + 0x04); |
| 435 | u32 e10 = nv_rd32(priv, ustatus_addr + 0x08); |
| 436 | u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c); |
| 437 | u32 e18 = nv_rd32(priv, ustatus_addr + 0x10); |
| 438 | u32 e1c = nv_rd32(priv, ustatus_addr + 0x14); |
| 439 | u32 e20 = nv_rd32(priv, ustatus_addr + 0x18); |
| 440 | u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c); |
| 441 | |
| 442 | /* CUDA memory: l[], g[] or stack. */ |
| 443 | if (ustatus & 0x00000080) { |
| 444 | if (e18 & 0x80000000) { |
| 445 | /* g[] read fault? */ |
| 446 | nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n", |
| 447 | tp, e14, e10 | ((e18 >> 24) & 0x1f)); |
| 448 | e18 &= ~0x1f000000; |
| 449 | } else if (e18 & 0xc) { |
| 450 | /* g[] write fault? */ |
| 451 | nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n", |
| 452 | tp, e14, e10 | ((e18 >> 7) & 0x1f)); |
| 453 | e18 &= ~0x00000f80; |
| 454 | } else { |
| 455 | nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n", |
| 456 | tp, e14, e10); |
| 457 | } |
| 458 | ustatus &= ~0x00000080; |
| 459 | } |
| 460 | if (ustatus) { |
| 461 | nv_error(priv, "TRAP_PROP - TP %d -", tp); |
| 462 | nouveau_bitfield_print(nv50_graph_trap_prop, ustatus); |
| 463 | pr_cont(" - Address %02x%08x\n", e14, e10); |
| 464 | } |
| 465 | nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", |
| 466 | tp, e0c, e18, e1c, e20, e24); |
| 467 | } |
| 468 | |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 469 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 470 | nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display) |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 471 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 472 | u32 units = nv_rd32(priv, 0x1540); |
| 473 | u32 addr, mp10, status, pc, oplow, ophigh; |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 474 | int i; |
| 475 | int mps = 0; |
| 476 | for (i = 0; i < 4; i++) { |
| 477 | if (!(units & 1 << (i+24))) |
| 478 | continue; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 479 | if (nv_device(priv)->chipset < 0xa0) |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 480 | addr = 0x408200 + (tpid << 12) + (i << 7); |
| 481 | else |
| 482 | addr = 0x408100 + (tpid << 11) + (i << 7); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 483 | mp10 = nv_rd32(priv, addr + 0x10); |
| 484 | status = nv_rd32(priv, addr + 0x14); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 485 | if (!status) |
| 486 | continue; |
| 487 | if (display) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 488 | nv_rd32(priv, addr + 0x20); |
| 489 | pc = nv_rd32(priv, addr + 0x24); |
| 490 | oplow = nv_rd32(priv, addr + 0x70); |
| 491 | ophigh = nv_rd32(priv, addr + 0x74); |
| 492 | nv_error(priv, "TRAP_MP_EXEC - " |
Ilia Mirkin | f750ecc | 2014-01-17 06:19:46 -0500 | [diff] [blame] | 493 | "TP %d MP %d:", tpid, i); |
| 494 | nouveau_bitfield_print(nv50_mp_exec_errors, status); |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 495 | pr_cont(" at %06x warp %d, opcode %08x %08x\n", |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 496 | pc&0xffffff, pc >> 24, |
| 497 | oplow, ophigh); |
| 498 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 499 | nv_wr32(priv, addr + 0x10, mp10); |
| 500 | nv_wr32(priv, addr + 0x14, 0); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 501 | mps++; |
| 502 | } |
| 503 | if (!mps && display) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 504 | nv_error(priv, "TRAP_MP_EXEC - TP %d: " |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 505 | "No MPs claiming errors?\n", tpid); |
| 506 | } |
| 507 | |
| 508 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 509 | nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old, |
| 510 | u32 ustatus_new, int display, const char *name) |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 511 | { |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 512 | int tps = 0; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 513 | u32 units = nv_rd32(priv, 0x1540); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 514 | int i, r; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 515 | u32 ustatus_addr, ustatus; |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 516 | for (i = 0; i < 16; i++) { |
| 517 | if (!(units & (1 << i))) |
| 518 | continue; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 519 | if (nv_device(priv)->chipset < 0xa0) |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 520 | ustatus_addr = ustatus_old + (i << 12); |
| 521 | else |
| 522 | ustatus_addr = ustatus_new + (i << 11); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 523 | ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff; |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 524 | if (!ustatus) |
| 525 | continue; |
| 526 | tps++; |
| 527 | switch (type) { |
| 528 | case 6: /* texture error... unknown for now */ |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 529 | if (display) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 530 | nv_error(priv, "magic set %d:\n", i); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 531 | for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 532 | nv_error(priv, "\t0x%08x: 0x%08x\n", r, |
| 533 | nv_rd32(priv, r)); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 534 | } |
| 535 | break; |
| 536 | case 7: /* MP error */ |
Maxim Levitsky | c983e6f | 2011-10-09 22:58:32 +0200 | [diff] [blame] | 537 | if (ustatus & 0x04030000) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 538 | nv50_priv_mp_trap(priv, i, display); |
Maxim Levitsky | c983e6f | 2011-10-09 22:58:32 +0200 | [diff] [blame] | 539 | ustatus &= ~0x04030000; |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 540 | } |
Ilia Mirkin | ea7dce9 | 2014-01-17 00:13:05 -0500 | [diff] [blame] | 541 | if (ustatus && display) { |
| 542 | nv_error("%s - TP%d:", name, i); |
| 543 | nouveau_bitfield_print(nv50_mpc_traps, ustatus); |
| 544 | pr_cont("\n"); |
| 545 | ustatus = 0; |
| 546 | } |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 547 | break; |
Ilia Mirkin | e2dd003 | 2014-01-16 02:47:11 -0500 | [diff] [blame] | 548 | case 8: /* PROP error */ |
| 549 | if (display) |
| 550 | nv50_priv_prop_trap( |
| 551 | priv, ustatus_addr, ustatus, i); |
| 552 | ustatus = 0; |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 553 | break; |
| 554 | } |
| 555 | if (ustatus) { |
| 556 | if (display) |
Marcin Slusarz | ae4ba73 | 2012-11-25 23:00:57 +0100 | [diff] [blame] | 557 | nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 558 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 559 | nv_wr32(priv, ustatus_addr, 0xc0000000); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 560 | } |
| 561 | |
| 562 | if (!tps && display) |
Marcin Slusarz | ae4ba73 | 2012-11-25 23:00:57 +0100 | [diff] [blame] | 563 | nv_warn(priv, "%s - No TPs claiming errors?\n", name); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 564 | } |
| 565 | |
| 566 | static int |
Ben Skeggs | 72a1482 | 2012-08-13 16:26:07 +1000 | [diff] [blame] | 567 | nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display, |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 568 | int chid, u64 inst, struct nouveau_object *engctx) |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 569 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 570 | u32 status = nv_rd32(priv, 0x400108); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 571 | u32 ustatus; |
| 572 | |
| 573 | if (!status && display) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 574 | nv_error(priv, "TRAP: no units reporting traps?\n"); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 575 | return 1; |
| 576 | } |
| 577 | |
| 578 | /* DISPATCH: Relays commands to other units and handles NOTIFY, |
| 579 | * COND, QUERY. If you get a trap from it, the command is still stuck |
| 580 | * in DISPATCH and you need to do something about it. */ |
| 581 | if (status & 0x001) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 582 | ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff; |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 583 | if (!ustatus && display) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 584 | nv_error(priv, "TRAP_DISPATCH - no ustatus?\n"); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 585 | } |
| 586 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 587 | nv_wr32(priv, 0x400500, 0x00000000); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 588 | |
| 589 | /* Known to be triggered by screwed up NOTIFY and COND... */ |
| 590 | if (ustatus & 0x00000001) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 591 | u32 addr = nv_rd32(priv, 0x400808); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 592 | u32 subc = (addr & 0x00070000) >> 16; |
| 593 | u32 mthd = (addr & 0x00001ffc); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 594 | u32 datal = nv_rd32(priv, 0x40080c); |
| 595 | u32 datah = nv_rd32(priv, 0x400810); |
| 596 | u32 class = nv_rd32(priv, 0x400814); |
| 597 | u32 r848 = nv_rd32(priv, 0x400848); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 598 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 599 | nv_error(priv, "TRAP DISPATCH_FAULT\n"); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 600 | if (display && (addr & 0x80000000)) { |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 601 | nv_error(priv, |
| 602 | "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n", |
| 603 | chid, inst, |
| 604 | nouveau_client_name(engctx), subc, |
| 605 | class, mthd, datah, datal, addr, r848); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 606 | } else |
| 607 | if (display) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 608 | nv_error(priv, "no stuck command?\n"); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 609 | } |
| 610 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 611 | nv_wr32(priv, 0x400808, 0); |
| 612 | nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3); |
| 613 | nv_wr32(priv, 0x400848, 0); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 614 | ustatus &= ~0x00000001; |
| 615 | } |
| 616 | |
| 617 | if (ustatus & 0x00000002) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 618 | u32 addr = nv_rd32(priv, 0x40084c); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 619 | u32 subc = (addr & 0x00070000) >> 16; |
| 620 | u32 mthd = (addr & 0x00001ffc); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 621 | u32 data = nv_rd32(priv, 0x40085c); |
| 622 | u32 class = nv_rd32(priv, 0x400814); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 623 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 624 | nv_error(priv, "TRAP DISPATCH_QUERY\n"); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 625 | if (display && (addr & 0x80000000)) { |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 626 | nv_error(priv, |
| 627 | "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n", |
| 628 | chid, inst, |
| 629 | nouveau_client_name(engctx), subc, |
| 630 | class, mthd, data, addr); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 631 | } else |
| 632 | if (display) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 633 | nv_error(priv, "no stuck command?\n"); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 634 | } |
| 635 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 636 | nv_wr32(priv, 0x40084c, 0); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 637 | ustatus &= ~0x00000002; |
| 638 | } |
| 639 | |
| 640 | if (ustatus && display) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 641 | nv_error(priv, "TRAP_DISPATCH (unknown " |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 642 | "0x%08x)\n", ustatus); |
| 643 | } |
| 644 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 645 | nv_wr32(priv, 0x400804, 0xc0000000); |
| 646 | nv_wr32(priv, 0x400108, 0x001); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 647 | status &= ~0x001; |
| 648 | if (!status) |
| 649 | return 0; |
| 650 | } |
| 651 | |
| 652 | /* M2MF: Memory to memory copy engine. */ |
| 653 | if (status & 0x002) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 654 | u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff; |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 655 | if (display) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 656 | nv_error(priv, "TRAP_M2MF"); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 657 | nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus); |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 658 | pr_cont("\n"); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 659 | nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n", |
| 660 | nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808), |
| 661 | nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810)); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 662 | |
| 663 | } |
| 664 | |
| 665 | /* No sane way found yet -- just reset the bugger. */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 666 | nv_wr32(priv, 0x400040, 2); |
| 667 | nv_wr32(priv, 0x400040, 0); |
| 668 | nv_wr32(priv, 0x406800, 0xc0000000); |
| 669 | nv_wr32(priv, 0x400108, 0x002); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 670 | status &= ~0x002; |
| 671 | } |
| 672 | |
| 673 | /* VFETCH: Fetches data from vertex buffers. */ |
| 674 | if (status & 0x004) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 675 | u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff; |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 676 | if (display) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 677 | nv_error(priv, "TRAP_VFETCH"); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 678 | nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus); |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 679 | pr_cont("\n"); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 680 | nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n", |
| 681 | nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08), |
| 682 | nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10)); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 683 | } |
| 684 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 685 | nv_wr32(priv, 0x400c04, 0xc0000000); |
| 686 | nv_wr32(priv, 0x400108, 0x004); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 687 | status &= ~0x004; |
| 688 | } |
| 689 | |
| 690 | /* STRMOUT: DirectX streamout / OpenGL transform feedback. */ |
| 691 | if (status & 0x008) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 692 | ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff; |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 693 | if (display) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 694 | nv_error(priv, "TRAP_STRMOUT"); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 695 | nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus); |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 696 | pr_cont("\n"); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 697 | nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n", |
| 698 | nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808), |
| 699 | nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810)); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 700 | |
| 701 | } |
| 702 | |
| 703 | /* No sane way found yet -- just reset the bugger. */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 704 | nv_wr32(priv, 0x400040, 0x80); |
| 705 | nv_wr32(priv, 0x400040, 0); |
| 706 | nv_wr32(priv, 0x401800, 0xc0000000); |
| 707 | nv_wr32(priv, 0x400108, 0x008); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 708 | status &= ~0x008; |
| 709 | } |
| 710 | |
| 711 | /* CCACHE: Handles code and c[] caches and fills them. */ |
| 712 | if (status & 0x010) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 713 | ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff; |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 714 | if (display) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 715 | nv_error(priv, "TRAP_CCACHE"); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 716 | nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus); |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 717 | pr_cont("\n"); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 718 | nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x" |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 719 | " %08x %08x %08x\n", |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 720 | nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004), |
| 721 | nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c), |
| 722 | nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014), |
| 723 | nv_rd32(priv, 0x40501c)); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 724 | |
| 725 | } |
| 726 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 727 | nv_wr32(priv, 0x405018, 0xc0000000); |
| 728 | nv_wr32(priv, 0x400108, 0x010); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 729 | status &= ~0x010; |
| 730 | } |
| 731 | |
| 732 | /* Unknown, not seen yet... 0x402000 is the only trap status reg |
| 733 | * remaining, so try to handle it anyway. Perhaps related to that |
| 734 | * unknown DMA slot on tesla? */ |
| 735 | if (status & 0x20) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 736 | ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff; |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 737 | if (display) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 738 | nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus); |
| 739 | nv_wr32(priv, 0x402000, 0xc0000000); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 740 | /* no status modifiction on purpose */ |
| 741 | } |
| 742 | |
| 743 | /* TEXTURE: CUDA texturing units */ |
| 744 | if (status & 0x040) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 745 | nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display, |
| 746 | "TRAP_TEXTURE"); |
| 747 | nv_wr32(priv, 0x400108, 0x040); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 748 | status &= ~0x040; |
| 749 | } |
| 750 | |
| 751 | /* MP: CUDA execution engines. */ |
| 752 | if (status & 0x080) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 753 | nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display, |
| 754 | "TRAP_MP"); |
| 755 | nv_wr32(priv, 0x400108, 0x080); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 756 | status &= ~0x080; |
| 757 | } |
| 758 | |
Ilia Mirkin | e2dd003 | 2014-01-16 02:47:11 -0500 | [diff] [blame] | 759 | /* PROP: Handles TP-initiated uncached memory accesses: |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 760 | * l[], g[], stack, 2d surfaces, render targets. */ |
| 761 | if (status & 0x100) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 762 | nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display, |
Ilia Mirkin | e2dd003 | 2014-01-16 02:47:11 -0500 | [diff] [blame] | 763 | "TRAP_PROP"); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 764 | nv_wr32(priv, 0x400108, 0x100); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 765 | status &= ~0x100; |
| 766 | } |
| 767 | |
| 768 | if (status) { |
| 769 | if (display) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 770 | nv_error(priv, "TRAP: unknown 0x%08x\n", status); |
| 771 | nv_wr32(priv, 0x400108, status); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | return 1; |
| 775 | } |
| 776 | |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 777 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 778 | nv50_graph_intr(struct nouveau_subdev *subdev) |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 779 | { |
Ben Skeggs | 72a1482 | 2012-08-13 16:26:07 +1000 | [diff] [blame] | 780 | struct nouveau_fifo *pfifo = nouveau_fifo(subdev); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 781 | struct nouveau_engine *engine = nv_engine(subdev); |
Ben Skeggs | 72a1482 | 2012-08-13 16:26:07 +1000 | [diff] [blame] | 782 | struct nouveau_object *engctx; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 783 | struct nouveau_handle *handle = NULL; |
Ben Skeggs | 72a1482 | 2012-08-13 16:26:07 +1000 | [diff] [blame] | 784 | struct nv50_graph_priv *priv = (void *)subdev; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 785 | u32 stat = nv_rd32(priv, 0x400100); |
Ben Skeggs | 72a1482 | 2012-08-13 16:26:07 +1000 | [diff] [blame] | 786 | u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 787 | u32 addr = nv_rd32(priv, 0x400704); |
| 788 | u32 subc = (addr & 0x00070000) >> 16; |
| 789 | u32 mthd = (addr & 0x00001ffc); |
| 790 | u32 data = nv_rd32(priv, 0x400708); |
| 791 | u32 class = nv_rd32(priv, 0x400814); |
Ilia Mirkin | e2dd003 | 2014-01-16 02:47:11 -0500 | [diff] [blame] | 792 | u32 show = stat, show_bitfield = stat; |
Ben Skeggs | 72a1482 | 2012-08-13 16:26:07 +1000 | [diff] [blame] | 793 | int chid; |
| 794 | |
| 795 | engctx = nouveau_engctx_get(engine, inst); |
| 796 | chid = pfifo->chid(pfifo, engctx); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 797 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 798 | if (stat & 0x00000010) { |
Ben Skeggs | 72a1482 | 2012-08-13 16:26:07 +1000 | [diff] [blame] | 799 | handle = nouveau_handle_get_class(engctx, class); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 800 | if (handle && !nv_call(handle->object, mthd, data)) |
| 801 | show &= ~0x00000010; |
Ben Skeggs | 72a1482 | 2012-08-13 16:26:07 +1000 | [diff] [blame] | 802 | nouveau_handle_put(handle); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 803 | } |
| 804 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 805 | if (show & 0x00100000) { |
| 806 | u32 ecode = nv_rd32(priv, 0x400110); |
| 807 | nv_error(priv, "DATA_ERROR "); |
| 808 | nouveau_enum_print(nv50_data_error_names, ecode); |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 809 | pr_cont("\n"); |
Ilia Mirkin | e2dd003 | 2014-01-16 02:47:11 -0500 | [diff] [blame] | 810 | show_bitfield &= ~0x00100000; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 811 | } |
| 812 | |
| 813 | if (stat & 0x00200000) { |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 814 | if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12, |
| 815 | engctx)) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 816 | show &= ~0x00200000; |
Ilia Mirkin | e2dd003 | 2014-01-16 02:47:11 -0500 | [diff] [blame] | 817 | show_bitfield &= ~0x00200000; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 818 | } |
| 819 | |
| 820 | nv_wr32(priv, 0x400100, stat); |
| 821 | nv_wr32(priv, 0x400500, 0x00010001); |
| 822 | |
| 823 | if (show) { |
Ilia Mirkin | e2dd003 | 2014-01-16 02:47:11 -0500 | [diff] [blame] | 824 | show &= show_bitfield; |
| 825 | if (show) { |
| 826 | nv_error(priv, "%s", ""); |
| 827 | nouveau_bitfield_print(nv50_graph_intr_name, show); |
| 828 | pr_cont("\n"); |
| 829 | } |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 830 | nv_error(priv, |
| 831 | "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", |
| 832 | chid, (u64)inst << 12, nouveau_client_name(engctx), |
| 833 | subc, class, mthd, data); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 834 | } |
| 835 | |
| 836 | if (nv_rd32(priv, 0x400824) & (1 << 31)) |
| 837 | nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31)); |
Ben Skeggs | 72a1482 | 2012-08-13 16:26:07 +1000 | [diff] [blame] | 838 | |
| 839 | nouveau_engctx_put(engctx); |
Ben Skeggs | 274fec9 | 2010-11-03 13:16:18 +1000 | [diff] [blame] | 840 | } |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 841 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 842 | static int |
| 843 | nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 844 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 845 | struct nouveau_object **pobject) |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 846 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 847 | struct nv50_graph_priv *priv; |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 848 | int ret; |
| 849 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 850 | ret = nouveau_graph_create(parent, engine, oclass, true, &priv); |
| 851 | *pobject = nv_object(priv); |
| 852 | if (ret) |
| 853 | return ret; |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 854 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 855 | nv_subdev(priv)->unit = 0x00201000; |
| 856 | nv_subdev(priv)->intr = nv50_graph_intr; |
| 857 | nv_engine(priv)->cclass = &nv50_graph_cclass; |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 858 | |
Christoph Bumiller | 7e22e71 | 2013-03-27 22:16:54 +0100 | [diff] [blame] | 859 | priv->base.units = nv50_graph_units; |
| 860 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 861 | switch (nv_device(priv)->chipset) { |
| 862 | case 0x50: |
| 863 | nv_engine(priv)->sclass = nv50_graph_sclass; |
| 864 | break; |
| 865 | case 0x84: |
| 866 | case 0x86: |
| 867 | case 0x92: |
| 868 | case 0x94: |
| 869 | case 0x96: |
| 870 | case 0x98: |
| 871 | nv_engine(priv)->sclass = nv84_graph_sclass; |
| 872 | break; |
| 873 | case 0xa0: |
| 874 | case 0xaa: |
| 875 | case 0xac: |
| 876 | nv_engine(priv)->sclass = nva0_graph_sclass; |
| 877 | break; |
| 878 | case 0xa3: |
| 879 | case 0xa5: |
| 880 | case 0xa8: |
| 881 | nv_engine(priv)->sclass = nva3_graph_sclass; |
| 882 | break; |
| 883 | case 0xaf: |
| 884 | nv_engine(priv)->sclass = nvaf_graph_sclass; |
| 885 | break; |
| 886 | |
| 887 | }; |
| 888 | |
Ben Skeggs | 464d636 | 2013-05-13 20:55:46 +1000 | [diff] [blame] | 889 | /* unfortunate hw bug workaround... */ |
| 890 | if (nv_device(priv)->chipset != 0x50 && |
| 891 | nv_device(priv)->chipset != 0xac) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 892 | nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush; |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 893 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 894 | spin_lock_init(&priv->lock); |
| 895 | return 0; |
| 896 | } |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 897 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 898 | static int |
| 899 | nv50_graph_init(struct nouveau_object *object) |
| 900 | { |
| 901 | struct nv50_graph_priv *priv = (void *)object; |
| 902 | int ret, units, i; |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 903 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 904 | ret = nouveau_graph_init(&priv->base); |
| 905 | if (ret) |
| 906 | return ret; |
| 907 | |
| 908 | /* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */ |
| 909 | nv_wr32(priv, 0x40008c, 0x00000004); |
| 910 | |
| 911 | /* reset/enable traps and interrupts */ |
| 912 | nv_wr32(priv, 0x400804, 0xc0000000); |
| 913 | nv_wr32(priv, 0x406800, 0xc0000000); |
| 914 | nv_wr32(priv, 0x400c04, 0xc0000000); |
| 915 | nv_wr32(priv, 0x401800, 0xc0000000); |
| 916 | nv_wr32(priv, 0x405018, 0xc0000000); |
| 917 | nv_wr32(priv, 0x402000, 0xc0000000); |
| 918 | |
| 919 | units = nv_rd32(priv, 0x001540); |
| 920 | for (i = 0; i < 16; i++) { |
| 921 | if (!(units & (1 << i))) |
| 922 | continue; |
| 923 | |
| 924 | if (nv_device(priv)->chipset < 0xa0) { |
| 925 | nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000); |
| 926 | nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000); |
| 927 | nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000); |
| 928 | } else { |
| 929 | nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000); |
| 930 | nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000); |
| 931 | nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000); |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 932 | } |
| 933 | } |
| 934 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 935 | nv_wr32(priv, 0x400108, 0xffffffff); |
| 936 | nv_wr32(priv, 0x400138, 0xffffffff); |
| 937 | nv_wr32(priv, 0x400100, 0xffffffff); |
| 938 | nv_wr32(priv, 0x40013c, 0xffffffff); |
| 939 | nv_wr32(priv, 0x400500, 0x00010001); |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 940 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 941 | /* upload context program, initialise ctxctl defaults */ |
| 942 | ret = nv50_grctx_init(nv_device(priv), &priv->size); |
| 943 | if (ret) |
| 944 | return ret; |
| 945 | |
| 946 | nv_wr32(priv, 0x400824, 0x00000000); |
| 947 | nv_wr32(priv, 0x400828, 0x00000000); |
| 948 | nv_wr32(priv, 0x40082c, 0x00000000); |
| 949 | nv_wr32(priv, 0x400830, 0x00000000); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 950 | nv_wr32(priv, 0x40032c, 0x00000000); |
Ben Skeggs | f63740f | 2013-02-17 11:31:17 +1000 | [diff] [blame] | 951 | nv_wr32(priv, 0x400330, 0x00000000); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 952 | |
| 953 | /* some unknown zcull magic */ |
| 954 | switch (nv_device(priv)->chipset & 0xf0) { |
| 955 | case 0x50: |
| 956 | case 0x80: |
| 957 | case 0x90: |
| 958 | nv_wr32(priv, 0x402ca8, 0x00000800); |
| 959 | break; |
| 960 | case 0xa0: |
| 961 | default: |
| 962 | nv_wr32(priv, 0x402cc0, 0x00000000); |
| 963 | if (nv_device(priv)->chipset == 0xa0 || |
| 964 | nv_device(priv)->chipset == 0xaa || |
| 965 | nv_device(priv)->chipset == 0xac) { |
| 966 | nv_wr32(priv, 0x402ca8, 0x00000802); |
| 967 | } else { |
| 968 | nv_wr32(priv, 0x402cc0, 0x00000000); |
| 969 | nv_wr32(priv, 0x402ca8, 0x00000002); |
| 970 | } |
| 971 | |
| 972 | break; |
| 973 | } |
| 974 | |
| 975 | /* zero out zcull regions */ |
| 976 | for (i = 0; i < 8; i++) { |
| 977 | nv_wr32(priv, 0x402c20 + (i * 8), 0x00000000); |
| 978 | nv_wr32(priv, 0x402c24 + (i * 8), 0x00000000); |
| 979 | nv_wr32(priv, 0x402c28 + (i * 8), 0x00000000); |
| 980 | nv_wr32(priv, 0x402c2c + (i * 8), 0x00000000); |
| 981 | } |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 982 | return 0; |
| 983 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 984 | |
| 985 | struct nouveau_oclass |
| 986 | nv50_graph_oclass = { |
| 987 | .handle = NV_ENGINE(GR, 0x50), |
| 988 | .ofuncs = &(struct nouveau_ofuncs) { |
| 989 | .ctor = nv50_graph_ctor, |
| 990 | .dtor = _nouveau_graph_dtor, |
| 991 | .init = nv50_graph_init, |
| 992 | .fini = _nouveau_graph_fini, |
| 993 | }, |
| 994 | }; |