Fabio Estevam | 9aaf880 | 2013-11-29 08:46:32 -0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * SH-Mobile High-Definition Multimedia Interface (HDMI) driver |
| 10 | * for SLISHDMI13T and SLIPHDMIT IP cores |
| 11 | * |
| 12 | * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
| 13 | */ |
| 14 | |
| 15 | #include <linux/irq.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/clk.h> |
| 19 | #include <linux/regmap.h> |
| 20 | #include <linux/mfd/syscon.h> |
| 21 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> |
| 22 | #include <linux/of_device.h> |
| 23 | |
| 24 | #include <drm/drmP.h> |
| 25 | #include <drm/drm_crtc_helper.h> |
| 26 | #include <drm/drm_edid.h> |
| 27 | #include <drm/drm_encoder_slave.h> |
| 28 | |
| 29 | #include "ipu-v3/imx-ipu-v3.h" |
| 30 | #include "imx-hdmi.h" |
| 31 | #include "imx-drm.h" |
| 32 | |
| 33 | #define HDMI_EDID_LEN 512 |
| 34 | |
| 35 | #define RGB 0 |
| 36 | #define YCBCR444 1 |
| 37 | #define YCBCR422_16BITS 2 |
| 38 | #define YCBCR422_8BITS 3 |
| 39 | #define XVYCC444 4 |
| 40 | |
| 41 | enum hdmi_datamap { |
| 42 | RGB444_8B = 0x01, |
| 43 | RGB444_10B = 0x03, |
| 44 | RGB444_12B = 0x05, |
| 45 | RGB444_16B = 0x07, |
| 46 | YCbCr444_8B = 0x09, |
| 47 | YCbCr444_10B = 0x0B, |
| 48 | YCbCr444_12B = 0x0D, |
| 49 | YCbCr444_16B = 0x0F, |
| 50 | YCbCr422_8B = 0x16, |
| 51 | YCbCr422_10B = 0x14, |
| 52 | YCbCr422_12B = 0x12, |
| 53 | }; |
| 54 | |
| 55 | enum hdmi_colorimetry { |
| 56 | ITU601, |
| 57 | ITU709, |
| 58 | }; |
| 59 | |
| 60 | enum imx_hdmi_devtype { |
| 61 | IMX6Q_HDMI, |
| 62 | IMX6DL_HDMI, |
| 63 | }; |
| 64 | |
| 65 | static const u16 csc_coeff_default[3][4] = { |
| 66 | { 0x2000, 0x0000, 0x0000, 0x0000 }, |
| 67 | { 0x0000, 0x2000, 0x0000, 0x0000 }, |
| 68 | { 0x0000, 0x0000, 0x2000, 0x0000 } |
| 69 | }; |
| 70 | |
| 71 | static const u16 csc_coeff_rgb_out_eitu601[3][4] = { |
| 72 | { 0x2000, 0x6926, 0x74fd, 0x010e }, |
| 73 | { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, |
| 74 | { 0x2000, 0x0000, 0x38b4, 0x7e3b } |
| 75 | }; |
| 76 | |
| 77 | static const u16 csc_coeff_rgb_out_eitu709[3][4] = { |
| 78 | { 0x2000, 0x7106, 0x7a02, 0x00a7 }, |
| 79 | { 0x2000, 0x3264, 0x0000, 0x7e6d }, |
| 80 | { 0x2000, 0x0000, 0x3b61, 0x7e25 } |
| 81 | }; |
| 82 | |
| 83 | static const u16 csc_coeff_rgb_in_eitu601[3][4] = { |
| 84 | { 0x2591, 0x1322, 0x074b, 0x0000 }, |
| 85 | { 0x6535, 0x2000, 0x7acc, 0x0200 }, |
| 86 | { 0x6acd, 0x7534, 0x2000, 0x0200 } |
| 87 | }; |
| 88 | |
| 89 | static const u16 csc_coeff_rgb_in_eitu709[3][4] = { |
| 90 | { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, |
| 91 | { 0x62f0, 0x2000, 0x7d11, 0x0200 }, |
| 92 | { 0x6756, 0x78ab, 0x2000, 0x0200 } |
| 93 | }; |
| 94 | |
| 95 | struct hdmi_vmode { |
| 96 | bool mdvi; |
| 97 | bool mhsyncpolarity; |
| 98 | bool mvsyncpolarity; |
| 99 | bool minterlaced; |
| 100 | bool mdataenablepolarity; |
| 101 | |
| 102 | unsigned int mpixelclock; |
| 103 | unsigned int mpixelrepetitioninput; |
| 104 | unsigned int mpixelrepetitionoutput; |
| 105 | }; |
| 106 | |
| 107 | struct hdmi_data_info { |
| 108 | unsigned int enc_in_format; |
| 109 | unsigned int enc_out_format; |
| 110 | unsigned int enc_color_depth; |
| 111 | unsigned int colorimetry; |
| 112 | unsigned int pix_repet_factor; |
| 113 | unsigned int hdcp_enable; |
| 114 | struct hdmi_vmode video_mode; |
| 115 | }; |
| 116 | |
| 117 | struct imx_hdmi { |
| 118 | struct drm_connector connector; |
| 119 | struct imx_drm_connector *imx_drm_connector; |
| 120 | struct drm_encoder encoder; |
| 121 | struct imx_drm_encoder *imx_drm_encoder; |
| 122 | |
| 123 | enum imx_hdmi_devtype dev_type; |
| 124 | struct device *dev; |
| 125 | struct clk *isfr_clk; |
| 126 | struct clk *iahb_clk; |
| 127 | |
| 128 | struct hdmi_data_info hdmi_data; |
| 129 | int vic; |
| 130 | |
| 131 | u8 edid[HDMI_EDID_LEN]; |
| 132 | bool cable_plugin; |
| 133 | |
| 134 | bool phy_enabled; |
| 135 | struct drm_display_mode previous_mode; |
| 136 | |
| 137 | struct regmap *regmap; |
| 138 | struct i2c_adapter *ddc; |
| 139 | void __iomem *regs; |
| 140 | |
| 141 | unsigned long pixel_clk_rate; |
| 142 | unsigned int sample_rate; |
| 143 | int ratio; |
| 144 | }; |
| 145 | |
| 146 | static void imx_hdmi_set_ipu_di_mux(struct imx_hdmi *hdmi, int ipu_di) |
| 147 | { |
| 148 | regmap_update_bits(hdmi->regmap, IOMUXC_GPR3, |
| 149 | IMX6Q_GPR3_HDMI_MUX_CTL_MASK, |
| 150 | ipu_di << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT); |
| 151 | } |
| 152 | |
| 153 | static inline void hdmi_writeb(struct imx_hdmi *hdmi, u8 val, int offset) |
| 154 | { |
| 155 | writeb(val, hdmi->regs + offset); |
| 156 | } |
| 157 | |
| 158 | static inline u8 hdmi_readb(struct imx_hdmi *hdmi, int offset) |
| 159 | { |
| 160 | return readb(hdmi->regs + offset); |
| 161 | } |
| 162 | |
| 163 | static void hdmi_mask_writeb(struct imx_hdmi *hdmi, u8 data, unsigned int reg, |
| 164 | u8 shift, u8 mask) |
| 165 | { |
| 166 | u8 value = hdmi_readb(hdmi, reg) & ~mask; |
| 167 | value |= (data << shift) & mask; |
| 168 | hdmi_writeb(hdmi, value, reg); |
| 169 | } |
| 170 | |
| 171 | static void hdmi_set_clock_regenerator_n(struct imx_hdmi *hdmi, |
| 172 | unsigned int value) |
| 173 | { |
| 174 | u8 val; |
| 175 | |
| 176 | hdmi_writeb(hdmi, value & 0xff, HDMI_AUD_N1); |
| 177 | hdmi_writeb(hdmi, (value >> 8) & 0xff, HDMI_AUD_N2); |
| 178 | hdmi_writeb(hdmi, (value >> 16) & 0x0f, HDMI_AUD_N3); |
| 179 | |
| 180 | /* nshift factor = 0 */ |
| 181 | val = hdmi_readb(hdmi, HDMI_AUD_CTS3); |
| 182 | val &= ~HDMI_AUD_CTS3_N_SHIFT_MASK; |
| 183 | hdmi_writeb(hdmi, val, HDMI_AUD_CTS3); |
| 184 | } |
| 185 | |
| 186 | static void hdmi_regenerate_cts(struct imx_hdmi *hdmi, unsigned int cts) |
| 187 | { |
| 188 | u8 val; |
| 189 | |
| 190 | /* Must be set/cleared first */ |
| 191 | val = hdmi_readb(hdmi, HDMI_AUD_CTS3); |
| 192 | val &= ~HDMI_AUD_CTS3_CTS_MANUAL; |
| 193 | hdmi_writeb(hdmi, val, HDMI_AUD_CTS3); |
| 194 | |
| 195 | hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); |
| 196 | hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); |
| 197 | hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | |
| 198 | HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); |
| 199 | } |
| 200 | |
| 201 | static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk, |
| 202 | unsigned int ratio) |
| 203 | { |
| 204 | unsigned int n = (128 * freq) / 1000; |
| 205 | |
| 206 | switch (freq) { |
| 207 | case 32000: |
| 208 | if (pixel_clk == 25170000) |
| 209 | n = (ratio == 150) ? 9152 : 4576; |
| 210 | else if (pixel_clk == 27020000) |
| 211 | n = (ratio == 150) ? 8192 : 4096; |
| 212 | else if (pixel_clk == 74170000 || pixel_clk == 148350000) |
| 213 | n = 11648; |
| 214 | else |
| 215 | n = 4096; |
| 216 | break; |
| 217 | |
| 218 | case 44100: |
| 219 | if (pixel_clk == 25170000) |
| 220 | n = 7007; |
| 221 | else if (pixel_clk == 74170000) |
| 222 | n = 17836; |
| 223 | else if (pixel_clk == 148350000) |
| 224 | n = (ratio == 150) ? 17836 : 8918; |
| 225 | else |
| 226 | n = 6272; |
| 227 | break; |
| 228 | |
| 229 | case 48000: |
| 230 | if (pixel_clk == 25170000) |
| 231 | n = (ratio == 150) ? 9152 : 6864; |
| 232 | else if (pixel_clk == 27020000) |
| 233 | n = (ratio == 150) ? 8192 : 6144; |
| 234 | else if (pixel_clk == 74170000) |
| 235 | n = 11648; |
| 236 | else if (pixel_clk == 148350000) |
| 237 | n = (ratio == 150) ? 11648 : 5824; |
| 238 | else |
| 239 | n = 6144; |
| 240 | break; |
| 241 | |
| 242 | case 88200: |
| 243 | n = hdmi_compute_n(44100, pixel_clk, ratio) * 2; |
| 244 | break; |
| 245 | |
| 246 | case 96000: |
| 247 | n = hdmi_compute_n(48000, pixel_clk, ratio) * 2; |
| 248 | break; |
| 249 | |
| 250 | case 176400: |
| 251 | n = hdmi_compute_n(44100, pixel_clk, ratio) * 4; |
| 252 | break; |
| 253 | |
| 254 | case 192000: |
| 255 | n = hdmi_compute_n(48000, pixel_clk, ratio) * 4; |
| 256 | break; |
| 257 | |
| 258 | default: |
| 259 | break; |
| 260 | } |
| 261 | |
| 262 | return n; |
| 263 | } |
| 264 | |
| 265 | static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk, |
| 266 | unsigned int ratio) |
| 267 | { |
| 268 | unsigned int cts = 0; |
| 269 | |
| 270 | pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq, |
| 271 | pixel_clk, ratio); |
| 272 | |
| 273 | switch (freq) { |
| 274 | case 32000: |
| 275 | if (pixel_clk == 297000000) { |
| 276 | cts = 222750; |
| 277 | break; |
| 278 | } |
| 279 | case 48000: |
| 280 | case 96000: |
| 281 | case 192000: |
| 282 | switch (pixel_clk) { |
| 283 | case 25200000: |
| 284 | case 27000000: |
| 285 | case 54000000: |
| 286 | case 74250000: |
| 287 | case 148500000: |
| 288 | cts = pixel_clk / 1000; |
| 289 | break; |
| 290 | case 297000000: |
| 291 | cts = 247500; |
| 292 | break; |
| 293 | /* |
| 294 | * All other TMDS clocks are not supported by |
| 295 | * DWC_hdmi_tx. The TMDS clocks divided or |
| 296 | * multiplied by 1,001 coefficients are not |
| 297 | * supported. |
| 298 | */ |
| 299 | default: |
| 300 | break; |
| 301 | } |
| 302 | break; |
| 303 | case 44100: |
| 304 | case 88200: |
| 305 | case 176400: |
| 306 | switch (pixel_clk) { |
| 307 | case 25200000: |
| 308 | cts = 28000; |
| 309 | break; |
| 310 | case 27000000: |
| 311 | cts = 30000; |
| 312 | break; |
| 313 | case 54000000: |
| 314 | cts = 60000; |
| 315 | break; |
| 316 | case 74250000: |
| 317 | cts = 82500; |
| 318 | break; |
| 319 | case 148500000: |
| 320 | cts = 165000; |
| 321 | break; |
| 322 | case 297000000: |
| 323 | cts = 247500; |
| 324 | break; |
| 325 | default: |
| 326 | break; |
| 327 | } |
| 328 | break; |
| 329 | default: |
| 330 | break; |
| 331 | } |
| 332 | if (ratio == 100) |
| 333 | return cts; |
| 334 | else |
| 335 | return (cts * ratio) / 100; |
| 336 | } |
| 337 | |
| 338 | static void hdmi_get_pixel_clk(struct imx_hdmi *hdmi) |
| 339 | { |
| 340 | unsigned long rate; |
| 341 | |
| 342 | rate = 65000000; /* FIXME */ |
| 343 | |
| 344 | if (rate) |
| 345 | hdmi->pixel_clk_rate = rate; |
| 346 | } |
| 347 | |
| 348 | static void hdmi_set_clk_regenerator(struct imx_hdmi *hdmi) |
| 349 | { |
| 350 | unsigned int clk_n, clk_cts; |
| 351 | |
| 352 | clk_n = hdmi_compute_n(hdmi->sample_rate, hdmi->pixel_clk_rate, |
| 353 | hdmi->ratio); |
| 354 | clk_cts = hdmi_compute_cts(hdmi->sample_rate, hdmi->pixel_clk_rate, |
| 355 | hdmi->ratio); |
| 356 | |
| 357 | if (!clk_cts) { |
| 358 | dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n", |
| 359 | __func__, hdmi->pixel_clk_rate); |
| 360 | return; |
| 361 | } |
| 362 | |
| 363 | dev_dbg(hdmi->dev, "%s: samplerate=%d ratio=%d pixelclk=%lu N=%d cts=%d\n", |
| 364 | __func__, hdmi->sample_rate, hdmi->ratio, |
| 365 | hdmi->pixel_clk_rate, clk_n, clk_cts); |
| 366 | |
| 367 | hdmi_set_clock_regenerator_n(hdmi, clk_n); |
| 368 | hdmi_regenerate_cts(hdmi, clk_cts); |
| 369 | } |
| 370 | |
| 371 | static void hdmi_init_clk_regenerator(struct imx_hdmi *hdmi) |
| 372 | { |
| 373 | unsigned int clk_n, clk_cts; |
| 374 | |
| 375 | clk_n = hdmi_compute_n(hdmi->sample_rate, hdmi->pixel_clk_rate, |
| 376 | hdmi->ratio); |
| 377 | clk_cts = hdmi_compute_cts(hdmi->sample_rate, hdmi->pixel_clk_rate, |
| 378 | hdmi->ratio); |
| 379 | |
| 380 | if (!clk_cts) { |
| 381 | dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n", |
| 382 | __func__, hdmi->pixel_clk_rate); |
| 383 | return; |
| 384 | } |
| 385 | |
| 386 | dev_dbg(hdmi->dev, "%s: samplerate=%d ratio=%d pixelclk=%lu N=%d cts=%d\n", |
| 387 | __func__, hdmi->sample_rate, hdmi->ratio, |
| 388 | hdmi->pixel_clk_rate, clk_n, clk_cts); |
| 389 | |
| 390 | hdmi_set_clock_regenerator_n(hdmi, clk_n); |
| 391 | hdmi_regenerate_cts(hdmi, clk_cts); |
| 392 | } |
| 393 | |
| 394 | static void hdmi_clk_regenerator_update_pixel_clock(struct imx_hdmi *hdmi) |
| 395 | { |
| 396 | /* Get pixel clock from ipu */ |
| 397 | hdmi_get_pixel_clk(hdmi); |
| 398 | hdmi_set_clk_regenerator(hdmi); |
| 399 | } |
| 400 | |
| 401 | /* |
| 402 | * this submodule is responsible for the video data synchronization. |
| 403 | * for example, for RGB 4:4:4 input, the data map is defined as |
| 404 | * pin{47~40} <==> R[7:0] |
| 405 | * pin{31~24} <==> G[7:0] |
| 406 | * pin{15~8} <==> B[7:0] |
| 407 | */ |
| 408 | static void hdmi_video_sample(struct imx_hdmi *hdmi) |
| 409 | { |
| 410 | int color_format = 0; |
| 411 | u8 val; |
| 412 | |
| 413 | if (hdmi->hdmi_data.enc_in_format == RGB) { |
| 414 | if (hdmi->hdmi_data.enc_color_depth == 8) |
| 415 | color_format = 0x01; |
| 416 | else if (hdmi->hdmi_data.enc_color_depth == 10) |
| 417 | color_format = 0x03; |
| 418 | else if (hdmi->hdmi_data.enc_color_depth == 12) |
| 419 | color_format = 0x05; |
| 420 | else if (hdmi->hdmi_data.enc_color_depth == 16) |
| 421 | color_format = 0x07; |
| 422 | else |
| 423 | return; |
| 424 | } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) { |
| 425 | if (hdmi->hdmi_data.enc_color_depth == 8) |
| 426 | color_format = 0x09; |
| 427 | else if (hdmi->hdmi_data.enc_color_depth == 10) |
| 428 | color_format = 0x0B; |
| 429 | else if (hdmi->hdmi_data.enc_color_depth == 12) |
| 430 | color_format = 0x0D; |
| 431 | else if (hdmi->hdmi_data.enc_color_depth == 16) |
| 432 | color_format = 0x0F; |
| 433 | else |
| 434 | return; |
| 435 | } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) { |
| 436 | if (hdmi->hdmi_data.enc_color_depth == 8) |
| 437 | color_format = 0x16; |
| 438 | else if (hdmi->hdmi_data.enc_color_depth == 10) |
| 439 | color_format = 0x14; |
| 440 | else if (hdmi->hdmi_data.enc_color_depth == 12) |
| 441 | color_format = 0x12; |
| 442 | else |
| 443 | return; |
| 444 | } |
| 445 | |
| 446 | val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | |
| 447 | ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & |
| 448 | HDMI_TX_INVID0_VIDEO_MAPPING_MASK); |
| 449 | hdmi_writeb(hdmi, val, HDMI_TX_INVID0); |
| 450 | |
| 451 | /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ |
| 452 | val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | |
| 453 | HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | |
| 454 | HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; |
| 455 | hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); |
| 456 | hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); |
| 457 | hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); |
| 458 | hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); |
| 459 | hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); |
| 460 | hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); |
| 461 | hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); |
| 462 | } |
| 463 | |
| 464 | static int is_color_space_conversion(struct imx_hdmi *hdmi) |
| 465 | { |
| 466 | return (hdmi->hdmi_data.enc_in_format != |
| 467 | hdmi->hdmi_data.enc_out_format); |
| 468 | } |
| 469 | |
| 470 | static int is_color_space_decimation(struct imx_hdmi *hdmi) |
| 471 | { |
| 472 | return ((hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS) && |
| 473 | (hdmi->hdmi_data.enc_in_format == RGB || |
| 474 | hdmi->hdmi_data.enc_in_format == YCBCR444)); |
| 475 | } |
| 476 | |
| 477 | static int is_color_space_interpolation(struct imx_hdmi *hdmi) |
| 478 | { |
| 479 | return ((hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) && |
| 480 | (hdmi->hdmi_data.enc_out_format == RGB || |
| 481 | hdmi->hdmi_data.enc_out_format == YCBCR444)); |
| 482 | } |
| 483 | |
| 484 | static void imx_hdmi_update_csc_coeffs(struct imx_hdmi *hdmi) |
| 485 | { |
| 486 | const u16 (*csc_coeff)[3][4] = &csc_coeff_default; |
| 487 | u32 csc_scale = 1; |
| 488 | u8 val; |
| 489 | |
| 490 | if (is_color_space_conversion(hdmi)) { |
| 491 | if (hdmi->hdmi_data.enc_out_format == RGB) { |
| 492 | if (hdmi->hdmi_data.colorimetry == ITU601) |
| 493 | csc_coeff = &csc_coeff_rgb_out_eitu601; |
| 494 | else |
| 495 | csc_coeff = &csc_coeff_rgb_out_eitu709; |
| 496 | } else if (hdmi->hdmi_data.enc_in_format == RGB) { |
| 497 | if (hdmi->hdmi_data.colorimetry == ITU601) |
| 498 | csc_coeff = &csc_coeff_rgb_in_eitu601; |
| 499 | else |
| 500 | csc_coeff = &csc_coeff_rgb_in_eitu709; |
| 501 | csc_scale = 0; |
| 502 | } |
| 503 | } |
| 504 | |
| 505 | hdmi_writeb(hdmi, ((*csc_coeff)[0][0] & 0xff), HDMI_CSC_COEF_A1_LSB); |
| 506 | hdmi_writeb(hdmi, ((*csc_coeff)[0][0] >> 8), HDMI_CSC_COEF_A1_MSB); |
| 507 | hdmi_writeb(hdmi, ((*csc_coeff)[0][1] & 0xff), HDMI_CSC_COEF_A2_LSB); |
| 508 | hdmi_writeb(hdmi, ((*csc_coeff)[0][1] >> 8), HDMI_CSC_COEF_A2_MSB); |
| 509 | hdmi_writeb(hdmi, ((*csc_coeff)[0][2] & 0xff), HDMI_CSC_COEF_A3_LSB); |
| 510 | hdmi_writeb(hdmi, ((*csc_coeff)[0][2] >> 8), HDMI_CSC_COEF_A3_MSB); |
| 511 | hdmi_writeb(hdmi, ((*csc_coeff)[0][3] & 0xff), HDMI_CSC_COEF_A4_LSB); |
| 512 | hdmi_writeb(hdmi, ((*csc_coeff)[0][3] >> 8), HDMI_CSC_COEF_A4_MSB); |
| 513 | |
| 514 | hdmi_writeb(hdmi, ((*csc_coeff)[1][0] & 0xff), HDMI_CSC_COEF_B1_LSB); |
| 515 | hdmi_writeb(hdmi, ((*csc_coeff)[1][0] >> 8), HDMI_CSC_COEF_B1_MSB); |
| 516 | hdmi_writeb(hdmi, ((*csc_coeff)[1][1] & 0xff), HDMI_CSC_COEF_B2_LSB); |
| 517 | hdmi_writeb(hdmi, ((*csc_coeff)[1][1] >> 8), HDMI_CSC_COEF_B2_MSB); |
| 518 | hdmi_writeb(hdmi, ((*csc_coeff)[1][2] & 0xff), HDMI_CSC_COEF_B3_LSB); |
| 519 | hdmi_writeb(hdmi, ((*csc_coeff)[1][2] >> 8), HDMI_CSC_COEF_B3_MSB); |
| 520 | hdmi_writeb(hdmi, ((*csc_coeff)[1][3] & 0xff), HDMI_CSC_COEF_B4_LSB); |
| 521 | hdmi_writeb(hdmi, ((*csc_coeff)[1][3] >> 8), HDMI_CSC_COEF_B4_MSB); |
| 522 | |
| 523 | hdmi_writeb(hdmi, ((*csc_coeff)[2][0] & 0xff), HDMI_CSC_COEF_C1_LSB); |
| 524 | hdmi_writeb(hdmi, ((*csc_coeff)[2][0] >> 8), HDMI_CSC_COEF_C1_MSB); |
| 525 | hdmi_writeb(hdmi, ((*csc_coeff)[2][1] & 0xff), HDMI_CSC_COEF_C2_LSB); |
| 526 | hdmi_writeb(hdmi, ((*csc_coeff)[2][1] >> 8), HDMI_CSC_COEF_C2_MSB); |
| 527 | hdmi_writeb(hdmi, ((*csc_coeff)[2][2] & 0xff), HDMI_CSC_COEF_C3_LSB); |
| 528 | hdmi_writeb(hdmi, ((*csc_coeff)[2][2] >> 8), HDMI_CSC_COEF_C3_MSB); |
| 529 | hdmi_writeb(hdmi, ((*csc_coeff)[2][3] & 0xff), HDMI_CSC_COEF_C4_LSB); |
| 530 | hdmi_writeb(hdmi, ((*csc_coeff)[2][3] >> 8), HDMI_CSC_COEF_C4_MSB); |
| 531 | |
| 532 | val = hdmi_readb(hdmi, HDMI_CSC_SCALE); |
| 533 | val &= ~HDMI_CSC_SCALE_CSCSCALE_MASK; |
| 534 | val |= csc_scale & HDMI_CSC_SCALE_CSCSCALE_MASK; |
| 535 | hdmi_writeb(hdmi, val, HDMI_CSC_SCALE); |
| 536 | } |
| 537 | |
| 538 | static void hdmi_video_csc(struct imx_hdmi *hdmi) |
| 539 | { |
| 540 | int color_depth = 0; |
| 541 | int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; |
| 542 | int decimation = 0; |
| 543 | u8 val; |
| 544 | |
| 545 | /* YCC422 interpolation to 444 mode */ |
| 546 | if (is_color_space_interpolation(hdmi)) |
| 547 | interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; |
| 548 | else if (is_color_space_decimation(hdmi)) |
| 549 | decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; |
| 550 | |
| 551 | if (hdmi->hdmi_data.enc_color_depth == 8) |
| 552 | color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; |
| 553 | else if (hdmi->hdmi_data.enc_color_depth == 10) |
| 554 | color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; |
| 555 | else if (hdmi->hdmi_data.enc_color_depth == 12) |
| 556 | color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; |
| 557 | else if (hdmi->hdmi_data.enc_color_depth == 16) |
| 558 | color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; |
| 559 | else |
| 560 | return; |
| 561 | |
| 562 | /* Configure the CSC registers */ |
| 563 | hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); |
| 564 | val = hdmi_readb(hdmi, HDMI_CSC_SCALE); |
| 565 | val &= ~HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK; |
| 566 | val |= color_depth; |
| 567 | hdmi_writeb(hdmi, val, HDMI_CSC_SCALE); |
| 568 | |
| 569 | imx_hdmi_update_csc_coeffs(hdmi); |
| 570 | } |
| 571 | |
| 572 | /* |
| 573 | * HDMI video packetizer is used to packetize the data. |
| 574 | * for example, if input is YCC422 mode or repeater is used, |
| 575 | * data should be repacked this module can be bypassed. |
| 576 | */ |
| 577 | static void hdmi_video_packetize(struct imx_hdmi *hdmi) |
| 578 | { |
| 579 | unsigned int color_depth = 0; |
| 580 | unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; |
| 581 | unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; |
| 582 | struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; |
| 583 | u8 val; |
| 584 | |
| 585 | if (hdmi_data->enc_out_format == RGB |
| 586 | || hdmi_data->enc_out_format == YCBCR444) { |
| 587 | if (!hdmi_data->enc_color_depth) |
| 588 | output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; |
| 589 | else if (hdmi_data->enc_color_depth == 8) { |
| 590 | color_depth = 4; |
| 591 | output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; |
| 592 | } else if (hdmi_data->enc_color_depth == 10) |
| 593 | color_depth = 5; |
| 594 | else if (hdmi_data->enc_color_depth == 12) |
| 595 | color_depth = 6; |
| 596 | else if (hdmi_data->enc_color_depth == 16) |
| 597 | color_depth = 7; |
| 598 | else |
| 599 | return; |
| 600 | } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) { |
| 601 | if (!hdmi_data->enc_color_depth || |
| 602 | hdmi_data->enc_color_depth == 8) |
| 603 | remap_size = HDMI_VP_REMAP_YCC422_16bit; |
| 604 | else if (hdmi_data->enc_color_depth == 10) |
| 605 | remap_size = HDMI_VP_REMAP_YCC422_20bit; |
| 606 | else if (hdmi_data->enc_color_depth == 12) |
| 607 | remap_size = HDMI_VP_REMAP_YCC422_24bit; |
| 608 | else |
| 609 | return; |
| 610 | output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; |
| 611 | } else |
| 612 | return; |
| 613 | |
| 614 | /* set the packetizer registers */ |
| 615 | val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & |
| 616 | HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | |
| 617 | ((hdmi_data->pix_repet_factor << |
| 618 | HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & |
| 619 | HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); |
| 620 | hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); |
| 621 | |
| 622 | val = hdmi_readb(hdmi, HDMI_VP_STUFF); |
| 623 | val &= ~HDMI_VP_STUFF_PR_STUFFING_MASK; |
| 624 | val |= HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE; |
| 625 | hdmi_writeb(hdmi, val, HDMI_VP_STUFF); |
| 626 | |
| 627 | /* Data from pixel repeater block */ |
| 628 | if (hdmi_data->pix_repet_factor > 1) { |
| 629 | val = hdmi_readb(hdmi, HDMI_VP_CONF); |
| 630 | val &= ~(HDMI_VP_CONF_PR_EN_MASK | |
| 631 | HDMI_VP_CONF_BYPASS_SELECT_MASK); |
| 632 | val |= HDMI_VP_CONF_PR_EN_ENABLE | |
| 633 | HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; |
| 634 | hdmi_writeb(hdmi, val, HDMI_VP_CONF); |
| 635 | } else { /* data from packetizer block */ |
| 636 | val = hdmi_readb(hdmi, HDMI_VP_CONF); |
| 637 | val &= ~(HDMI_VP_CONF_PR_EN_MASK | |
| 638 | HDMI_VP_CONF_BYPASS_SELECT_MASK); |
| 639 | val |= HDMI_VP_CONF_PR_EN_DISABLE | |
| 640 | HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; |
| 641 | hdmi_writeb(hdmi, val, HDMI_VP_CONF); |
| 642 | } |
| 643 | |
| 644 | val = hdmi_readb(hdmi, HDMI_VP_STUFF); |
| 645 | val &= ~HDMI_VP_STUFF_IDEFAULT_PHASE_MASK; |
| 646 | val |= 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET; |
| 647 | hdmi_writeb(hdmi, val, HDMI_VP_STUFF); |
| 648 | |
| 649 | hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); |
| 650 | |
| 651 | if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { |
| 652 | val = hdmi_readb(hdmi, HDMI_VP_CONF); |
| 653 | val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK | |
| 654 | HDMI_VP_CONF_PP_EN_ENMASK | |
| 655 | HDMI_VP_CONF_YCC422_EN_MASK); |
| 656 | val |= HDMI_VP_CONF_BYPASS_EN_DISABLE | |
| 657 | HDMI_VP_CONF_PP_EN_ENABLE | |
| 658 | HDMI_VP_CONF_YCC422_EN_DISABLE; |
| 659 | hdmi_writeb(hdmi, val, HDMI_VP_CONF); |
| 660 | } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { |
| 661 | val = hdmi_readb(hdmi, HDMI_VP_CONF); |
| 662 | val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK | |
| 663 | HDMI_VP_CONF_PP_EN_ENMASK | |
| 664 | HDMI_VP_CONF_YCC422_EN_MASK); |
| 665 | val |= HDMI_VP_CONF_BYPASS_EN_DISABLE | |
| 666 | HDMI_VP_CONF_PP_EN_DISABLE | |
| 667 | HDMI_VP_CONF_YCC422_EN_ENABLE; |
| 668 | hdmi_writeb(hdmi, val, HDMI_VP_CONF); |
| 669 | } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { |
| 670 | val = hdmi_readb(hdmi, HDMI_VP_CONF); |
| 671 | val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK | |
| 672 | HDMI_VP_CONF_PP_EN_ENMASK | |
| 673 | HDMI_VP_CONF_YCC422_EN_MASK); |
| 674 | val |= HDMI_VP_CONF_BYPASS_EN_ENABLE | |
| 675 | HDMI_VP_CONF_PP_EN_DISABLE | |
| 676 | HDMI_VP_CONF_YCC422_EN_DISABLE; |
| 677 | hdmi_writeb(hdmi, val, HDMI_VP_CONF); |
| 678 | } else { |
| 679 | return; |
| 680 | } |
| 681 | |
| 682 | val = hdmi_readb(hdmi, HDMI_VP_STUFF); |
| 683 | val &= ~(HDMI_VP_STUFF_PP_STUFFING_MASK | |
| 684 | HDMI_VP_STUFF_YCC422_STUFFING_MASK); |
| 685 | val |= HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | |
| 686 | HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE; |
| 687 | hdmi_writeb(hdmi, val, HDMI_VP_STUFF); |
| 688 | |
| 689 | val = hdmi_readb(hdmi, HDMI_VP_CONF); |
| 690 | val &= ~HDMI_VP_CONF_OUTPUT_SELECTOR_MASK; |
| 691 | val |= output_select; |
| 692 | hdmi_writeb(hdmi, val, HDMI_VP_CONF); |
| 693 | } |
| 694 | |
| 695 | static inline void hdmi_phy_test_clear(struct imx_hdmi *hdmi, |
| 696 | unsigned char bit) |
| 697 | { |
| 698 | u8 val = hdmi_readb(hdmi, HDMI_PHY_TST0); |
| 699 | val &= ~HDMI_PHY_TST0_TSTCLR_MASK; |
| 700 | val |= (bit << HDMI_PHY_TST0_TSTCLR_OFFSET) & |
| 701 | HDMI_PHY_TST0_TSTCLR_MASK; |
| 702 | hdmi_writeb(hdmi, val, HDMI_PHY_TST0); |
| 703 | } |
| 704 | |
| 705 | static inline void hdmi_phy_test_enable(struct imx_hdmi *hdmi, |
| 706 | unsigned char bit) |
| 707 | { |
| 708 | u8 val = hdmi_readb(hdmi, HDMI_PHY_TST0); |
| 709 | val &= ~HDMI_PHY_TST0_TSTEN_MASK; |
| 710 | val |= (bit << HDMI_PHY_TST0_TSTEN_OFFSET) & |
| 711 | HDMI_PHY_TST0_TSTEN_MASK; |
| 712 | hdmi_writeb(hdmi, val, HDMI_PHY_TST0); |
| 713 | } |
| 714 | |
| 715 | static inline void hdmi_phy_test_clock(struct imx_hdmi *hdmi, |
| 716 | unsigned char bit) |
| 717 | { |
| 718 | u8 val = hdmi_readb(hdmi, HDMI_PHY_TST0); |
| 719 | val &= ~HDMI_PHY_TST0_TSTCLK_MASK; |
| 720 | val |= (bit << HDMI_PHY_TST0_TSTCLK_OFFSET) & |
| 721 | HDMI_PHY_TST0_TSTCLK_MASK; |
| 722 | hdmi_writeb(hdmi, val, HDMI_PHY_TST0); |
| 723 | } |
| 724 | |
| 725 | static inline void hdmi_phy_test_din(struct imx_hdmi *hdmi, |
| 726 | unsigned char bit) |
| 727 | { |
| 728 | hdmi_writeb(hdmi, bit, HDMI_PHY_TST1); |
| 729 | } |
| 730 | |
| 731 | static inline void hdmi_phy_test_dout(struct imx_hdmi *hdmi, |
| 732 | unsigned char bit) |
| 733 | { |
| 734 | hdmi_writeb(hdmi, bit, HDMI_PHY_TST2); |
| 735 | } |
| 736 | |
| 737 | static bool hdmi_phy_wait_i2c_done(struct imx_hdmi *hdmi, int msec) |
| 738 | { |
| 739 | unsigned char val = 0; |
| 740 | val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3; |
| 741 | while (!val) { |
| 742 | udelay(1000); |
| 743 | if (msec-- == 0) |
| 744 | return false; |
| 745 | val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3; |
| 746 | } |
| 747 | return true; |
| 748 | } |
| 749 | |
| 750 | static void __hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data, |
| 751 | unsigned char addr) |
| 752 | { |
| 753 | hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); |
| 754 | hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); |
| 755 | hdmi_writeb(hdmi, (unsigned char)(data >> 8), |
| 756 | HDMI_PHY_I2CM_DATAO_1_ADDR); |
| 757 | hdmi_writeb(hdmi, (unsigned char)(data >> 0), |
| 758 | HDMI_PHY_I2CM_DATAO_0_ADDR); |
| 759 | hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, |
| 760 | HDMI_PHY_I2CM_OPERATION_ADDR); |
| 761 | hdmi_phy_wait_i2c_done(hdmi, 1000); |
| 762 | } |
| 763 | |
| 764 | static int hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data, |
| 765 | unsigned char addr) |
| 766 | { |
| 767 | __hdmi_phy_i2c_write(hdmi, data, addr); |
| 768 | return 0; |
| 769 | } |
| 770 | |
| 771 | static void imx_hdmi_phy_enable_power(struct imx_hdmi *hdmi, u8 enable) |
| 772 | { |
| 773 | hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, |
| 774 | HDMI_PHY_CONF0_PDZ_OFFSET, |
| 775 | HDMI_PHY_CONF0_PDZ_MASK); |
| 776 | } |
| 777 | |
| 778 | static void imx_hdmi_phy_enable_tmds(struct imx_hdmi *hdmi, u8 enable) |
| 779 | { |
| 780 | hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, |
| 781 | HDMI_PHY_CONF0_ENTMDS_OFFSET, |
| 782 | HDMI_PHY_CONF0_ENTMDS_MASK); |
| 783 | } |
| 784 | |
| 785 | static void imx_hdmi_phy_gen2_pddq(struct imx_hdmi *hdmi, u8 enable) |
| 786 | { |
| 787 | hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, |
| 788 | HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, |
| 789 | HDMI_PHY_CONF0_GEN2_PDDQ_MASK); |
| 790 | } |
| 791 | |
| 792 | static void imx_hdmi_phy_gen2_txpwron(struct imx_hdmi *hdmi, u8 enable) |
| 793 | { |
| 794 | hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, |
| 795 | HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, |
| 796 | HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); |
| 797 | } |
| 798 | |
| 799 | static void imx_hdmi_phy_sel_data_en_pol(struct imx_hdmi *hdmi, u8 enable) |
| 800 | { |
| 801 | hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, |
| 802 | HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, |
| 803 | HDMI_PHY_CONF0_SELDATAENPOL_MASK); |
| 804 | } |
| 805 | |
| 806 | static void imx_hdmi_phy_sel_interface_control(struct imx_hdmi *hdmi, u8 enable) |
| 807 | { |
| 808 | hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, |
| 809 | HDMI_PHY_CONF0_SELDIPIF_OFFSET, |
| 810 | HDMI_PHY_CONF0_SELDIPIF_MASK); |
| 811 | } |
| 812 | |
| 813 | static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep, |
| 814 | unsigned char res, int cscon) |
| 815 | { |
| 816 | u8 val, msec; |
| 817 | |
| 818 | /* color resolution 0 is 8 bit colour depth */ |
| 819 | if (!res) |
| 820 | res = 8; |
| 821 | |
| 822 | if (prep) |
| 823 | return -EINVAL; |
| 824 | else if (res != 8 && res != 12) |
| 825 | return -EINVAL; |
| 826 | |
| 827 | /* Enable csc path */ |
| 828 | if (cscon) |
| 829 | val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH; |
| 830 | else |
| 831 | val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS; |
| 832 | |
| 833 | hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL); |
| 834 | |
| 835 | /* gen2 tx power off */ |
| 836 | imx_hdmi_phy_gen2_txpwron(hdmi, 0); |
| 837 | |
| 838 | /* gen2 pddq */ |
| 839 | imx_hdmi_phy_gen2_pddq(hdmi, 1); |
| 840 | |
| 841 | /* PHY reset */ |
| 842 | hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ); |
| 843 | hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ); |
| 844 | |
| 845 | hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); |
| 846 | |
| 847 | hdmi_phy_test_clear(hdmi, 1); |
| 848 | hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, |
| 849 | HDMI_PHY_I2CM_SLAVE_ADDR); |
| 850 | hdmi_phy_test_clear(hdmi, 0); |
| 851 | |
| 852 | if (hdmi->hdmi_data.video_mode.mpixelclock <= 45250000) { |
| 853 | switch (res) { |
| 854 | case 8: |
| 855 | /* PLL/MPLL Cfg */ |
| 856 | hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06); |
| 857 | hdmi_phy_i2c_write(hdmi, 0x0000, 0x15); /* GMPCTRL */ |
| 858 | break; |
| 859 | case 10: |
| 860 | hdmi_phy_i2c_write(hdmi, 0x21e1, 0x06); |
| 861 | hdmi_phy_i2c_write(hdmi, 0x0000, 0x15); |
| 862 | break; |
| 863 | case 12: |
| 864 | hdmi_phy_i2c_write(hdmi, 0x41e2, 0x06); |
| 865 | hdmi_phy_i2c_write(hdmi, 0x0000, 0x15); |
| 866 | break; |
| 867 | default: |
| 868 | return -EINVAL; |
| 869 | } |
| 870 | } else if (hdmi->hdmi_data.video_mode.mpixelclock <= 92500000) { |
| 871 | switch (res) { |
| 872 | case 8: |
| 873 | hdmi_phy_i2c_write(hdmi, 0x0140, 0x06); |
| 874 | hdmi_phy_i2c_write(hdmi, 0x0005, 0x15); |
| 875 | break; |
| 876 | case 10: |
| 877 | hdmi_phy_i2c_write(hdmi, 0x2141, 0x06); |
| 878 | hdmi_phy_i2c_write(hdmi, 0x0005, 0x15); |
| 879 | break; |
| 880 | case 12: |
| 881 | hdmi_phy_i2c_write(hdmi, 0x4142, 0x06); |
| 882 | hdmi_phy_i2c_write(hdmi, 0x0005, 0x15); |
| 883 | default: |
| 884 | return -EINVAL; |
| 885 | } |
| 886 | } else if (hdmi->hdmi_data.video_mode.mpixelclock <= 148500000) { |
| 887 | switch (res) { |
| 888 | case 8: |
| 889 | hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06); |
| 890 | hdmi_phy_i2c_write(hdmi, 0x000a, 0x15); |
| 891 | break; |
| 892 | case 10: |
| 893 | hdmi_phy_i2c_write(hdmi, 0x20a1, 0x06); |
| 894 | hdmi_phy_i2c_write(hdmi, 0x000a, 0x15); |
| 895 | break; |
| 896 | case 12: |
| 897 | hdmi_phy_i2c_write(hdmi, 0x40a2, 0x06); |
| 898 | hdmi_phy_i2c_write(hdmi, 0x000a, 0x15); |
| 899 | default: |
| 900 | return -EINVAL; |
| 901 | } |
| 902 | } else { |
| 903 | switch (res) { |
| 904 | case 8: |
| 905 | hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06); |
| 906 | hdmi_phy_i2c_write(hdmi, 0x000a, 0x15); |
| 907 | break; |
| 908 | case 10: |
| 909 | hdmi_phy_i2c_write(hdmi, 0x2001, 0x06); |
| 910 | hdmi_phy_i2c_write(hdmi, 0x000f, 0x15); |
| 911 | break; |
| 912 | case 12: |
| 913 | hdmi_phy_i2c_write(hdmi, 0x4002, 0x06); |
| 914 | hdmi_phy_i2c_write(hdmi, 0x000f, 0x15); |
| 915 | default: |
| 916 | return -EINVAL; |
| 917 | } |
| 918 | } |
| 919 | |
| 920 | if (hdmi->hdmi_data.video_mode.mpixelclock <= 54000000) { |
| 921 | switch (res) { |
| 922 | case 8: |
| 923 | hdmi_phy_i2c_write(hdmi, 0x091c, 0x10); /* CURRCTRL */ |
| 924 | break; |
| 925 | case 10: |
| 926 | hdmi_phy_i2c_write(hdmi, 0x091c, 0x10); |
| 927 | break; |
| 928 | case 12: |
| 929 | hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10); |
| 930 | break; |
| 931 | default: |
| 932 | return -EINVAL; |
| 933 | } |
| 934 | } else if (hdmi->hdmi_data.video_mode.mpixelclock <= 58400000) { |
| 935 | switch (res) { |
| 936 | case 8: |
| 937 | hdmi_phy_i2c_write(hdmi, 0x091c, 0x10); |
| 938 | break; |
| 939 | case 10: |
| 940 | hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10); |
| 941 | break; |
| 942 | case 12: |
| 943 | hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10); |
| 944 | break; |
| 945 | default: |
| 946 | return -EINVAL; |
| 947 | } |
| 948 | } else if (hdmi->hdmi_data.video_mode.mpixelclock <= 72000000) { |
| 949 | switch (res) { |
| 950 | case 8: |
| 951 | hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10); |
| 952 | break; |
| 953 | case 10: |
| 954 | hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10); |
| 955 | break; |
| 956 | case 12: |
| 957 | hdmi_phy_i2c_write(hdmi, 0x091c, 0x10); |
| 958 | break; |
| 959 | default: |
| 960 | return -EINVAL; |
| 961 | } |
| 962 | } else if (hdmi->hdmi_data.video_mode.mpixelclock <= 74250000) { |
| 963 | switch (res) { |
| 964 | case 8: |
| 965 | hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10); |
| 966 | break; |
| 967 | case 10: |
| 968 | hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10); |
| 969 | break; |
| 970 | case 12: |
| 971 | hdmi_phy_i2c_write(hdmi, 0x091c, 0x10); |
| 972 | break; |
| 973 | default: |
| 974 | return -EINVAL; |
| 975 | } |
| 976 | } else if (hdmi->hdmi_data.video_mode.mpixelclock <= 118800000) { |
| 977 | switch (res) { |
| 978 | case 8: |
| 979 | hdmi_phy_i2c_write(hdmi, 0x091c, 0x10); |
| 980 | break; |
| 981 | case 10: |
| 982 | hdmi_phy_i2c_write(hdmi, 0x091c, 0x10); |
| 983 | break; |
| 984 | case 12: |
| 985 | hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10); |
| 986 | break; |
| 987 | default: |
| 988 | return -EINVAL; |
| 989 | } |
| 990 | } else if (hdmi->hdmi_data.video_mode.mpixelclock <= 216000000) { |
| 991 | switch (res) { |
| 992 | case 8: |
| 993 | hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10); |
| 994 | break; |
| 995 | case 10: |
| 996 | hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10); |
| 997 | break; |
| 998 | case 12: |
| 999 | hdmi_phy_i2c_write(hdmi, 0x091c, 0x10); |
| 1000 | break; |
| 1001 | default: |
| 1002 | return -EINVAL; |
| 1003 | } |
| 1004 | } else { |
| 1005 | dev_err(hdmi->dev, |
| 1006 | "Pixel clock %d - unsupported by HDMI\n", |
| 1007 | hdmi->hdmi_data.video_mode.mpixelclock); |
| 1008 | return -EINVAL; |
| 1009 | } |
| 1010 | |
| 1011 | hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */ |
| 1012 | hdmi_phy_i2c_write(hdmi, 0x0006, 0x17); |
| 1013 | /* RESISTANCE TERM 133Ohm Cfg */ |
| 1014 | hdmi_phy_i2c_write(hdmi, 0x0005, 0x19); /* TXTERM */ |
| 1015 | /* PREEMP Cgf 0.00 */ |
| 1016 | hdmi_phy_i2c_write(hdmi, 0x800d, 0x09); /* CKSYMTXCTRL */ |
| 1017 | /* TX/CK LVL 10 */ |
| 1018 | hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */ |
| 1019 | /* REMOVE CLK TERM */ |
| 1020 | hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */ |
| 1021 | |
| 1022 | imx_hdmi_phy_enable_power(hdmi, 1); |
| 1023 | |
| 1024 | /* toggle TMDS enable */ |
| 1025 | imx_hdmi_phy_enable_tmds(hdmi, 0); |
| 1026 | imx_hdmi_phy_enable_tmds(hdmi, 1); |
| 1027 | |
| 1028 | /* gen2 tx power on */ |
| 1029 | imx_hdmi_phy_gen2_txpwron(hdmi, 1); |
| 1030 | imx_hdmi_phy_gen2_pddq(hdmi, 0); |
| 1031 | |
| 1032 | /*Wait for PHY PLL lock */ |
| 1033 | msec = 5; |
| 1034 | do { |
| 1035 | val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; |
| 1036 | if (!val) |
| 1037 | break; |
| 1038 | |
| 1039 | if (msec == 0) { |
| 1040 | dev_err(hdmi->dev, "PHY PLL not locked\n"); |
| 1041 | return -ETIMEDOUT; |
| 1042 | } |
| 1043 | |
| 1044 | udelay(1000); |
| 1045 | msec--; |
| 1046 | } while (1); |
| 1047 | |
| 1048 | return 0; |
| 1049 | } |
| 1050 | |
| 1051 | static int imx_hdmi_phy_init(struct imx_hdmi *hdmi) |
| 1052 | { |
| 1053 | int i, ret; |
| 1054 | bool cscon = false; |
| 1055 | |
| 1056 | /*check csc whether needed activated in HDMI mode */ |
| 1057 | cscon = (is_color_space_conversion(hdmi) && |
| 1058 | !hdmi->hdmi_data.video_mode.mdvi); |
| 1059 | |
| 1060 | /* HDMI Phy spec says to do the phy initialization sequence twice */ |
| 1061 | for (i = 0; i < 2; i++) { |
| 1062 | imx_hdmi_phy_sel_data_en_pol(hdmi, 1); |
| 1063 | imx_hdmi_phy_sel_interface_control(hdmi, 0); |
| 1064 | imx_hdmi_phy_enable_tmds(hdmi, 0); |
| 1065 | imx_hdmi_phy_enable_power(hdmi, 0); |
| 1066 | |
| 1067 | /* Enable CSC */ |
| 1068 | ret = hdmi_phy_configure(hdmi, 0, 8, cscon); |
| 1069 | if (ret) |
| 1070 | return ret; |
| 1071 | } |
| 1072 | |
| 1073 | hdmi->phy_enabled = true; |
| 1074 | return 0; |
| 1075 | } |
| 1076 | |
| 1077 | static void hdmi_tx_hdcp_config(struct imx_hdmi *hdmi) |
| 1078 | { |
| 1079 | u8 de, val; |
| 1080 | |
| 1081 | if (hdmi->hdmi_data.video_mode.mdataenablepolarity) |
| 1082 | de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; |
| 1083 | else |
| 1084 | de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; |
| 1085 | |
| 1086 | /* disable rx detect */ |
| 1087 | val = hdmi_readb(hdmi, HDMI_A_HDCPCFG0); |
| 1088 | val &= HDMI_A_HDCPCFG0_RXDETECT_MASK; |
| 1089 | val |= HDMI_A_HDCPCFG0_RXDETECT_DISABLE; |
| 1090 | hdmi_writeb(hdmi, val, HDMI_A_HDCPCFG0); |
| 1091 | |
| 1092 | val = hdmi_readb(hdmi, HDMI_A_VIDPOLCFG); |
| 1093 | val &= HDMI_A_VIDPOLCFG_DATAENPOL_MASK; |
| 1094 | val |= de; |
| 1095 | hdmi_writeb(hdmi, val, HDMI_A_VIDPOLCFG); |
| 1096 | |
| 1097 | val = hdmi_readb(hdmi, HDMI_A_HDCPCFG1); |
| 1098 | val &= HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK; |
| 1099 | val |= HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE; |
| 1100 | hdmi_writeb(hdmi, val, HDMI_A_HDCPCFG1); |
| 1101 | } |
| 1102 | |
| 1103 | static void hdmi_config_AVI(struct imx_hdmi *hdmi) |
| 1104 | { |
| 1105 | u8 val, pix_fmt, under_scan; |
| 1106 | u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry; |
| 1107 | bool aspect_16_9; |
| 1108 | |
| 1109 | aspect_16_9 = false; /* FIXME */ |
| 1110 | |
| 1111 | /* AVI Data Byte 1 */ |
| 1112 | if (hdmi->hdmi_data.enc_out_format == YCBCR444) |
| 1113 | pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444; |
| 1114 | else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS) |
| 1115 | pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422; |
| 1116 | else |
| 1117 | pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB; |
| 1118 | |
| 1119 | under_scan = HDMI_FC_AVICONF0_SCAN_INFO_NODATA; |
| 1120 | |
| 1121 | /* |
| 1122 | * Active format identification data is present in the AVI InfoFrame. |
| 1123 | * Under scan info, no bar data |
| 1124 | */ |
| 1125 | val = pix_fmt | under_scan | |
| 1126 | HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT | |
| 1127 | HDMI_FC_AVICONF0_BAR_DATA_NO_DATA; |
| 1128 | |
| 1129 | hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); |
| 1130 | |
| 1131 | /* AVI Data Byte 2 -Set the Aspect Ratio */ |
| 1132 | if (aspect_16_9) { |
| 1133 | act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9; |
| 1134 | coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9; |
| 1135 | } else { |
| 1136 | act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3; |
| 1137 | coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3; |
| 1138 | } |
| 1139 | |
| 1140 | /* Set up colorimetry */ |
| 1141 | if (hdmi->hdmi_data.enc_out_format == XVYCC444) { |
| 1142 | colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO; |
| 1143 | if (hdmi->hdmi_data.colorimetry == ITU601) |
| 1144 | ext_colorimetry = |
| 1145 | HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601; |
| 1146 | else /* hdmi->hdmi_data.colorimetry == ITU709 */ |
| 1147 | ext_colorimetry = |
| 1148 | HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709; |
| 1149 | } else if (hdmi->hdmi_data.enc_out_format != RGB) { |
| 1150 | if (hdmi->hdmi_data.colorimetry == ITU601) |
| 1151 | colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE; |
| 1152 | else /* hdmi->hdmi_data.colorimetry == ITU709 */ |
| 1153 | colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR; |
| 1154 | ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601; |
| 1155 | } else { /* Carries no data */ |
| 1156 | colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA; |
| 1157 | ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601; |
| 1158 | } |
| 1159 | |
| 1160 | val = colorimetry | coded_ratio | act_ratio; |
| 1161 | hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); |
| 1162 | |
| 1163 | /* AVI Data Byte 3 */ |
| 1164 | val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry | |
| 1165 | HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT | |
| 1166 | HDMI_FC_AVICONF2_SCALING_NONE; |
| 1167 | hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); |
| 1168 | |
| 1169 | /* AVI Data Byte 4 */ |
| 1170 | hdmi_writeb(hdmi, hdmi->vic, HDMI_FC_AVIVID); |
| 1171 | |
| 1172 | /* AVI Data Byte 5- set up input and output pixel repetition */ |
| 1173 | val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << |
| 1174 | HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & |
| 1175 | HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | |
| 1176 | ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << |
| 1177 | HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & |
| 1178 | HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); |
| 1179 | hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); |
| 1180 | |
| 1181 | /* IT Content and quantization range = don't care */ |
| 1182 | val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS | |
| 1183 | HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED; |
| 1184 | hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); |
| 1185 | |
| 1186 | /* AVI Data Bytes 6-13 */ |
| 1187 | hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB0); |
| 1188 | hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB1); |
| 1189 | hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB0); |
| 1190 | hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB1); |
| 1191 | hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB0); |
| 1192 | hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB1); |
| 1193 | hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB0); |
| 1194 | hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB1); |
| 1195 | } |
| 1196 | |
| 1197 | static void hdmi_av_composer(struct imx_hdmi *hdmi, |
| 1198 | const struct drm_display_mode *mode) |
| 1199 | { |
| 1200 | u8 inv_val; |
| 1201 | struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; |
| 1202 | int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; |
| 1203 | |
| 1204 | vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC); |
| 1205 | vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC); |
| 1206 | vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); |
| 1207 | vmode->mpixelclock = mode->clock * 1000; |
| 1208 | |
| 1209 | dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); |
| 1210 | |
| 1211 | /* Set up HDMI_FC_INVIDCONF */ |
| 1212 | inv_val = (hdmi->hdmi_data.hdcp_enable ? |
| 1213 | HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : |
| 1214 | HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); |
| 1215 | |
| 1216 | inv_val |= (vmode->mvsyncpolarity ? |
| 1217 | HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : |
| 1218 | HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW); |
| 1219 | |
| 1220 | inv_val |= (vmode->mhsyncpolarity ? |
| 1221 | HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : |
| 1222 | HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW); |
| 1223 | |
| 1224 | inv_val |= (vmode->mdataenablepolarity ? |
| 1225 | HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : |
| 1226 | HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); |
| 1227 | |
| 1228 | if (hdmi->vic == 39) |
| 1229 | inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; |
| 1230 | else |
| 1231 | inv_val |= (vmode->minterlaced ? |
| 1232 | HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : |
| 1233 | HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW); |
| 1234 | |
| 1235 | inv_val |= (vmode->minterlaced ? |
| 1236 | HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : |
| 1237 | HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE); |
| 1238 | |
| 1239 | inv_val |= (vmode->mdvi ? |
| 1240 | HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE : |
| 1241 | HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE); |
| 1242 | |
| 1243 | hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); |
| 1244 | |
| 1245 | /* Set up horizontal active pixel width */ |
| 1246 | hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1); |
| 1247 | hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0); |
| 1248 | |
| 1249 | /* Set up vertical active lines */ |
| 1250 | hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1); |
| 1251 | hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0); |
| 1252 | |
| 1253 | /* Set up horizontal blanking pixel region width */ |
| 1254 | hblank = mode->htotal - mode->hdisplay; |
| 1255 | hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); |
| 1256 | hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); |
| 1257 | |
| 1258 | /* Set up vertical blanking pixel region width */ |
| 1259 | vblank = mode->vtotal - mode->vdisplay; |
| 1260 | hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); |
| 1261 | |
| 1262 | /* Set up HSYNC active edge delay width (in pixel clks) */ |
| 1263 | h_de_hs = mode->hsync_start - mode->hdisplay; |
| 1264 | hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); |
| 1265 | hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); |
| 1266 | |
| 1267 | /* Set up VSYNC active edge delay (in lines) */ |
| 1268 | v_de_vs = mode->vsync_start - mode->vdisplay; |
| 1269 | hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); |
| 1270 | |
| 1271 | /* Set up HSYNC active pulse width (in pixel clks) */ |
| 1272 | hsync_len = mode->hsync_end - mode->hsync_start; |
| 1273 | hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); |
| 1274 | hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); |
| 1275 | |
| 1276 | /* Set up VSYNC active edge delay (in lines) */ |
| 1277 | vsync_len = mode->vsync_end - mode->vsync_start; |
| 1278 | hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); |
| 1279 | } |
| 1280 | |
| 1281 | static void imx_hdmi_phy_disable(struct imx_hdmi *hdmi) |
| 1282 | { |
| 1283 | if (!hdmi->phy_enabled) |
| 1284 | return; |
| 1285 | |
| 1286 | imx_hdmi_phy_enable_tmds(hdmi, 0); |
| 1287 | imx_hdmi_phy_enable_power(hdmi, 0); |
| 1288 | |
| 1289 | hdmi->phy_enabled = false; |
| 1290 | } |
| 1291 | |
| 1292 | /* HDMI Initialization Step B.4 */ |
| 1293 | static void imx_hdmi_enable_video_path(struct imx_hdmi *hdmi) |
| 1294 | { |
| 1295 | u8 clkdis; |
| 1296 | |
| 1297 | /* control period minimum duration */ |
| 1298 | hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); |
| 1299 | hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); |
| 1300 | hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); |
| 1301 | |
| 1302 | /* Set to fill TMDS data channels */ |
| 1303 | hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); |
| 1304 | hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); |
| 1305 | hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); |
| 1306 | |
| 1307 | /* Enable pixel clock and tmds data path */ |
| 1308 | clkdis = 0x7F; |
| 1309 | clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; |
| 1310 | hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); |
| 1311 | |
| 1312 | clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; |
| 1313 | hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); |
| 1314 | |
| 1315 | /* Enable csc path */ |
| 1316 | if (is_color_space_conversion(hdmi)) { |
| 1317 | clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; |
| 1318 | hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); |
| 1319 | } |
| 1320 | } |
| 1321 | |
| 1322 | static void hdmi_enable_audio_clk(struct imx_hdmi *hdmi) |
| 1323 | { |
| 1324 | u8 clkdis; |
| 1325 | |
| 1326 | clkdis = hdmi_readb(hdmi, HDMI_MC_CLKDIS); |
| 1327 | clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; |
| 1328 | hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); |
| 1329 | } |
| 1330 | |
| 1331 | /* Workaround to clear the overflow condition */ |
| 1332 | static void imx_hdmi_clear_overflow(struct imx_hdmi *hdmi) |
| 1333 | { |
| 1334 | int count; |
| 1335 | u8 val; |
| 1336 | |
| 1337 | /* TMDS software reset */ |
| 1338 | hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); |
| 1339 | |
| 1340 | val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); |
| 1341 | if (hdmi->dev_type == IMX6DL_HDMI) { |
| 1342 | hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); |
| 1343 | return; |
| 1344 | } |
| 1345 | |
| 1346 | for (count = 0; count < 4; count++) |
| 1347 | hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); |
| 1348 | } |
| 1349 | |
| 1350 | static void hdmi_enable_overflow_interrupts(struct imx_hdmi *hdmi) |
| 1351 | { |
| 1352 | hdmi_writeb(hdmi, 0, HDMI_FC_MASK2); |
| 1353 | hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2); |
| 1354 | } |
| 1355 | |
| 1356 | static void hdmi_disable_overflow_interrupts(struct imx_hdmi *hdmi) |
| 1357 | { |
| 1358 | hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, |
| 1359 | HDMI_IH_MUTE_FC_STAT2); |
| 1360 | } |
| 1361 | |
| 1362 | static int imx_hdmi_setup(struct imx_hdmi *hdmi, struct drm_display_mode *mode) |
| 1363 | { |
| 1364 | int ret; |
| 1365 | |
| 1366 | hdmi_disable_overflow_interrupts(hdmi); |
| 1367 | |
| 1368 | hdmi->vic = drm_match_cea_mode(mode); |
| 1369 | |
| 1370 | if (!hdmi->vic) { |
| 1371 | dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); |
| 1372 | hdmi->hdmi_data.video_mode.mdvi = true; |
| 1373 | } else { |
| 1374 | dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); |
| 1375 | hdmi->hdmi_data.video_mode.mdvi = false; |
| 1376 | } |
| 1377 | |
| 1378 | if ((hdmi->vic == 6) || (hdmi->vic == 7) || |
| 1379 | (hdmi->vic == 21) || (hdmi->vic == 22) || |
| 1380 | (hdmi->vic == 2) || (hdmi->vic == 3) || |
| 1381 | (hdmi->vic == 17) || (hdmi->vic == 18)) |
| 1382 | hdmi->hdmi_data.colorimetry = ITU601; |
| 1383 | else |
| 1384 | hdmi->hdmi_data.colorimetry = ITU709; |
| 1385 | |
| 1386 | if ((hdmi->vic == 10) || (hdmi->vic == 11) || |
| 1387 | (hdmi->vic == 12) || (hdmi->vic == 13) || |
| 1388 | (hdmi->vic == 14) || (hdmi->vic == 15) || |
| 1389 | (hdmi->vic == 25) || (hdmi->vic == 26) || |
| 1390 | (hdmi->vic == 27) || (hdmi->vic == 28) || |
| 1391 | (hdmi->vic == 29) || (hdmi->vic == 30) || |
| 1392 | (hdmi->vic == 35) || (hdmi->vic == 36) || |
| 1393 | (hdmi->vic == 37) || (hdmi->vic == 38)) |
| 1394 | hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; |
| 1395 | else |
| 1396 | hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; |
| 1397 | |
| 1398 | hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; |
| 1399 | |
| 1400 | /* TODO: Get input format from IPU (via FB driver interface) */ |
| 1401 | hdmi->hdmi_data.enc_in_format = RGB; |
| 1402 | |
| 1403 | hdmi->hdmi_data.enc_out_format = RGB; |
| 1404 | |
| 1405 | hdmi->hdmi_data.enc_color_depth = 8; |
| 1406 | hdmi->hdmi_data.pix_repet_factor = 0; |
| 1407 | hdmi->hdmi_data.hdcp_enable = 0; |
| 1408 | hdmi->hdmi_data.video_mode.mdataenablepolarity = true; |
| 1409 | |
| 1410 | /* HDMI Initialization Step B.1 */ |
| 1411 | hdmi_av_composer(hdmi, mode); |
| 1412 | |
| 1413 | /* HDMI Initializateion Step B.2 */ |
| 1414 | ret = imx_hdmi_phy_init(hdmi); |
| 1415 | if (ret) |
| 1416 | return ret; |
| 1417 | |
| 1418 | /* HDMI Initialization Step B.3 */ |
| 1419 | imx_hdmi_enable_video_path(hdmi); |
| 1420 | |
| 1421 | /* not for DVI mode */ |
| 1422 | if (hdmi->hdmi_data.video_mode.mdvi) |
| 1423 | dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); |
| 1424 | else { |
| 1425 | dev_dbg(hdmi->dev, "%s CEA mode\n", __func__); |
| 1426 | |
| 1427 | /* HDMI Initialization Step E - Configure audio */ |
| 1428 | hdmi_clk_regenerator_update_pixel_clock(hdmi); |
| 1429 | hdmi_enable_audio_clk(hdmi); |
| 1430 | |
| 1431 | /* HDMI Initialization Step F - Configure AVI InfoFrame */ |
| 1432 | hdmi_config_AVI(hdmi); |
| 1433 | } |
| 1434 | |
| 1435 | hdmi_video_packetize(hdmi); |
| 1436 | hdmi_video_csc(hdmi); |
| 1437 | hdmi_video_sample(hdmi); |
| 1438 | hdmi_tx_hdcp_config(hdmi); |
| 1439 | |
| 1440 | imx_hdmi_clear_overflow(hdmi); |
| 1441 | if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi) |
| 1442 | hdmi_enable_overflow_interrupts(hdmi); |
| 1443 | |
| 1444 | return 0; |
| 1445 | } |
| 1446 | |
| 1447 | /* Wait until we are registered to enable interrupts */ |
| 1448 | static int imx_hdmi_fb_registered(struct imx_hdmi *hdmi) |
| 1449 | { |
| 1450 | hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, |
| 1451 | HDMI_PHY_I2CM_INT_ADDR); |
| 1452 | |
| 1453 | hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | |
| 1454 | HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, |
| 1455 | HDMI_PHY_I2CM_CTLINT_ADDR); |
| 1456 | |
| 1457 | /* enable cable hot plug irq */ |
| 1458 | hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0); |
| 1459 | |
| 1460 | /* Clear Hotplug interrupts */ |
| 1461 | hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0); |
| 1462 | |
| 1463 | /* Unmute interrupts */ |
| 1464 | hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0); |
| 1465 | |
| 1466 | return 0; |
| 1467 | } |
| 1468 | |
| 1469 | static void initialize_hdmi_ih_mutes(struct imx_hdmi *hdmi) |
| 1470 | { |
| 1471 | u8 ih_mute; |
| 1472 | |
| 1473 | /* |
| 1474 | * Boot up defaults are: |
| 1475 | * HDMI_IH_MUTE = 0x03 (disabled) |
| 1476 | * HDMI_IH_MUTE_* = 0x00 (enabled) |
| 1477 | * |
| 1478 | * Disable top level interrupt bits in HDMI block |
| 1479 | */ |
| 1480 | ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | |
| 1481 | HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | |
| 1482 | HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; |
| 1483 | |
| 1484 | hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); |
| 1485 | |
| 1486 | /* by default mask all interrupts */ |
| 1487 | hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); |
| 1488 | hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); |
| 1489 | hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); |
| 1490 | hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); |
| 1491 | hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); |
| 1492 | hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); |
| 1493 | hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); |
| 1494 | hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); |
| 1495 | hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); |
| 1496 | hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); |
| 1497 | hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); |
| 1498 | hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); |
| 1499 | hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK); |
| 1500 | hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); |
| 1501 | hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); |
| 1502 | |
| 1503 | /* Disable interrupts in the IH_MUTE_* registers */ |
| 1504 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); |
| 1505 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); |
| 1506 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); |
| 1507 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); |
| 1508 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); |
| 1509 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); |
| 1510 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); |
| 1511 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); |
| 1512 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); |
| 1513 | hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); |
| 1514 | |
| 1515 | /* Enable top level interrupt bits in HDMI block */ |
| 1516 | ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | |
| 1517 | HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); |
| 1518 | hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); |
| 1519 | } |
| 1520 | |
| 1521 | static void imx_hdmi_poweron(struct imx_hdmi *hdmi) |
| 1522 | { |
| 1523 | imx_hdmi_setup(hdmi, &hdmi->previous_mode); |
| 1524 | } |
| 1525 | |
| 1526 | static void imx_hdmi_poweroff(struct imx_hdmi *hdmi) |
| 1527 | { |
| 1528 | imx_hdmi_phy_disable(hdmi); |
| 1529 | } |
| 1530 | |
| 1531 | static enum drm_connector_status imx_hdmi_connector_detect(struct drm_connector |
| 1532 | *connector, bool force) |
| 1533 | { |
| 1534 | /* FIXME */ |
| 1535 | return connector_status_connected; |
| 1536 | } |
| 1537 | |
| 1538 | static void imx_hdmi_connector_destroy(struct drm_connector *connector) |
| 1539 | { |
| 1540 | } |
| 1541 | |
| 1542 | static int imx_hdmi_connector_get_modes(struct drm_connector *connector) |
| 1543 | { |
| 1544 | struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi, |
| 1545 | connector); |
| 1546 | struct edid *edid; |
| 1547 | int ret; |
| 1548 | |
| 1549 | if (!hdmi->ddc) |
| 1550 | return 0; |
| 1551 | |
| 1552 | edid = drm_get_edid(connector, hdmi->ddc); |
| 1553 | if (edid) { |
| 1554 | dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", |
| 1555 | edid->width_cm, edid->height_cm); |
| 1556 | |
| 1557 | drm_mode_connector_update_edid_property(connector, edid); |
| 1558 | ret = drm_add_edid_modes(connector, edid); |
| 1559 | kfree(edid); |
| 1560 | } else { |
| 1561 | dev_dbg(hdmi->dev, "failed to get edid\n"); |
| 1562 | } |
| 1563 | |
| 1564 | return 0; |
| 1565 | } |
| 1566 | |
| 1567 | static int imx_hdmi_connector_mode_valid(struct drm_connector *connector, |
| 1568 | struct drm_display_mode *mode) |
| 1569 | { |
| 1570 | |
| 1571 | return MODE_OK; |
| 1572 | } |
| 1573 | |
| 1574 | static struct drm_encoder *imx_hdmi_connector_best_encoder(struct drm_connector |
| 1575 | *connector) |
| 1576 | { |
| 1577 | struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi, |
| 1578 | connector); |
| 1579 | |
| 1580 | return &hdmi->encoder; |
| 1581 | } |
| 1582 | |
| 1583 | static void imx_hdmi_encoder_mode_set(struct drm_encoder *encoder, |
| 1584 | struct drm_display_mode *mode, |
| 1585 | struct drm_display_mode *adjusted_mode) |
| 1586 | { |
| 1587 | struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder); |
| 1588 | |
| 1589 | imx_hdmi_setup(hdmi, mode); |
| 1590 | |
| 1591 | /* Store the display mode for plugin/DKMS poweron events */ |
| 1592 | memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); |
| 1593 | } |
| 1594 | |
| 1595 | static bool imx_hdmi_encoder_mode_fixup(struct drm_encoder *encoder, |
| 1596 | const struct drm_display_mode *mode, |
| 1597 | struct drm_display_mode *adjusted_mode) |
| 1598 | { |
| 1599 | return true; |
| 1600 | } |
| 1601 | |
| 1602 | static void imx_hdmi_encoder_disable(struct drm_encoder *encoder) |
| 1603 | { |
| 1604 | } |
| 1605 | |
| 1606 | static void imx_hdmi_encoder_dpms(struct drm_encoder *encoder, int mode) |
| 1607 | { |
| 1608 | struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder); |
| 1609 | |
| 1610 | if (mode) |
| 1611 | imx_hdmi_poweroff(hdmi); |
| 1612 | else |
| 1613 | imx_hdmi_poweron(hdmi); |
| 1614 | } |
| 1615 | |
| 1616 | static void imx_hdmi_encoder_prepare(struct drm_encoder *encoder) |
| 1617 | { |
| 1618 | struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder); |
| 1619 | |
| 1620 | imx_hdmi_poweroff(hdmi); |
| 1621 | imx_drm_crtc_panel_format(encoder->crtc, DRM_MODE_ENCODER_NONE, |
| 1622 | V4L2_PIX_FMT_RGB24); |
| 1623 | } |
| 1624 | |
| 1625 | static void imx_hdmi_encoder_commit(struct drm_encoder *encoder) |
| 1626 | { |
| 1627 | struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder); |
| 1628 | int mux = imx_drm_encoder_get_mux_id(hdmi->imx_drm_encoder, |
| 1629 | encoder->crtc); |
| 1630 | |
| 1631 | imx_hdmi_set_ipu_di_mux(hdmi, mux); |
| 1632 | |
| 1633 | imx_hdmi_poweron(hdmi); |
| 1634 | } |
| 1635 | |
| 1636 | static void imx_hdmi_encoder_destroy(struct drm_encoder *encoder) |
| 1637 | { |
| 1638 | return; |
| 1639 | } |
| 1640 | |
| 1641 | static struct drm_encoder_funcs imx_hdmi_encoder_funcs = { |
| 1642 | .destroy = imx_hdmi_encoder_destroy, |
| 1643 | }; |
| 1644 | |
| 1645 | static struct drm_encoder_helper_funcs imx_hdmi_encoder_helper_funcs = { |
| 1646 | .dpms = imx_hdmi_encoder_dpms, |
| 1647 | .prepare = imx_hdmi_encoder_prepare, |
| 1648 | .commit = imx_hdmi_encoder_commit, |
| 1649 | .mode_set = imx_hdmi_encoder_mode_set, |
| 1650 | .mode_fixup = imx_hdmi_encoder_mode_fixup, |
| 1651 | .disable = imx_hdmi_encoder_disable, |
| 1652 | }; |
| 1653 | |
| 1654 | static struct drm_connector_funcs imx_hdmi_connector_funcs = { |
| 1655 | .dpms = drm_helper_connector_dpms, |
| 1656 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 1657 | .detect = imx_hdmi_connector_detect, |
| 1658 | .destroy = imx_hdmi_connector_destroy, |
| 1659 | }; |
| 1660 | |
| 1661 | static struct drm_connector_helper_funcs imx_hdmi_connector_helper_funcs = { |
| 1662 | .get_modes = imx_hdmi_connector_get_modes, |
| 1663 | .mode_valid = imx_hdmi_connector_mode_valid, |
| 1664 | .best_encoder = imx_hdmi_connector_best_encoder, |
| 1665 | }; |
| 1666 | |
| 1667 | static irqreturn_t imx_hdmi_irq(int irq, void *dev_id) |
| 1668 | { |
| 1669 | struct imx_hdmi *hdmi = dev_id; |
| 1670 | u8 intr_stat; |
| 1671 | u8 phy_int_pol; |
| 1672 | u8 val; |
| 1673 | |
| 1674 | intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); |
| 1675 | |
| 1676 | phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); |
| 1677 | |
| 1678 | if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { |
| 1679 | if (phy_int_pol & HDMI_PHY_HPD) { |
| 1680 | dev_dbg(hdmi->dev, "EVENT=plugin\n"); |
| 1681 | |
| 1682 | val = hdmi_readb(hdmi, HDMI_PHY_POL0); |
| 1683 | val &= ~HDMI_PHY_HPD; |
| 1684 | hdmi_writeb(hdmi, val, HDMI_PHY_POL0); |
| 1685 | |
| 1686 | imx_hdmi_poweron(hdmi); |
| 1687 | } else { |
| 1688 | dev_dbg(hdmi->dev, "EVENT=plugout\n"); |
| 1689 | |
| 1690 | val = hdmi_readb(hdmi, HDMI_PHY_POL0); |
| 1691 | val |= HDMI_PHY_HPD; |
| 1692 | hdmi_writeb(hdmi, val, HDMI_PHY_POL0); |
| 1693 | |
| 1694 | imx_hdmi_poweroff(hdmi); |
| 1695 | } |
| 1696 | } |
| 1697 | |
| 1698 | hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); |
| 1699 | |
| 1700 | return IRQ_HANDLED; |
| 1701 | } |
| 1702 | |
| 1703 | static int imx_hdmi_register(struct imx_hdmi *hdmi) |
| 1704 | { |
| 1705 | int ret; |
| 1706 | |
| 1707 | hdmi->connector.funcs = &imx_hdmi_connector_funcs; |
| 1708 | hdmi->encoder.funcs = &imx_hdmi_encoder_funcs; |
| 1709 | |
| 1710 | hdmi->encoder.encoder_type = DRM_MODE_ENCODER_TMDS; |
| 1711 | hdmi->connector.connector_type = DRM_MODE_CONNECTOR_HDMIA; |
| 1712 | |
| 1713 | drm_encoder_helper_add(&hdmi->encoder, &imx_hdmi_encoder_helper_funcs); |
| 1714 | ret = imx_drm_add_encoder(&hdmi->encoder, &hdmi->imx_drm_encoder, |
| 1715 | THIS_MODULE); |
| 1716 | if (ret) { |
| 1717 | dev_err(hdmi->dev, "adding encoder failed: %d\n", ret); |
| 1718 | return ret; |
| 1719 | } |
| 1720 | |
| 1721 | drm_connector_helper_add(&hdmi->connector, |
| 1722 | &imx_hdmi_connector_helper_funcs); |
| 1723 | |
| 1724 | ret = imx_drm_add_connector(&hdmi->connector, |
| 1725 | &hdmi->imx_drm_connector, THIS_MODULE); |
| 1726 | if (ret) { |
| 1727 | imx_drm_remove_encoder(hdmi->imx_drm_encoder); |
| 1728 | dev_err(hdmi->dev, "adding connector failed: %d\n", ret); |
| 1729 | return ret; |
| 1730 | } |
| 1731 | |
| 1732 | hdmi->connector.encoder = &hdmi->encoder; |
| 1733 | |
| 1734 | drm_mode_connector_attach_encoder(&hdmi->connector, &hdmi->encoder); |
| 1735 | |
| 1736 | return 0; |
| 1737 | } |
| 1738 | |
| 1739 | static struct platform_device_id imx_hdmi_devtype[] = { |
| 1740 | { |
| 1741 | .name = "imx6q-hdmi", |
| 1742 | .driver_data = IMX6Q_HDMI, |
| 1743 | }, { |
| 1744 | .name = "imx6dl-hdmi", |
| 1745 | .driver_data = IMX6DL_HDMI, |
| 1746 | }, { /* sentinel */ } |
| 1747 | }; |
| 1748 | MODULE_DEVICE_TABLE(platform, imx_hdmi_devtype); |
| 1749 | |
| 1750 | static const struct of_device_id imx_hdmi_dt_ids[] = { |
| 1751 | { .compatible = "fsl,imx6q-hdmi", .data = &imx_hdmi_devtype[IMX6Q_HDMI], }, |
| 1752 | { .compatible = "fsl,imx6dl-hdmi", .data = &imx_hdmi_devtype[IMX6DL_HDMI], }, |
| 1753 | { /* sentinel */ } |
| 1754 | }; |
| 1755 | MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids); |
| 1756 | |
| 1757 | static int imx_hdmi_platform_probe(struct platform_device *pdev) |
| 1758 | { |
| 1759 | const struct of_device_id *of_id = |
| 1760 | of_match_device(imx_hdmi_dt_ids, &pdev->dev); |
| 1761 | struct device_node *np = pdev->dev.of_node; |
| 1762 | struct device_node *ddc_node; |
| 1763 | struct imx_hdmi *hdmi; |
| 1764 | struct resource *iores; |
| 1765 | int ret, irq; |
| 1766 | |
| 1767 | hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); |
| 1768 | if (!hdmi) |
| 1769 | return -ENOMEM; |
| 1770 | |
| 1771 | hdmi->dev = &pdev->dev; |
| 1772 | |
| 1773 | if (of_id) { |
| 1774 | const struct platform_device_id *device_id = of_id->data; |
| 1775 | hdmi->dev_type = device_id->driver_data; |
| 1776 | } |
| 1777 | |
| 1778 | ddc_node = of_parse_phandle(np, "ddc", 0); |
| 1779 | if (ddc_node) { |
| 1780 | hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); |
| 1781 | if (!hdmi->ddc) |
| 1782 | dev_dbg(hdmi->dev, "failed to read ddc node\n"); |
| 1783 | |
| 1784 | of_node_put(ddc_node); |
| 1785 | } else { |
| 1786 | dev_dbg(hdmi->dev, "no ddc property found\n"); |
| 1787 | } |
| 1788 | |
| 1789 | irq = platform_get_irq(pdev, 0); |
| 1790 | if (irq < 0) |
| 1791 | return -EINVAL; |
| 1792 | |
| 1793 | ret = devm_request_irq(&pdev->dev, irq, imx_hdmi_irq, 0, |
| 1794 | dev_name(&pdev->dev), hdmi); |
| 1795 | if (ret) |
| 1796 | return ret; |
| 1797 | |
| 1798 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1799 | hdmi->regs = devm_ioremap_resource(&pdev->dev, iores); |
| 1800 | if (IS_ERR(hdmi->regs)) |
| 1801 | return PTR_ERR(hdmi->regs); |
| 1802 | |
| 1803 | hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); |
| 1804 | if (IS_ERR(hdmi->regmap)) |
| 1805 | return PTR_ERR(hdmi->regmap); |
| 1806 | |
| 1807 | hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); |
| 1808 | if (IS_ERR(hdmi->isfr_clk)) { |
| 1809 | ret = PTR_ERR(hdmi->isfr_clk); |
| 1810 | dev_err(hdmi->dev, |
| 1811 | "Unable to get HDMI isfr clk: %d\n", ret); |
| 1812 | return ret; |
| 1813 | } |
| 1814 | |
| 1815 | ret = clk_prepare_enable(hdmi->isfr_clk); |
| 1816 | if (ret) { |
| 1817 | dev_err(hdmi->dev, |
| 1818 | "Cannot enable HDMI isfr clock: %d\n", ret); |
| 1819 | return ret; |
| 1820 | } |
| 1821 | |
| 1822 | hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); |
| 1823 | if (IS_ERR(hdmi->iahb_clk)) { |
| 1824 | ret = PTR_ERR(hdmi->iahb_clk); |
| 1825 | dev_err(hdmi->dev, |
| 1826 | "Unable to get HDMI iahb clk: %d\n", ret); |
| 1827 | goto err_isfr; |
| 1828 | } |
| 1829 | |
| 1830 | ret = clk_prepare_enable(hdmi->iahb_clk); |
| 1831 | if (ret) { |
| 1832 | dev_err(hdmi->dev, |
| 1833 | "Cannot enable HDMI iahb clock: %d\n", ret); |
| 1834 | goto err_isfr; |
| 1835 | } |
| 1836 | |
| 1837 | /* Product and revision IDs */ |
| 1838 | dev_info(&pdev->dev, |
| 1839 | "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n", |
| 1840 | hdmi_readb(hdmi, HDMI_DESIGN_ID), |
| 1841 | hdmi_readb(hdmi, HDMI_REVISION_ID), |
| 1842 | hdmi_readb(hdmi, HDMI_PRODUCT_ID0), |
| 1843 | hdmi_readb(hdmi, HDMI_PRODUCT_ID1)); |
| 1844 | |
| 1845 | initialize_hdmi_ih_mutes(hdmi); |
| 1846 | |
| 1847 | /* |
| 1848 | * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator |
| 1849 | * N and cts values before enabling phy |
| 1850 | */ |
| 1851 | hdmi_init_clk_regenerator(hdmi); |
| 1852 | |
| 1853 | /* |
| 1854 | * Configure registers related to HDMI interrupt |
| 1855 | * generation before registering IRQ. |
| 1856 | */ |
| 1857 | hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0); |
| 1858 | |
| 1859 | /* Clear Hotplug interrupts */ |
| 1860 | hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0); |
| 1861 | |
| 1862 | ret = imx_hdmi_fb_registered(hdmi); |
| 1863 | if (ret) |
| 1864 | goto err_iahb; |
| 1865 | |
| 1866 | ret = imx_hdmi_register(hdmi); |
| 1867 | if (ret) |
| 1868 | goto err_iahb; |
| 1869 | |
| 1870 | imx_drm_encoder_add_possible_crtcs(hdmi->imx_drm_encoder, np); |
| 1871 | |
| 1872 | platform_set_drvdata(pdev, hdmi); |
| 1873 | |
| 1874 | return 0; |
| 1875 | |
| 1876 | err_iahb: |
| 1877 | clk_disable_unprepare(hdmi->iahb_clk); |
| 1878 | err_isfr: |
| 1879 | clk_disable_unprepare(hdmi->isfr_clk); |
| 1880 | |
| 1881 | return ret; |
| 1882 | } |
| 1883 | |
| 1884 | static int imx_hdmi_platform_remove(struct platform_device *pdev) |
| 1885 | { |
| 1886 | struct imx_hdmi *hdmi = platform_get_drvdata(pdev); |
| 1887 | struct drm_connector *connector = &hdmi->connector; |
| 1888 | struct drm_encoder *encoder = &hdmi->encoder; |
| 1889 | |
| 1890 | drm_mode_connector_detach_encoder(connector, encoder); |
| 1891 | imx_drm_remove_connector(hdmi->imx_drm_connector); |
| 1892 | imx_drm_remove_encoder(hdmi->imx_drm_encoder); |
| 1893 | |
| 1894 | clk_disable_unprepare(hdmi->iahb_clk); |
| 1895 | clk_disable_unprepare(hdmi->isfr_clk); |
| 1896 | i2c_put_adapter(hdmi->ddc); |
| 1897 | |
| 1898 | return 0; |
| 1899 | } |
| 1900 | |
| 1901 | static struct platform_driver imx_hdmi_driver = { |
| 1902 | .probe = imx_hdmi_platform_probe, |
| 1903 | .remove = imx_hdmi_platform_remove, |
| 1904 | .driver = { |
| 1905 | .name = "imx-hdmi", |
| 1906 | .owner = THIS_MODULE, |
| 1907 | .of_match_table = imx_hdmi_dt_ids, |
| 1908 | }, |
| 1909 | }; |
| 1910 | |
| 1911 | module_platform_driver(imx_hdmi_driver); |
| 1912 | |
| 1913 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); |
| 1914 | MODULE_DESCRIPTION("i.MX6 HDMI transmitter driver"); |
| 1915 | MODULE_LICENSE("GPL"); |
| 1916 | MODULE_ALIAS("platform:imx-hdmi"); |