Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/clock.c |
| 3 | * |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2004-2008 Nokia Corporation |
| 6 | * |
| 7 | * Contacts: |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 9 | * Paul Walmsley |
| 10 | * |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | #undef DEBUG |
| 16 | |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/device.h> |
| 20 | #include <linux/list.h> |
| 21 | #include <linux/errno.h> |
| 22 | #include <linux/delay.h> |
| 23 | #include <linux/clk.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 24 | #include <linux/io.h> |
Russell King | fbd3bdb | 2008-09-06 12:13:59 +0100 | [diff] [blame] | 25 | #include <linux/bitops.h> |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 26 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 27 | #include <mach/clock.h> |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 28 | #include <mach/clockdomain.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 29 | #include <mach/sram.h> |
| 30 | #include <mach/cpu.h> |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 31 | #include <asm/div64.h> |
| 32 | |
| 33 | #include "memory.h" |
| 34 | #include "sdrc.h" |
| 35 | #include "clock.h" |
| 36 | #include "prm.h" |
| 37 | #include "prm-regbits-24xx.h" |
| 38 | #include "cm.h" |
| 39 | #include "cm-regbits-24xx.h" |
| 40 | #include "cm-regbits-34xx.h" |
| 41 | |
| 42 | #define MAX_CLOCK_ENABLE_WAIT 100000 |
| 43 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 44 | /* DPLL rate rounding: minimum DPLL multiplier, divider values */ |
| 45 | #define DPLL_MIN_MULTIPLIER 1 |
| 46 | #define DPLL_MIN_DIVIDER 1 |
| 47 | |
| 48 | /* Possible error results from _dpll_test_mult */ |
| 49 | #define DPLL_MULT_UNDERFLOW (1 << 0) |
| 50 | |
| 51 | /* |
| 52 | * Scale factor to mitigate roundoff errors in DPLL rate rounding. |
| 53 | * The higher the scale factor, the greater the risk of arithmetic overflow, |
| 54 | * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR |
| 55 | * must be a power of DPLL_SCALE_BASE. |
| 56 | */ |
| 57 | #define DPLL_SCALE_FACTOR 64 |
| 58 | #define DPLL_SCALE_BASE 2 |
| 59 | #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ |
| 60 | (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) |
| 61 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 62 | u8 cpu_mask; |
| 63 | |
| 64 | /*------------------------------------------------------------------------- |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 65 | * OMAP2/3 specific clock functions |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 66 | *-------------------------------------------------------------------------*/ |
| 67 | |
| 68 | /** |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 69 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk |
| 70 | * @clk: OMAP clock struct ptr to use |
| 71 | * |
| 72 | * Convert a clockdomain name stored in a struct clk 'clk' into a |
| 73 | * clockdomain pointer, and save it into the struct clk. Intended to be |
| 74 | * called during clk_register(). No return value. |
| 75 | */ |
| 76 | void omap2_init_clk_clkdm(struct clk *clk) |
| 77 | { |
| 78 | struct clockdomain *clkdm; |
| 79 | |
| 80 | if (!clk->clkdm_name) |
| 81 | return; |
| 82 | |
| 83 | clkdm = clkdm_lookup(clk->clkdm_name); |
| 84 | if (clkdm) { |
| 85 | pr_debug("clock: associated clk %s to clkdm %s\n", |
| 86 | clk->name, clk->clkdm_name); |
| 87 | clk->clkdm = clkdm; |
| 88 | } else { |
| 89 | pr_debug("clock: could not associate clk %s to " |
| 90 | "clkdm %s\n", clk->name, clk->clkdm_name); |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | /** |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 95 | * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware |
| 96 | * @clk: OMAP clock struct ptr to use |
| 97 | * |
| 98 | * Given a pointer to a source-selectable struct clk, read the hardware |
| 99 | * register and determine what its parent is currently set to. Update the |
| 100 | * clk->parent field with the appropriate clk ptr. |
| 101 | */ |
| 102 | void omap2_init_clksel_parent(struct clk *clk) |
| 103 | { |
| 104 | const struct clksel *clks; |
| 105 | const struct clksel_rate *clkr; |
| 106 | u32 r, found = 0; |
| 107 | |
| 108 | if (!clk->clksel) |
| 109 | return; |
| 110 | |
| 111 | r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; |
| 112 | r >>= __ffs(clk->clksel_mask); |
| 113 | |
| 114 | for (clks = clk->clksel; clks->parent && !found; clks++) { |
| 115 | for (clkr = clks->rates; clkr->div && !found; clkr++) { |
| 116 | if ((clkr->flags & cpu_mask) && (clkr->val == r)) { |
| 117 | if (clk->parent != clks->parent) { |
| 118 | pr_debug("clock: inited %s parent " |
| 119 | "to %s (was %s)\n", |
| 120 | clk->name, clks->parent->name, |
| 121 | ((clk->parent) ? |
| 122 | clk->parent->name : "NULL")); |
| 123 | clk->parent = clks->parent; |
| 124 | }; |
| 125 | found = 1; |
| 126 | } |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | if (!found) |
| 131 | printk(KERN_ERR "clock: init parent: could not find " |
| 132 | "regval %0x for clock %s\n", r, clk->name); |
| 133 | |
| 134 | return; |
| 135 | } |
| 136 | |
| 137 | /* Returns the DPLL rate */ |
| 138 | u32 omap2_get_dpll_rate(struct clk *clk) |
| 139 | { |
| 140 | long long dpll_clk; |
| 141 | u32 dpll_mult, dpll_div, dpll; |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 142 | struct dpll_data *dd; |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 143 | |
| 144 | dd = clk->dpll_data; |
| 145 | /* REVISIT: What do we return on error? */ |
| 146 | if (!dd) |
| 147 | return 0; |
| 148 | |
| 149 | dpll = __raw_readl(dd->mult_div1_reg); |
| 150 | dpll_mult = dpll & dd->mult_mask; |
| 151 | dpll_mult >>= __ffs(dd->mult_mask); |
| 152 | dpll_div = dpll & dd->div1_mask; |
| 153 | dpll_div >>= __ffs(dd->div1_mask); |
| 154 | |
| 155 | dpll_clk = (long long)clk->parent->rate * dpll_mult; |
| 156 | do_div(dpll_clk, dpll_div + 1); |
| 157 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 158 | return dpll_clk; |
| 159 | } |
| 160 | |
| 161 | /* |
| 162 | * Used for clocks that have the same value as the parent clock, |
| 163 | * divided by some factor |
| 164 | */ |
| 165 | void omap2_fixed_divisor_recalc(struct clk *clk) |
| 166 | { |
| 167 | WARN_ON(!clk->fixed_div); |
| 168 | |
| 169 | clk->rate = clk->parent->rate / clk->fixed_div; |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | /** |
| 173 | * omap2_wait_clock_ready - wait for clock to enable |
| 174 | * @reg: physical address of clock IDLEST register |
| 175 | * @mask: value to mask against to determine if the clock is active |
| 176 | * @name: name of the clock (for printk) |
| 177 | * |
| 178 | * Returns 1 if the clock enabled in time, or 0 if it failed to enable |
| 179 | * in roughly MAX_CLOCK_ENABLE_WAIT microseconds. |
| 180 | */ |
| 181 | int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) |
| 182 | { |
| 183 | int i = 0; |
| 184 | int ena = 0; |
| 185 | |
| 186 | /* |
| 187 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. |
| 188 | * 34xx reverses this, just to keep us on our toes |
| 189 | */ |
| 190 | if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) { |
| 191 | ena = mask; |
| 192 | } else if (cpu_mask & RATE_IN_343X) { |
| 193 | ena = 0; |
| 194 | } |
| 195 | |
| 196 | /* Wait for lock */ |
| 197 | while (((__raw_readl(reg) & mask) != ena) && |
| 198 | (i++ < MAX_CLOCK_ENABLE_WAIT)) { |
| 199 | udelay(1); |
| 200 | } |
| 201 | |
| 202 | if (i < MAX_CLOCK_ENABLE_WAIT) |
| 203 | pr_debug("Clock %s stable after %d loops\n", name, i); |
| 204 | else |
| 205 | printk(KERN_ERR "Clock %s didn't enable in %d tries\n", |
| 206 | name, MAX_CLOCK_ENABLE_WAIT); |
| 207 | |
| 208 | |
| 209 | return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0; |
| 210 | }; |
| 211 | |
| 212 | |
| 213 | /* |
| 214 | * Note: We don't need special code here for INVERT_ENABLE |
| 215 | * for the time being since INVERT_ENABLE only applies to clocks enabled by |
| 216 | * CM_CLKEN_PLL |
| 217 | */ |
| 218 | static void omap2_clk_wait_ready(struct clk *clk) |
| 219 | { |
| 220 | void __iomem *reg, *other_reg, *st_reg; |
| 221 | u32 bit; |
| 222 | |
| 223 | /* |
| 224 | * REVISIT: This code is pretty ugly. It would be nice to generalize |
| 225 | * it and pull it into struct clk itself somehow. |
| 226 | */ |
| 227 | reg = clk->enable_reg; |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 228 | |
| 229 | /* |
| 230 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes |
| 231 | * it's just a matter of XORing the bits. |
| 232 | */ |
| 233 | other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN)); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 234 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 235 | /* Check if both functional and interface clocks |
| 236 | * are running. */ |
| 237 | bit = 1 << clk->enable_bit; |
| 238 | if (!(__raw_readl(other_reg) & bit)) |
| 239 | return; |
| 240 | st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */ |
| 241 | |
| 242 | omap2_wait_clock_ready(st_reg, bit, clk->name); |
| 243 | } |
| 244 | |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 245 | static int omap2_dflt_clk_enable(struct clk *clk) |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 246 | { |
| 247 | u32 regval32; |
| 248 | |
Russell King | c0fc18c5 | 2008-09-05 15:10:27 +0100 | [diff] [blame] | 249 | if (unlikely(clk->enable_reg == NULL)) { |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 250 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", |
| 251 | clk->name); |
| 252 | return 0; /* REVISIT: -EINVAL */ |
| 253 | } |
| 254 | |
| 255 | regval32 = __raw_readl(clk->enable_reg); |
| 256 | if (clk->flags & INVERT_ENABLE) |
| 257 | regval32 &= ~(1 << clk->enable_bit); |
| 258 | else |
| 259 | regval32 |= (1 << clk->enable_bit); |
| 260 | __raw_writel(regval32, clk->enable_reg); |
| 261 | wmb(); |
| 262 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 263 | return 0; |
| 264 | } |
| 265 | |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 266 | static int omap2_dflt_clk_enable_wait(struct clk *clk) |
| 267 | { |
| 268 | int ret; |
| 269 | |
| 270 | if (unlikely(clk->enable_reg == NULL)) { |
| 271 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", |
| 272 | clk->name); |
| 273 | return 0; /* REVISIT: -EINVAL */ |
| 274 | } |
| 275 | |
| 276 | ret = omap2_dflt_clk_enable(clk); |
| 277 | if (ret == 0) |
| 278 | omap2_clk_wait_ready(clk); |
| 279 | return ret; |
| 280 | } |
| 281 | |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 282 | static void omap2_dflt_clk_disable(struct clk *clk) |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 283 | { |
| 284 | u32 regval32; |
| 285 | |
Russell King | c0fc18c5 | 2008-09-05 15:10:27 +0100 | [diff] [blame] | 286 | if (clk->enable_reg == NULL) { |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 287 | /* |
| 288 | * 'Independent' here refers to a clock which is not |
| 289 | * controlled by its parent. |
| 290 | */ |
| 291 | printk(KERN_ERR "clock: clk_disable called on independent " |
| 292 | "clock %s which has no enable_reg\n", clk->name); |
| 293 | return; |
| 294 | } |
| 295 | |
| 296 | regval32 = __raw_readl(clk->enable_reg); |
| 297 | if (clk->flags & INVERT_ENABLE) |
| 298 | regval32 |= (1 << clk->enable_bit); |
| 299 | else |
| 300 | regval32 &= ~(1 << clk->enable_bit); |
| 301 | __raw_writel(regval32, clk->enable_reg); |
| 302 | wmb(); |
| 303 | } |
| 304 | |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 305 | const struct clkops clkops_omap2_dflt_wait = { |
| 306 | .enable = omap2_dflt_clk_enable_wait, |
| 307 | .disable = omap2_dflt_clk_disable, |
| 308 | }; |
| 309 | |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 310 | const struct clkops clkops_omap2_dflt = { |
| 311 | .enable = omap2_dflt_clk_enable, |
| 312 | .disable = omap2_dflt_clk_disable, |
| 313 | }; |
| 314 | |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 315 | /* Enables clock without considering parent dependencies or use count |
| 316 | * REVISIT: Maybe change this to use clk->enable like on omap1? |
| 317 | */ |
| 318 | static int _omap2_clk_enable(struct clk *clk) |
| 319 | { |
| 320 | return clk->ops->enable(clk); |
| 321 | } |
| 322 | |
| 323 | /* Disables clock without considering parent dependencies or use count */ |
| 324 | static void _omap2_clk_disable(struct clk *clk) |
| 325 | { |
| 326 | clk->ops->disable(clk); |
| 327 | } |
| 328 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 329 | void omap2_clk_disable(struct clk *clk) |
| 330 | { |
| 331 | if (clk->usecount > 0 && !(--clk->usecount)) { |
| 332 | _omap2_clk_disable(clk); |
| 333 | if (likely((u32)clk->parent)) |
| 334 | omap2_clk_disable(clk->parent); |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 335 | if (clk->clkdm) |
| 336 | omap2_clkdm_clk_disable(clk->clkdm, clk); |
| 337 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 338 | } |
| 339 | } |
| 340 | |
| 341 | int omap2_clk_enable(struct clk *clk) |
| 342 | { |
| 343 | int ret = 0; |
| 344 | |
| 345 | if (clk->usecount++ == 0) { |
| 346 | if (likely((u32)clk->parent)) |
| 347 | ret = omap2_clk_enable(clk->parent); |
| 348 | |
| 349 | if (unlikely(ret != 0)) { |
| 350 | clk->usecount--; |
| 351 | return ret; |
| 352 | } |
| 353 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 354 | if (clk->clkdm) |
| 355 | omap2_clkdm_clk_enable(clk->clkdm, clk); |
| 356 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 357 | ret = _omap2_clk_enable(clk); |
| 358 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 359 | if (unlikely(ret != 0)) { |
| 360 | if (clk->clkdm) |
| 361 | omap2_clkdm_clk_disable(clk->clkdm, clk); |
| 362 | |
| 363 | if (clk->parent) { |
| 364 | omap2_clk_disable(clk->parent); |
| 365 | clk->usecount--; |
| 366 | } |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 367 | } |
| 368 | } |
| 369 | |
| 370 | return ret; |
| 371 | } |
| 372 | |
| 373 | /* |
| 374 | * Used for clocks that are part of CLKSEL_xyz governed clocks. |
| 375 | * REVISIT: Maybe change to use clk->enable() functions like on omap1? |
| 376 | */ |
| 377 | void omap2_clksel_recalc(struct clk *clk) |
| 378 | { |
| 379 | u32 div = 0; |
| 380 | |
| 381 | pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); |
| 382 | |
| 383 | div = omap2_clksel_get_divisor(clk); |
| 384 | if (div == 0) |
| 385 | return; |
| 386 | |
| 387 | if (unlikely(clk->rate == clk->parent->rate / div)) |
| 388 | return; |
| 389 | clk->rate = clk->parent->rate / div; |
| 390 | |
| 391 | pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 392 | } |
| 393 | |
| 394 | /** |
| 395 | * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent |
| 396 | * @clk: OMAP struct clk ptr to inspect |
| 397 | * @src_clk: OMAP struct clk ptr of the parent clk to search for |
| 398 | * |
| 399 | * Scan the struct clksel array associated with the clock to find |
| 400 | * the element associated with the supplied parent clock address. |
| 401 | * Returns a pointer to the struct clksel on success or NULL on error. |
| 402 | */ |
| 403 | const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, |
| 404 | struct clk *src_clk) |
| 405 | { |
| 406 | const struct clksel *clks; |
| 407 | |
| 408 | if (!clk->clksel) |
| 409 | return NULL; |
| 410 | |
| 411 | for (clks = clk->clksel; clks->parent; clks++) { |
| 412 | if (clks->parent == src_clk) |
| 413 | break; /* Found the requested parent */ |
| 414 | } |
| 415 | |
| 416 | if (!clks->parent) { |
| 417 | printk(KERN_ERR "clock: Could not find parent clock %s in " |
| 418 | "clksel array of clock %s\n", src_clk->name, |
| 419 | clk->name); |
| 420 | return NULL; |
| 421 | } |
| 422 | |
| 423 | return clks; |
| 424 | } |
| 425 | |
| 426 | /** |
| 427 | * omap2_clksel_round_rate_div - find divisor for the given clock and rate |
| 428 | * @clk: OMAP struct clk to use |
| 429 | * @target_rate: desired clock rate |
| 430 | * @new_div: ptr to where we should store the divisor |
| 431 | * |
| 432 | * Finds 'best' divider value in an array based on the source and target |
| 433 | * rates. The divider array must be sorted with smallest divider first. |
| 434 | * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, |
| 435 | * they are only settable as part of virtual_prcm set. |
| 436 | * |
| 437 | * Returns the rounded clock rate or returns 0xffffffff on error. |
| 438 | */ |
| 439 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, |
| 440 | u32 *new_div) |
| 441 | { |
| 442 | unsigned long test_rate; |
| 443 | const struct clksel *clks; |
| 444 | const struct clksel_rate *clkr; |
| 445 | u32 last_div = 0; |
| 446 | |
| 447 | printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n", |
| 448 | clk->name, target_rate); |
| 449 | |
| 450 | *new_div = 1; |
| 451 | |
| 452 | clks = omap2_get_clksel_by_parent(clk, clk->parent); |
| 453 | if (clks == NULL) |
| 454 | return ~0; |
| 455 | |
| 456 | for (clkr = clks->rates; clkr->div; clkr++) { |
| 457 | if (!(clkr->flags & cpu_mask)) |
| 458 | continue; |
| 459 | |
| 460 | /* Sanity check */ |
| 461 | if (clkr->div <= last_div) |
| 462 | printk(KERN_ERR "clock: clksel_rate table not sorted " |
| 463 | "for clock %s", clk->name); |
| 464 | |
| 465 | last_div = clkr->div; |
| 466 | |
| 467 | test_rate = clk->parent->rate / clkr->div; |
| 468 | |
| 469 | if (test_rate <= target_rate) |
| 470 | break; /* found it */ |
| 471 | } |
| 472 | |
| 473 | if (!clkr->div) { |
| 474 | printk(KERN_ERR "clock: Could not find divisor for target " |
| 475 | "rate %ld for clock %s parent %s\n", target_rate, |
| 476 | clk->name, clk->parent->name); |
| 477 | return ~0; |
| 478 | } |
| 479 | |
| 480 | *new_div = clkr->div; |
| 481 | |
| 482 | printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div, |
| 483 | (clk->parent->rate / clkr->div)); |
| 484 | |
| 485 | return (clk->parent->rate / clkr->div); |
| 486 | } |
| 487 | |
| 488 | /** |
| 489 | * omap2_clksel_round_rate - find rounded rate for the given clock and rate |
| 490 | * @clk: OMAP struct clk to use |
| 491 | * @target_rate: desired clock rate |
| 492 | * |
| 493 | * Compatibility wrapper for OMAP clock framework |
| 494 | * Finds best target rate based on the source clock and possible dividers. |
| 495 | * rates. The divider array must be sorted with smallest divider first. |
| 496 | * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, |
| 497 | * they are only settable as part of virtual_prcm set. |
| 498 | * |
| 499 | * Returns the rounded clock rate or returns 0xffffffff on error. |
| 500 | */ |
| 501 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) |
| 502 | { |
| 503 | u32 new_div; |
| 504 | |
| 505 | return omap2_clksel_round_rate_div(clk, target_rate, &new_div); |
| 506 | } |
| 507 | |
| 508 | |
| 509 | /* Given a clock and a rate apply a clock specific rounding function */ |
| 510 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate) |
| 511 | { |
Russell King | c0fc18c5 | 2008-09-05 15:10:27 +0100 | [diff] [blame] | 512 | if (clk->round_rate != NULL) |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 513 | return clk->round_rate(clk, rate); |
| 514 | |
| 515 | if (clk->flags & RATE_FIXED) |
| 516 | printk(KERN_ERR "clock: generic omap2_clk_round_rate called " |
| 517 | "on fixed-rate clock %s\n", clk->name); |
| 518 | |
| 519 | return clk->rate; |
| 520 | } |
| 521 | |
| 522 | /** |
| 523 | * omap2_clksel_to_divisor() - turn clksel field value into integer divider |
| 524 | * @clk: OMAP struct clk to use |
| 525 | * @field_val: register field value to find |
| 526 | * |
| 527 | * Given a struct clk of a rate-selectable clksel clock, and a register field |
| 528 | * value to search for, find the corresponding clock divisor. The register |
| 529 | * field value should be pre-masked and shifted down so the LSB is at bit 0 |
| 530 | * before calling. Returns 0 on error |
| 531 | */ |
| 532 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) |
| 533 | { |
| 534 | const struct clksel *clks; |
| 535 | const struct clksel_rate *clkr; |
| 536 | |
| 537 | clks = omap2_get_clksel_by_parent(clk, clk->parent); |
| 538 | if (clks == NULL) |
| 539 | return 0; |
| 540 | |
| 541 | for (clkr = clks->rates; clkr->div; clkr++) { |
| 542 | if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) |
| 543 | break; |
| 544 | } |
| 545 | |
| 546 | if (!clkr->div) { |
| 547 | printk(KERN_ERR "clock: Could not find fieldval %d for " |
| 548 | "clock %s parent %s\n", field_val, clk->name, |
| 549 | clk->parent->name); |
| 550 | return 0; |
| 551 | } |
| 552 | |
| 553 | return clkr->div; |
| 554 | } |
| 555 | |
| 556 | /** |
| 557 | * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value |
| 558 | * @clk: OMAP struct clk to use |
| 559 | * @div: integer divisor to search for |
| 560 | * |
| 561 | * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, |
| 562 | * find the corresponding register field value. The return register value is |
| 563 | * the value before left-shifting. Returns 0xffffffff on error |
| 564 | */ |
| 565 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) |
| 566 | { |
| 567 | const struct clksel *clks; |
| 568 | const struct clksel_rate *clkr; |
| 569 | |
| 570 | /* should never happen */ |
| 571 | WARN_ON(div == 0); |
| 572 | |
| 573 | clks = omap2_get_clksel_by_parent(clk, clk->parent); |
| 574 | if (clks == NULL) |
| 575 | return 0; |
| 576 | |
| 577 | for (clkr = clks->rates; clkr->div; clkr++) { |
| 578 | if ((clkr->flags & cpu_mask) && (clkr->div == div)) |
| 579 | break; |
| 580 | } |
| 581 | |
| 582 | if (!clkr->div) { |
| 583 | printk(KERN_ERR "clock: Could not find divisor %d for " |
| 584 | "clock %s parent %s\n", div, clk->name, |
| 585 | clk->parent->name); |
| 586 | return 0; |
| 587 | } |
| 588 | |
| 589 | return clkr->val; |
| 590 | } |
| 591 | |
| 592 | /** |
| 593 | * omap2_get_clksel - find clksel register addr & field mask for a clk |
| 594 | * @clk: struct clk to use |
| 595 | * @field_mask: ptr to u32 to store the register field mask |
| 596 | * |
| 597 | * Returns the address of the clksel register upon success or NULL on error. |
| 598 | */ |
| 599 | void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) |
| 600 | { |
Russell King | c0fc18c5 | 2008-09-05 15:10:27 +0100 | [diff] [blame] | 601 | if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL))) |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 602 | return NULL; |
| 603 | |
| 604 | *field_mask = clk->clksel_mask; |
| 605 | |
| 606 | return clk->clksel_reg; |
| 607 | } |
| 608 | |
| 609 | /** |
| 610 | * omap2_clksel_get_divisor - get current divider applied to parent clock. |
| 611 | * @clk: OMAP struct clk to use. |
| 612 | * |
| 613 | * Returns the integer divisor upon success or 0 on error. |
| 614 | */ |
| 615 | u32 omap2_clksel_get_divisor(struct clk *clk) |
| 616 | { |
| 617 | u32 field_mask, field_val; |
| 618 | void __iomem *div_addr; |
| 619 | |
| 620 | div_addr = omap2_get_clksel(clk, &field_mask); |
Russell King | c0fc18c5 | 2008-09-05 15:10:27 +0100 | [diff] [blame] | 621 | if (div_addr == NULL) |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 622 | return 0; |
| 623 | |
| 624 | field_val = __raw_readl(div_addr) & field_mask; |
| 625 | field_val >>= __ffs(field_mask); |
| 626 | |
| 627 | return omap2_clksel_to_divisor(clk, field_val); |
| 628 | } |
| 629 | |
| 630 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) |
| 631 | { |
| 632 | u32 field_mask, field_val, reg_val, validrate, new_div = 0; |
| 633 | void __iomem *div_addr; |
| 634 | |
| 635 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); |
| 636 | if (validrate != rate) |
| 637 | return -EINVAL; |
| 638 | |
| 639 | div_addr = omap2_get_clksel(clk, &field_mask); |
Russell King | c0fc18c5 | 2008-09-05 15:10:27 +0100 | [diff] [blame] | 640 | if (div_addr == NULL) |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 641 | return -EINVAL; |
| 642 | |
| 643 | field_val = omap2_divisor_to_clksel(clk, new_div); |
| 644 | if (field_val == ~0) |
| 645 | return -EINVAL; |
| 646 | |
| 647 | reg_val = __raw_readl(div_addr); |
| 648 | reg_val &= ~field_mask; |
| 649 | reg_val |= (field_val << __ffs(field_mask)); |
| 650 | __raw_writel(reg_val, div_addr); |
| 651 | wmb(); |
| 652 | |
| 653 | clk->rate = clk->parent->rate / new_div; |
| 654 | |
| 655 | if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { |
Tony Lindgren | c2d43e3 | 2008-07-03 12:24:38 +0300 | [diff] [blame] | 656 | prm_write_mod_reg(OMAP24XX_VALID_CONFIG, |
| 657 | OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 658 | wmb(); |
| 659 | } |
| 660 | |
| 661 | return 0; |
| 662 | } |
| 663 | |
| 664 | |
| 665 | /* Set the clock rate for a clock source */ |
| 666 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate) |
| 667 | { |
| 668 | int ret = -EINVAL; |
| 669 | |
| 670 | pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); |
| 671 | |
| 672 | /* CONFIG_PARTICIPANT clocks are changed only in sets via the |
| 673 | rate table mechanism, driven by mpu_speed */ |
| 674 | if (clk->flags & CONFIG_PARTICIPANT) |
| 675 | return -EINVAL; |
| 676 | |
| 677 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ |
Russell King | c0fc18c5 | 2008-09-05 15:10:27 +0100 | [diff] [blame] | 678 | if (clk->set_rate != NULL) |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 679 | ret = clk->set_rate(clk, rate); |
| 680 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 681 | return ret; |
| 682 | } |
| 683 | |
| 684 | /* |
| 685 | * Converts encoded control register address into a full address |
| 686 | * On error, *src_addr will be returned as 0. |
| 687 | */ |
| 688 | static u32 omap2_clksel_get_src_field(void __iomem **src_addr, |
| 689 | struct clk *src_clk, u32 *field_mask, |
| 690 | struct clk *clk, u32 *parent_div) |
| 691 | { |
| 692 | const struct clksel *clks; |
| 693 | const struct clksel_rate *clkr; |
| 694 | |
| 695 | *parent_div = 0; |
Russell King | c0fc18c5 | 2008-09-05 15:10:27 +0100 | [diff] [blame] | 696 | *src_addr = NULL; |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 697 | |
| 698 | clks = omap2_get_clksel_by_parent(clk, src_clk); |
| 699 | if (clks == NULL) |
| 700 | return 0; |
| 701 | |
| 702 | for (clkr = clks->rates; clkr->div; clkr++) { |
| 703 | if (clkr->flags & (cpu_mask | DEFAULT_RATE)) |
| 704 | break; /* Found the default rate for this platform */ |
| 705 | } |
| 706 | |
| 707 | if (!clkr->div) { |
| 708 | printk(KERN_ERR "clock: Could not find default rate for " |
| 709 | "clock %s parent %s\n", clk->name, |
| 710 | src_clk->parent->name); |
| 711 | return 0; |
| 712 | } |
| 713 | |
| 714 | /* Should never happen. Add a clksel mask to the struct clk. */ |
| 715 | WARN_ON(clk->clksel_mask == 0); |
| 716 | |
| 717 | *field_mask = clk->clksel_mask; |
| 718 | *src_addr = clk->clksel_reg; |
| 719 | *parent_div = clkr->div; |
| 720 | |
| 721 | return clkr->val; |
| 722 | } |
| 723 | |
| 724 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) |
| 725 | { |
| 726 | void __iomem *src_addr; |
| 727 | u32 field_val, field_mask, reg_val, parent_div; |
| 728 | |
| 729 | if (unlikely(clk->flags & CONFIG_PARTICIPANT)) |
| 730 | return -EINVAL; |
| 731 | |
| 732 | if (!clk->clksel) |
| 733 | return -EINVAL; |
| 734 | |
| 735 | field_val = omap2_clksel_get_src_field(&src_addr, new_parent, |
| 736 | &field_mask, clk, &parent_div); |
Russell King | c0fc18c5 | 2008-09-05 15:10:27 +0100 | [diff] [blame] | 737 | if (src_addr == NULL) |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 738 | return -EINVAL; |
| 739 | |
| 740 | if (clk->usecount > 0) |
| 741 | _omap2_clk_disable(clk); |
| 742 | |
| 743 | /* Set new source value (previous dividers if any in effect) */ |
| 744 | reg_val = __raw_readl(src_addr) & ~field_mask; |
| 745 | reg_val |= (field_val << __ffs(field_mask)); |
| 746 | __raw_writel(reg_val, src_addr); |
| 747 | wmb(); |
| 748 | |
| 749 | if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { |
| 750 | __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); |
| 751 | wmb(); |
| 752 | } |
| 753 | |
| 754 | if (clk->usecount > 0) |
| 755 | _omap2_clk_enable(clk); |
| 756 | |
| 757 | clk->parent = new_parent; |
| 758 | |
| 759 | /* CLKSEL clocks follow their parents' rates, divided by a divisor */ |
| 760 | clk->rate = new_parent->rate; |
| 761 | |
| 762 | if (parent_div > 0) |
| 763 | clk->rate /= parent_div; |
| 764 | |
| 765 | pr_debug("clock: set parent of %s to %s (new rate %ld)\n", |
| 766 | clk->name, clk->parent->name, clk->rate); |
| 767 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 768 | return 0; |
| 769 | } |
| 770 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 771 | /* DPLL rate rounding code */ |
| 772 | |
| 773 | /** |
| 774 | * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding |
| 775 | * @clk: struct clk * of the DPLL |
| 776 | * @tolerance: maximum rate error tolerance |
| 777 | * |
| 778 | * Set the maximum DPLL rate error tolerance for the rate rounding |
| 779 | * algorithm. The rate tolerance is an attempt to balance DPLL power |
| 780 | * saving (the least divider value "n") vs. rate fidelity (the least |
| 781 | * difference between the desired DPLL target rate and the rounded |
| 782 | * rate out of the algorithm). So, increasing the tolerance is likely |
| 783 | * to decrease DPLL power consumption and increase DPLL rate error. |
| 784 | * Returns -EINVAL if provided a null clock ptr or a clk that is not a |
| 785 | * DPLL; or 0 upon success. |
| 786 | */ |
| 787 | int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) |
| 788 | { |
| 789 | if (!clk || !clk->dpll_data) |
| 790 | return -EINVAL; |
| 791 | |
| 792 | clk->dpll_data->rate_tolerance = tolerance; |
| 793 | |
| 794 | return 0; |
| 795 | } |
| 796 | |
| 797 | static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n) |
| 798 | { |
| 799 | unsigned long long num; |
| 800 | |
| 801 | num = (unsigned long long)parent_rate * m; |
| 802 | do_div(num, n); |
| 803 | return num; |
| 804 | } |
| 805 | |
| 806 | /* |
| 807 | * _dpll_test_mult - test a DPLL multiplier value |
| 808 | * @m: pointer to the DPLL m (multiplier) value under test |
| 809 | * @n: current DPLL n (divider) value under test |
| 810 | * @new_rate: pointer to storage for the resulting rounded rate |
| 811 | * @target_rate: the desired DPLL rate |
| 812 | * @parent_rate: the DPLL's parent clock rate |
| 813 | * |
| 814 | * This code tests a DPLL multiplier value, ensuring that the |
| 815 | * resulting rate will not be higher than the target_rate, and that |
| 816 | * the multiplier value itself is valid for the DPLL. Initially, the |
| 817 | * integer pointed to by the m argument should be prescaled by |
| 818 | * multiplying by DPLL_SCALE_FACTOR. The code will replace this with |
| 819 | * a non-scaled m upon return. This non-scaled m will result in a |
| 820 | * new_rate as close as possible to target_rate (but not greater than |
| 821 | * target_rate) given the current (parent_rate, n, prescaled m) |
| 822 | * triple. Returns DPLL_MULT_UNDERFLOW in the event that the |
| 823 | * non-scaled m attempted to underflow, which can allow the calling |
| 824 | * function to bail out early; or 0 upon success. |
| 825 | */ |
| 826 | static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, |
| 827 | unsigned long target_rate, |
| 828 | unsigned long parent_rate) |
| 829 | { |
| 830 | int flags = 0, carry = 0; |
| 831 | |
| 832 | /* Unscale m and round if necessary */ |
| 833 | if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) |
| 834 | carry = 1; |
| 835 | *m = (*m / DPLL_SCALE_FACTOR) + carry; |
| 836 | |
| 837 | /* |
| 838 | * The new rate must be <= the target rate to avoid programming |
| 839 | * a rate that is impossible for the hardware to handle |
| 840 | */ |
| 841 | *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); |
| 842 | if (*new_rate > target_rate) { |
| 843 | (*m)--; |
| 844 | *new_rate = 0; |
| 845 | } |
| 846 | |
| 847 | /* Guard against m underflow */ |
| 848 | if (*m < DPLL_MIN_MULTIPLIER) { |
| 849 | *m = DPLL_MIN_MULTIPLIER; |
| 850 | *new_rate = 0; |
| 851 | flags = DPLL_MULT_UNDERFLOW; |
| 852 | } |
| 853 | |
| 854 | if (*new_rate == 0) |
| 855 | *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); |
| 856 | |
| 857 | return flags; |
| 858 | } |
| 859 | |
| 860 | /** |
| 861 | * omap2_dpll_round_rate - round a target rate for an OMAP DPLL |
| 862 | * @clk: struct clk * for a DPLL |
| 863 | * @target_rate: desired DPLL clock rate |
| 864 | * |
| 865 | * Given a DPLL, a desired target rate, and a rate tolerance, round |
| 866 | * the target rate to a possible, programmable rate for this DPLL. |
| 867 | * Rate tolerance is assumed to be set by the caller before this |
| 868 | * function is called. Attempts to select the minimum possible n |
| 869 | * within the tolerance to reduce power consumption. Stores the |
| 870 | * computed (m, n) in the DPLL's dpll_data structure so set_rate() |
| 871 | * will not need to call this (expensive) function again. Returns ~0 |
| 872 | * if the target rate cannot be rounded, either because the rate is |
| 873 | * too low or because the rate tolerance is set too tightly; or the |
| 874 | * rounded rate upon success. |
| 875 | */ |
| 876 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) |
| 877 | { |
| 878 | int m, n, r, e, scaled_max_m; |
| 879 | unsigned long scaled_rt_rp, new_rate; |
| 880 | int min_e = -1, min_e_m = -1, min_e_n = -1; |
| 881 | |
| 882 | if (!clk || !clk->dpll_data) |
| 883 | return ~0; |
| 884 | |
| 885 | pr_debug("clock: starting DPLL round_rate for clock %s, target rate " |
| 886 | "%ld\n", clk->name, target_rate); |
| 887 | |
| 888 | scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR); |
| 889 | scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR; |
| 890 | |
| 891 | clk->dpll_data->last_rounded_rate = 0; |
| 892 | |
| 893 | for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) { |
| 894 | |
| 895 | /* Compute the scaled DPLL multiplier, based on the divider */ |
| 896 | m = scaled_rt_rp * n; |
| 897 | |
| 898 | /* |
| 899 | * Since we're counting n down, a m overflow means we can |
| 900 | * can immediately skip to the next n |
| 901 | */ |
| 902 | if (m > scaled_max_m) |
| 903 | continue; |
| 904 | |
| 905 | r = _dpll_test_mult(&m, n, &new_rate, target_rate, |
| 906 | clk->parent->rate); |
| 907 | |
| 908 | e = target_rate - new_rate; |
| 909 | pr_debug("clock: n = %d: m = %d: rate error is %d " |
| 910 | "(new_rate = %ld)\n", n, m, e, new_rate); |
| 911 | |
| 912 | if (min_e == -1 || |
| 913 | min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) { |
| 914 | min_e = e; |
| 915 | min_e_m = m; |
| 916 | min_e_n = n; |
| 917 | |
| 918 | pr_debug("clock: found new least error %d\n", min_e); |
| 919 | } |
| 920 | |
| 921 | /* |
| 922 | * Since we're counting n down, a m underflow means we |
| 923 | * can bail out completely (since as n decreases in |
| 924 | * the next iteration, there's no way that m can |
| 925 | * increase beyond the current m) |
| 926 | */ |
| 927 | if (r & DPLL_MULT_UNDERFLOW) |
| 928 | break; |
| 929 | } |
| 930 | |
| 931 | if (min_e < 0) { |
| 932 | pr_debug("clock: error: target rate or tolerance too low\n"); |
| 933 | return ~0; |
| 934 | } |
| 935 | |
| 936 | clk->dpll_data->last_rounded_m = min_e_m; |
| 937 | clk->dpll_data->last_rounded_n = min_e_n; |
| 938 | clk->dpll_data->last_rounded_rate = |
| 939 | _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n); |
| 940 | |
| 941 | pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", |
| 942 | min_e, min_e_m, min_e_n); |
| 943 | pr_debug("clock: final rate: %ld (target rate: %ld)\n", |
| 944 | clk->dpll_data->last_rounded_rate, target_rate); |
| 945 | |
| 946 | return clk->dpll_data->last_rounded_rate; |
| 947 | } |
| 948 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 949 | /*------------------------------------------------------------------------- |
| 950 | * Omap2 clock reset and init functions |
| 951 | *-------------------------------------------------------------------------*/ |
| 952 | |
| 953 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
| 954 | void omap2_clk_disable_unused(struct clk *clk) |
| 955 | { |
| 956 | u32 regval32, v; |
| 957 | |
| 958 | v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; |
| 959 | |
| 960 | regval32 = __raw_readl(clk->enable_reg); |
| 961 | if ((regval32 & (1 << clk->enable_bit)) == v) |
| 962 | return; |
| 963 | |
| 964 | printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); |
| 965 | _omap2_clk_disable(clk); |
| 966 | } |
| 967 | #endif |