blob: 1f49bb02a6afe35678437d44b27ade3264a88893 [file] [log] [blame]
Haojian Zhuangf4e66982012-01-04 10:26:33 +08001/*
2 * linux/drivers/pinctrl/pinctrl-pxa3xx.c
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * publishhed by the Free Software Foundation.
7 *
8 * Copyright (C) 2011, Marvell Technology Group Ltd.
9 *
10 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
11 *
12 */
13
Thierry Reding9e0c1fb2013-01-21 11:09:14 +010014#include <linux/err.h>
Haojian Zhuangf4e66982012-01-04 10:26:33 +080015#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/io.h>
18#include <linux/platform_device.h>
19#include <linux/slab.h>
20#include "pinctrl-pxa3xx.h"
21
22static struct pinctrl_gpio_range pxa3xx_pinctrl_gpio_range = {
23 .name = "PXA3xx GPIO",
24 .id = 0,
25 .base = 0,
26 .pin_base = 0,
27};
28
Viresh Kumard1e90e92012-03-30 11:25:40 +053029static int pxa3xx_get_groups_count(struct pinctrl_dev *pctrldev)
Haojian Zhuangf4e66982012-01-04 10:26:33 +080030{
31 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
Viresh Kumard1e90e92012-03-30 11:25:40 +053032
33 return info->num_grps;
Haojian Zhuangf4e66982012-01-04 10:26:33 +080034}
35
36static const char *pxa3xx_get_group_name(struct pinctrl_dev *pctrldev,
37 unsigned selector)
38{
39 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
Viresh Kumard1e90e92012-03-30 11:25:40 +053040
Haojian Zhuangf4e66982012-01-04 10:26:33 +080041 return info->grps[selector].name;
42}
43
44static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev,
45 unsigned selector,
46 const unsigned **pins,
47 unsigned *num_pins)
48{
49 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
Viresh Kumard1e90e92012-03-30 11:25:40 +053050
Haojian Zhuangf4e66982012-01-04 10:26:33 +080051 *pins = info->grps[selector].pins;
52 *num_pins = info->grps[selector].npins;
53 return 0;
54}
55
56static struct pinctrl_ops pxa3xx_pctrl_ops = {
Viresh Kumard1e90e92012-03-30 11:25:40 +053057 .get_groups_count = pxa3xx_get_groups_count,
Haojian Zhuangf4e66982012-01-04 10:26:33 +080058 .get_group_name = pxa3xx_get_group_name,
59 .get_group_pins = pxa3xx_get_group_pins,
60};
61
Viresh Kumard1e90e92012-03-30 11:25:40 +053062static int pxa3xx_pmx_get_funcs_count(struct pinctrl_dev *pctrldev)
Haojian Zhuangf4e66982012-01-04 10:26:33 +080063{
64 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
Viresh Kumard1e90e92012-03-30 11:25:40 +053065
66 return info->num_funcs;
Haojian Zhuangf4e66982012-01-04 10:26:33 +080067}
68
69static const char *pxa3xx_pmx_get_func_name(struct pinctrl_dev *pctrldev,
70 unsigned func)
71{
72 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
73 return info->funcs[func].name;
74}
75
76static int pxa3xx_pmx_get_groups(struct pinctrl_dev *pctrldev, unsigned func,
77 const char * const **groups,
78 unsigned * const num_groups)
79{
80 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
81 *groups = info->funcs[func].groups;
82 *num_groups = info->funcs[func].num_groups;
83 return 0;
84}
85
86/* Return function number. If failure, return negative value. */
87static int match_mux(struct pxa3xx_mfp_pin *mfp, unsigned mux)
88{
89 int i;
90 for (i = 0; i < PXA3xx_MAX_MUX; i++) {
91 if (mfp->func[i] == mux)
92 break;
93 }
94 if (i >= PXA3xx_MAX_MUX)
95 return -EINVAL;
96 return i;
97}
98
99/* check whether current pin configuration is valid. Negative for failure */
100static int match_group_mux(struct pxa3xx_pin_group *grp,
101 struct pxa3xx_pinmux_info *info,
102 unsigned mux)
103{
104 int i, pin, ret = 0;
105 for (i = 0; i < grp->npins; i++) {
106 pin = grp->pins[i];
107 ret = match_mux(&info->mfp[pin], mux);
108 if (ret < 0) {
109 dev_err(info->dev, "Can't find mux %d on pin%d\n",
110 mux, pin);
111 break;
112 }
113 }
114 return ret;
115}
116
117static int pxa3xx_pmx_enable(struct pinctrl_dev *pctrldev, unsigned func,
118 unsigned group)
119{
120 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
121 struct pxa3xx_pin_group *pin_grp = &info->grps[group];
122 unsigned int data;
123 int i, mfpr, pin, pin_func;
124
125 if (!pin_grp->npins ||
126 (match_group_mux(pin_grp, info, pin_grp->mux) < 0)) {
127 dev_err(info->dev, "Failed to set the pin group: %d\n", group);
128 return -EINVAL;
129 }
130 for (i = 0; i < pin_grp->npins; i++) {
131 pin = pin_grp->pins[i];
132 pin_func = match_mux(&info->mfp[pin], pin_grp->mux);
133 mfpr = info->mfp[pin].mfpr;
134 data = readl_relaxed(info->virt_base + mfpr);
135 data &= ~MFPR_FUNC_MASK;
136 data |= pin_func;
137 writel_relaxed(data, info->virt_base + mfpr);
138 }
139 return 0;
140}
141
Haojian Zhuangf4e66982012-01-04 10:26:33 +0800142static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev,
143 struct pinctrl_gpio_range *range,
144 unsigned pin)
145{
146 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
147 unsigned int data;
148 int pin_func, mfpr;
149
150 pin_func = match_mux(&info->mfp[pin], PXA3xx_MUX_GPIO);
151 if (pin_func < 0) {
152 dev_err(info->dev, "No GPIO function on pin%d (%s)\n",
153 pin, info->pads[pin].name);
154 return -EINVAL;
155 }
156 mfpr = info->mfp[pin].mfpr;
157 /* write gpio function into mfpr register */
158 data = readl_relaxed(info->virt_base + mfpr) & ~MFPR_FUNC_MASK;
159 data |= pin_func;
160 writel_relaxed(data, info->virt_base + mfpr);
161 return 0;
162}
163
164static struct pinmux_ops pxa3xx_pmx_ops = {
Viresh Kumard1e90e92012-03-30 11:25:40 +0530165 .get_functions_count = pxa3xx_pmx_get_funcs_count,
Haojian Zhuangf4e66982012-01-04 10:26:33 +0800166 .get_function_name = pxa3xx_pmx_get_func_name,
167 .get_function_groups = pxa3xx_pmx_get_groups,
168 .enable = pxa3xx_pmx_enable,
Haojian Zhuangf4e66982012-01-04 10:26:33 +0800169 .gpio_request_enable = pxa3xx_pmx_request_gpio,
170};
171
172int pxa3xx_pinctrl_register(struct platform_device *pdev,
173 struct pxa3xx_pinmux_info *info)
174{
175 struct pinctrl_desc *desc;
176 struct resource *res;
Haojian Zhuangf4e66982012-01-04 10:26:33 +0800177
178 if (!info || !info->cputype)
179 return -EINVAL;
180 desc = info->desc;
181 desc->pins = info->pads;
182 desc->npins = info->num_pads;
183 desc->pctlops = &pxa3xx_pctrl_ops;
184 desc->pmxops = &pxa3xx_pmx_ops;
185 info->dev = &pdev->dev;
186 pxa3xx_pinctrl_gpio_range.npins = info->num_gpio;
187
188 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
189 if (!res)
190 return -ENOENT;
Thierry Reding9e0c1fb2013-01-21 11:09:14 +0100191 info->virt_base = devm_ioremap_resource(&pdev->dev, res);
192 if (IS_ERR(info->virt_base))
193 return PTR_ERR(info->virt_base);
Haojian Zhuangf4e66982012-01-04 10:26:33 +0800194 info->pctrl = pinctrl_register(desc, &pdev->dev, info);
195 if (!info->pctrl) {
196 dev_err(&pdev->dev, "failed to register PXA pinmux driver\n");
Axel Lin93877602012-11-12 14:45:50 +0800197 return -EINVAL;
Haojian Zhuangf4e66982012-01-04 10:26:33 +0800198 }
199 pinctrl_add_gpio_range(info->pctrl, &pxa3xx_pinctrl_gpio_range);
200 platform_set_drvdata(pdev, info);
201 return 0;
Haojian Zhuangf4e66982012-01-04 10:26:33 +0800202}
203
204int pxa3xx_pinctrl_unregister(struct platform_device *pdev)
205{
206 struct pxa3xx_pinmux_info *info = platform_get_drvdata(pdev);
207
208 pinctrl_unregister(info->pctrl);
Haojian Zhuangf4e66982012-01-04 10:26:33 +0800209 platform_set_drvdata(pdev, NULL);
210 return 0;
211}
212
213static int __init pxa3xx_pinctrl_init(void)
214{
215 pr_info("pxa3xx-pinctrl: PXA3xx pinctrl driver initializing\n");
216 return 0;
217}
218core_initcall_sync(pxa3xx_pinctrl_init);
219
220static void __exit pxa3xx_pinctrl_exit(void)
221{
222}
223module_exit(pxa3xx_pinctrl_exit);
224
225MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com>");
226MODULE_DESCRIPTION("PXA3xx pin control driver");
227MODULE_LICENSE("GPL v2");