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Maxime Ripard3b526342012-11-08 12:40:16 +01001/*
2 * Device Tree support for Allwinner A1X SoCs
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
Josh Cartwright5e516512012-11-29 19:37:30 -060013#include <linux/delay.h>
Maxime Ripard3b526342012-11-08 12:40:16 +010014#include <linux/kernel.h>
15#include <linux/init.h>
Maxime Ripard67bea882012-11-19 18:57:08 +010016#include <linux/of_address.h>
Maxime Ripard3b526342012-11-08 12:40:16 +010017#include <linux/of_irq.h>
18#include <linux/of_platform.h>
19#include <linux/io.h>
20#include <linux/sunxi_timer.h>
21
22#include <linux/irqchip/sunxi.h>
23
Maxime Ripard3b526342012-11-08 12:40:16 +010024#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26
27#include "sunxi.h"
28
Maxime Ripard67bea882012-11-19 18:57:08 +010029#define WATCHDOG_CTRL_REG 0x00
Maxime Ripardb60deca2013-02-04 23:32:39 +010030#define WATCHDOG_CTRL_RESTART (1 << 0)
Maxime Ripard67bea882012-11-19 18:57:08 +010031#define WATCHDOG_MODE_REG 0x04
Maxime Ripardb60deca2013-02-04 23:32:39 +010032#define WATCHDOG_MODE_ENABLE (1 << 0)
33#define WATCHDOG_MODE_RESET_ENABLE (1 << 1)
Maxime Ripard67bea882012-11-19 18:57:08 +010034
35static void __iomem *wdt_base;
36
37static void sunxi_setup_restart(void)
38{
39 struct device_node *np = of_find_compatible_node(NULL, NULL,
40 "allwinner,sunxi-wdt");
41 if (WARN(!np, "unable to setup watchdog restart"))
42 return;
43
44 wdt_base = of_iomap(np, 0);
45 WARN(!wdt_base, "failed to map watchdog base address");
46}
47
48static void sunxi_restart(char mode, const char *cmd)
49{
50 if (!wdt_base)
51 return;
52
53 /* Enable timer and set reset bit in the watchdog */
Maxime Ripardb60deca2013-02-04 23:32:39 +010054 writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
55 wdt_base + WATCHDOG_MODE_REG);
56
57 /*
58 * Restart the watchdog. The default (and lowest) interval
59 * value for the watchdog is 0.5s.
60 */
61 writel(WATCHDOG_CTRL_RESTART, wdt_base + WATCHDOG_CTRL_REG);
62
63 while (1) {
Maxime Ripard67bea882012-11-19 18:57:08 +010064 mdelay(5);
Maxime Ripardb60deca2013-02-04 23:32:39 +010065 writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
66 wdt_base + WATCHDOG_MODE_REG);
Maxime Ripard67bea882012-11-19 18:57:08 +010067 }
68}
69
Maxime Ripard3b526342012-11-08 12:40:16 +010070static struct map_desc sunxi_io_desc[] __initdata = {
71 {
72 .virtual = (unsigned long) SUNXI_REGS_VIRT_BASE,
73 .pfn = __phys_to_pfn(SUNXI_REGS_PHYS_BASE),
74 .length = SUNXI_REGS_SIZE,
75 .type = MT_DEVICE,
76 },
77};
78
79void __init sunxi_map_io(void)
80{
81 iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
82}
83
84static void __init sunxi_dt_init(void)
85{
Maxime Ripard67bea882012-11-19 18:57:08 +010086 sunxi_setup_restart();
87
Maxime Ripard3b526342012-11-08 12:40:16 +010088 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
89}
90
91static const char * const sunxi_board_dt_compat[] = {
Maxime Ripard43880f72012-12-18 15:17:12 +010092 "allwinner,sun4i-a10",
93 "allwinner,sun5i-a13",
Maxime Ripard3b526342012-11-08 12:40:16 +010094 NULL,
95};
96
97DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
98 .init_machine = sunxi_dt_init,
99 .map_io = sunxi_map_io,
100 .init_irq = sunxi_init_irq,
101 .handle_irq = sunxi_handle_irq,
Maxime Ripard67bea882012-11-19 18:57:08 +0100102 .restart = sunxi_restart,
Stephen Warren1c2584c2013-01-08 10:33:37 -0700103 .init_time = &sunxi_timer_init,
Maxime Ripard3b526342012-11-08 12:40:16 +0100104 .dt_compat = sunxi_board_dt_compat,
105MACHINE_END