Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * rocket_int.h --- internal header file for rocket.c |
| 3 | * |
| 4 | * Written by Theodore Ts'o, Copyright 1997. |
| 5 | * Copyright 1997 Comtrol Corporation. |
| 6 | * |
| 7 | */ |
| 8 | |
| 9 | /* |
| 10 | * Definition of the types in rcktpt_type |
| 11 | */ |
| 12 | #define ROCKET_TYPE_NORMAL 0 |
| 13 | #define ROCKET_TYPE_MODEM 1 |
| 14 | #define ROCKET_TYPE_MODEMII 2 |
| 15 | #define ROCKET_TYPE_MODEMIII 3 |
| 16 | #define ROCKET_TYPE_PC104 4 |
| 17 | |
Matthias Kaehlcke | 69f545e | 2007-05-08 00:32:00 -0700 | [diff] [blame] | 18 | #include <linux/mutex.h> |
| 19 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | #include <asm/io.h> |
| 21 | #include <asm/byteorder.h> |
| 22 | |
| 23 | typedef unsigned char Byte_t; |
| 24 | typedef unsigned int ByteIO_t; |
| 25 | |
| 26 | typedef unsigned int Word_t; |
| 27 | typedef unsigned int WordIO_t; |
| 28 | |
| 29 | typedef unsigned long DWord_t; |
| 30 | typedef unsigned int DWordIO_t; |
| 31 | |
| 32 | /* |
| 33 | * Note! Normally the Linux I/O macros already take care of |
| 34 | * byte-swapping the I/O instructions. However, all accesses using |
| 35 | * sOutDW aren't really 32-bit accesses, but should be handled in byte |
| 36 | * order. Hence the use of the cpu_to_le32() macro to byte-swap |
| 37 | * things to no-op the byte swapping done by the big-endian outl() |
| 38 | * instruction. |
| 39 | */ |
| 40 | |
| 41 | #ifdef ROCKET_DEBUG_IO |
| 42 | static inline void sOutB(unsigned short port, unsigned char value) |
| 43 | { |
| 44 | #ifdef ROCKET_DEBUG_IO |
Jiri Slaby | 68562b7 | 2008-02-07 00:16:33 -0800 | [diff] [blame] | 45 | printk(KERN_DEBUG "sOutB(%x, %x)...\n", port, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | #endif |
| 47 | outb_p(value, port); |
| 48 | } |
| 49 | |
| 50 | static inline void sOutW(unsigned short port, unsigned short value) |
| 51 | { |
| 52 | #ifdef ROCKET_DEBUG_IO |
Jiri Slaby | 68562b7 | 2008-02-07 00:16:33 -0800 | [diff] [blame] | 53 | printk(KERN_DEBUG "sOutW(%x, %x)...\n", port, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | #endif |
| 55 | outw_p(value, port); |
| 56 | } |
| 57 | |
| 58 | static inline void sOutDW(unsigned short port, unsigned long value) |
| 59 | { |
| 60 | #ifdef ROCKET_DEBUG_IO |
Jiri Slaby | 68562b7 | 2008-02-07 00:16:33 -0800 | [diff] [blame] | 61 | printk(KERN_DEBUG "sOutDW(%x, %lx)...\n", port, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | #endif |
| 63 | outl_p(cpu_to_le32(value), port); |
| 64 | } |
| 65 | |
| 66 | static inline unsigned char sInB(unsigned short port) |
| 67 | { |
| 68 | return inb_p(port); |
| 69 | } |
| 70 | |
| 71 | static inline unsigned short sInW(unsigned short port) |
| 72 | { |
| 73 | return inw_p(port); |
| 74 | } |
| 75 | |
| 76 | #else /* !ROCKET_DEBUG_IO */ |
| 77 | #define sOutB(a, b) outb_p(b, a) |
| 78 | #define sOutW(a, b) outw_p(b, a) |
| 79 | #define sOutDW(port, value) outl_p(cpu_to_le32(value), port) |
| 80 | #define sInB(a) (inb_p(a)) |
| 81 | #define sInW(a) (inw_p(a)) |
| 82 | #endif /* ROCKET_DEBUG_IO */ |
| 83 | |
| 84 | /* This is used to move arrays of bytes so byte swapping isn't appropriate. */ |
| 85 | #define sOutStrW(port, addr, count) if (count) outsw(port, addr, count) |
| 86 | #define sInStrW(port, addr, count) if (count) insw(port, addr, count) |
| 87 | |
| 88 | #define CTL_SIZE 8 |
| 89 | #define AIOP_CTL_SIZE 4 |
| 90 | #define CHAN_AIOP_SIZE 8 |
| 91 | #define MAX_PORTS_PER_AIOP 8 |
| 92 | #define MAX_AIOPS_PER_BOARD 4 |
| 93 | #define MAX_PORTS_PER_BOARD 32 |
| 94 | |
| 95 | /* Bus type ID */ |
| 96 | #define isISA 0 |
| 97 | #define isPCI 1 |
| 98 | #define isMC 2 |
| 99 | |
| 100 | /* Controller ID numbers */ |
| 101 | #define CTLID_NULL -1 /* no controller exists */ |
| 102 | #define CTLID_0001 0x0001 /* controller release 1 */ |
| 103 | |
| 104 | /* AIOP ID numbers, identifies AIOP type implementing channel */ |
| 105 | #define AIOPID_NULL -1 /* no AIOP or channel exists */ |
| 106 | #define AIOPID_0001 0x0001 /* AIOP release 1 */ |
| 107 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 108 | /************************************************************************ |
| 109 | Global Register Offsets - Direct Access - Fixed values |
| 110 | ************************************************************************/ |
| 111 | |
| 112 | #define _CMD_REG 0x38 /* Command Register 8 Write */ |
| 113 | #define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */ |
| 114 | #define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */ |
| 115 | #define _UNUSED 0x3B /* Unused 8 */ |
| 116 | #define _INDX_ADDR 0x3C /* Index Register Address 16 Write */ |
| 117 | #define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */ |
| 118 | |
| 119 | /************************************************************************ |
| 120 | Channel Register Offsets for 1st channel in AIOP - Direct Access |
| 121 | ************************************************************************/ |
| 122 | #define _TD0 0x00 /* Transmit Data 16 Write */ |
| 123 | #define _RD0 0x00 /* Receive Data 16 Read */ |
| 124 | #define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */ |
| 125 | #define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */ |
| 126 | #define _INT_ID0 0x30 /* Interrupt Identification 8 Read */ |
| 127 | |
| 128 | /************************************************************************ |
| 129 | Tx Control Register Offsets - Indexed - External - Fixed |
| 130 | ************************************************************************/ |
| 131 | #define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */ |
| 132 | #define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */ |
| 133 | #define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */ |
| 134 | #define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */ |
| 135 | #define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */ |
| 136 | #define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */ |
| 137 | |
| 138 | /************************************************************************ |
| 139 | Memory Controller Register Offsets - Indexed - External - Fixed |
| 140 | ************************************************************************/ |
| 141 | #define _RX_FIFO 0x000 /* Rx FIFO */ |
| 142 | #define _TX_FIFO 0x800 /* Tx FIFO */ |
| 143 | #define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */ |
| 144 | #define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */ |
| 145 | #define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */ |
| 146 | #define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */ |
| 147 | #define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */ |
| 148 | #define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */ |
| 149 | |
| 150 | #define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */ |
| 151 | #define TXFIFO_SIZE 255 /* size of Tx FIFO */ |
| 152 | #define RXFIFO_SIZE 1023 /* size of Rx FIFO */ |
| 153 | |
| 154 | /************************************************************************ |
| 155 | Tx Priority Buffer - Indexed - External - Fixed |
| 156 | ************************************************************************/ |
| 157 | #define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */ |
| 158 | #define TXP_SIZE 0x20 /* 32 bytes */ |
| 159 | |
| 160 | /************************************************************************ |
| 161 | Channel Register Offsets - Indexed - Internal - Fixed |
| 162 | ************************************************************************/ |
| 163 | |
| 164 | #define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */ |
| 165 | #define _RX_CTRL 0xFF2 /* Receive Control 8 Write */ |
| 166 | #define _BAUD 0xFF4 /* Baud Rate 16 Write */ |
| 167 | #define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */ |
| 168 | |
| 169 | #define STMBREAK 0x08 /* BREAK */ |
| 170 | #define STMFRAME 0x04 /* framing error */ |
| 171 | #define STMRCVROVR 0x02 /* receiver over run error */ |
| 172 | #define STMPARITY 0x01 /* parity error */ |
| 173 | #define STMERROR (STMBREAK | STMFRAME | STMPARITY) |
| 174 | #define STMBREAKH 0x800 /* BREAK */ |
| 175 | #define STMFRAMEH 0x400 /* framing error */ |
| 176 | #define STMRCVROVRH 0x200 /* receiver over run error */ |
| 177 | #define STMPARITYH 0x100 /* parity error */ |
| 178 | #define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH) |
| 179 | |
| 180 | #define CTS_ACT 0x20 /* CTS input asserted */ |
| 181 | #define DSR_ACT 0x10 /* DSR input asserted */ |
| 182 | #define CD_ACT 0x08 /* CD input asserted */ |
| 183 | #define TXFIFOMT 0x04 /* Tx FIFO is empty */ |
| 184 | #define TXSHRMT 0x02 /* Tx shift register is empty */ |
| 185 | #define RDA 0x01 /* Rx data available */ |
| 186 | #define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */ |
| 187 | |
| 188 | #define STATMODE 0x8000 /* status mode enable bit */ |
| 189 | #define RXFOVERFL 0x2000 /* receive FIFO overflow */ |
| 190 | #define RX2MATCH 0x1000 /* receive compare byte 2 match */ |
| 191 | #define RX1MATCH 0x0800 /* receive compare byte 1 match */ |
| 192 | #define RXBREAK 0x0400 /* received BREAK */ |
| 193 | #define RXFRAME 0x0200 /* received framing error */ |
| 194 | #define RXPARITY 0x0100 /* received parity error */ |
| 195 | #define STATERROR (RXBREAK | RXFRAME | RXPARITY) |
| 196 | |
| 197 | #define CTSFC_EN 0x80 /* CTS flow control enable bit */ |
| 198 | #define RTSTOG_EN 0x40 /* RTS toggle enable bit */ |
| 199 | #define TXINT_EN 0x10 /* transmit interrupt enable */ |
| 200 | #define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */ |
| 201 | #define PARITY_EN 0x04 /* enable parity (0 = no parity) */ |
| 202 | #define EVEN_PAR 0x02 /* even parity (0 = odd parity) */ |
| 203 | #define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */ |
| 204 | |
| 205 | #define SETBREAK 0x10 /* send break condition (must clear) */ |
| 206 | #define LOCALLOOP 0x08 /* local loopback set for test */ |
| 207 | #define SET_DTR 0x04 /* assert DTR */ |
| 208 | #define SET_RTS 0x02 /* assert RTS */ |
| 209 | #define TX_ENABLE 0x01 /* enable transmitter */ |
| 210 | |
| 211 | #define RTSFC_EN 0x40 /* RTS flow control enable */ |
| 212 | #define RXPROC_EN 0x20 /* receive processor enable */ |
| 213 | #define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */ |
| 214 | #define TRIG_1 0x08 /* trigger level 1 char */ |
| 215 | #define TRIG_1_2 0x10 /* trigger level 1/2 */ |
| 216 | #define TRIG_7_8 0x18 /* trigger level 7/8 */ |
| 217 | #define TRIG_MASK 0x18 /* trigger level mask */ |
| 218 | #define SRCINT_EN 0x04 /* special Rx condition interrupt enable */ |
| 219 | #define RXINT_EN 0x02 /* Rx interrupt enable */ |
| 220 | #define MCINT_EN 0x01 /* modem change interrupt enable */ |
| 221 | |
| 222 | #define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */ |
| 223 | #define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */ |
| 224 | #define SRC_INT 0x08 /* special receive condition interrupt */ |
| 225 | #define DELTA_CD 0x04 /* CD change interrupt */ |
| 226 | #define DELTA_CTS 0x02 /* CTS change interrupt */ |
| 227 | #define DELTA_DSR 0x01 /* DSR change interrupt */ |
| 228 | |
| 229 | #define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */ |
| 230 | #define IGN2_EN 0x08 /* ignore byte 2 enable */ |
| 231 | #define IGN1_EN 0x04 /* ignore byte 1 enable */ |
| 232 | #define COMP2_EN 0x02 /* compare byte 2 enable */ |
| 233 | #define COMP1_EN 0x01 /* compare byte 1 enable */ |
| 234 | |
| 235 | #define RESET_ALL 0x80 /* reset AIOP (all channels) */ |
| 236 | #define TXOVERIDE 0x40 /* Transmit software off override */ |
| 237 | #define RESETUART 0x20 /* reset channel's UART */ |
| 238 | #define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */ |
| 239 | #define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */ |
| 240 | |
| 241 | #define INTSTAT0 0x01 /* AIOP 0 interrupt status */ |
| 242 | #define INTSTAT1 0x02 /* AIOP 1 interrupt status */ |
| 243 | #define INTSTAT2 0x04 /* AIOP 2 interrupt status */ |
| 244 | #define INTSTAT3 0x08 /* AIOP 3 interrupt status */ |
| 245 | |
| 246 | #define INTR_EN 0x08 /* allow interrupts to host */ |
| 247 | #define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */ |
| 248 | |
| 249 | /************************************************************************** |
| 250 | MUDBAC remapped for PCI |
| 251 | **************************************************************************/ |
| 252 | |
| 253 | #define _CFG_INT_PCI 0x40 |
| 254 | #define _PCI_INT_FUNC 0x3A |
| 255 | |
| 256 | #define PCI_STROB 0x2000 /* bit 13 of int aiop register */ |
| 257 | #define INTR_EN_PCI 0x0010 /* allow interrupts to host */ |
| 258 | |
| 259 | /* |
| 260 | * Definitions for Universal PCI board registers |
| 261 | */ |
| 262 | #define _PCI_9030_INT_CTRL 0x4c /* Offsets from BAR1 */ |
| 263 | #define _PCI_9030_GPIO_CTRL 0x54 |
| 264 | #define PCI_INT_CTRL_AIOP 0x0001 |
| 265 | #define PCI_GPIO_CTRL_8PORT 0x4000 |
| 266 | #define _PCI_9030_RING_IND 0xc0 /* Offsets from BAR1 */ |
| 267 | |
| 268 | #define CHAN3_EN 0x08 /* enable AIOP 3 */ |
| 269 | #define CHAN2_EN 0x04 /* enable AIOP 2 */ |
| 270 | #define CHAN1_EN 0x02 /* enable AIOP 1 */ |
| 271 | #define CHAN0_EN 0x01 /* enable AIOP 0 */ |
| 272 | #define FREQ_DIS 0x00 |
| 273 | #define FREQ_274HZ 0x60 |
| 274 | #define FREQ_137HZ 0x50 |
| 275 | #define FREQ_69HZ 0x40 |
| 276 | #define FREQ_34HZ 0x30 |
| 277 | #define FREQ_17HZ 0x20 |
| 278 | #define FREQ_9HZ 0x10 |
| 279 | #define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */ |
| 280 | |
| 281 | #define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */ |
| 282 | |
| 283 | #define RDATASIZE 72 |
| 284 | #define RREGDATASIZE 52 |
| 285 | |
| 286 | /* |
| 287 | * AIOP interrupt bits for ISA/PCI boards and UPCI boards. |
| 288 | */ |
| 289 | #define AIOP_INTR_BIT_0 0x0001 |
| 290 | #define AIOP_INTR_BIT_1 0x0002 |
| 291 | #define AIOP_INTR_BIT_2 0x0004 |
| 292 | #define AIOP_INTR_BIT_3 0x0008 |
| 293 | |
| 294 | #define AIOP_INTR_BITS ( \ |
| 295 | AIOP_INTR_BIT_0 \ |
| 296 | | AIOP_INTR_BIT_1 \ |
| 297 | | AIOP_INTR_BIT_2 \ |
| 298 | | AIOP_INTR_BIT_3) |
| 299 | |
| 300 | #define UPCI_AIOP_INTR_BIT_0 0x0004 |
| 301 | #define UPCI_AIOP_INTR_BIT_1 0x0020 |
| 302 | #define UPCI_AIOP_INTR_BIT_2 0x0100 |
| 303 | #define UPCI_AIOP_INTR_BIT_3 0x0800 |
| 304 | |
| 305 | #define UPCI_AIOP_INTR_BITS ( \ |
| 306 | UPCI_AIOP_INTR_BIT_0 \ |
| 307 | | UPCI_AIOP_INTR_BIT_1 \ |
| 308 | | UPCI_AIOP_INTR_BIT_2 \ |
| 309 | | UPCI_AIOP_INTR_BIT_3) |
| 310 | |
| 311 | /* Controller level information structure */ |
| 312 | typedef struct { |
| 313 | int CtlID; |
| 314 | int CtlNum; |
| 315 | int BusType; |
| 316 | int boardType; |
| 317 | int isUPCI; |
| 318 | WordIO_t PCIIO; |
| 319 | WordIO_t PCIIO2; |
| 320 | ByteIO_t MBaseIO; |
| 321 | ByteIO_t MReg1IO; |
| 322 | ByteIO_t MReg2IO; |
| 323 | ByteIO_t MReg3IO; |
| 324 | Byte_t MReg2; |
| 325 | Byte_t MReg3; |
| 326 | int NumAiop; |
| 327 | int AltChanRingIndicator; |
| 328 | ByteIO_t UPCIRingInd; |
| 329 | WordIO_t AiopIO[AIOP_CTL_SIZE]; |
| 330 | ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE]; |
| 331 | int AiopID[AIOP_CTL_SIZE]; |
| 332 | int AiopNumChan[AIOP_CTL_SIZE]; |
| 333 | Word_t *AiopIntrBits; |
| 334 | } CONTROLLER_T; |
| 335 | |
| 336 | typedef CONTROLLER_T CONTROLLER_t; |
| 337 | |
| 338 | /* Channel level information structure */ |
| 339 | typedef struct { |
| 340 | CONTROLLER_T *CtlP; |
| 341 | int AiopNum; |
| 342 | int ChanID; |
| 343 | int ChanNum; |
| 344 | int rtsToggle; |
| 345 | |
| 346 | ByteIO_t Cmd; |
| 347 | ByteIO_t IntChan; |
| 348 | ByteIO_t IntMask; |
| 349 | DWordIO_t IndexAddr; |
| 350 | WordIO_t IndexData; |
| 351 | |
| 352 | WordIO_t TxRxData; |
| 353 | WordIO_t ChanStat; |
| 354 | WordIO_t TxRxCount; |
| 355 | ByteIO_t IntID; |
| 356 | |
| 357 | Word_t TxFIFO; |
| 358 | Word_t TxFIFOPtrs; |
| 359 | Word_t RxFIFO; |
| 360 | Word_t RxFIFOPtrs; |
| 361 | Word_t TxPrioCnt; |
| 362 | Word_t TxPrioPtr; |
| 363 | Word_t TxPrioBuf; |
| 364 | |
| 365 | Byte_t R[RREGDATASIZE]; |
| 366 | |
| 367 | Byte_t BaudDiv[4]; |
| 368 | Byte_t TxControl[4]; |
| 369 | Byte_t RxControl[4]; |
| 370 | Byte_t TxEnables[4]; |
| 371 | Byte_t TxCompare[4]; |
| 372 | Byte_t TxReplace1[4]; |
| 373 | Byte_t TxReplace2[4]; |
| 374 | } CHANNEL_T; |
| 375 | |
| 376 | typedef CHANNEL_T CHANNEL_t; |
| 377 | typedef CHANNEL_T *CHANPTR_T; |
| 378 | |
| 379 | #define InterfaceModeRS232 0x00 |
| 380 | #define InterfaceModeRS422 0x08 |
| 381 | #define InterfaceModeRS485 0x10 |
| 382 | #define InterfaceModeRS232T 0x18 |
| 383 | |
| 384 | /*************************************************************************** |
| 385 | Function: sClrBreak |
| 386 | Purpose: Stop sending a transmit BREAK signal |
| 387 | Call: sClrBreak(ChP) |
| 388 | CHANNEL_T *ChP; Ptr to channel structure |
| 389 | */ |
| 390 | #define sClrBreak(ChP) \ |
| 391 | do { \ |
| 392 | (ChP)->TxControl[3] &= ~SETBREAK; \ |
| 393 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 394 | } while (0) |
| 395 | |
| 396 | /*************************************************************************** |
| 397 | Function: sClrDTR |
| 398 | Purpose: Clr the DTR output |
| 399 | Call: sClrDTR(ChP) |
| 400 | CHANNEL_T *ChP; Ptr to channel structure |
| 401 | */ |
| 402 | #define sClrDTR(ChP) \ |
| 403 | do { \ |
| 404 | (ChP)->TxControl[3] &= ~SET_DTR; \ |
| 405 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 406 | } while (0) |
| 407 | |
| 408 | /*************************************************************************** |
| 409 | Function: sClrRTS |
| 410 | Purpose: Clr the RTS output |
| 411 | Call: sClrRTS(ChP) |
| 412 | CHANNEL_T *ChP; Ptr to channel structure |
| 413 | */ |
| 414 | #define sClrRTS(ChP) \ |
| 415 | do { \ |
| 416 | if ((ChP)->rtsToggle) break; \ |
| 417 | (ChP)->TxControl[3] &= ~SET_RTS; \ |
| 418 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 419 | } while (0) |
| 420 | |
| 421 | /*************************************************************************** |
| 422 | Function: sClrTxXOFF |
| 423 | Purpose: Clear any existing transmit software flow control off condition |
| 424 | Call: sClrTxXOFF(ChP) |
| 425 | CHANNEL_T *ChP; Ptr to channel structure |
| 426 | */ |
| 427 | #define sClrTxXOFF(ChP) \ |
| 428 | do { \ |
| 429 | sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \ |
| 430 | sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \ |
| 431 | } while (0) |
| 432 | |
| 433 | /*************************************************************************** |
| 434 | Function: sCtlNumToCtlPtr |
| 435 | Purpose: Convert a controller number to controller structure pointer |
| 436 | Call: sCtlNumToCtlPtr(CtlNum) |
| 437 | int CtlNum; Controller number |
| 438 | Return: CONTROLLER_T *: Ptr to controller structure |
| 439 | */ |
| 440 | #define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM] |
| 441 | |
| 442 | /*************************************************************************** |
| 443 | Function: sControllerEOI |
| 444 | Purpose: Strobe the MUDBAC's End Of Interrupt bit. |
| 445 | Call: sControllerEOI(CtlP) |
| 446 | CONTROLLER_T *CtlP; Ptr to controller structure |
| 447 | */ |
| 448 | #define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB) |
| 449 | |
| 450 | /*************************************************************************** |
| 451 | Function: sPCIControllerEOI |
| 452 | Purpose: Strobe the PCI End Of Interrupt bit. |
| 453 | For the UPCI boards, toggle the AIOP interrupt enable bit |
| 454 | (this was taken from the Windows driver). |
| 455 | Call: sPCIControllerEOI(CtlP) |
| 456 | CONTROLLER_T *CtlP; Ptr to controller structure |
| 457 | */ |
| 458 | #define sPCIControllerEOI(CTLP) \ |
| 459 | do { \ |
| 460 | if ((CTLP)->isUPCI) { \ |
| 461 | Word_t w = sInW((CTLP)->PCIIO); \ |
| 462 | sOutW((CTLP)->PCIIO, (w ^ PCI_INT_CTRL_AIOP)); \ |
| 463 | sOutW((CTLP)->PCIIO, w); \ |
| 464 | } \ |
| 465 | else { \ |
| 466 | sOutW((CTLP)->PCIIO, PCI_STROB); \ |
| 467 | } \ |
| 468 | } while (0) |
| 469 | |
| 470 | /*************************************************************************** |
| 471 | Function: sDisAiop |
| 472 | Purpose: Disable I/O access to an AIOP |
| 473 | Call: sDisAiop(CltP) |
| 474 | CONTROLLER_T *CtlP; Ptr to controller structure |
| 475 | int AiopNum; Number of AIOP on controller |
| 476 | */ |
| 477 | #define sDisAiop(CTLP,AIOPNUM) \ |
| 478 | do { \ |
| 479 | (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \ |
| 480 | sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \ |
| 481 | } while (0) |
| 482 | |
| 483 | /*************************************************************************** |
| 484 | Function: sDisCTSFlowCtl |
| 485 | Purpose: Disable output flow control using CTS |
| 486 | Call: sDisCTSFlowCtl(ChP) |
| 487 | CHANNEL_T *ChP; Ptr to channel structure |
| 488 | */ |
| 489 | #define sDisCTSFlowCtl(ChP) \ |
| 490 | do { \ |
| 491 | (ChP)->TxControl[2] &= ~CTSFC_EN; \ |
| 492 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 493 | } while (0) |
| 494 | |
| 495 | /*************************************************************************** |
| 496 | Function: sDisIXANY |
| 497 | Purpose: Disable IXANY Software Flow Control |
| 498 | Call: sDisIXANY(ChP) |
| 499 | CHANNEL_T *ChP; Ptr to channel structure |
| 500 | */ |
| 501 | #define sDisIXANY(ChP) \ |
| 502 | do { \ |
| 503 | (ChP)->R[0x0e] = 0x86; \ |
| 504 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \ |
| 505 | } while (0) |
| 506 | |
| 507 | /*************************************************************************** |
| 508 | Function: DisParity |
| 509 | Purpose: Disable parity |
| 510 | Call: sDisParity(ChP) |
| 511 | CHANNEL_T *ChP; Ptr to channel structure |
| 512 | Comments: Function sSetParity() can be used in place of functions sEnParity(), |
| 513 | sDisParity(), sSetOddParity(), and sSetEvenParity(). |
| 514 | */ |
| 515 | #define sDisParity(ChP) \ |
| 516 | do { \ |
| 517 | (ChP)->TxControl[2] &= ~PARITY_EN; \ |
| 518 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 519 | } while (0) |
| 520 | |
| 521 | /*************************************************************************** |
| 522 | Function: sDisRTSToggle |
| 523 | Purpose: Disable RTS toggle |
| 524 | Call: sDisRTSToggle(ChP) |
| 525 | CHANNEL_T *ChP; Ptr to channel structure |
| 526 | */ |
| 527 | #define sDisRTSToggle(ChP) \ |
| 528 | do { \ |
| 529 | (ChP)->TxControl[2] &= ~RTSTOG_EN; \ |
| 530 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 531 | (ChP)->rtsToggle = 0; \ |
| 532 | } while (0) |
| 533 | |
| 534 | /*************************************************************************** |
| 535 | Function: sDisRxFIFO |
| 536 | Purpose: Disable Rx FIFO |
| 537 | Call: sDisRxFIFO(ChP) |
| 538 | CHANNEL_T *ChP; Ptr to channel structure |
| 539 | */ |
| 540 | #define sDisRxFIFO(ChP) \ |
| 541 | do { \ |
| 542 | (ChP)->R[0x32] = 0x0a; \ |
| 543 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ |
| 544 | } while (0) |
| 545 | |
| 546 | /*************************************************************************** |
| 547 | Function: sDisRxStatusMode |
| 548 | Purpose: Disable the Rx status mode |
| 549 | Call: sDisRxStatusMode(ChP) |
| 550 | CHANNEL_T *ChP; Ptr to channel structure |
| 551 | Comments: This takes the channel out of the receive status mode. All |
| 552 | subsequent reads of receive data using sReadRxWord() will return |
| 553 | two data bytes. |
| 554 | */ |
| 555 | #define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0) |
| 556 | |
| 557 | /*************************************************************************** |
| 558 | Function: sDisTransmit |
| 559 | Purpose: Disable transmit |
| 560 | Call: sDisTransmit(ChP) |
| 561 | CHANNEL_T *ChP; Ptr to channel structure |
| 562 | This disables movement of Tx data from the Tx FIFO into the 1 byte |
| 563 | Tx buffer. Therefore there could be up to a 2 byte latency |
| 564 | between the time sDisTransmit() is called and the transmit buffer |
| 565 | and transmit shift register going completely empty. |
| 566 | */ |
| 567 | #define sDisTransmit(ChP) \ |
| 568 | do { \ |
| 569 | (ChP)->TxControl[3] &= ~TX_ENABLE; \ |
| 570 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 571 | } while (0) |
| 572 | |
| 573 | /*************************************************************************** |
| 574 | Function: sDisTxSoftFlowCtl |
| 575 | Purpose: Disable Tx Software Flow Control |
| 576 | Call: sDisTxSoftFlowCtl(ChP) |
| 577 | CHANNEL_T *ChP; Ptr to channel structure |
| 578 | */ |
| 579 | #define sDisTxSoftFlowCtl(ChP) \ |
| 580 | do { \ |
| 581 | (ChP)->R[0x06] = 0x8a; \ |
| 582 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ |
| 583 | } while (0) |
| 584 | |
| 585 | /*************************************************************************** |
| 586 | Function: sEnAiop |
| 587 | Purpose: Enable I/O access to an AIOP |
| 588 | Call: sEnAiop(CltP) |
| 589 | CONTROLLER_T *CtlP; Ptr to controller structure |
| 590 | int AiopNum; Number of AIOP on controller |
| 591 | */ |
| 592 | #define sEnAiop(CTLP,AIOPNUM) \ |
| 593 | do { \ |
| 594 | (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \ |
| 595 | sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \ |
| 596 | } while (0) |
| 597 | |
| 598 | /*************************************************************************** |
| 599 | Function: sEnCTSFlowCtl |
| 600 | Purpose: Enable output flow control using CTS |
| 601 | Call: sEnCTSFlowCtl(ChP) |
| 602 | CHANNEL_T *ChP; Ptr to channel structure |
| 603 | */ |
| 604 | #define sEnCTSFlowCtl(ChP) \ |
| 605 | do { \ |
| 606 | (ChP)->TxControl[2] |= CTSFC_EN; \ |
| 607 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 608 | } while (0) |
| 609 | |
| 610 | /*************************************************************************** |
| 611 | Function: sEnIXANY |
| 612 | Purpose: Enable IXANY Software Flow Control |
| 613 | Call: sEnIXANY(ChP) |
| 614 | CHANNEL_T *ChP; Ptr to channel structure |
| 615 | */ |
| 616 | #define sEnIXANY(ChP) \ |
| 617 | do { \ |
| 618 | (ChP)->R[0x0e] = 0x21; \ |
| 619 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \ |
| 620 | } while (0) |
| 621 | |
| 622 | /*************************************************************************** |
| 623 | Function: EnParity |
| 624 | Purpose: Enable parity |
| 625 | Call: sEnParity(ChP) |
| 626 | CHANNEL_T *ChP; Ptr to channel structure |
| 627 | Comments: Function sSetParity() can be used in place of functions sEnParity(), |
| 628 | sDisParity(), sSetOddParity(), and sSetEvenParity(). |
| 629 | |
| 630 | Warnings: Before enabling parity odd or even parity should be chosen using |
| 631 | functions sSetOddParity() or sSetEvenParity(). |
| 632 | */ |
| 633 | #define sEnParity(ChP) \ |
| 634 | do { \ |
| 635 | (ChP)->TxControl[2] |= PARITY_EN; \ |
| 636 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 637 | } while (0) |
| 638 | |
| 639 | /*************************************************************************** |
| 640 | Function: sEnRTSToggle |
| 641 | Purpose: Enable RTS toggle |
| 642 | Call: sEnRTSToggle(ChP) |
| 643 | CHANNEL_T *ChP; Ptr to channel structure |
| 644 | Comments: This function will disable RTS flow control and clear the RTS |
| 645 | line to allow operation of RTS toggle. |
| 646 | */ |
| 647 | #define sEnRTSToggle(ChP) \ |
| 648 | do { \ |
| 649 | (ChP)->RxControl[2] &= ~RTSFC_EN; \ |
| 650 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ |
| 651 | (ChP)->TxControl[2] |= RTSTOG_EN; \ |
| 652 | (ChP)->TxControl[3] &= ~SET_RTS; \ |
| 653 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 654 | (ChP)->rtsToggle = 1; \ |
| 655 | } while (0) |
| 656 | |
| 657 | /*************************************************************************** |
| 658 | Function: sEnRxFIFO |
| 659 | Purpose: Enable Rx FIFO |
| 660 | Call: sEnRxFIFO(ChP) |
| 661 | CHANNEL_T *ChP; Ptr to channel structure |
| 662 | */ |
| 663 | #define sEnRxFIFO(ChP) \ |
| 664 | do { \ |
| 665 | (ChP)->R[0x32] = 0x08; \ |
| 666 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ |
| 667 | } while (0) |
| 668 | |
| 669 | /*************************************************************************** |
| 670 | Function: sEnRxProcessor |
| 671 | Purpose: Enable the receive processor |
| 672 | Call: sEnRxProcessor(ChP) |
| 673 | CHANNEL_T *ChP; Ptr to channel structure |
| 674 | Comments: This function is used to start the receive processor. When |
| 675 | the channel is in the reset state the receive processor is not |
| 676 | running. This is done to prevent the receive processor from |
| 677 | executing invalid microcode instructions prior to the |
| 678 | downloading of the microcode. |
| 679 | |
| 680 | Warnings: This function must be called after valid microcode has been |
| 681 | downloaded to the AIOP, and it must not be called before the |
| 682 | microcode has been downloaded. |
| 683 | */ |
| 684 | #define sEnRxProcessor(ChP) \ |
| 685 | do { \ |
| 686 | (ChP)->RxControl[2] |= RXPROC_EN; \ |
| 687 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ |
| 688 | } while (0) |
| 689 | |
| 690 | /*************************************************************************** |
| 691 | Function: sEnRxStatusMode |
| 692 | Purpose: Enable the Rx status mode |
| 693 | Call: sEnRxStatusMode(ChP) |
| 694 | CHANNEL_T *ChP; Ptr to channel structure |
| 695 | Comments: This places the channel in the receive status mode. All subsequent |
| 696 | reads of receive data using sReadRxWord() will return a data byte |
| 697 | in the low word and a status byte in the high word. |
| 698 | |
| 699 | */ |
| 700 | #define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE) |
| 701 | |
| 702 | /*************************************************************************** |
| 703 | Function: sEnTransmit |
| 704 | Purpose: Enable transmit |
| 705 | Call: sEnTransmit(ChP) |
| 706 | CHANNEL_T *ChP; Ptr to channel structure |
| 707 | */ |
| 708 | #define sEnTransmit(ChP) \ |
| 709 | do { \ |
| 710 | (ChP)->TxControl[3] |= TX_ENABLE; \ |
| 711 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 712 | } while (0) |
| 713 | |
| 714 | /*************************************************************************** |
| 715 | Function: sEnTxSoftFlowCtl |
| 716 | Purpose: Enable Tx Software Flow Control |
| 717 | Call: sEnTxSoftFlowCtl(ChP) |
| 718 | CHANNEL_T *ChP; Ptr to channel structure |
| 719 | */ |
| 720 | #define sEnTxSoftFlowCtl(ChP) \ |
| 721 | do { \ |
| 722 | (ChP)->R[0x06] = 0xc5; \ |
| 723 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ |
| 724 | } while (0) |
| 725 | |
| 726 | /*************************************************************************** |
| 727 | Function: sGetAiopIntStatus |
| 728 | Purpose: Get the AIOP interrupt status |
| 729 | Call: sGetAiopIntStatus(CtlP,AiopNum) |
| 730 | CONTROLLER_T *CtlP; Ptr to controller structure |
| 731 | int AiopNum; AIOP number |
| 732 | Return: Byte_t: The AIOP interrupt status. Bits 0 through 7 |
| 733 | represent channels 0 through 7 respectively. If a |
| 734 | bit is set that channel is interrupting. |
| 735 | */ |
| 736 | #define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM]) |
| 737 | |
| 738 | /*************************************************************************** |
| 739 | Function: sGetAiopNumChan |
| 740 | Purpose: Get the number of channels supported by an AIOP |
| 741 | Call: sGetAiopNumChan(CtlP,AiopNum) |
| 742 | CONTROLLER_T *CtlP; Ptr to controller structure |
| 743 | int AiopNum; AIOP number |
| 744 | Return: int: The number of channels supported by the AIOP |
| 745 | */ |
| 746 | #define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM] |
| 747 | |
| 748 | /*************************************************************************** |
| 749 | Function: sGetChanIntID |
| 750 | Purpose: Get a channel's interrupt identification byte |
| 751 | Call: sGetChanIntID(ChP) |
| 752 | CHANNEL_T *ChP; Ptr to channel structure |
| 753 | Return: Byte_t: The channel interrupt ID. Can be any |
| 754 | combination of the following flags: |
| 755 | RXF_TRIG: Rx FIFO trigger level interrupt |
| 756 | TXFIFO_MT: Tx FIFO empty interrupt |
| 757 | SRC_INT: Special receive condition interrupt |
| 758 | DELTA_CD: CD change interrupt |
| 759 | DELTA_CTS: CTS change interrupt |
| 760 | DELTA_DSR: DSR change interrupt |
| 761 | */ |
| 762 | #define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR)) |
| 763 | |
| 764 | /*************************************************************************** |
| 765 | Function: sGetChanNum |
| 766 | Purpose: Get the number of a channel within an AIOP |
| 767 | Call: sGetChanNum(ChP) |
| 768 | CHANNEL_T *ChP; Ptr to channel structure |
| 769 | Return: int: Channel number within AIOP, or NULLCHAN if channel does |
| 770 | not exist. |
| 771 | */ |
| 772 | #define sGetChanNum(ChP) (ChP)->ChanNum |
| 773 | |
| 774 | /*************************************************************************** |
| 775 | Function: sGetChanStatus |
| 776 | Purpose: Get the channel status |
| 777 | Call: sGetChanStatus(ChP) |
| 778 | CHANNEL_T *ChP; Ptr to channel structure |
| 779 | Return: Word_t: The channel status. Can be any combination of |
| 780 | the following flags: |
| 781 | LOW BYTE FLAGS |
| 782 | CTS_ACT: CTS input asserted |
| 783 | DSR_ACT: DSR input asserted |
| 784 | CD_ACT: CD input asserted |
| 785 | TXFIFOMT: Tx FIFO is empty |
| 786 | TXSHRMT: Tx shift register is empty |
| 787 | RDA: Rx data available |
| 788 | |
| 789 | HIGH BYTE FLAGS |
| 790 | STATMODE: status mode enable bit |
| 791 | RXFOVERFL: receive FIFO overflow |
| 792 | RX2MATCH: receive compare byte 2 match |
| 793 | RX1MATCH: receive compare byte 1 match |
| 794 | RXBREAK: received BREAK |
| 795 | RXFRAME: received framing error |
| 796 | RXPARITY: received parity error |
| 797 | Warnings: This function will clear the high byte flags in the Channel |
| 798 | Status Register. |
| 799 | */ |
| 800 | #define sGetChanStatus(ChP) sInW((ChP)->ChanStat) |
| 801 | |
| 802 | /*************************************************************************** |
| 803 | Function: sGetChanStatusLo |
| 804 | Purpose: Get the low byte only of the channel status |
| 805 | Call: sGetChanStatusLo(ChP) |
| 806 | CHANNEL_T *ChP; Ptr to channel structure |
| 807 | Return: Byte_t: The channel status low byte. Can be any combination |
| 808 | of the following flags: |
| 809 | CTS_ACT: CTS input asserted |
| 810 | DSR_ACT: DSR input asserted |
| 811 | CD_ACT: CD input asserted |
| 812 | TXFIFOMT: Tx FIFO is empty |
| 813 | TXSHRMT: Tx shift register is empty |
| 814 | RDA: Rx data available |
| 815 | */ |
| 816 | #define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat) |
| 817 | |
| 818 | /********************************************************************** |
| 819 | * Get RI status of channel |
| 820 | * Defined as a function in rocket.c -aes |
| 821 | */ |
| 822 | #if 0 |
| 823 | #define sGetChanRI(ChP) ((ChP)->CtlP->AltChanRingIndicator ? \ |
| 824 | (sInB((ByteIO_t)((ChP)->ChanStat+8)) & DSR_ACT) : \ |
| 825 | (((ChP)->CtlP->boardType == ROCKET_TYPE_PC104) ? \ |
| 826 | (!(sInB((ChP)->CtlP->AiopIO[3]) & sBitMapSetTbl[(ChP)->ChanNum])) : \ |
| 827 | 0)) |
| 828 | #endif |
| 829 | |
| 830 | /*************************************************************************** |
| 831 | Function: sGetControllerIntStatus |
| 832 | Purpose: Get the controller interrupt status |
| 833 | Call: sGetControllerIntStatus(CtlP) |
| 834 | CONTROLLER_T *CtlP; Ptr to controller structure |
| 835 | Return: Byte_t: The controller interrupt status in the lower 4 |
| 836 | bits. Bits 0 through 3 represent AIOP's 0 |
| 837 | through 3 respectively. If a bit is set that |
| 838 | AIOP is interrupting. Bits 4 through 7 will |
| 839 | always be cleared. |
| 840 | */ |
| 841 | #define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f) |
| 842 | |
| 843 | /*************************************************************************** |
| 844 | Function: sPCIGetControllerIntStatus |
| 845 | Purpose: Get the controller interrupt status |
| 846 | Call: sPCIGetControllerIntStatus(CtlP) |
| 847 | CONTROLLER_T *CtlP; Ptr to controller structure |
| 848 | Return: unsigned char: The controller interrupt status in the lower 4 |
| 849 | bits and bit 4. Bits 0 through 3 represent AIOP's 0 |
| 850 | through 3 respectively. Bit 4 is set if the int |
| 851 | was generated from periodic. If a bit is set the |
| 852 | AIOP is interrupting. |
| 853 | */ |
| 854 | #define sPCIGetControllerIntStatus(CTLP) \ |
| 855 | ((CTLP)->isUPCI ? \ |
| 856 | (sInW((CTLP)->PCIIO2) & UPCI_AIOP_INTR_BITS) : \ |
| 857 | ((sInW((CTLP)->PCIIO) >> 8) & AIOP_INTR_BITS)) |
| 858 | |
| 859 | /*************************************************************************** |
| 860 | |
| 861 | Function: sGetRxCnt |
| 862 | Purpose: Get the number of data bytes in the Rx FIFO |
| 863 | Call: sGetRxCnt(ChP) |
| 864 | CHANNEL_T *ChP; Ptr to channel structure |
| 865 | Return: int: The number of data bytes in the Rx FIFO. |
| 866 | Comments: Byte read of count register is required to obtain Rx count. |
| 867 | |
| 868 | */ |
| 869 | #define sGetRxCnt(ChP) sInW((ChP)->TxRxCount) |
| 870 | |
| 871 | /*************************************************************************** |
| 872 | Function: sGetTxCnt |
| 873 | Purpose: Get the number of data bytes in the Tx FIFO |
| 874 | Call: sGetTxCnt(ChP) |
| 875 | CHANNEL_T *ChP; Ptr to channel structure |
| 876 | Return: Byte_t: The number of data bytes in the Tx FIFO. |
| 877 | Comments: Byte read of count register is required to obtain Tx count. |
| 878 | |
| 879 | */ |
| 880 | #define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount) |
| 881 | |
| 882 | /***************************************************************************** |
| 883 | Function: sGetTxRxDataIO |
| 884 | Purpose: Get the I/O address of a channel's TxRx Data register |
| 885 | Call: sGetTxRxDataIO(ChP) |
| 886 | CHANNEL_T *ChP; Ptr to channel structure |
| 887 | Return: WordIO_t: I/O address of a channel's TxRx Data register |
| 888 | */ |
| 889 | #define sGetTxRxDataIO(ChP) (ChP)->TxRxData |
| 890 | |
| 891 | /*************************************************************************** |
| 892 | Function: sInitChanDefaults |
| 893 | Purpose: Initialize a channel structure to it's default state. |
| 894 | Call: sInitChanDefaults(ChP) |
| 895 | CHANNEL_T *ChP; Ptr to the channel structure |
| 896 | Comments: This function must be called once for every channel structure |
| 897 | that exists before any other SSCI calls can be made. |
| 898 | |
| 899 | */ |
| 900 | #define sInitChanDefaults(ChP) \ |
| 901 | do { \ |
| 902 | (ChP)->CtlP = NULLCTLPTR; \ |
| 903 | (ChP)->AiopNum = NULLAIOP; \ |
| 904 | (ChP)->ChanID = AIOPID_NULL; \ |
| 905 | (ChP)->ChanNum = NULLCHAN; \ |
| 906 | } while (0) |
| 907 | |
| 908 | /*************************************************************************** |
| 909 | Function: sResetAiopByNum |
| 910 | Purpose: Reset the AIOP by number |
| 911 | Call: sResetAiopByNum(CTLP,AIOPNUM) |
| 912 | CONTROLLER_T CTLP; Ptr to controller structure |
| 913 | AIOPNUM; AIOP index |
| 914 | */ |
| 915 | #define sResetAiopByNum(CTLP,AIOPNUM) \ |
| 916 | do { \ |
| 917 | sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \ |
| 918 | sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \ |
| 919 | } while (0) |
| 920 | |
| 921 | /*************************************************************************** |
| 922 | Function: sSendBreak |
| 923 | Purpose: Send a transmit BREAK signal |
| 924 | Call: sSendBreak(ChP) |
| 925 | CHANNEL_T *ChP; Ptr to channel structure |
| 926 | */ |
| 927 | #define sSendBreak(ChP) \ |
| 928 | do { \ |
| 929 | (ChP)->TxControl[3] |= SETBREAK; \ |
| 930 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 931 | } while (0) |
| 932 | |
| 933 | /*************************************************************************** |
| 934 | Function: sSetBaud |
| 935 | Purpose: Set baud rate |
| 936 | Call: sSetBaud(ChP,Divisor) |
| 937 | CHANNEL_T *ChP; Ptr to channel structure |
| 938 | Word_t Divisor; 16 bit baud rate divisor for channel |
| 939 | */ |
| 940 | #define sSetBaud(ChP,DIVISOR) \ |
| 941 | do { \ |
| 942 | (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \ |
| 943 | (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \ |
| 944 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \ |
| 945 | } while (0) |
| 946 | |
| 947 | /*************************************************************************** |
| 948 | Function: sSetData7 |
| 949 | Purpose: Set data bits to 7 |
| 950 | Call: sSetData7(ChP) |
| 951 | CHANNEL_T *ChP; Ptr to channel structure |
| 952 | */ |
| 953 | #define sSetData7(ChP) \ |
| 954 | do { \ |
| 955 | (ChP)->TxControl[2] &= ~DATA8BIT; \ |
| 956 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 957 | } while (0) |
| 958 | |
| 959 | /*************************************************************************** |
| 960 | Function: sSetData8 |
| 961 | Purpose: Set data bits to 8 |
| 962 | Call: sSetData8(ChP) |
| 963 | CHANNEL_T *ChP; Ptr to channel structure |
| 964 | */ |
| 965 | #define sSetData8(ChP) \ |
| 966 | do { \ |
| 967 | (ChP)->TxControl[2] |= DATA8BIT; \ |
| 968 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 969 | } while (0) |
| 970 | |
| 971 | /*************************************************************************** |
| 972 | Function: sSetDTR |
| 973 | Purpose: Set the DTR output |
| 974 | Call: sSetDTR(ChP) |
| 975 | CHANNEL_T *ChP; Ptr to channel structure |
| 976 | */ |
| 977 | #define sSetDTR(ChP) \ |
| 978 | do { \ |
| 979 | (ChP)->TxControl[3] |= SET_DTR; \ |
| 980 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 981 | } while (0) |
| 982 | |
| 983 | /*************************************************************************** |
| 984 | Function: sSetEvenParity |
| 985 | Purpose: Set even parity |
| 986 | Call: sSetEvenParity(ChP) |
| 987 | CHANNEL_T *ChP; Ptr to channel structure |
| 988 | Comments: Function sSetParity() can be used in place of functions sEnParity(), |
| 989 | sDisParity(), sSetOddParity(), and sSetEvenParity(). |
| 990 | |
| 991 | Warnings: This function has no effect unless parity is enabled with function |
| 992 | sEnParity(). |
| 993 | */ |
| 994 | #define sSetEvenParity(ChP) \ |
| 995 | do { \ |
| 996 | (ChP)->TxControl[2] |= EVEN_PAR; \ |
| 997 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 998 | } while (0) |
| 999 | |
| 1000 | /*************************************************************************** |
| 1001 | Function: sSetOddParity |
| 1002 | Purpose: Set odd parity |
| 1003 | Call: sSetOddParity(ChP) |
| 1004 | CHANNEL_T *ChP; Ptr to channel structure |
| 1005 | Comments: Function sSetParity() can be used in place of functions sEnParity(), |
| 1006 | sDisParity(), sSetOddParity(), and sSetEvenParity(). |
| 1007 | |
| 1008 | Warnings: This function has no effect unless parity is enabled with function |
| 1009 | sEnParity(). |
| 1010 | */ |
| 1011 | #define sSetOddParity(ChP) \ |
| 1012 | do { \ |
| 1013 | (ChP)->TxControl[2] &= ~EVEN_PAR; \ |
| 1014 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 1015 | } while (0) |
| 1016 | |
| 1017 | /*************************************************************************** |
| 1018 | Function: sSetRTS |
| 1019 | Purpose: Set the RTS output |
| 1020 | Call: sSetRTS(ChP) |
| 1021 | CHANNEL_T *ChP; Ptr to channel structure |
| 1022 | */ |
| 1023 | #define sSetRTS(ChP) \ |
| 1024 | do { \ |
| 1025 | if ((ChP)->rtsToggle) break; \ |
| 1026 | (ChP)->TxControl[3] |= SET_RTS; \ |
| 1027 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 1028 | } while (0) |
| 1029 | |
| 1030 | /*************************************************************************** |
| 1031 | Function: sSetRxTrigger |
| 1032 | Purpose: Set the Rx FIFO trigger level |
| 1033 | Call: sSetRxProcessor(ChP,Level) |
| 1034 | CHANNEL_T *ChP; Ptr to channel structure |
| 1035 | Byte_t Level; Number of characters in Rx FIFO at which the |
| 1036 | interrupt will be generated. Can be any of the following flags: |
| 1037 | |
| 1038 | TRIG_NO: no trigger |
| 1039 | TRIG_1: 1 character in FIFO |
| 1040 | TRIG_1_2: FIFO 1/2 full |
| 1041 | TRIG_7_8: FIFO 7/8 full |
| 1042 | Comments: An interrupt will be generated when the trigger level is reached |
| 1043 | only if function sEnInterrupt() has been called with flag |
| 1044 | RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification |
| 1045 | register will be set whenever the trigger level is reached |
| 1046 | regardless of the setting of RXINT_EN. |
| 1047 | |
| 1048 | */ |
| 1049 | #define sSetRxTrigger(ChP,LEVEL) \ |
| 1050 | do { \ |
| 1051 | (ChP)->RxControl[2] &= ~TRIG_MASK; \ |
| 1052 | (ChP)->RxControl[2] |= LEVEL; \ |
| 1053 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ |
| 1054 | } while (0) |
| 1055 | |
| 1056 | /*************************************************************************** |
| 1057 | Function: sSetStop1 |
| 1058 | Purpose: Set stop bits to 1 |
| 1059 | Call: sSetStop1(ChP) |
| 1060 | CHANNEL_T *ChP; Ptr to channel structure |
| 1061 | */ |
| 1062 | #define sSetStop1(ChP) \ |
| 1063 | do { \ |
| 1064 | (ChP)->TxControl[2] &= ~STOP2; \ |
| 1065 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 1066 | } while (0) |
| 1067 | |
| 1068 | /*************************************************************************** |
| 1069 | Function: sSetStop2 |
| 1070 | Purpose: Set stop bits to 2 |
| 1071 | Call: sSetStop2(ChP) |
| 1072 | CHANNEL_T *ChP; Ptr to channel structure |
| 1073 | */ |
| 1074 | #define sSetStop2(ChP) \ |
| 1075 | do { \ |
| 1076 | (ChP)->TxControl[2] |= STOP2; \ |
| 1077 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ |
| 1078 | } while (0) |
| 1079 | |
| 1080 | /*************************************************************************** |
| 1081 | Function: sSetTxXOFFChar |
| 1082 | Purpose: Set the Tx XOFF flow control character |
| 1083 | Call: sSetTxXOFFChar(ChP,Ch) |
| 1084 | CHANNEL_T *ChP; Ptr to channel structure |
| 1085 | Byte_t Ch; The value to set the Tx XOFF character to |
| 1086 | */ |
| 1087 | #define sSetTxXOFFChar(ChP,CH) \ |
| 1088 | do { \ |
| 1089 | (ChP)->R[0x07] = (CH); \ |
| 1090 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ |
| 1091 | } while (0) |
| 1092 | |
| 1093 | /*************************************************************************** |
| 1094 | Function: sSetTxXONChar |
| 1095 | Purpose: Set the Tx XON flow control character |
| 1096 | Call: sSetTxXONChar(ChP,Ch) |
| 1097 | CHANNEL_T *ChP; Ptr to channel structure |
| 1098 | Byte_t Ch; The value to set the Tx XON character to |
| 1099 | */ |
| 1100 | #define sSetTxXONChar(ChP,CH) \ |
| 1101 | do { \ |
| 1102 | (ChP)->R[0x0b] = (CH); \ |
| 1103 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x08]); \ |
| 1104 | } while (0) |
| 1105 | |
| 1106 | /*************************************************************************** |
| 1107 | Function: sStartRxProcessor |
| 1108 | Purpose: Start a channel's receive processor |
| 1109 | Call: sStartRxProcessor(ChP) |
| 1110 | CHANNEL_T *ChP; Ptr to channel structure |
| 1111 | Comments: This function is used to start a Rx processor after it was |
| 1112 | stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It |
| 1113 | will restart both the Rx processor and software input flow control. |
| 1114 | |
| 1115 | */ |
| 1116 | #define sStartRxProcessor(ChP) sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0]) |
| 1117 | |
| 1118 | /*************************************************************************** |
| 1119 | Function: sWriteTxByte |
| 1120 | Purpose: Write a transmit data byte to a channel. |
| 1121 | ByteIO_t io: Channel transmit register I/O address. This can |
| 1122 | be obtained with sGetTxRxDataIO(). |
| 1123 | Byte_t Data; The transmit data byte. |
| 1124 | Warnings: This function writes the data byte without checking to see if |
| 1125 | sMaxTxSize is exceeded in the Tx FIFO. |
| 1126 | */ |
| 1127 | #define sWriteTxByte(IO,DATA) sOutB(IO,DATA) |
| 1128 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1129 | /* |
| 1130 | * Begin Linux specific definitions for the Rocketport driver |
| 1131 | * |
| 1132 | * This code is Copyright Theodore Ts'o, 1995-1997 |
| 1133 | */ |
| 1134 | |
| 1135 | struct r_port { |
| 1136 | int magic; |
| 1137 | int line; |
| 1138 | int flags; |
| 1139 | int count; |
| 1140 | int blocked_open; |
| 1141 | struct tty_struct *tty; |
| 1142 | unsigned int board:3; |
| 1143 | unsigned int aiop:2; |
| 1144 | unsigned int chan:3; |
| 1145 | CONTROLLER_t *ctlp; |
| 1146 | CHANNEL_t channel; |
| 1147 | int closing_wait; |
| 1148 | int close_delay; |
| 1149 | int intmask; |
| 1150 | int xmit_fifo_room; /* room in xmit fifo */ |
| 1151 | unsigned char *xmit_buf; |
| 1152 | int xmit_head; |
| 1153 | int xmit_tail; |
| 1154 | int xmit_cnt; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1155 | int cd_status; |
| 1156 | int ignore_status_mask; |
| 1157 | int read_status_mask; |
| 1158 | int cps; |
| 1159 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1160 | wait_queue_head_t open_wait; |
Jiri Slaby | 8cf5a8c | 2007-10-18 03:06:25 -0700 | [diff] [blame] | 1161 | struct completion close_wait; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1162 | spinlock_t slock; |
Matthias Kaehlcke | 69f545e | 2007-05-08 00:32:00 -0700 | [diff] [blame] | 1163 | struct mutex write_mtx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1164 | }; |
| 1165 | |
| 1166 | #define RPORT_MAGIC 0x525001 |
| 1167 | |
| 1168 | #define NUM_BOARDS 8 |
| 1169 | #define MAX_RP_PORTS (32*NUM_BOARDS) |
| 1170 | |
| 1171 | /* |
| 1172 | * The size of the xmit buffer is 1 page, or 4096 bytes |
| 1173 | */ |
| 1174 | #define XMIT_BUF_SIZE 4096 |
| 1175 | |
| 1176 | /* number of characters left in xmit buffer before we ask for more */ |
| 1177 | #define WAKEUP_CHARS 256 |
| 1178 | |
| 1179 | /* Internal flags used only by the rocketport driver */ |
| 1180 | #define ROCKET_INITIALIZED 0x80000000 /* Port is active */ |
| 1181 | #define ROCKET_CLOSING 0x40000000 /* Serial port is closing */ |
| 1182 | #define ROCKET_NORMAL_ACTIVE 0x20000000 /* Normal port is active */ |
| 1183 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1184 | /* |
| 1185 | * Assigned major numbers for the Comtrol Rocketport |
| 1186 | */ |
| 1187 | #define TTY_ROCKET_MAJOR 46 |
| 1188 | #define CUA_ROCKET_MAJOR 47 |
| 1189 | |
| 1190 | #ifdef PCI_VENDOR_ID_RP |
| 1191 | #undef PCI_VENDOR_ID_RP |
| 1192 | #undef PCI_DEVICE_ID_RP8OCTA |
| 1193 | #undef PCI_DEVICE_ID_RP8INTF |
| 1194 | #undef PCI_DEVICE_ID_RP16INTF |
| 1195 | #undef PCI_DEVICE_ID_RP32INTF |
| 1196 | #undef PCI_DEVICE_ID_URP8OCTA |
| 1197 | #undef PCI_DEVICE_ID_URP8INTF |
| 1198 | #undef PCI_DEVICE_ID_URP16INTF |
| 1199 | #undef PCI_DEVICE_ID_CRP16INTF |
| 1200 | #undef PCI_DEVICE_ID_URP32INTF |
| 1201 | #endif |
| 1202 | |
| 1203 | /* Comtrol PCI Vendor ID */ |
| 1204 | #define PCI_VENDOR_ID_RP 0x11fe |
| 1205 | |
| 1206 | /* Comtrol Device ID's */ |
| 1207 | #define PCI_DEVICE_ID_RP32INTF 0x0001 /* Rocketport 32 port w/external I/F */ |
| 1208 | #define PCI_DEVICE_ID_RP8INTF 0x0002 /* Rocketport 8 port w/external I/F */ |
| 1209 | #define PCI_DEVICE_ID_RP16INTF 0x0003 /* Rocketport 16 port w/external I/F */ |
| 1210 | #define PCI_DEVICE_ID_RP4QUAD 0x0004 /* Rocketport 4 port w/quad cable */ |
| 1211 | #define PCI_DEVICE_ID_RP8OCTA 0x0005 /* Rocketport 8 port w/octa cable */ |
| 1212 | #define PCI_DEVICE_ID_RP8J 0x0006 /* Rocketport 8 port w/RJ11 connectors */ |
| 1213 | #define PCI_DEVICE_ID_RP4J 0x0007 /* Rocketport 4 port w/RJ11 connectors */ |
| 1214 | #define PCI_DEVICE_ID_RP8SNI 0x0008 /* Rocketport 8 port w/ DB78 SNI (Siemens) connector */ |
| 1215 | #define PCI_DEVICE_ID_RP16SNI 0x0009 /* Rocketport 16 port w/ DB78 SNI (Siemens) connector */ |
| 1216 | #define PCI_DEVICE_ID_RPP4 0x000A /* Rocketport Plus 4 port */ |
| 1217 | #define PCI_DEVICE_ID_RPP8 0x000B /* Rocketport Plus 8 port */ |
| 1218 | #define PCI_DEVICE_ID_RP6M 0x000C /* RocketModem 6 port */ |
| 1219 | #define PCI_DEVICE_ID_RP4M 0x000D /* RocketModem 4 port */ |
| 1220 | #define PCI_DEVICE_ID_RP2_232 0x000E /* Rocketport Plus 2 port RS232 */ |
| 1221 | #define PCI_DEVICE_ID_RP2_422 0x000F /* Rocketport Plus 2 port RS422 */ |
| 1222 | |
| 1223 | /* Universal PCI boards */ |
| 1224 | #define PCI_DEVICE_ID_URP32INTF 0x0801 /* Rocketport UPCI 32 port w/external I/F */ |
| 1225 | #define PCI_DEVICE_ID_URP8INTF 0x0802 /* Rocketport UPCI 8 port w/external I/F */ |
| 1226 | #define PCI_DEVICE_ID_URP16INTF 0x0803 /* Rocketport UPCI 16 port w/external I/F */ |
| 1227 | #define PCI_DEVICE_ID_URP8OCTA 0x0805 /* Rocketport UPCI 8 port w/octa cable */ |
| 1228 | #define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C /* Rocketmodem III 8 port */ |
| 1229 | #define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D /* Rocketmodem III 4 port */ |
| 1230 | |
| 1231 | /* Compact PCI device */ |
| 1232 | #define PCI_DEVICE_ID_CRP16INTF 0x0903 /* Rocketport Compact PCI 16 port w/external I/F */ |
| 1233 | |