Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-iop13xx/msi.c |
| 3 | * |
| 4 | * PCI MSI support for the iop13xx processor |
| 5 | * |
| 6 | * Copyright (c) 2006, Intel Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms and conditions of the GNU General Public License, |
| 10 | * version 2, as published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along with |
| 18 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple |
| 19 | * Place - Suite 330, Boston, MA 02111-1307 USA. |
| 20 | * |
| 21 | */ |
| 22 | #include <linux/pci.h> |
| 23 | #include <linux/msi.h> |
| 24 | #include <asm/mach/irq.h> |
| 25 | #include <asm/irq.h> |
Arnd Bergmann | 8d2af85 | 2014-05-26 17:12:10 +0200 | [diff] [blame] | 26 | #include <mach/irqs.h> |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 27 | |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 28 | /* IMIPR0 CP6 R8 Page 1 |
| 29 | */ |
Dan Williams | d73d801 | 2007-05-15 01:03:36 +0100 | [diff] [blame] | 30 | static u32 read_imipr_0(void) |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 31 | { |
| 32 | u32 val; |
| 33 | asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); |
| 34 | return val; |
| 35 | } |
Dan Williams | d73d801 | 2007-05-15 01:03:36 +0100 | [diff] [blame] | 36 | static void write_imipr_0(u32 val) |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 37 | { |
| 38 | asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); |
| 39 | } |
| 40 | |
| 41 | /* IMIPR1 CP6 R9 Page 1 |
| 42 | */ |
Dan Williams | d73d801 | 2007-05-15 01:03:36 +0100 | [diff] [blame] | 43 | static u32 read_imipr_1(void) |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 44 | { |
| 45 | u32 val; |
| 46 | asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); |
| 47 | return val; |
| 48 | } |
Dan Williams | d73d801 | 2007-05-15 01:03:36 +0100 | [diff] [blame] | 49 | static void write_imipr_1(u32 val) |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 50 | { |
| 51 | asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); |
| 52 | } |
| 53 | |
| 54 | /* IMIPR2 CP6 R10 Page 1 |
| 55 | */ |
Dan Williams | d73d801 | 2007-05-15 01:03:36 +0100 | [diff] [blame] | 56 | static u32 read_imipr_2(void) |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 57 | { |
| 58 | u32 val; |
| 59 | asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); |
| 60 | return val; |
| 61 | } |
Dan Williams | d73d801 | 2007-05-15 01:03:36 +0100 | [diff] [blame] | 62 | static void write_imipr_2(u32 val) |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 63 | { |
| 64 | asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); |
| 65 | } |
| 66 | |
| 67 | /* IMIPR3 CP6 R11 Page 1 |
| 68 | */ |
Dan Williams | d73d801 | 2007-05-15 01:03:36 +0100 | [diff] [blame] | 69 | static u32 read_imipr_3(void) |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 70 | { |
| 71 | u32 val; |
| 72 | asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); |
| 73 | return val; |
| 74 | } |
Dan Williams | d73d801 | 2007-05-15 01:03:36 +0100 | [diff] [blame] | 75 | static void write_imipr_3(u32 val) |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 76 | { |
| 77 | asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); |
| 78 | } |
| 79 | |
| 80 | static u32 (*read_imipr[])(void) = { |
| 81 | read_imipr_0, |
| 82 | read_imipr_1, |
| 83 | read_imipr_2, |
| 84 | read_imipr_3, |
| 85 | }; |
| 86 | |
| 87 | static void (*write_imipr[])(u32) = { |
| 88 | write_imipr_0, |
| 89 | write_imipr_1, |
| 90 | write_imipr_2, |
| 91 | write_imipr_3, |
| 92 | }; |
| 93 | |
| 94 | static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc) |
| 95 | { |
| 96 | int i, j; |
| 97 | unsigned long status; |
| 98 | |
| 99 | /* read IMIPR registers and find any active interrupts, |
| 100 | * then call ISR for each active interrupt |
| 101 | */ |
| 102 | for (i = 0; i < ARRAY_SIZE(read_imipr); i++) { |
| 103 | status = (read_imipr[i])(); |
| 104 | if (!status) |
| 105 | continue; |
| 106 | |
| 107 | do { |
| 108 | j = find_first_bit(&status, 32); |
| 109 | (write_imipr[i])(1 << j); /* write back to clear bit */ |
Dmitry Baryshkov | d8aa025 | 2008-10-09 13:36:24 +0100 | [diff] [blame] | 110 | generic_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i)); |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 111 | status = (read_imipr[i])(); |
| 112 | } while (status); |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | void __init iop13xx_msi_init(void) |
| 117 | { |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 118 | irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 119 | } |
| 120 | |
Lennert Buytenhek | 418c990 | 2010-11-29 10:32:01 +0100 | [diff] [blame] | 121 | static void iop13xx_msi_nop(struct irq_data *d) |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 122 | { |
| 123 | return; |
| 124 | } |
| 125 | |
| 126 | static struct irq_chip iop13xx_msi_chip = { |
| 127 | .name = "PCI-MSI", |
Lennert Buytenhek | 418c990 | 2010-11-29 10:32:01 +0100 | [diff] [blame] | 128 | .irq_ack = iop13xx_msi_nop, |
Thomas Gleixner | 280510f | 2014-11-23 12:23:20 +0100 | [diff] [blame] | 129 | .irq_enable = pci_msi_unmask_irq, |
| 130 | .irq_disable = pci_msi_mask_irq, |
| 131 | .irq_mask = pci_msi_mask_irq, |
| 132 | .irq_unmask = pci_msi_unmask_irq, |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 133 | }; |
| 134 | |
| 135 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) |
| 136 | { |
Thomas Gleixner | 37ebbcf | 2014-05-07 15:44:04 +0000 | [diff] [blame] | 137 | int id, irq = irq_alloc_desc_from(IRQ_IOP13XX_MSI_0, -1); |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 138 | struct msi_msg msg; |
| 139 | |
| 140 | if (irq < 0) |
| 141 | return irq; |
| 142 | |
Thomas Gleixner | 37ebbcf | 2014-05-07 15:44:04 +0000 | [diff] [blame] | 143 | if (irq >= NR_IOP13XX_IRQS) { |
| 144 | irq_free_desc(irq); |
| 145 | return -ENOSPC; |
| 146 | } |
| 147 | |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 148 | irq_set_msi_desc(irq, desc); |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 149 | |
| 150 | msg.address_hi = 0x0; |
| 151 | msg.address_lo = IOP13XX_MU_MIMR_PCI; |
| 152 | |
| 153 | id = iop13xx_cpu_id(); |
| 154 | msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); |
| 155 | |
Jiang Liu | 83a1891 | 2014-11-09 23:10:34 +0800 | [diff] [blame] | 156 | pci_write_msi_msg(irq, &msg); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 157 | irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 158 | |
Dan Williams | e702a71 | 2007-05-15 01:03:31 +0100 | [diff] [blame] | 159 | return 0; |
Daniel Wolstenholme | 2fd0237 | 2007-05-10 22:33:02 -0700 | [diff] [blame] | 160 | } |
Thomas Gleixner | 37ebbcf | 2014-05-07 15:44:04 +0000 | [diff] [blame] | 161 | |
| 162 | void arch_teardown_msi_irq(unsigned int irq) |
| 163 | { |
| 164 | irq_free_desc(irq); |
| 165 | } |