Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1 | /* |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2 | cx231xx_avcore.c - driver for Conexant Cx23100/101/102 |
| 3 | USB video capture devices |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 4 | |
| 5 | Copyright (C) 2008 <srinivasa.deevi at conexant dot com> |
| 6 | |
| 7 | This program contains the specific code to control the avdecoder chip and |
| 8 | other related usb control functions for cx231xx based chipset. |
| 9 | |
| 10 | This program is free software; you can redistribute it and/or modify |
| 11 | it under the terms of the GNU General Public License as published by |
| 12 | the Free Software Foundation; either version 2 of the License, or |
| 13 | (at your option) any later version. |
| 14 | |
| 15 | This program is distributed in the hope that it will be useful, |
| 16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | GNU General Public License for more details. |
| 19 | |
| 20 | You should have received a copy of the GNU General Public License |
| 21 | along with this program; if not, write to the Free Software |
| 22 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 23 | */ |
| 24 | |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/list.h> |
| 27 | #include <linux/module.h> |
| 28 | #include <linux/kernel.h> |
| 29 | #include <linux/bitmap.h> |
| 30 | #include <linux/usb.h> |
| 31 | #include <linux/i2c.h> |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 32 | #include <linux/mm.h> |
| 33 | #include <linux/mutex.h> |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 34 | #include <media/tuner.h> |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 35 | |
| 36 | #include <media/v4l2-common.h> |
| 37 | #include <media/v4l2-ioctl.h> |
| 38 | #include <media/v4l2-chip-ident.h> |
| 39 | |
| 40 | #include "cx231xx.h" |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 41 | #include "cx231xx-dif.h" |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 42 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 43 | #define TUNER_MODE_FM_RADIO 0 |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 44 | /****************************************************************************** |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 45 | -: BLOCK ARRANGEMENT :- |
| 46 | I2S block ----------------------| |
| 47 | [I2S audio] | |
| 48 | | |
| 49 | Analog Front End --> Direct IF -|-> Cx25840 --> Audio |
| 50 | [video & audio] | [Audio] |
| 51 | | |
| 52 | |-> Cx25840 --> Video |
| 53 | [Video] |
| 54 | |
| 55 | *******************************************************************************/ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 56 | /****************************************************************************** |
| 57 | * VERVE REGISTER * |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 58 | * * |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 59 | ******************************************************************************/ |
| 60 | static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data) |
| 61 | { |
| 62 | return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS, |
| 63 | saddr, 1, data, 1); |
| 64 | } |
| 65 | |
| 66 | static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data) |
| 67 | { |
| 68 | int status; |
| 69 | u32 temp = 0; |
| 70 | |
| 71 | status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS, |
| 72 | saddr, 1, &temp, 1); |
| 73 | *data = (u8) temp; |
| 74 | return status; |
| 75 | } |
| 76 | void initGPIO(struct cx231xx *dev) |
| 77 | { |
| 78 | u32 _gpio_direction = 0; |
| 79 | u32 value = 0; |
| 80 | u8 val = 0; |
| 81 | |
| 82 | _gpio_direction = _gpio_direction & 0xFC0003FF; |
| 83 | _gpio_direction = _gpio_direction | 0x03FDFC00; |
| 84 | cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0); |
| 85 | |
| 86 | verve_read_byte(dev, 0x07, &val); |
| 87 | cx231xx_info(" verve_read_byte address0x07=0x%x\n", val); |
| 88 | verve_write_byte(dev, 0x07, 0xF4); |
| 89 | verve_read_byte(dev, 0x07, &val); |
| 90 | cx231xx_info(" verve_read_byte address0x07=0x%x\n", val); |
| 91 | |
| 92 | cx231xx_capture_start(dev, 1, 2); |
| 93 | |
| 94 | cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00); |
| 95 | cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF); |
| 96 | |
| 97 | } |
| 98 | void uninitGPIO(struct cx231xx *dev) |
| 99 | { |
| 100 | u8 value[4] = { 0, 0, 0, 0 }; |
| 101 | |
| 102 | cx231xx_capture_start(dev, 0, 2); |
| 103 | verve_write_byte(dev, 0x07, 0x14); |
| 104 | cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 105 | 0x68, value, 4); |
| 106 | } |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 107 | |
| 108 | /****************************************************************************** |
| 109 | * A F E - B L O C K C O N T R O L functions * |
| 110 | * [ANALOG FRONT END] * |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 111 | ******************************************************************************/ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 112 | static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data) |
| 113 | { |
| 114 | return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS, |
| 115 | saddr, 2, data, 1); |
| 116 | } |
| 117 | |
| 118 | static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) |
| 119 | { |
| 120 | int status; |
| 121 | u32 temp = 0; |
| 122 | |
| 123 | status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS, |
| 124 | saddr, 2, &temp, 1); |
| 125 | *data = (u8) temp; |
| 126 | return status; |
| 127 | } |
| 128 | |
| 129 | int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 130 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 131 | int status = 0; |
| 132 | u8 temp = 0; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 133 | u8 afe_power_status = 0; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 134 | int i = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 135 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 136 | /* super block initialize */ |
| 137 | temp = (u8) (ref_count & 0xff); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 138 | status = afe_write_byte(dev, SUP_BLK_TUNE2, temp); |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 139 | if (status < 0) |
| 140 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 141 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 142 | status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status); |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 143 | if (status < 0) |
| 144 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 145 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 146 | temp = (u8) ((ref_count & 0x300) >> 8); |
| 147 | temp |= 0x40; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 148 | status = afe_write_byte(dev, SUP_BLK_TUNE1, temp); |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 149 | if (status < 0) |
| 150 | return status; |
| 151 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 152 | status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f); |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 153 | if (status < 0) |
| 154 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 155 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 156 | /* enable pll */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 157 | while (afe_power_status != 0x18) { |
| 158 | status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18); |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 159 | if (status < 0) { |
| 160 | cx231xx_info( |
| 161 | ": Init Super Block failed in send cmd\n"); |
| 162 | break; |
| 163 | } |
| 164 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 165 | status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status); |
| 166 | afe_power_status &= 0xff; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 167 | if (status < 0) { |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 168 | cx231xx_info( |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 169 | ": Init Super Block failed in receive cmd\n"); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 170 | break; |
| 171 | } |
| 172 | i++; |
| 173 | if (i == 10) { |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 174 | cx231xx_info( |
| 175 | ": Init Super Block force break in loop !!!!\n"); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 176 | status = -1; |
| 177 | break; |
| 178 | } |
| 179 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 180 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 181 | if (status < 0) |
| 182 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 183 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 184 | /* start tuning filter */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 185 | status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40); |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 186 | if (status < 0) |
| 187 | return status; |
| 188 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 189 | msleep(5); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 190 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 191 | /* exit tuning */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 192 | status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 193 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 194 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 195 | } |
| 196 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 197 | int cx231xx_afe_init_channels(struct cx231xx *dev) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 198 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 199 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 200 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 201 | /* power up all 3 channels, clear pd_buffer */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 202 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00); |
| 203 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00); |
| 204 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 205 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 206 | /* Enable quantizer calibration */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 207 | status = afe_write_byte(dev, ADC_COM_QUANT, 0x02); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 208 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 209 | /* channel initialize, force modulator (fb) reset */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 210 | status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17); |
| 211 | status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17); |
| 212 | status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 213 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 214 | /* start quantilizer calibration */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 215 | status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10); |
| 216 | status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10); |
| 217 | status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 218 | msleep(5); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 219 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 220 | /* exit modulator (fb) reset */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 221 | status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07); |
| 222 | status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07); |
| 223 | status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 224 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 225 | /* enable the pre_clamp in each channel for single-ended input */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 226 | status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0); |
| 227 | status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0); |
| 228 | status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 229 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 230 | /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 231 | status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 232 | ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 233 | status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 234 | ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 235 | status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 236 | ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 237 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 238 | /* dynamic element matching off */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 239 | status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03); |
| 240 | status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03); |
| 241 | status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 242 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 243 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 244 | } |
| 245 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 246 | int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 247 | { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 248 | u8 c_value = 0; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 249 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 250 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 251 | status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 252 | c_value &= (~(0x50)); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 253 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 254 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 255 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 256 | } |
| 257 | |
| 258 | /* |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 259 | The Analog Front End in Cx231xx has 3 channels. These |
| 260 | channels are used to share between different inputs |
| 261 | like tuner, s-video and composite inputs. |
| 262 | |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 263 | channel 1 ----- pin 1 to pin4(in reg is 1-4) |
| 264 | channel 2 ----- pin 5 to pin8(in reg is 5-8) |
| 265 | channel 3 ----- pin 9 to pin 12(in reg is 9-11) |
| 266 | */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 267 | int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 268 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 269 | u8 ch1_setting = (u8) input_mux; |
| 270 | u8 ch2_setting = (u8) (input_mux >> 8); |
| 271 | u8 ch3_setting = (u8) (input_mux >> 16); |
| 272 | int status = 0; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 273 | u8 value = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 274 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 275 | if (ch1_setting != 0) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 276 | status = afe_read_byte(dev, ADC_INPUT_CH1, &value); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 277 | value &= (!INPUT_SEL_MASK); |
| 278 | value |= (ch1_setting - 1) << 4; |
| 279 | value &= 0xff; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 280 | status = afe_write_byte(dev, ADC_INPUT_CH1, value); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 281 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 282 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 283 | if (ch2_setting != 0) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 284 | status = afe_read_byte(dev, ADC_INPUT_CH2, &value); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 285 | value &= (!INPUT_SEL_MASK); |
| 286 | value |= (ch2_setting - 1) << 4; |
| 287 | value &= 0xff; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 288 | status = afe_write_byte(dev, ADC_INPUT_CH2, value); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 289 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 290 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 291 | /* For ch3_setting, the value to put in the register is |
| 292 | 7 less than the input number */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 293 | if (ch3_setting != 0) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 294 | status = afe_read_byte(dev, ADC_INPUT_CH3, &value); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 295 | value &= (!INPUT_SEL_MASK); |
| 296 | value |= (ch3_setting - 1) << 4; |
| 297 | value &= 0xff; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 298 | status = afe_write_byte(dev, ADC_INPUT_CH3, value); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 299 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 300 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 301 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 302 | } |
| 303 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 304 | int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 305 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 306 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 307 | |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 308 | /* |
| 309 | * FIXME: We need to implement the AFE code for LOW IF and for HI IF. |
| 310 | * Currently, only baseband works. |
| 311 | */ |
| 312 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 313 | switch (mode) { |
| 314 | case AFE_MODE_LOW_IF: |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 315 | cx231xx_Setup_AFE_for_LowIF(dev); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 316 | break; |
| 317 | case AFE_MODE_BASEBAND: |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 318 | status = cx231xx_afe_setup_AFE_for_baseband(dev); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 319 | break; |
| 320 | case AFE_MODE_EU_HI_IF: |
| 321 | /* SetupAFEforEuHiIF(); */ |
| 322 | break; |
| 323 | case AFE_MODE_US_HI_IF: |
| 324 | /* SetupAFEforUsHiIF(); */ |
| 325 | break; |
| 326 | case AFE_MODE_JAPAN_HI_IF: |
| 327 | /* SetupAFEforJapanHiIF(); */ |
| 328 | break; |
| 329 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 330 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 331 | if ((mode != dev->afe_mode) && |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 332 | (dev->video_input == CX231XX_VMUX_TELEVISION)) |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 333 | status = cx231xx_afe_adjust_ref_count(dev, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 334 | CX231XX_VMUX_TELEVISION); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 335 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 336 | dev->afe_mode = mode; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 337 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 338 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 339 | } |
| 340 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 341 | int cx231xx_afe_update_power_control(struct cx231xx *dev, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 342 | enum AV_MODE avmode) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 343 | { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 344 | u8 afe_power_status = 0; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 345 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 346 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 347 | switch (dev->model) { |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 348 | case CX231XX_BOARD_CNXT_CARRAERA: |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 349 | case CX231XX_BOARD_CNXT_RDE_250: |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 350 | case CX231XX_BOARD_CNXT_SHELBY: |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 351 | case CX231XX_BOARD_CNXT_RDU_250: |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 352 | case CX231XX_BOARD_CNXT_RDE_253S: |
| 353 | case CX231XX_BOARD_CNXT_RDU_253S: |
| 354 | case CX231XX_BOARD_CNXT_VIDEO_GRABBER: |
Michael Krufky | 1a50fdd | 2010-07-06 18:23:53 -0300 | [diff] [blame] | 355 | case CX231XX_BOARD_HAUPPAUGE_EXETER: |
Devin Heitmueller | 4270c3c | 2010-07-31 00:49:01 -0300 | [diff] [blame] | 356 | case CX231XX_BOARD_HAUPPAUGE_USBLIVE2: |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 357 | if (avmode == POLARIS_AVMODE_ANALOGT_TV) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 358 | while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 359 | FLD_PWRDN_ENABLE_PLL)) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 360 | status = afe_write_byte(dev, SUP_BLK_PWRDN, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 361 | FLD_PWRDN_TUNING_BIAS | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 362 | FLD_PWRDN_ENABLE_PLL); |
| 363 | status |= afe_read_byte(dev, SUP_BLK_PWRDN, |
| 364 | &afe_power_status); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 365 | if (status < 0) |
| 366 | break; |
| 367 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 368 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 369 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, |
| 370 | 0x00); |
| 371 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, |
| 372 | 0x00); |
| 373 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, |
| 374 | 0x00); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 375 | } else if (avmode == POLARIS_AVMODE_DIGITAL) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 376 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, |
| 377 | 0x70); |
| 378 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, |
| 379 | 0x70); |
| 380 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, |
| 381 | 0x70); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 382 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 383 | status |= afe_read_byte(dev, SUP_BLK_PWRDN, |
| 384 | &afe_power_status); |
| 385 | afe_power_status |= FLD_PWRDN_PD_BANDGAP | |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 386 | FLD_PWRDN_PD_BIAS | |
| 387 | FLD_PWRDN_PD_TUNECK; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 388 | status |= afe_write_byte(dev, SUP_BLK_PWRDN, |
| 389 | afe_power_status); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 390 | } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 391 | while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 392 | FLD_PWRDN_ENABLE_PLL)) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 393 | status = afe_write_byte(dev, SUP_BLK_PWRDN, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 394 | FLD_PWRDN_TUNING_BIAS | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 395 | FLD_PWRDN_ENABLE_PLL); |
| 396 | status |= afe_read_byte(dev, SUP_BLK_PWRDN, |
| 397 | &afe_power_status); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 398 | if (status < 0) |
| 399 | break; |
| 400 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 401 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 402 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, |
| 403 | 0x00); |
| 404 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, |
| 405 | 0x00); |
| 406 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, |
| 407 | 0x00); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 408 | } else { |
| 409 | cx231xx_info("Invalid AV mode input\n"); |
| 410 | status = -1; |
| 411 | } |
| 412 | break; |
| 413 | default: |
| 414 | if (avmode == POLARIS_AVMODE_ANALOGT_TV) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 415 | while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 416 | FLD_PWRDN_ENABLE_PLL)) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 417 | status = afe_write_byte(dev, SUP_BLK_PWRDN, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 418 | FLD_PWRDN_TUNING_BIAS | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 419 | FLD_PWRDN_ENABLE_PLL); |
| 420 | status |= afe_read_byte(dev, SUP_BLK_PWRDN, |
| 421 | &afe_power_status); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 422 | if (status < 0) |
| 423 | break; |
| 424 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 425 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 426 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, |
| 427 | 0x40); |
| 428 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, |
| 429 | 0x40); |
| 430 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, |
| 431 | 0x00); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 432 | } else if (avmode == POLARIS_AVMODE_DIGITAL) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 433 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, |
| 434 | 0x70); |
| 435 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, |
| 436 | 0x70); |
| 437 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, |
| 438 | 0x70); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 439 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 440 | status |= afe_read_byte(dev, SUP_BLK_PWRDN, |
| 441 | &afe_power_status); |
| 442 | afe_power_status |= FLD_PWRDN_PD_BANDGAP | |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 443 | FLD_PWRDN_PD_BIAS | |
| 444 | FLD_PWRDN_PD_TUNECK; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 445 | status |= afe_write_byte(dev, SUP_BLK_PWRDN, |
| 446 | afe_power_status); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 447 | } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 448 | while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 449 | FLD_PWRDN_ENABLE_PLL)) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 450 | status = afe_write_byte(dev, SUP_BLK_PWRDN, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 451 | FLD_PWRDN_TUNING_BIAS | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 452 | FLD_PWRDN_ENABLE_PLL); |
| 453 | status |= afe_read_byte(dev, SUP_BLK_PWRDN, |
| 454 | &afe_power_status); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 455 | if (status < 0) |
| 456 | break; |
| 457 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 458 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 459 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, |
| 460 | 0x00); |
| 461 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, |
| 462 | 0x00); |
| 463 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, |
| 464 | 0x40); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 465 | } else { |
| 466 | cx231xx_info("Invalid AV mode input\n"); |
| 467 | status = -1; |
| 468 | } |
| 469 | } /* switch */ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 470 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 471 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 472 | } |
| 473 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 474 | int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 475 | { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 476 | u8 input_mode = 0; |
| 477 | u8 ntf_mode = 0; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 478 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 479 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 480 | dev->video_input = video_input; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 481 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 482 | if (video_input == CX231XX_VMUX_TELEVISION) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 483 | status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode); |
| 484 | status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, |
| 485 | &ntf_mode); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 486 | } else { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 487 | status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode); |
| 488 | status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1, |
| 489 | &ntf_mode); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 490 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 491 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 492 | input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 493 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 494 | switch (input_mode) { |
| 495 | case SINGLE_ENDED: |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 496 | dev->afe_ref_count = 0x23C; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 497 | break; |
| 498 | case LOW_IF: |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 499 | dev->afe_ref_count = 0x24C; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 500 | break; |
| 501 | case EU_IF: |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 502 | dev->afe_ref_count = 0x258; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 503 | break; |
| 504 | case US_IF: |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 505 | dev->afe_ref_count = 0x260; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 506 | break; |
| 507 | default: |
| 508 | break; |
| 509 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 510 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 511 | status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 512 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 513 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 514 | } |
| 515 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 516 | /****************************************************************************** |
| 517 | * V I D E O / A U D I O D E C O D E R C O N T R O L functions * |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 518 | ******************************************************************************/ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 519 | static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data) |
| 520 | { |
| 521 | return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, |
| 522 | saddr, 2, data, 1); |
| 523 | } |
| 524 | |
| 525 | static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) |
| 526 | { |
| 527 | int status; |
| 528 | u32 temp = 0; |
| 529 | |
| 530 | status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, |
| 531 | saddr, 2, &temp, 1); |
| 532 | *data = (u8) temp; |
| 533 | return status; |
| 534 | } |
| 535 | |
| 536 | static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data) |
| 537 | { |
| 538 | return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, |
| 539 | saddr, 2, data, 4); |
| 540 | } |
| 541 | |
| 542 | static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data) |
| 543 | { |
| 544 | return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, |
| 545 | saddr, 2, data, 4); |
| 546 | } |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 547 | int cx231xx_check_fw(struct cx231xx *dev) |
| 548 | { |
| 549 | u8 temp = 0; |
| 550 | int status = 0; |
| 551 | status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp); |
| 552 | if (status < 0) |
| 553 | return status; |
| 554 | else |
| 555 | return temp; |
| 556 | |
| 557 | } |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 558 | |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 559 | int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) |
| 560 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 561 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 562 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 563 | switch (INPUT(input)->type) { |
| 564 | case CX231XX_VMUX_COMPOSITE1: |
| 565 | case CX231XX_VMUX_SVIDEO: |
| 566 | if ((dev->current_pcb_config.type == USB_BUS_POWER) && |
| 567 | (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 568 | /* External AV */ |
| 569 | status = cx231xx_set_power_mode(dev, |
| 570 | POLARIS_AVMODE_ENXTERNAL_AV); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 571 | if (status < 0) { |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 572 | cx231xx_errdev("%s: set_power_mode : Failed to" |
| 573 | " set Power - errCode [%d]!\n", |
| 574 | __func__, status); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 575 | return status; |
| 576 | } |
| 577 | } |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 578 | status = cx231xx_set_decoder_video_input(dev, |
| 579 | INPUT(input)->type, |
| 580 | INPUT(input)->vmux); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 581 | break; |
| 582 | case CX231XX_VMUX_TELEVISION: |
| 583 | case CX231XX_VMUX_CABLE: |
| 584 | if ((dev->current_pcb_config.type == USB_BUS_POWER) && |
| 585 | (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 586 | /* Tuner */ |
| 587 | status = cx231xx_set_power_mode(dev, |
| 588 | POLARIS_AVMODE_ANALOGT_TV); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 589 | if (status < 0) { |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 590 | cx231xx_errdev("%s: set_power_mode:Failed" |
| 591 | " to set Power - errCode [%d]!\n", |
| 592 | __func__, status); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 593 | return status; |
| 594 | } |
| 595 | } |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 596 | if (dev->tuner_type == TUNER_NXP_TDA18271) |
| 597 | status = cx231xx_set_decoder_video_input(dev, |
| 598 | CX231XX_VMUX_TELEVISION, |
| 599 | INPUT(input)->vmux); |
| 600 | else |
| 601 | status = cx231xx_set_decoder_video_input(dev, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 602 | CX231XX_VMUX_COMPOSITE1, |
| 603 | INPUT(input)->vmux); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 604 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 605 | break; |
| 606 | default: |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 607 | cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n", |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 608 | __func__, INPUT(input)->type); |
| 609 | break; |
| 610 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 611 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 612 | /* save the selection */ |
| 613 | dev->video_input = input; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 614 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 615 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 616 | } |
| 617 | |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 618 | int cx231xx_set_decoder_video_input(struct cx231xx *dev, |
| 619 | u8 pin_type, u8 input) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 620 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 621 | int status = 0; |
| 622 | u32 value = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 623 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 624 | if (pin_type != dev->video_input) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 625 | status = cx231xx_afe_adjust_ref_count(dev, pin_type); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 626 | if (status < 0) { |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 627 | cx231xx_errdev("%s: adjust_ref_count :Failed to set" |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 628 | "AFE input mux - errCode [%d]!\n", |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 629 | __func__, status); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 630 | return status; |
| 631 | } |
| 632 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 633 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 634 | /* call afe block to set video inputs */ |
| 635 | status = cx231xx_afe_set_input_mux(dev, input); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 636 | if (status < 0) { |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 637 | cx231xx_errdev("%s: set_input_mux :Failed to set" |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 638 | " AFE input mux - errCode [%d]!\n", |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 639 | __func__, status); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 640 | return status; |
| 641 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 642 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 643 | switch (pin_type) { |
| 644 | case CX231XX_VMUX_COMPOSITE1: |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 645 | status = vid_blk_read_word(dev, AFE_CTRL, &value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 646 | value |= (0 << 13) | (1 << 4); |
| 647 | value &= ~(1 << 5); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 648 | |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 649 | /* set [24:23] [22:15] to 0 */ |
| 650 | value &= (~(0x1ff8000)); |
| 651 | /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ |
| 652 | value |= 0x1000000; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 653 | status = vid_blk_write_word(dev, AFE_CTRL, value); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 654 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 655 | status = vid_blk_read_word(dev, OUT_CTRL1, &value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 656 | value |= (1 << 7); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 657 | status = vid_blk_write_word(dev, OUT_CTRL1, value); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 658 | |
Devin Heitmueller | 8880621 | 2010-08-18 17:50:07 -0300 | [diff] [blame] | 659 | /* Set output mode */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 660 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 661 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 662 | OUT_CTRL1, |
| 663 | FLD_OUT_MODE, |
Devin Heitmueller | 8880621 | 2010-08-18 17:50:07 -0300 | [diff] [blame] | 664 | dev->board.output_mode); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 665 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 666 | /* Tell DIF object to go to baseband mode */ |
| 667 | status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); |
| 668 | if (status < 0) { |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 669 | cx231xx_errdev("%s: cx231xx_dif set to By pass" |
| 670 | " mode- errCode [%d]!\n", |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 671 | __func__, status); |
| 672 | return status; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 673 | } |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 674 | |
| 675 | /* Read the DFE_CTRL1 register */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 676 | status = vid_blk_read_word(dev, DFE_CTRL1, &value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 677 | |
| 678 | /* enable the VBI_GATE_EN */ |
| 679 | value |= FLD_VBI_GATE_EN; |
| 680 | |
| 681 | /* Enable the auto-VGA enable */ |
| 682 | value |= FLD_VGA_AUTO_EN; |
| 683 | |
| 684 | /* Write it back */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 685 | status = vid_blk_write_word(dev, DFE_CTRL1, value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 686 | |
| 687 | /* Disable auto config of registers */ |
| 688 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 689 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 690 | MODE_CTRL, FLD_ACFG_DIS, |
| 691 | cx231xx_set_field(FLD_ACFG_DIS, 1)); |
| 692 | |
| 693 | /* Set CVBS input mode */ |
| 694 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 695 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 696 | MODE_CTRL, FLD_INPUT_MODE, |
| 697 | cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 698 | break; |
| 699 | case CX231XX_VMUX_SVIDEO: |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 700 | /* Disable the use of DIF */ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 701 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 702 | status = vid_blk_read_word(dev, AFE_CTRL, &value); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 703 | |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 704 | /* set [24:23] [22:15] to 0 */ |
| 705 | value &= (~(0x1ff8000)); |
| 706 | /* set FUNC_MODE[24:23] = 2 |
| 707 | IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ |
| 708 | value |= 0x1000010; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 709 | status = vid_blk_write_word(dev, AFE_CTRL, value); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 710 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 711 | /* Tell DIF object to go to baseband mode */ |
| 712 | status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); |
| 713 | if (status < 0) { |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 714 | cx231xx_errdev("%s: cx231xx_dif set to By pass" |
| 715 | " mode- errCode [%d]!\n", |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 716 | __func__, status); |
| 717 | return status; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 718 | } |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 719 | |
| 720 | /* Read the DFE_CTRL1 register */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 721 | status = vid_blk_read_word(dev, DFE_CTRL1, &value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 722 | |
| 723 | /* enable the VBI_GATE_EN */ |
| 724 | value |= FLD_VBI_GATE_EN; |
| 725 | |
| 726 | /* Enable the auto-VGA enable */ |
| 727 | value |= FLD_VGA_AUTO_EN; |
| 728 | |
| 729 | /* Write it back */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 730 | status = vid_blk_write_word(dev, DFE_CTRL1, value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 731 | |
| 732 | /* Disable auto config of registers */ |
| 733 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 734 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 735 | MODE_CTRL, FLD_ACFG_DIS, |
| 736 | cx231xx_set_field(FLD_ACFG_DIS, 1)); |
| 737 | |
| 738 | /* Set YC input mode */ |
| 739 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 740 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 741 | MODE_CTRL, |
| 742 | FLD_INPUT_MODE, |
| 743 | cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); |
| 744 | |
| 745 | /* Chroma to ADC2 */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 746 | status = vid_blk_read_word(dev, AFE_CTRL, &value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 747 | value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ |
| 748 | |
| 749 | /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) |
| 750 | This sets them to use video |
| 751 | rather than audio. Only one of the two will be in use. */ |
| 752 | value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); |
| 753 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 754 | status = vid_blk_write_word(dev, AFE_CTRL, value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 755 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 756 | status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 757 | break; |
| 758 | case CX231XX_VMUX_TELEVISION: |
| 759 | case CX231XX_VMUX_CABLE: |
| 760 | default: |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 761 | switch (dev->model) { |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 762 | case CX231XX_BOARD_CNXT_CARRAERA: |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 763 | case CX231XX_BOARD_CNXT_RDE_250: |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 764 | case CX231XX_BOARD_CNXT_SHELBY: |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 765 | case CX231XX_BOARD_CNXT_RDU_250: |
| 766 | /* Disable the use of DIF */ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 767 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 768 | status = vid_blk_read_word(dev, AFE_CTRL, &value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 769 | value |= (0 << 13) | (1 << 4); |
| 770 | value &= ~(1 << 5); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 771 | |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 772 | /* set [24:23] [22:15] to 0 */ |
| 773 | value &= (~(0x1FF8000)); |
| 774 | /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ |
| 775 | value |= 0x1000000; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 776 | status = vid_blk_write_word(dev, AFE_CTRL, value); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 777 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 778 | status = vid_blk_read_word(dev, OUT_CTRL1, &value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 779 | value |= (1 << 7); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 780 | status = vid_blk_write_word(dev, OUT_CTRL1, value); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 781 | |
Devin Heitmueller | 8880621 | 2010-08-18 17:50:07 -0300 | [diff] [blame] | 782 | /* Set output mode */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 783 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 784 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 785 | OUT_CTRL1, FLD_OUT_MODE, |
Devin Heitmueller | 8880621 | 2010-08-18 17:50:07 -0300 | [diff] [blame] | 786 | dev->board.output_mode); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 787 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 788 | /* Tell DIF object to go to baseband mode */ |
| 789 | status = cx231xx_dif_set_standard(dev, |
| 790 | DIF_USE_BASEBAND); |
| 791 | if (status < 0) { |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 792 | cx231xx_errdev("%s: cx231xx_dif set to By pass" |
| 793 | " mode- errCode [%d]!\n", |
| 794 | __func__, status); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 795 | return status; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 796 | } |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 797 | |
| 798 | /* Read the DFE_CTRL1 register */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 799 | status = vid_blk_read_word(dev, DFE_CTRL1, &value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 800 | |
| 801 | /* enable the VBI_GATE_EN */ |
| 802 | value |= FLD_VBI_GATE_EN; |
| 803 | |
| 804 | /* Enable the auto-VGA enable */ |
| 805 | value |= FLD_VGA_AUTO_EN; |
| 806 | |
| 807 | /* Write it back */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 808 | status = vid_blk_write_word(dev, DFE_CTRL1, value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 809 | |
| 810 | /* Disable auto config of registers */ |
| 811 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 812 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 813 | MODE_CTRL, FLD_ACFG_DIS, |
| 814 | cx231xx_set_field(FLD_ACFG_DIS, 1)); |
| 815 | |
| 816 | /* Set CVBS input mode */ |
| 817 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 818 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 819 | MODE_CTRL, FLD_INPUT_MODE, |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 820 | cx231xx_set_field(FLD_INPUT_MODE, |
| 821 | INPUT_MODE_CVBS_0)); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 822 | break; |
| 823 | default: |
| 824 | /* Enable the DIF for the tuner */ |
| 825 | |
| 826 | /* Reinitialize the DIF */ |
| 827 | status = cx231xx_dif_set_standard(dev, dev->norm); |
| 828 | if (status < 0) { |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 829 | cx231xx_errdev("%s: cx231xx_dif set to By pass" |
| 830 | " mode- errCode [%d]!\n", |
| 831 | __func__, status); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 832 | return status; |
| 833 | } |
| 834 | |
| 835 | /* Make sure bypass is cleared */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 836 | status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 837 | |
| 838 | /* Clear the bypass bit */ |
| 839 | value &= ~FLD_DIF_DIF_BYPASS; |
| 840 | |
| 841 | /* Enable the use of the DIF block */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 842 | status = vid_blk_write_word(dev, DIF_MISC_CTRL, value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 843 | |
| 844 | /* Read the DFE_CTRL1 register */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 845 | status = vid_blk_read_word(dev, DFE_CTRL1, &value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 846 | |
| 847 | /* Disable the VBI_GATE_EN */ |
| 848 | value &= ~FLD_VBI_GATE_EN; |
| 849 | |
| 850 | /* Enable the auto-VGA enable, AGC, and |
| 851 | set the skip count to 2 */ |
| 852 | value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; |
| 853 | |
| 854 | /* Write it back */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 855 | status = vid_blk_write_word(dev, DFE_CTRL1, value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 856 | |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 857 | /* Wait until AGC locks up */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 858 | msleep(1); |
| 859 | |
| 860 | /* Disable the auto-VGA enable AGC */ |
| 861 | value &= ~(FLD_VGA_AUTO_EN); |
| 862 | |
| 863 | /* Write it back */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 864 | status = vid_blk_write_word(dev, DFE_CTRL1, value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 865 | |
| 866 | /* Enable Polaris B0 AGC output */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 867 | status = vid_blk_read_word(dev, PIN_CTRL, &value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 868 | value |= (FLD_OEF_AGC_RF) | |
| 869 | (FLD_OEF_AGC_IFVGA) | |
| 870 | (FLD_OEF_AGC_IF); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 871 | status = vid_blk_write_word(dev, PIN_CTRL, value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 872 | |
Devin Heitmueller | 8880621 | 2010-08-18 17:50:07 -0300 | [diff] [blame] | 873 | /* Set output mode */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 874 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 875 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 876 | OUT_CTRL1, FLD_OUT_MODE, |
Devin Heitmueller | 8880621 | 2010-08-18 17:50:07 -0300 | [diff] [blame] | 877 | dev->board.output_mode); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 878 | |
| 879 | /* Disable auto config of registers */ |
| 880 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 881 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 882 | MODE_CTRL, FLD_ACFG_DIS, |
| 883 | cx231xx_set_field(FLD_ACFG_DIS, 1)); |
| 884 | |
| 885 | /* Set CVBS input mode */ |
| 886 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 887 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 888 | MODE_CTRL, FLD_INPUT_MODE, |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 889 | cx231xx_set_field(FLD_INPUT_MODE, |
| 890 | INPUT_MODE_CVBS_0)); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 891 | |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 892 | /* Set some bits in AFE_CTRL so that channel 2 or 3 |
| 893 | * is ready to receive audio */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 894 | /* Clear clamp for channels 2 and 3 (bit 16-17) */ |
| 895 | /* Clear droop comp (bit 19-20) */ |
| 896 | /* Set VGA_SEL (for audio control) (bit 7-8) */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 897 | status = vid_blk_read_word(dev, AFE_CTRL, &value); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 898 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 899 | /*Set Func mode:01-DIF 10-baseband 11-YUV*/ |
| 900 | value &= (~(FLD_FUNC_MODE)); |
| 901 | value |= 0x800000; |
| 902 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 903 | value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; |
| 904 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 905 | status = vid_blk_write_word(dev, AFE_CTRL, value); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 906 | |
| 907 | if (dev->tuner_type == TUNER_NXP_TDA18271) { |
| 908 | status = vid_blk_read_word(dev, PIN_CTRL, |
| 909 | &value); |
| 910 | status = vid_blk_write_word(dev, PIN_CTRL, |
| 911 | (value & 0xFFFFFFEF)); |
| 912 | } |
| 913 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 914 | break; |
| 915 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 916 | } |
| 917 | break; |
| 918 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 919 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 920 | /* Set raw VBI mode */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 921 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 922 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 923 | OUT_CTRL1, FLD_VBIHACTRAW_EN, |
| 924 | cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 925 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 926 | status = vid_blk_read_word(dev, OUT_CTRL1, &value); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 927 | if (value & 0x02) { |
| 928 | value |= (1 << 19); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 929 | status = vid_blk_write_word(dev, OUT_CTRL1, value); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 930 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 931 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 932 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 933 | } |
| 934 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 935 | void cx231xx_enable656(struct cx231xx *dev) |
| 936 | { |
| 937 | u8 temp = 0; |
| 938 | int status; |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 939 | /*enable TS1 data[0:7] as output to export 656*/ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 940 | |
| 941 | status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF); |
| 942 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 943 | /*enable TS1 clock as output to export 656*/ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 944 | |
| 945 | status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); |
| 946 | temp = temp|0x04; |
| 947 | |
| 948 | status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); |
| 949 | |
| 950 | } |
| 951 | EXPORT_SYMBOL_GPL(cx231xx_enable656); |
| 952 | |
| 953 | void cx231xx_disable656(struct cx231xx *dev) |
| 954 | { |
| 955 | u8 temp = 0; |
| 956 | int status; |
| 957 | |
| 958 | |
| 959 | status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00); |
| 960 | |
| 961 | status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); |
| 962 | temp = temp&0xFB; |
| 963 | |
| 964 | status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); |
| 965 | } |
| 966 | EXPORT_SYMBOL_GPL(cx231xx_disable656); |
| 967 | |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 968 | /* |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 969 | * Handle any video-mode specific overrides that are different |
| 970 | * on a per video standards basis after touching the MODE_CTRL |
| 971 | * register which resets many values for autodetect |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 972 | */ |
| 973 | int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) |
| 974 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 975 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 976 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 977 | cx231xx_info("do_mode_ctrl_overrides : 0x%x\n", |
| 978 | (unsigned int)dev->norm); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 979 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 980 | /* Change the DFE_CTRL3 bp_percent to fix flagging */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 981 | status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 982 | |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 983 | if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 984 | cx231xx_info("do_mode_ctrl_overrides NTSC\n"); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 985 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 986 | /* Move the close caption lines out of active video, |
| 987 | adjust the active video start point */ |
| 988 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 989 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 990 | VERT_TIM_CTRL, |
| 991 | FLD_VBLANK_CNT, 0x18); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 992 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 993 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 994 | VERT_TIM_CTRL, |
| 995 | FLD_VACTIVE_CNT, |
Devin Heitmueller | 435b4f7 | 2010-07-09 13:29:31 -0300 | [diff] [blame] | 996 | 0x1E7000); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 997 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 998 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 999 | VERT_TIM_CTRL, |
| 1000 | FLD_V656BLANK_CNT, |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1001 | 0x1C000000); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1002 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1003 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1004 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1005 | HORIZ_TIM_CTRL, |
| 1006 | FLD_HBLANK_CNT, |
| 1007 | cx231xx_set_field |
| 1008 | (FLD_HBLANK_CNT, 0x79)); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1009 | |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 1010 | } else if (dev->norm & V4L2_STD_SECAM) { |
| 1011 | cx231xx_info("do_mode_ctrl_overrides SECAM\n"); |
| 1012 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1013 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1014 | VERT_TIM_CTRL, |
Devin Heitmueller | 6af8cc0 | 2010-08-19 15:18:32 -0300 | [diff] [blame] | 1015 | FLD_VBLANK_CNT, 0x20); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1016 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| 1017 | VID_BLK_I2C_ADDRESS, |
| 1018 | VERT_TIM_CTRL, |
Devin Heitmueller | 222c435 | 2010-08-19 13:45:56 -0300 | [diff] [blame] | 1019 | FLD_VACTIVE_CNT, |
| 1020 | cx231xx_set_field |
| 1021 | (FLD_VACTIVE_CNT, |
Devin Heitmueller | 6af8cc0 | 2010-08-19 15:18:32 -0300 | [diff] [blame] | 1022 | 0x244)); |
Devin Heitmueller | 222c435 | 2010-08-19 13:45:56 -0300 | [diff] [blame] | 1023 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| 1024 | VID_BLK_I2C_ADDRESS, |
| 1025 | VERT_TIM_CTRL, |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1026 | FLD_V656BLANK_CNT, |
| 1027 | cx231xx_set_field |
| 1028 | (FLD_V656BLANK_CNT, |
Devin Heitmueller | 6af8cc0 | 2010-08-19 15:18:32 -0300 | [diff] [blame] | 1029 | 0x24)); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1030 | /* Adjust the active video horizontal start point */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1031 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1032 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1033 | HORIZ_TIM_CTRL, |
| 1034 | FLD_HBLANK_CNT, |
| 1035 | cx231xx_set_field |
| 1036 | (FLD_HBLANK_CNT, 0x85)); |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 1037 | } else { |
| 1038 | cx231xx_info("do_mode_ctrl_overrides PAL\n"); |
| 1039 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1040 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1041 | VERT_TIM_CTRL, |
Devin Heitmueller | 6af8cc0 | 2010-08-19 15:18:32 -0300 | [diff] [blame] | 1042 | FLD_VBLANK_CNT, 0x20); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1043 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| 1044 | VID_BLK_I2C_ADDRESS, |
| 1045 | VERT_TIM_CTRL, |
Devin Heitmueller | 222c435 | 2010-08-19 13:45:56 -0300 | [diff] [blame] | 1046 | FLD_VACTIVE_CNT, |
| 1047 | cx231xx_set_field |
| 1048 | (FLD_VACTIVE_CNT, |
Devin Heitmueller | 6af8cc0 | 2010-08-19 15:18:32 -0300 | [diff] [blame] | 1049 | 0x244)); |
Devin Heitmueller | 222c435 | 2010-08-19 13:45:56 -0300 | [diff] [blame] | 1050 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| 1051 | VID_BLK_I2C_ADDRESS, |
| 1052 | VERT_TIM_CTRL, |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1053 | FLD_V656BLANK_CNT, |
| 1054 | cx231xx_set_field |
| 1055 | (FLD_V656BLANK_CNT, |
Devin Heitmueller | 6af8cc0 | 2010-08-19 15:18:32 -0300 | [diff] [blame] | 1056 | 0x24)); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1057 | /* Adjust the active video horizontal start point */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1058 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1059 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1060 | HORIZ_TIM_CTRL, |
| 1061 | FLD_HBLANK_CNT, |
| 1062 | cx231xx_set_field |
| 1063 | (FLD_HBLANK_CNT, 0x85)); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1064 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1065 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1066 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1067 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1068 | } |
| 1069 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1070 | int cx231xx_unmute_audio(struct cx231xx *dev) |
| 1071 | { |
| 1072 | return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24); |
| 1073 | } |
| 1074 | EXPORT_SYMBOL_GPL(cx231xx_unmute_audio); |
| 1075 | |
| 1076 | int stopAudioFirmware(struct cx231xx *dev) |
| 1077 | { |
| 1078 | return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03); |
| 1079 | } |
| 1080 | |
| 1081 | int restartAudioFirmware(struct cx231xx *dev) |
| 1082 | { |
| 1083 | return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13); |
| 1084 | } |
| 1085 | |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1086 | int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) |
| 1087 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1088 | int status = 0; |
| 1089 | enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1090 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1091 | switch (INPUT(input)->amux) { |
| 1092 | case CX231XX_AMUX_VIDEO: |
| 1093 | ainput = AUDIO_INPUT_TUNER_TV; |
| 1094 | break; |
| 1095 | case CX231XX_AMUX_LINE_IN: |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1096 | status = cx231xx_i2s_blk_set_audio_input(dev, input); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1097 | ainput = AUDIO_INPUT_LINE; |
| 1098 | break; |
| 1099 | default: |
| 1100 | break; |
| 1101 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1102 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1103 | status = cx231xx_set_audio_decoder_input(dev, ainput); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1104 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1105 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1106 | } |
| 1107 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1108 | int cx231xx_set_audio_decoder_input(struct cx231xx *dev, |
| 1109 | enum AUDIO_INPUT audio_input) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1110 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1111 | u32 dwval; |
| 1112 | int status; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1113 | u8 gen_ctrl; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1114 | u32 value = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1115 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1116 | /* Put it in soft reset */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1117 | status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1118 | gen_ctrl |= 1; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1119 | status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1120 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1121 | switch (audio_input) { |
| 1122 | case AUDIO_INPUT_LINE: |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1123 | /* setup AUD_IO control from Merlin paralle output */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1124 | value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, |
| 1125 | AUD_CHAN_SRC_PARALLEL); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1126 | status = vid_blk_write_word(dev, AUD_IO_CTRL, value); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1127 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1128 | /* setup input to Merlin, SRC2 connect to AC97 |
| 1129 | bypass upsample-by-2, slave mode, sony mode, left justify |
| 1130 | adr 091c, dat 01000000 */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1131 | status = vid_blk_read_word(dev, AC97_CTL, &dwval); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1132 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1133 | status = vid_blk_write_word(dev, AC97_CTL, |
| 1134 | (dwval | FLD_AC97_UP2X_BYPASS)); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1135 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1136 | /* select the parallel1 and SRC3 */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1137 | status = vid_blk_write_word(dev, BAND_OUT_SEL, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1138 | cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | |
| 1139 | cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1140 | cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0)); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1141 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1142 | /* unmute all, AC97 in, independence mode |
| 1143 | adr 08d0, data 0x00063073 */ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1144 | status = vid_blk_write_word(dev, DL_CTL, 0x3000001); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1145 | status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1146 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1147 | /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1148 | status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval); |
| 1149 | status = vid_blk_write_word(dev, PATH1_VOL_CTL, |
| 1150 | (dwval | FLD_PATH1_AVC_THRESHOLD)); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1151 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1152 | /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1153 | status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval); |
| 1154 | status = vid_blk_write_word(dev, PATH1_SC_CTL, |
| 1155 | (dwval | FLD_PATH1_SC_THRESHOLD)); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1156 | break; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1157 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1158 | case AUDIO_INPUT_TUNER_TV: |
| 1159 | default: |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1160 | status = stopAudioFirmware(dev); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1161 | /* Setup SRC sources and clocks */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1162 | status = vid_blk_write_word(dev, BAND_OUT_SEL, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1163 | cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | |
| 1164 | cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | |
| 1165 | cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | |
| 1166 | cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) | |
| 1167 | cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) | |
| 1168 | cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) | |
| 1169 | cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) | |
| 1170 | cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) | |
| 1171 | cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) | |
| 1172 | cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | |
| 1173 | cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | |
| 1174 | cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1175 | cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01)); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1176 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1177 | /* Setup the AUD_IO control */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1178 | status = vid_blk_write_word(dev, AUD_IO_CTRL, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1179 | cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | |
| 1180 | cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | |
| 1181 | cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | |
| 1182 | cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1183 | cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03)); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1184 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1185 | status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1186 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1187 | /* setAudioStandard(_audio_standard); */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1188 | status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1189 | |
| 1190 | status = restartAudioFirmware(dev); |
| 1191 | |
Devin Heitmueller | 8aed3f4 | 2010-08-19 10:55:05 -0300 | [diff] [blame] | 1192 | switch (dev->board.tuner_type) { |
| 1193 | case TUNER_XC5000: |
| 1194 | /* SIF passthrough at 28.6363 MHz sample rate */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1195 | status = cx231xx_read_modify_write_i2c_dword(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1196 | VID_BLK_I2C_ADDRESS, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1197 | CHIP_CTRL, |
| 1198 | FLD_SIF_EN, |
| 1199 | cx231xx_set_field(FLD_SIF_EN, 1)); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1200 | break; |
Devin Heitmueller | 8aed3f4 | 2010-08-19 10:55:05 -0300 | [diff] [blame] | 1201 | case TUNER_NXP_TDA18271: |
| 1202 | /* Normal mode: SIF passthrough at 14.32 MHz */ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1203 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| 1204 | VID_BLK_I2C_ADDRESS, |
| 1205 | CHIP_CTRL, |
| 1206 | FLD_SIF_EN, |
| 1207 | cx231xx_set_field(FLD_SIF_EN, 0)); |
| 1208 | break; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1209 | default: |
Devin Heitmueller | 8aed3f4 | 2010-08-19 10:55:05 -0300 | [diff] [blame] | 1210 | /* This is just a casual suggestion to people adding |
| 1211 | new boards in case they use a tuner type we don't |
| 1212 | currently know about */ |
| 1213 | printk(KERN_INFO "Unknown tuner type configuring SIF"); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1214 | break; |
| 1215 | } |
| 1216 | break; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1217 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1218 | case AUDIO_INPUT_TUNER_FM: |
| 1219 | /* use SIF for FM radio |
| 1220 | setupFM(); |
| 1221 | setAudioStandard(_audio_standard); |
| 1222 | */ |
| 1223 | break; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1224 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1225 | case AUDIO_INPUT_MUTE: |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1226 | status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1227 | break; |
| 1228 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1229 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1230 | /* Take it out of soft reset */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1231 | status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1232 | gen_ctrl &= ~1; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1233 | status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1234 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1235 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1236 | } |
| 1237 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1238 | /****************************************************************************** |
| 1239 | * C H I P Specific C O N T R O L functions * |
| 1240 | ******************************************************************************/ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1241 | int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) |
| 1242 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1243 | u32 value; |
| 1244 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1245 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1246 | status = vid_blk_read_word(dev, PIN_CTRL, &value); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1247 | value |= (~dev->board.ctl_pin_status_mask); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1248 | status = vid_blk_write_word(dev, PIN_CTRL, value); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1249 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1250 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1251 | } |
| 1252 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1253 | int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, |
| 1254 | u8 analog_or_digital) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1255 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1256 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1257 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1258 | /* first set the direction to output */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1259 | status = cx231xx_set_gpio_direction(dev, |
| 1260 | dev->board. |
| 1261 | agc_analog_digital_select_gpio, 1); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1262 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1263 | /* 0 - demod ; 1 - Analog mode */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1264 | status = cx231xx_set_gpio_value(dev, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1265 | dev->board.agc_analog_digital_select_gpio, |
| 1266 | analog_or_digital); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1267 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1268 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1269 | } |
| 1270 | |
Mauro Carvalho Chehab | a6f6fb9 | 2010-09-26 20:38:24 -0300 | [diff] [blame] | 1271 | int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1272 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1273 | u8 value[4] = { 0, 0, 0, 0 }; |
| 1274 | int status = 0; |
Mauro Carvalho Chehab | a6f6fb9 | 2010-09-26 20:38:24 -0300 | [diff] [blame] | 1275 | bool current_is_port_3; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1276 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1277 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, |
| 1278 | PWR_CTL_EN, value, 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1279 | if (status < 0) |
| 1280 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1281 | |
Mauro Carvalho Chehab | a6f6fb9 | 2010-09-26 20:38:24 -0300 | [diff] [blame] | 1282 | current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false; |
| 1283 | |
| 1284 | /* Just return, if already using the right port */ |
| 1285 | if (current_is_port_3 == is_port_3) |
| 1286 | return 0; |
| 1287 | |
| 1288 | if (is_port_3) |
| 1289 | value[0] |= I2C_DEMOD_EN; |
| 1290 | else |
| 1291 | value[0] &= ~I2C_DEMOD_EN; |
| 1292 | |
| 1293 | cx231xx_info("Changing the i2c master port to %d\n", |
| 1294 | is_port_3 ? 3 : 1); |
| 1295 | |
| 1296 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 1297 | PWR_CTL_EN, value, 4); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1298 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1299 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1300 | |
| 1301 | } |
Mauro Carvalho Chehab | a6f6fb9 | 2010-09-26 20:38:24 -0300 | [diff] [blame] | 1302 | EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3); |
| 1303 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1304 | void update_HH_register_after_set_DIF(struct cx231xx *dev) |
| 1305 | { |
| 1306 | /* |
| 1307 | u8 status = 0; |
| 1308 | u32 value = 0; |
| 1309 | |
| 1310 | vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F); |
| 1311 | vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11); |
| 1312 | vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06); |
| 1313 | |
| 1314 | status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); |
| 1315 | vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); |
| 1316 | status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); |
| 1317 | */ |
| 1318 | } |
| 1319 | |
| 1320 | void cx231xx_dump_HH_reg(struct cx231xx *dev) |
| 1321 | { |
| 1322 | u8 status = 0; |
| 1323 | u32 value = 0; |
| 1324 | u16 i = 0; |
| 1325 | |
| 1326 | value = 0x45005390; |
| 1327 | status = vid_blk_write_word(dev, 0x104, value); |
| 1328 | |
| 1329 | for (i = 0x100; i < 0x140; i++) { |
| 1330 | status = vid_blk_read_word(dev, i, &value); |
| 1331 | cx231xx_info("reg0x%x=0x%x\n", i, value); |
| 1332 | i = i+3; |
| 1333 | } |
| 1334 | |
| 1335 | for (i = 0x300; i < 0x400; i++) { |
| 1336 | status = vid_blk_read_word(dev, i, &value); |
| 1337 | cx231xx_info("reg0x%x=0x%x\n", i, value); |
| 1338 | i = i+3; |
| 1339 | } |
| 1340 | |
| 1341 | for (i = 0x400; i < 0x440; i++) { |
| 1342 | status = vid_blk_read_word(dev, i, &value); |
| 1343 | cx231xx_info("reg0x%x=0x%x\n", i, value); |
| 1344 | i = i+3; |
| 1345 | } |
| 1346 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1347 | status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); |
| 1348 | cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); |
| 1349 | vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); |
| 1350 | status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); |
| 1351 | cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1352 | } |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1353 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1354 | void cx231xx_dump_SC_reg(struct cx231xx *dev) |
| 1355 | { |
| 1356 | u8 value[4] = { 0, 0, 0, 0 }; |
| 1357 | int status = 0; |
| 1358 | cx231xx_info("cx231xx_dump_SC_reg %s!\n", __TIME__); |
| 1359 | |
| 1360 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, |
| 1361 | value, 4); |
| 1362 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0], |
| 1363 | value[1], value[2], value[3]); |
| 1364 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG, |
| 1365 | value, 4); |
| 1366 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0], |
| 1367 | value[1], value[2], value[3]); |
| 1368 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG, |
| 1369 | value, 4); |
| 1370 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0], |
| 1371 | value[1], value[2], value[3]); |
| 1372 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG, |
| 1373 | value, 4); |
| 1374 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0], |
| 1375 | value[1], value[2], value[3]); |
| 1376 | |
| 1377 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG, |
| 1378 | value, 4); |
| 1379 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0], |
| 1380 | value[1], value[2], value[3]); |
| 1381 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG, |
| 1382 | value, 4); |
| 1383 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0], |
| 1384 | value[1], value[2], value[3]); |
| 1385 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, |
| 1386 | value, 4); |
| 1387 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0], |
| 1388 | value[1], value[2], value[3]); |
| 1389 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1, |
| 1390 | value, 4); |
| 1391 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0], |
| 1392 | value[1], value[2], value[3]); |
| 1393 | |
| 1394 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2, |
| 1395 | value, 4); |
| 1396 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0], |
| 1397 | value[1], value[2], value[3]); |
| 1398 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3, |
| 1399 | value, 4); |
| 1400 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0], |
| 1401 | value[1], value[2], value[3]); |
| 1402 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0, |
| 1403 | value, 4); |
| 1404 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0], |
| 1405 | value[1], value[2], value[3]); |
| 1406 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1, |
| 1407 | value, 4); |
| 1408 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0], |
| 1409 | value[1], value[2], value[3]); |
| 1410 | |
| 1411 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2, |
| 1412 | value, 4); |
| 1413 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0], |
| 1414 | value[1], value[2], value[3]); |
| 1415 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN, |
| 1416 | value, 4); |
| 1417 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0], |
| 1418 | value[1], value[2], value[3]); |
| 1419 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG, |
| 1420 | value, 4); |
| 1421 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0], |
| 1422 | value[1], value[2], value[3]); |
| 1423 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1, |
| 1424 | value, 4); |
| 1425 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0], |
| 1426 | value[1], value[2], value[3]); |
| 1427 | |
| 1428 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2, |
| 1429 | value, 4); |
| 1430 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0], |
| 1431 | value[1], value[2], value[3]); |
| 1432 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, |
| 1433 | value, 4); |
| 1434 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0], |
| 1435 | value[1], value[2], value[3]); |
| 1436 | |
| 1437 | |
| 1438 | } |
| 1439 | |
| 1440 | void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev) |
| 1441 | |
| 1442 | { |
| 1443 | u8 status = 0; |
| 1444 | u8 value = 0; |
| 1445 | |
| 1446 | |
| 1447 | |
| 1448 | status = afe_read_byte(dev, ADC_STATUS2_CH3, &value); |
| 1449 | value = (value & 0xFE)|0x01; |
| 1450 | status = afe_write_byte(dev, ADC_STATUS2_CH3, value); |
| 1451 | |
| 1452 | status = afe_read_byte(dev, ADC_STATUS2_CH3, &value); |
| 1453 | value = (value & 0xFE)|0x00; |
| 1454 | status = afe_write_byte(dev, ADC_STATUS2_CH3, value); |
| 1455 | |
| 1456 | |
| 1457 | /* |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1458 | config colibri to lo-if mode |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1459 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1460 | FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce |
| 1461 | the diff IF input by half, |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1462 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1463 | for low-if agc defect |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1464 | */ |
| 1465 | |
| 1466 | status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value); |
| 1467 | value = (value & 0xFC)|0x00; |
| 1468 | status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value); |
| 1469 | |
| 1470 | status = afe_read_byte(dev, ADC_INPUT_CH3, &value); |
| 1471 | value = (value & 0xF9)|0x02; |
| 1472 | status = afe_write_byte(dev, ADC_INPUT_CH3, value); |
| 1473 | |
| 1474 | status = afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value); |
| 1475 | value = (value & 0xFB)|0x04; |
| 1476 | status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, value); |
| 1477 | |
| 1478 | status = afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value); |
| 1479 | value = (value & 0xFC)|0x03; |
| 1480 | status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value); |
| 1481 | |
| 1482 | status = afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value); |
| 1483 | value = (value & 0xFB)|0x04; |
| 1484 | status = afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value); |
| 1485 | |
| 1486 | status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); |
| 1487 | value = (value & 0xF8)|0x06; |
| 1488 | status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); |
| 1489 | |
| 1490 | status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); |
| 1491 | value = (value & 0x8F)|0x40; |
| 1492 | status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); |
| 1493 | |
| 1494 | status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value); |
| 1495 | value = (value & 0xDF)|0x20; |
| 1496 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value); |
| 1497 | } |
| 1498 | |
| 1499 | void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq, |
| 1500 | u8 spectral_invert, u32 mode) |
| 1501 | { |
Devin Heitmueller | 2ded0fe | 2010-08-19 11:09:28 -0300 | [diff] [blame] | 1502 | u32 colibri_carrier_offset = 0; |
| 1503 | u8 status = 0; |
| 1504 | u32 func_mode = 0x01; /* Device has a DIF if this function is called */ |
| 1505 | u32 standard = 0; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1506 | u8 value[4] = { 0, 0, 0, 0 }; |
| 1507 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1508 | cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n"); |
Devin Heitmueller | 2ded0fe | 2010-08-19 11:09:28 -0300 | [diff] [blame] | 1509 | value[0] = (u8) 0x6F; |
| 1510 | value[1] = (u8) 0x6F; |
| 1511 | value[2] = (u8) 0x6F; |
| 1512 | value[3] = (u8) 0x6F; |
| 1513 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 1514 | PWR_CTL_EN, value, 4); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1515 | |
| 1516 | /*Set colibri for low IF*/ |
| 1517 | status = cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF); |
| 1518 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1519 | /* Set C2HH for low IF operation.*/ |
| 1520 | standard = dev->norm; |
| 1521 | status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, |
Devin Heitmueller | 2ded0fe | 2010-08-19 11:09:28 -0300 | [diff] [blame] | 1522 | func_mode, standard); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1523 | |
| 1524 | /* Get colibri offsets.*/ |
| 1525 | colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode, |
Devin Heitmueller | 2ded0fe | 2010-08-19 11:09:28 -0300 | [diff] [blame] | 1526 | standard); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1527 | |
| 1528 | cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n", |
Devin Heitmueller | 2ded0fe | 2010-08-19 11:09:28 -0300 | [diff] [blame] | 1529 | colibri_carrier_offset, standard); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1530 | |
| 1531 | /* Set the band Pass filter for DIF*/ |
Devin Heitmueller | 2ded0fe | 2010-08-19 11:09:28 -0300 | [diff] [blame] | 1532 | cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset), |
| 1533 | spectral_invert, mode); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1534 | } |
| 1535 | |
| 1536 | u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd) |
| 1537 | { |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1538 | u32 colibri_carrier_offset = 0; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1539 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1540 | if (mode == TUNER_MODE_FM_RADIO) { |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1541 | colibri_carrier_offset = 1100000; |
Mauro Carvalho Chehab | 0f861583 | 2010-10-09 12:04:25 -0300 | [diff] [blame] | 1542 | } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) { |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1543 | colibri_carrier_offset = 4832000; /*4.83MHz */ |
| 1544 | } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { |
| 1545 | colibri_carrier_offset = 2700000; /*2.70MHz */ |
| 1546 | } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I |
| 1547 | | V4L2_STD_SECAM)) { |
| 1548 | colibri_carrier_offset = 2100000; /*2.10MHz */ |
| 1549 | } |
| 1550 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1551 | return colibri_carrier_offset; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1552 | } |
| 1553 | |
| 1554 | void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq, |
| 1555 | u8 spectral_invert, u32 mode) |
| 1556 | { |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1557 | unsigned long pll_freq_word; |
| 1558 | int status = 0; |
| 1559 | u32 dif_misc_ctrl_value = 0; |
| 1560 | u64 pll_freq_u64 = 0; |
| 1561 | u32 i = 0; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1562 | |
| 1563 | cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n", |
| 1564 | if_freq, spectral_invert, mode); |
| 1565 | |
| 1566 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1567 | if (mode == TUNER_MODE_FM_RADIO) { |
| 1568 | pll_freq_word = 0x905A1CAC; |
| 1569 | status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1570 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1571 | } else /*KSPROPERTY_TUNER_MODE_TV*/{ |
| 1572 | /* Calculate the PLL frequency word based on the adjusted if_freq*/ |
| 1573 | pll_freq_word = if_freq; |
| 1574 | pll_freq_u64 = (u64)pll_freq_word << 28L; |
| 1575 | do_div(pll_freq_u64, 50000000); |
| 1576 | pll_freq_word = (u32)pll_freq_u64; |
| 1577 | /*pll_freq_word = 0x3463497;*/ |
| 1578 | status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1579 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1580 | if (spectral_invert) { |
| 1581 | if_freq -= 400000; |
| 1582 | /* Enable Spectral Invert*/ |
| 1583 | status = vid_blk_read_word(dev, DIF_MISC_CTRL, |
| 1584 | &dif_misc_ctrl_value); |
| 1585 | dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000; |
| 1586 | status = vid_blk_write_word(dev, DIF_MISC_CTRL, |
| 1587 | dif_misc_ctrl_value); |
| 1588 | } else { |
| 1589 | if_freq += 400000; |
| 1590 | /* Disable Spectral Invert*/ |
| 1591 | status = vid_blk_read_word(dev, DIF_MISC_CTRL, |
| 1592 | &dif_misc_ctrl_value); |
| 1593 | dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF; |
| 1594 | status = vid_blk_write_word(dev, DIF_MISC_CTRL, |
| 1595 | dif_misc_ctrl_value); |
| 1596 | } |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1597 | |
| 1598 | if_freq = (if_freq/100000)*100000; |
| 1599 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1600 | if (if_freq < 3000000) |
| 1601 | if_freq = 3000000; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1602 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1603 | if (if_freq > 16000000) |
| 1604 | if_freq = 16000000; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1605 | } |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1606 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1607 | cx231xx_info("Enter IF=%zd\n", |
| 1608 | sizeof(Dif_set_array)/sizeof(struct dif_settings)); |
| 1609 | for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) { |
| 1610 | if (Dif_set_array[i].if_freq == if_freq) { |
| 1611 | status = vid_blk_write_word(dev, |
| 1612 | Dif_set_array[i].register_address, Dif_set_array[i].value); |
| 1613 | } |
| 1614 | } |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1615 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1616 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1617 | /****************************************************************************** |
| 1618 | * D I F - B L O C K C O N T R O L functions * |
| 1619 | ******************************************************************************/ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1620 | int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1621 | u32 function_mode, u32 standard) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1622 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1623 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1624 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1625 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1626 | if (mode == V4L2_TUNER_RADIO) { |
| 1627 | /* C2HH */ |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1628 | /* lo if big signal */ |
| 1629 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1630 | VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1631 | AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); |
| 1632 | /* FUNC_MODE = DIF */ |
| 1633 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1634 | VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1635 | AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); |
| 1636 | /* IF_MODE */ |
| 1637 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1638 | VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1639 | AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); |
| 1640 | /* no inv */ |
| 1641 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1642 | VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1643 | AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 1644 | } else if (standard != DIF_USE_BASEBAND) { |
| 1645 | if (standard & V4L2_STD_MN) { |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1646 | /* lo if big signal */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1647 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1648 | VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1649 | AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); |
| 1650 | /* FUNC_MODE = DIF */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1651 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1652 | VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1653 | AFE_CTRL_C2HH_SRC_CTRL, 23, 24, |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1654 | function_mode); |
| 1655 | /* IF_MODE */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1656 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1657 | VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1658 | AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); |
| 1659 | /* no inv */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1660 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1661 | VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1662 | AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); |
| 1663 | /* 0x124, AUD_CHAN1_SRC = 0x3 */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1664 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1665 | VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1666 | AUD_IO_CTRL, 0, 31, 0x00000003); |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 1667 | } else if ((standard == V4L2_STD_PAL_I) | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1668 | (standard & V4L2_STD_PAL_D) | |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 1669 | (standard & V4L2_STD_SECAM)) { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1670 | /* C2HH setup */ |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1671 | /* lo if big signal */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1672 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1673 | VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1674 | AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); |
| 1675 | /* FUNC_MODE = DIF */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1676 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1677 | VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1678 | AFE_CTRL_C2HH_SRC_CTRL, 23, 24, |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1679 | function_mode); |
| 1680 | /* IF_MODE */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1681 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1682 | VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1683 | AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); |
| 1684 | /* no inv */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1685 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1686 | VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 1687 | AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 1688 | } else { |
| 1689 | /* default PAL BG */ |
| 1690 | /* C2HH setup */ |
| 1691 | /* lo if big signal */ |
| 1692 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1693 | VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 1694 | AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); |
| 1695 | /* FUNC_MODE = DIF */ |
| 1696 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1697 | VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 1698 | AFE_CTRL_C2HH_SRC_CTRL, 23, 24, |
| 1699 | function_mode); |
| 1700 | /* IF_MODE */ |
| 1701 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1702 | VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 1703 | AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); |
| 1704 | /* no inv */ |
| 1705 | status = cx231xx_reg_mask_write(dev, |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1706 | VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 1707 | AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1708 | } |
| 1709 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1710 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1711 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1712 | } |
| 1713 | |
| 1714 | int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) |
| 1715 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1716 | int status = 0; |
| 1717 | u32 dif_misc_ctrl_value = 0; |
| 1718 | u32 func_mode = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1719 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1720 | cx231xx_info("%s: setStandard to %x\n", __func__, standard); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1721 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1722 | status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1723 | if (standard != DIF_USE_BASEBAND) |
| 1724 | dev->norm = standard; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1725 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1726 | switch (dev->model) { |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1727 | case CX231XX_BOARD_CNXT_CARRAERA: |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1728 | case CX231XX_BOARD_CNXT_RDE_250: |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1729 | case CX231XX_BOARD_CNXT_SHELBY: |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1730 | case CX231XX_BOARD_CNXT_RDU_250: |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1731 | case CX231XX_BOARD_CNXT_VIDEO_GRABBER: |
Michael Krufky | 1a50fdd | 2010-07-06 18:23:53 -0300 | [diff] [blame] | 1732 | case CX231XX_BOARD_HAUPPAUGE_EXETER: |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1733 | func_mode = 0x03; |
| 1734 | break; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1735 | case CX231XX_BOARD_CNXT_RDE_253S: |
| 1736 | case CX231XX_BOARD_CNXT_RDU_253S: |
| 1737 | func_mode = 0x01; |
| 1738 | break; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1739 | default: |
| 1740 | func_mode = 0x01; |
| 1741 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1742 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1743 | status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1744 | func_mode, standard); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1745 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1746 | if (standard == DIF_USE_BASEBAND) { /* base band */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1747 | /* There is a different SRC_PHASE_INC value |
| 1748 | for baseband vs. DIF */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1749 | status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83); |
| 1750 | status = vid_blk_read_word(dev, DIF_MISC_CTRL, |
| 1751 | &dif_misc_ctrl_value); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1752 | dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1753 | status = vid_blk_write_word(dev, DIF_MISC_CTRL, |
| 1754 | dif_misc_ctrl_value); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1755 | } else if (standard & V4L2_STD_PAL_D) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1756 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1757 | DIF_PLL_CTRL, 0, 31, 0x6503bc0c); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1758 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1759 | DIF_PLL_CTRL1, 0, 31, 0xbd038c85); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1760 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1761 | DIF_PLL_CTRL2, 0, 31, 0x1db4640a); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1762 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1763 | DIF_PLL_CTRL3, 0, 31, 0x00008800); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1764 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1765 | DIF_AGC_IF_REF, 0, 31, 0x444C1380); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1766 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1767 | DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1768 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1769 | DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1770 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1771 | DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1772 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1773 | DIF_AGC_IF_INT_CURRENT, 0, 31, |
| 1774 | 0x26001700); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1775 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1776 | DIF_AGC_RF_CURRENT, 0, 31, |
| 1777 | 0x00002660); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1778 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1779 | DIF_VIDEO_AGC_CTRL, 0, 31, |
| 1780 | 0x72500800); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1781 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1782 | DIF_VID_AUD_OVERRIDE, 0, 31, |
| 1783 | 0x27000100); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1784 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1785 | DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1786 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1787 | DIF_COMP_FLT_CTRL, 0, 31, |
| 1788 | 0x00000000); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1789 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1790 | DIF_SRC_PHASE_INC, 0, 31, |
| 1791 | 0x1befbf06); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1792 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1793 | DIF_SRC_GAIN_CONTROL, 0, 31, |
| 1794 | 0x000035e8); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1795 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1796 | DIF_RPT_VARIANCE, 0, 31, 0x00000000); |
| 1797 | /* Save the Spec Inversion value */ |
| 1798 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; |
| 1799 | dif_misc_ctrl_value |= 0x3a023F11; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1800 | } else if (standard & V4L2_STD_PAL_I) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1801 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1802 | DIF_PLL_CTRL, 0, 31, 0x6503bc0c); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1803 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1804 | DIF_PLL_CTRL1, 0, 31, 0xbd038c85); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1805 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1806 | DIF_PLL_CTRL2, 0, 31, 0x1db4640a); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1807 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1808 | DIF_PLL_CTRL3, 0, 31, 0x00008800); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1809 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1810 | DIF_AGC_IF_REF, 0, 31, 0x444C1380); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1811 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1812 | DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1813 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1814 | DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1815 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1816 | DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1817 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1818 | DIF_AGC_IF_INT_CURRENT, 0, 31, |
| 1819 | 0x26001700); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1820 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1821 | DIF_AGC_RF_CURRENT, 0, 31, |
| 1822 | 0x00002660); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1823 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1824 | DIF_VIDEO_AGC_CTRL, 0, 31, |
| 1825 | 0x72500800); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1826 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1827 | DIF_VID_AUD_OVERRIDE, 0, 31, |
| 1828 | 0x27000100); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1829 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1830 | DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1831 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1832 | DIF_COMP_FLT_CTRL, 0, 31, |
| 1833 | 0x00000000); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1834 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1835 | DIF_SRC_PHASE_INC, 0, 31, |
| 1836 | 0x1befbf06); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1837 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1838 | DIF_SRC_GAIN_CONTROL, 0, 31, |
| 1839 | 0x000035e8); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1840 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1841 | DIF_RPT_VARIANCE, 0, 31, 0x00000000); |
| 1842 | /* Save the Spec Inversion value */ |
| 1843 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; |
| 1844 | dif_misc_ctrl_value |= 0x3a033F11; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1845 | } else if (standard & V4L2_STD_PAL_M) { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1846 | /* improved Low Frequency Phase Noise */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1847 | status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); |
| 1848 | status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); |
| 1849 | status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); |
| 1850 | status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); |
| 1851 | status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); |
| 1852 | status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, |
| 1853 | 0x26001700); |
| 1854 | status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, |
| 1855 | 0x00002660); |
| 1856 | status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, |
| 1857 | 0x72500800); |
| 1858 | status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, |
| 1859 | 0x27000100); |
| 1860 | status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d); |
| 1861 | status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, |
| 1862 | 0x009f50c1); |
| 1863 | status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, |
| 1864 | 0x1befbf06); |
| 1865 | status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, |
| 1866 | 0x000035e8); |
| 1867 | status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, |
| 1868 | 0x00000000); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1869 | /* Save the Spec Inversion value */ |
| 1870 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; |
| 1871 | dif_misc_ctrl_value |= 0x3A0A3F10; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1872 | } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1873 | /* improved Low Frequency Phase Noise */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1874 | status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); |
| 1875 | status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); |
| 1876 | status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); |
| 1877 | status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); |
| 1878 | status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); |
| 1879 | status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, |
| 1880 | 0x26001700); |
| 1881 | status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, |
| 1882 | 0x00002660); |
| 1883 | status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, |
| 1884 | 0x72500800); |
| 1885 | status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, |
| 1886 | 0x27000100); |
| 1887 | status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, |
| 1888 | 0x012c405d); |
| 1889 | status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, |
| 1890 | 0x009f50c1); |
| 1891 | status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, |
| 1892 | 0x1befbf06); |
| 1893 | status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, |
| 1894 | 0x000035e8); |
| 1895 | status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, |
| 1896 | 0x00000000); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1897 | /* Save the Spec Inversion value */ |
| 1898 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; |
| 1899 | dif_misc_ctrl_value = 0x3A093F10; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1900 | } else if (standard & |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 1901 | (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | |
| 1902 | V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1903 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1904 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1905 | DIF_PLL_CTRL, 0, 31, 0x6503bc0c); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1906 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1907 | DIF_PLL_CTRL1, 0, 31, 0xbd038c85); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1908 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1909 | DIF_PLL_CTRL2, 0, 31, 0x1db4640a); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1910 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1911 | DIF_PLL_CTRL3, 0, 31, 0x00008800); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1912 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1913 | DIF_AGC_IF_REF, 0, 31, 0x888C0380); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1914 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1915 | DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1916 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1917 | DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1918 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1919 | DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1920 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1921 | DIF_AGC_IF_INT_CURRENT, 0, 31, |
| 1922 | 0x26001700); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1923 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1924 | DIF_AGC_RF_CURRENT, 0, 31, |
| 1925 | 0x00002660); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1926 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1927 | DIF_VID_AUD_OVERRIDE, 0, 31, |
| 1928 | 0x27000100); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1929 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1930 | DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1931 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1932 | DIF_COMP_FLT_CTRL, 0, 31, |
| 1933 | 0x00000000); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1934 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1935 | DIF_SRC_PHASE_INC, 0, 31, |
| 1936 | 0x1befbf06); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1937 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1938 | DIF_SRC_GAIN_CONTROL, 0, 31, |
| 1939 | 0x000035e8); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1940 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1941 | DIF_RPT_VARIANCE, 0, 31, 0x00000000); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1942 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1943 | DIF_VIDEO_AGC_CTRL, 0, 31, |
| 1944 | 0xf4000000); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1945 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1946 | /* Save the Spec Inversion value */ |
| 1947 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; |
| 1948 | dif_misc_ctrl_value |= 0x3a023F11; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1949 | } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1950 | /* Is it SECAM_L1? */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1951 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1952 | DIF_PLL_CTRL, 0, 31, 0x6503bc0c); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1953 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1954 | DIF_PLL_CTRL1, 0, 31, 0xbd038c85); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1955 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1956 | DIF_PLL_CTRL2, 0, 31, 0x1db4640a); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1957 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1958 | DIF_PLL_CTRL3, 0, 31, 0x00008800); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1959 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1960 | DIF_AGC_IF_REF, 0, 31, 0x888C0380); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1961 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1962 | DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1963 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1964 | DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1965 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1966 | DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1967 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1968 | DIF_AGC_IF_INT_CURRENT, 0, 31, |
| 1969 | 0x26001700); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1970 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1971 | DIF_AGC_RF_CURRENT, 0, 31, |
| 1972 | 0x00002660); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1973 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1974 | DIF_VID_AUD_OVERRIDE, 0, 31, |
| 1975 | 0x27000100); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1976 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1977 | DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1978 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1979 | DIF_COMP_FLT_CTRL, 0, 31, |
| 1980 | 0x00000000); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1981 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1982 | DIF_SRC_PHASE_INC, 0, 31, |
| 1983 | 0x1befbf06); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1984 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1985 | DIF_SRC_GAIN_CONTROL, 0, 31, |
| 1986 | 0x000035e8); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1987 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1988 | DIF_RPT_VARIANCE, 0, 31, 0x00000000); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 1989 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1990 | DIF_VIDEO_AGC_CTRL, 0, 31, |
| 1991 | 0xf2560000); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1992 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 1993 | /* Save the Spec Inversion value */ |
| 1994 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; |
| 1995 | dif_misc_ctrl_value |= 0x3a023F11; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1996 | |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 1997 | } else if (standard & V4L2_STD_NTSC_M) { |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 1998 | /* V4L2_STD_NTSC_M (75 IRE Setup) Or |
| 1999 | V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2000 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2001 | /* For NTSC the centre frequency of video coming out of |
| 2002 | sidewinder is around 7.1MHz or 3.6MHz depending on the |
| 2003 | spectral inversion. so for a non spectrally inverted channel |
| 2004 | the pll freq word is 0x03420c49 |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2005 | */ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2006 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2007 | status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C); |
| 2008 | status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85); |
| 2009 | status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A); |
| 2010 | status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); |
| 2011 | status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380); |
| 2012 | status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, |
| 2013 | 0x26001700); |
| 2014 | status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, |
| 2015 | 0x00002660); |
| 2016 | status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, |
| 2017 | 0x04000800); |
| 2018 | status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, |
| 2019 | 0x27000100); |
| 2020 | status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2021 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2022 | status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, |
| 2023 | 0x009f50c1); |
| 2024 | status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, |
| 2025 | 0x1befbf06); |
| 2026 | status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, |
| 2027 | 0x000035e8); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2028 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2029 | status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600); |
| 2030 | status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT, |
| 2031 | 0xC2262600); |
| 2032 | status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2033 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2034 | /* Save the Spec Inversion value */ |
| 2035 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; |
| 2036 | dif_misc_ctrl_value |= 0x3a003F10; |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2037 | } else { |
| 2038 | /* default PAL BG */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2039 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2040 | DIF_PLL_CTRL, 0, 31, 0x6503bc0c); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2041 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2042 | DIF_PLL_CTRL1, 0, 31, 0xbd038c85); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2043 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2044 | DIF_PLL_CTRL2, 0, 31, 0x1db4640a); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2045 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2046 | DIF_PLL_CTRL3, 0, 31, 0x00008800); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2047 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2048 | DIF_AGC_IF_REF, 0, 31, 0x444C1380); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2049 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2050 | DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2051 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2052 | DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2053 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2054 | DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2055 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2056 | DIF_AGC_IF_INT_CURRENT, 0, 31, |
| 2057 | 0x26001700); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2058 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2059 | DIF_AGC_RF_CURRENT, 0, 31, |
| 2060 | 0x00002660); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2061 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2062 | DIF_VIDEO_AGC_CTRL, 0, 31, |
| 2063 | 0x72500800); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2064 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2065 | DIF_VID_AUD_OVERRIDE, 0, 31, |
| 2066 | 0x27000100); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2067 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2068 | DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2069 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2070 | DIF_COMP_FLT_CTRL, 0, 31, |
| 2071 | 0x00A653A8); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2072 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2073 | DIF_SRC_PHASE_INC, 0, 31, |
| 2074 | 0x1befbf06); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2075 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2076 | DIF_SRC_GAIN_CONTROL, 0, 31, |
| 2077 | 0x000035e8); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2078 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2079 | DIF_RPT_VARIANCE, 0, 31, 0x00000000); |
| 2080 | /* Save the Spec Inversion value */ |
| 2081 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; |
| 2082 | dif_misc_ctrl_value |= 0x3a013F11; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2083 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2084 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2085 | /* The AGC values should be the same for all standards, |
| 2086 | AUD_SRC_SEL[19] should always be disabled */ |
| 2087 | dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2088 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2089 | /* It is still possible to get Set Standard calls even when we |
| 2090 | are in FM mode. |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2091 | This is done to override the value for FM. */ |
| 2092 | if (dev->active_mode == V4L2_TUNER_RADIO) |
| 2093 | dif_misc_ctrl_value = 0x7a080000; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2094 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2095 | /* Write the calculated value for misc ontrol register */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2096 | status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2097 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2098 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2099 | } |
| 2100 | |
| 2101 | int cx231xx_tuner_pre_channel_change(struct cx231xx *dev) |
| 2102 | { |
| 2103 | int status = 0; |
| 2104 | u32 dwval; |
| 2105 | |
| 2106 | /* Set the RF and IF k_agc values to 3 */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2107 | status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2108 | dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); |
| 2109 | dwval |= 0x33000000; |
| 2110 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2111 | status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2112 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2113 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2114 | } |
| 2115 | |
| 2116 | int cx231xx_tuner_post_channel_change(struct cx231xx *dev) |
| 2117 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2118 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2119 | u32 dwval; |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 2120 | cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n", |
| 2121 | dev->tuner_type); |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2122 | /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for |
| 2123 | * SECAM L/B/D standards */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2124 | status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2125 | dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2126 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2127 | if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 2128 | V4L2_STD_SECAM_D)) { |
| 2129 | if (dev->tuner_type == TUNER_NXP_TDA18271) { |
| 2130 | dwval &= ~FLD_DIF_IF_REF; |
| 2131 | dwval |= 0x88000300; |
| 2132 | } else |
| 2133 | dwval |= 0x88000000; |
| 2134 | } else { |
| 2135 | if (dev->tuner_type == TUNER_NXP_TDA18271) { |
| 2136 | dwval &= ~FLD_DIF_IF_REF; |
| 2137 | dwval |= 0xCC000300; |
| 2138 | } else |
| 2139 | dwval |= 0x44000000; |
| 2140 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2141 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2142 | status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2143 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2144 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2145 | } |
| 2146 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2147 | /****************************************************************************** |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2148 | * I 2 S - B L O C K C O N T R O L functions * |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2149 | ******************************************************************************/ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2150 | int cx231xx_i2s_blk_initialize(struct cx231xx *dev) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2151 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2152 | int status = 0; |
| 2153 | u32 value; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2154 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2155 | status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2156 | CH_PWR_CTRL1, 1, &value, 1); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2157 | /* enables clock to delta-sigma and decimation filter */ |
| 2158 | value |= 0x80; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2159 | status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2160 | CH_PWR_CTRL1, 1, value, 1); |
| 2161 | /* power up all channel */ |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2162 | status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2163 | CH_PWR_CTRL2, 1, 0x00, 1); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2164 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2165 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2166 | } |
| 2167 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2168 | int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev, |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2169 | enum AV_MODE avmode) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2170 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2171 | int status = 0; |
| 2172 | u32 value = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2173 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2174 | if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2175 | status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2176 | CH_PWR_CTRL2, 1, &value, 1); |
| 2177 | value |= 0xfe; |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2178 | status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2179 | CH_PWR_CTRL2, 1, value, 1); |
| 2180 | } else { |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2181 | status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2182 | CH_PWR_CTRL2, 1, 0x00, 1); |
| 2183 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2184 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2185 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2186 | } |
| 2187 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2188 | /* set i2s_blk for audio input types */ |
| 2189 | int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2190 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2191 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2192 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2193 | switch (audio_input) { |
| 2194 | case CX231XX_AMUX_LINE_IN: |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2195 | status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2196 | CH_PWR_CTRL2, 1, 0x00, 1); |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2197 | status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2198 | CH_PWR_CTRL1, 1, 0x80, 1); |
| 2199 | break; |
| 2200 | case CX231XX_AMUX_VIDEO: |
| 2201 | default: |
| 2202 | break; |
| 2203 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2204 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2205 | dev->ctl_ainput = audio_input; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2206 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2207 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2208 | } |
| 2209 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2210 | /****************************************************************************** |
| 2211 | * P O W E R C O N T R O L functions * |
| 2212 | ******************************************************************************/ |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2213 | int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2214 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2215 | u8 value[4] = { 0, 0, 0, 0 }; |
| 2216 | u32 tmp = 0; |
| 2217 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2218 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2219 | if (dev->power_mode != mode) |
| 2220 | dev->power_mode = mode; |
| 2221 | else { |
| 2222 | cx231xx_info(" setPowerMode::mode = %d, No Change req.\n", |
| 2223 | mode); |
| 2224 | return 0; |
| 2225 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2226 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2227 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, |
| 2228 | 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2229 | if (status < 0) |
| 2230 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2231 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2232 | tmp = *((u32 *) value); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2233 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2234 | switch (mode) { |
| 2235 | case POLARIS_AVMODE_ENXTERNAL_AV: |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2236 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2237 | tmp &= (~PWR_MODE_MASK); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2238 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2239 | tmp |= PWR_AV_EN; |
| 2240 | value[0] = (u8) tmp; |
| 2241 | value[1] = (u8) (tmp >> 8); |
| 2242 | value[2] = (u8) (tmp >> 16); |
| 2243 | value[3] = (u8) (tmp >> 24); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2244 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2245 | PWR_CTL_EN, value, 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2246 | msleep(PWR_SLEEP_INTERVAL); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2247 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2248 | tmp |= PWR_ISO_EN; |
| 2249 | value[0] = (u8) tmp; |
| 2250 | value[1] = (u8) (tmp >> 8); |
| 2251 | value[2] = (u8) (tmp >> 16); |
| 2252 | value[3] = (u8) (tmp >> 24); |
| 2253 | status = |
| 2254 | cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, |
| 2255 | value, 4); |
| 2256 | msleep(PWR_SLEEP_INTERVAL); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2257 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2258 | tmp |= POLARIS_AVMODE_ENXTERNAL_AV; |
| 2259 | value[0] = (u8) tmp; |
| 2260 | value[1] = (u8) (tmp >> 8); |
| 2261 | value[2] = (u8) (tmp >> 16); |
| 2262 | value[3] = (u8) (tmp >> 24); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2263 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2264 | PWR_CTL_EN, value, 4); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2265 | |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 2266 | /* reset state of xceive tuner */ |
| 2267 | dev->xc_fw_load_done = 0; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2268 | break; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2269 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2270 | case POLARIS_AVMODE_ANALOGT_TV: |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2271 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 2272 | tmp |= PWR_DEMOD_EN; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2273 | tmp |= (I2C_DEMOD_EN); |
| 2274 | value[0] = (u8) tmp; |
| 2275 | value[1] = (u8) (tmp >> 8); |
| 2276 | value[2] = (u8) (tmp >> 16); |
| 2277 | value[3] = (u8) (tmp >> 24); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2278 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2279 | PWR_CTL_EN, value, 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2280 | msleep(PWR_SLEEP_INTERVAL); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2281 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2282 | if (!(tmp & PWR_TUNER_EN)) { |
| 2283 | tmp |= (PWR_TUNER_EN); |
| 2284 | value[0] = (u8) tmp; |
| 2285 | value[1] = (u8) (tmp >> 8); |
| 2286 | value[2] = (u8) (tmp >> 16); |
| 2287 | value[3] = (u8) (tmp >> 24); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2288 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2289 | PWR_CTL_EN, value, 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2290 | msleep(PWR_SLEEP_INTERVAL); |
| 2291 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2292 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2293 | if (!(tmp & PWR_AV_EN)) { |
| 2294 | tmp |= PWR_AV_EN; |
| 2295 | value[0] = (u8) tmp; |
| 2296 | value[1] = (u8) (tmp >> 8); |
| 2297 | value[2] = (u8) (tmp >> 16); |
| 2298 | value[3] = (u8) (tmp >> 24); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2299 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2300 | PWR_CTL_EN, value, 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2301 | msleep(PWR_SLEEP_INTERVAL); |
| 2302 | } |
| 2303 | if (!(tmp & PWR_ISO_EN)) { |
| 2304 | tmp |= PWR_ISO_EN; |
| 2305 | value[0] = (u8) tmp; |
| 2306 | value[1] = (u8) (tmp >> 8); |
| 2307 | value[2] = (u8) (tmp >> 16); |
| 2308 | value[3] = (u8) (tmp >> 24); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2309 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2310 | PWR_CTL_EN, value, 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2311 | msleep(PWR_SLEEP_INTERVAL); |
| 2312 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2313 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2314 | if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) { |
| 2315 | tmp |= POLARIS_AVMODE_ANALOGT_TV; |
| 2316 | value[0] = (u8) tmp; |
| 2317 | value[1] = (u8) (tmp >> 8); |
| 2318 | value[2] = (u8) (tmp >> 16); |
| 2319 | value[3] = (u8) (tmp >> 24); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2320 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2321 | PWR_CTL_EN, value, 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2322 | msleep(PWR_SLEEP_INTERVAL); |
| 2323 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2324 | |
Mauro Carvalho Chehab | a6f6fb9 | 2010-09-26 20:38:24 -0300 | [diff] [blame] | 2325 | if (dev->board.tuner_type != TUNER_ABSENT) { |
| 2326 | /* Enable tuner */ |
| 2327 | cx231xx_enable_i2c_port_3(dev, true); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2328 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 2329 | /* reset the Tuner */ |
Mauro Carvalho Chehab | a6f6fb9 | 2010-09-26 20:38:24 -0300 | [diff] [blame] | 2330 | if (dev->board.tuner_gpio) |
| 2331 | cx231xx_gpio_set(dev, dev->board.tuner_gpio); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 2332 | |
| 2333 | if (dev->cx231xx_reset_analog_tuner) |
| 2334 | dev->cx231xx_reset_analog_tuner(dev); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2335 | } |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 2336 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2337 | break; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2338 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2339 | case POLARIS_AVMODE_DIGITAL: |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2340 | if (!(tmp & PWR_TUNER_EN)) { |
| 2341 | tmp |= (PWR_TUNER_EN); |
| 2342 | value[0] = (u8) tmp; |
| 2343 | value[1] = (u8) (tmp >> 8); |
| 2344 | value[2] = (u8) (tmp >> 16); |
| 2345 | value[3] = (u8) (tmp >> 24); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2346 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2347 | PWR_CTL_EN, value, 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2348 | msleep(PWR_SLEEP_INTERVAL); |
| 2349 | } |
| 2350 | if (!(tmp & PWR_AV_EN)) { |
| 2351 | tmp |= PWR_AV_EN; |
| 2352 | value[0] = (u8) tmp; |
| 2353 | value[1] = (u8) (tmp >> 8); |
| 2354 | value[2] = (u8) (tmp >> 16); |
| 2355 | value[3] = (u8) (tmp >> 24); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2356 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2357 | PWR_CTL_EN, value, 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2358 | msleep(PWR_SLEEP_INTERVAL); |
| 2359 | } |
| 2360 | if (!(tmp & PWR_ISO_EN)) { |
| 2361 | tmp |= PWR_ISO_EN; |
| 2362 | value[0] = (u8) tmp; |
| 2363 | value[1] = (u8) (tmp >> 8); |
| 2364 | value[2] = (u8) (tmp >> 16); |
| 2365 | value[3] = (u8) (tmp >> 24); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2366 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2367 | PWR_CTL_EN, value, 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2368 | msleep(PWR_SLEEP_INTERVAL); |
| 2369 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2370 | |
Devin Heitmueller | cc35575 | 2010-07-12 15:31:56 -0300 | [diff] [blame] | 2371 | tmp &= (~PWR_AV_MODE); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2372 | tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN; |
| 2373 | value[0] = (u8) tmp; |
| 2374 | value[1] = (u8) (tmp >> 8); |
| 2375 | value[2] = (u8) (tmp >> 16); |
| 2376 | value[3] = (u8) (tmp >> 24); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2377 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2378 | PWR_CTL_EN, value, 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2379 | msleep(PWR_SLEEP_INTERVAL); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2380 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2381 | if (!(tmp & PWR_DEMOD_EN)) { |
| 2382 | tmp |= PWR_DEMOD_EN; |
| 2383 | value[0] = (u8) tmp; |
| 2384 | value[1] = (u8) (tmp >> 8); |
| 2385 | value[2] = (u8) (tmp >> 16); |
| 2386 | value[3] = (u8) (tmp >> 24); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2387 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2388 | PWR_CTL_EN, value, 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2389 | msleep(PWR_SLEEP_INTERVAL); |
| 2390 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2391 | |
Mauro Carvalho Chehab | a6f6fb9 | 2010-09-26 20:38:24 -0300 | [diff] [blame] | 2392 | if (dev->board.tuner_type != TUNER_ABSENT) { |
| 2393 | /* |
| 2394 | * Enable tuner |
| 2395 | * Hauppauge Exeter seems to need to do something different! |
| 2396 | */ |
| 2397 | if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER) |
| 2398 | cx231xx_enable_i2c_port_3(dev, false); |
| 2399 | else |
| 2400 | cx231xx_enable_i2c_port_3(dev, true); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2401 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 2402 | /* reset the Tuner */ |
Mauro Carvalho Chehab | a6f6fb9 | 2010-09-26 20:38:24 -0300 | [diff] [blame] | 2403 | if (dev->board.tuner_gpio) |
| 2404 | cx231xx_gpio_set(dev, dev->board.tuner_gpio); |
Michael Krufky | 1a50fdd | 2010-07-06 18:23:53 -0300 | [diff] [blame] | 2405 | |
| 2406 | if (dev->cx231xx_reset_analog_tuner) |
| 2407 | dev->cx231xx_reset_analog_tuner(dev); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2408 | } |
| 2409 | break; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2410 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2411 | default: |
| 2412 | break; |
| 2413 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2414 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2415 | msleep(PWR_SLEEP_INTERVAL); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2416 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2417 | /* For power saving, only enable Pwr_resetout_n |
| 2418 | when digital TV is selected. */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2419 | if (mode == POLARIS_AVMODE_DIGITAL) { |
| 2420 | tmp |= PWR_RESETOUT_EN; |
| 2421 | value[0] = (u8) tmp; |
| 2422 | value[1] = (u8) (tmp >> 8); |
| 2423 | value[2] = (u8) (tmp >> 16); |
| 2424 | value[3] = (u8) (tmp >> 24); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2425 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2426 | PWR_CTL_EN, value, 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2427 | msleep(PWR_SLEEP_INTERVAL); |
| 2428 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2429 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2430 | /* update power control for afe */ |
| 2431 | status = cx231xx_afe_update_power_control(dev, mode); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2432 | |
Sri Deevi | ecc67d1 | 2009-03-21 22:00:20 -0300 | [diff] [blame] | 2433 | /* update power control for i2s_blk */ |
| 2434 | status = cx231xx_i2s_blk_update_power_control(dev, mode); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2435 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2436 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, |
| 2437 | 4); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2438 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2439 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2440 | } |
| 2441 | |
| 2442 | int cx231xx_power_suspend(struct cx231xx *dev) |
| 2443 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2444 | u8 value[4] = { 0, 0, 0, 0 }; |
| 2445 | u32 tmp = 0; |
| 2446 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2447 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2448 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, |
| 2449 | value, 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2450 | if (status > 0) |
| 2451 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2452 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2453 | tmp = *((u32 *) value); |
| 2454 | tmp &= (~PWR_MODE_MASK); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2455 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2456 | value[0] = (u8) tmp; |
| 2457 | value[1] = (u8) (tmp >> 8); |
| 2458 | value[2] = (u8) (tmp >> 16); |
| 2459 | value[3] = (u8) (tmp >> 24); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2460 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, |
| 2461 | value, 4); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2462 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2463 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2464 | } |
| 2465 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2466 | /****************************************************************************** |
| 2467 | * S T R E A M C O N T R O L functions * |
| 2468 | ******************************************************************************/ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2469 | int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) |
| 2470 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2471 | u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; |
| 2472 | u32 tmp = 0; |
| 2473 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2474 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2475 | cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2476 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, |
| 2477 | value, 4); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2478 | if (status < 0) |
| 2479 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2480 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2481 | tmp = *((u32 *) value); |
| 2482 | tmp |= ep_mask; |
| 2483 | value[0] = (u8) tmp; |
| 2484 | value[1] = (u8) (tmp >> 8); |
| 2485 | value[2] = (u8) (tmp >> 16); |
| 2486 | value[3] = (u8) (tmp >> 24); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2487 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2488 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, |
| 2489 | value, 4); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2490 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2491 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2492 | } |
| 2493 | |
| 2494 | int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask) |
| 2495 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2496 | u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; |
| 2497 | u32 tmp = 0; |
| 2498 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2499 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2500 | cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask); |
| 2501 | status = |
| 2502 | cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4); |
| 2503 | if (status < 0) |
| 2504 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2505 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2506 | tmp = *((u32 *) value); |
| 2507 | tmp &= (~ep_mask); |
| 2508 | value[0] = (u8) tmp; |
| 2509 | value[1] = (u8) (tmp >> 8); |
| 2510 | value[2] = (u8) (tmp >> 16); |
| 2511 | value[3] = (u8) (tmp >> 24); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2512 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2513 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, |
| 2514 | value, 4); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2515 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2516 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2517 | } |
| 2518 | |
| 2519 | int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) |
| 2520 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2521 | int status = 0; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 2522 | u32 value = 0; |
| 2523 | u8 val[4] = { 0, 0, 0, 0 }; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2524 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2525 | if (dev->udev->speed == USB_SPEED_HIGH) { |
| 2526 | switch (media_type) { |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2527 | case 81: /* audio */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2528 | cx231xx_info("%s: Audio enter HANC\n", __func__); |
| 2529 | status = |
| 2530 | cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); |
| 2531 | break; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2532 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2533 | case 2: /* vbi */ |
| 2534 | cx231xx_info("%s: set vanc registers\n", __func__); |
| 2535 | status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300); |
| 2536 | break; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2537 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2538 | case 3: /* sliced cc */ |
| 2539 | cx231xx_info("%s: set hanc registers\n", __func__); |
| 2540 | status = |
| 2541 | cx231xx_mode_register(dev, TS_MODE_REG, 0x1300); |
| 2542 | break; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2543 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2544 | case 0: /* video */ |
| 2545 | cx231xx_info("%s: set video registers\n", __func__); |
| 2546 | status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); |
| 2547 | break; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2548 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2549 | case 4: /* ts1 */ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 2550 | cx231xx_info("%s: set ts1 registers", __func__); |
| 2551 | |
| 2552 | if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) { |
| 2553 | cx231xx_info(" MPEG\n"); |
| 2554 | value &= 0xFFFFFFFC; |
| 2555 | value |= 0x3; |
| 2556 | |
| 2557 | status = cx231xx_mode_register(dev, TS_MODE_REG, value); |
| 2558 | |
| 2559 | val[0] = 0x04; |
| 2560 | val[1] = 0xA3; |
| 2561 | val[2] = 0x3B; |
| 2562 | val[3] = 0x00; |
| 2563 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2564 | TS1_CFG_REG, val, 4); |
| 2565 | |
| 2566 | val[0] = 0x00; |
| 2567 | val[1] = 0x08; |
| 2568 | val[2] = 0x00; |
| 2569 | val[3] = 0x08; |
| 2570 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2571 | TS1_LENGTH_REG, val, 4); |
| 2572 | |
| 2573 | } else { |
| 2574 | cx231xx_info(" BDA\n"); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2575 | status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 2576 | status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010); |
| 2577 | } |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2578 | break; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 2579 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2580 | case 6: /* ts1 parallel mode */ |
| 2581 | cx231xx_info("%s: set ts1 parrallel mode registers\n", |
| 2582 | __func__); |
| 2583 | status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); |
| 2584 | status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); |
| 2585 | break; |
| 2586 | } |
| 2587 | } else { |
| 2588 | status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); |
| 2589 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2590 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2591 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2592 | } |
| 2593 | |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2594 | int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) |
| 2595 | { |
Hans Verkuil | aad40d3 | 2009-06-20 09:21:37 -0300 | [diff] [blame] | 2596 | int rc = -1; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2597 | u32 ep_mask = -1; |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 2598 | struct pcb_config *pcb_config; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2599 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2600 | /* get EP for media type */ |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 2601 | pcb_config = (struct pcb_config *)&dev->current_pcb_config; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2602 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2603 | if (pcb_config->config_num == 1) { |
| 2604 | switch (media_type) { |
| 2605 | case 0: /* Video */ |
| 2606 | ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ |
| 2607 | break; |
| 2608 | case 1: /* Audio */ |
| 2609 | ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ |
| 2610 | break; |
| 2611 | case 2: /* Vbi */ |
| 2612 | ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ |
| 2613 | break; |
| 2614 | case 3: /* Sliced_cc */ |
| 2615 | ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ |
| 2616 | break; |
| 2617 | case 4: /* ts1 */ |
| 2618 | case 6: /* ts1 parallel mode */ |
| 2619 | ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ |
| 2620 | break; |
| 2621 | case 5: /* ts2 */ |
| 2622 | ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ |
| 2623 | break; |
| 2624 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2625 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2626 | } else if (pcb_config->config_num > 1) { |
| 2627 | switch (media_type) { |
| 2628 | case 0: /* Video */ |
| 2629 | ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ |
| 2630 | break; |
| 2631 | case 1: /* Audio */ |
| 2632 | ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ |
| 2633 | break; |
| 2634 | case 2: /* Vbi */ |
| 2635 | ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ |
| 2636 | break; |
| 2637 | case 3: /* Sliced_cc */ |
| 2638 | ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ |
| 2639 | break; |
| 2640 | case 4: /* ts1 */ |
| 2641 | case 6: /* ts1 parallel mode */ |
| 2642 | ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ |
| 2643 | break; |
| 2644 | case 5: /* ts2 */ |
| 2645 | ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ |
| 2646 | break; |
| 2647 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2648 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2649 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2650 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2651 | if (start) { |
| 2652 | rc = cx231xx_initialize_stream_xfer(dev, media_type); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2653 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2654 | if (rc < 0) |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2655 | return rc; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2656 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2657 | /* enable video capture */ |
| 2658 | if (ep_mask > 0) |
| 2659 | rc = cx231xx_start_stream(dev, ep_mask); |
| 2660 | } else { |
| 2661 | /* disable video capture */ |
| 2662 | if (ep_mask > 0) |
| 2663 | rc = cx231xx_stop_stream(dev, ep_mask); |
| 2664 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2665 | |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 2666 | if (dev->mode == CX231XX_ANALOG_MODE) |
| 2667 | ;/* do any in Analog mode */ |
| 2668 | else |
| 2669 | ;/* do any in digital mode */ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2670 | |
| 2671 | return rc; |
| 2672 | } |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2673 | EXPORT_SYMBOL_GPL(cx231xx_capture_start); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2674 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2675 | /***************************************************************************** |
| 2676 | * G P I O B I T control functions * |
| 2677 | ******************************************************************************/ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 2678 | int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2679 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2680 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2681 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2682 | status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2683 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2684 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2685 | } |
| 2686 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 2687 | int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2688 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2689 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2690 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2691 | status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2692 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2693 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2694 | } |
| 2695 | |
| 2696 | /* |
| 2697 | * cx231xx_set_gpio_direction |
| 2698 | * Sets the direction of the GPIO pin to input or output |
| 2699 | * |
| 2700 | * Parameters : |
| 2701 | * pin_number : The GPIO Pin number to program the direction for |
| 2702 | * from 0 to 31 |
| 2703 | * pin_value : The Direction of the GPIO Pin under reference. |
| 2704 | * 0 = Input direction |
| 2705 | * 1 = Output direction |
| 2706 | */ |
| 2707 | int cx231xx_set_gpio_direction(struct cx231xx *dev, |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2708 | int pin_number, int pin_value) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2709 | { |
| 2710 | int status = 0; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2711 | u32 value = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2712 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2713 | /* Check for valid pin_number - if 32 , bail out */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2714 | if (pin_number >= 32) |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2715 | return -EINVAL; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2716 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2717 | /* input */ |
| 2718 | if (pin_value == 0) |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2719 | value = dev->gpio_dir & (~(1 << pin_number)); /* clear */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2720 | else |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2721 | value = dev->gpio_dir | (1 << pin_number); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2722 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2723 | status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2724 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2725 | /* cache the value for future */ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2726 | dev->gpio_dir = value; |
| 2727 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2728 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2729 | } |
| 2730 | |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2731 | /* |
Sri Deevi | 6e4f574 | 2009-03-10 21:16:26 -0300 | [diff] [blame] | 2732 | * cx231xx_set_gpio_value |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2733 | * Sets the value of the GPIO pin to Logic high or low. The Pin under |
| 2734 | * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! |
| 2735 | * |
| 2736 | * Parameters : |
| 2737 | * pin_number : The GPIO Pin number to program the direction for |
| 2738 | * pin_value : The value of the GPIO Pin under reference. |
| 2739 | * 0 = set it to 0 |
| 2740 | * 1 = set it to 1 |
| 2741 | */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2742 | int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2743 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2744 | int status = 0; |
| 2745 | u32 value = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2746 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2747 | /* Check for valid pin_number - if 0xFF , bail out */ |
| 2748 | if (pin_number >= 32) |
| 2749 | return -EINVAL; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2750 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2751 | /* first do a sanity check - if the Pin is not output, make it output */ |
| 2752 | if ((dev->gpio_dir & (1 << pin_number)) == 0x00) { |
| 2753 | /* It was in input mode */ |
| 2754 | value = dev->gpio_dir | (1 << pin_number); |
| 2755 | dev->gpio_dir = value; |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2756 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2757 | (u8 *) &dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2758 | value = 0; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2759 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2760 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2761 | if (pin_value == 0) |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2762 | value = dev->gpio_val & (~(1 << pin_number)); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2763 | else |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2764 | value = dev->gpio_val | (1 << pin_number); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2765 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2766 | /* store the value */ |
| 2767 | dev->gpio_val = value; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2768 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2769 | /* toggle bit0 of GP_IO */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2770 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2771 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2772 | return status; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2773 | } |
| 2774 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2775 | /***************************************************************************** |
| 2776 | * G P I O I2C related functions * |
| 2777 | ******************************************************************************/ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2778 | int cx231xx_gpio_i2c_start(struct cx231xx *dev) |
| 2779 | { |
| 2780 | int status = 0; |
| 2781 | |
| 2782 | /* set SCL to output 1 ; set SDA to output 1 */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2783 | dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; |
| 2784 | dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; |
| 2785 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; |
| 2786 | dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2787 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2788 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| 2789 | if (status < 0) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2790 | return -EINVAL; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2791 | |
| 2792 | /* set SCL to output 1; set SDA to output 0 */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2793 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; |
| 2794 | dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2795 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2796 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| 2797 | if (status < 0) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2798 | return -EINVAL; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2799 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2800 | /* set SCL to output 0; set SDA to output 0 */ |
| 2801 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
| 2802 | dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2803 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2804 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| 2805 | if (status < 0) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2806 | return -EINVAL; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2807 | |
| 2808 | return status; |
| 2809 | } |
| 2810 | |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2811 | int cx231xx_gpio_i2c_end(struct cx231xx *dev) |
| 2812 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2813 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2814 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2815 | /* set SCL to output 0; set SDA to output 0 */ |
| 2816 | dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; |
| 2817 | dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2818 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2819 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
| 2820 | dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2821 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2822 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| 2823 | if (status < 0) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2824 | return -EINVAL; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2825 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2826 | /* set SCL to output 1; set SDA to output 0 */ |
| 2827 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; |
| 2828 | dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2829 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2830 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| 2831 | if (status < 0) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2832 | return -EINVAL; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2833 | |
| 2834 | /* set SCL to input ,release SCL cable control |
| 2835 | set SDA to input ,release SDA cable control */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2836 | dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); |
| 2837 | dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2838 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2839 | status = |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2840 | cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| 2841 | if (status < 0) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2842 | return -EINVAL; |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2843 | |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2844 | return status; |
| 2845 | } |
| 2846 | |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2847 | int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data) |
| 2848 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2849 | int status = 0; |
| 2850 | u8 i; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2851 | |
| 2852 | /* set SCL to output ; set SDA to output */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2853 | dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; |
| 2854 | dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2855 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2856 | for (i = 0; i < 8; i++) { |
| 2857 | if (((data << i) & 0x80) == 0) { |
| 2858 | /* set SCL to output 0; set SDA to output 0 */ |
| 2859 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
| 2860 | dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2861 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2862 | (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2863 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2864 | /* set SCL to output 1; set SDA to output 0 */ |
| 2865 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2866 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2867 | (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2868 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2869 | /* set SCL to output 0; set SDA to output 0 */ |
| 2870 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2871 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2872 | (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2873 | } else { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2874 | /* set SCL to output 0; set SDA to output 1 */ |
| 2875 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
| 2876 | dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2877 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2878 | (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2879 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2880 | /* set SCL to output 1; set SDA to output 1 */ |
| 2881 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2882 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2883 | (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2884 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2885 | /* set SCL to output 0; set SDA to output 1 */ |
| 2886 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2887 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2888 | (u8 *)&dev->gpio_val); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2889 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2890 | } |
| 2891 | return status; |
| 2892 | } |
| 2893 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 2894 | int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2895 | { |
| 2896 | u8 value = 0; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2897 | int status = 0; |
| 2898 | u32 gpio_logic_value = 0; |
| 2899 | u8 i; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2900 | |
| 2901 | /* read byte */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2902 | for (i = 0; i < 8; i++) { /* send write I2c addr */ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2903 | |
| 2904 | /* set SCL to output 0; set SDA to input */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2905 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2906 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2907 | (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2908 | |
| 2909 | /* set SCL to output 1; set SDA to input */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2910 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2911 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2912 | (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2913 | |
| 2914 | /* get SDA data bit */ |
| 2915 | gpio_logic_value = dev->gpio_val; |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2916 | status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, |
| 2917 | (u8 *)&dev->gpio_val); |
| 2918 | if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2919 | value |= (1 << (8 - i - 1)); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2920 | |
| 2921 | dev->gpio_val = gpio_logic_value; |
| 2922 | } |
| 2923 | |
| 2924 | /* set SCL to output 0,finish the read latest SCL signal. |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2925 | !!!set SDA to input, never to modify SDA direction at |
| 2926 | the same times */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2927 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2928 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2929 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2930 | /* store the value */ |
| 2931 | *buf = value & 0xff; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2932 | |
| 2933 | return status; |
| 2934 | } |
| 2935 | |
| 2936 | int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) |
| 2937 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2938 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2939 | u32 gpio_logic_value = 0; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2940 | int nCnt = 10; |
| 2941 | int nInit = nCnt; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2942 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2943 | /* clock stretch; set SCL to input; set SDA to input; |
| 2944 | get SCL value till SCL = 1 */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2945 | dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); |
| 2946 | dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2947 | |
| 2948 | gpio_logic_value = dev->gpio_val; |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2949 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2950 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2951 | do { |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2952 | msleep(2); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2953 | status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, |
| 2954 | (u8 *)&dev->gpio_val); |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2955 | nCnt--; |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 2956 | } while (((dev->gpio_val & |
| 2957 | (1 << dev->board.tuner_scl_gpio)) == 0) && |
| 2958 | (nCnt > 0)); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2959 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2960 | if (nCnt == 0) |
Sri Deevi | b925517 | 2009-03-04 17:49:01 -0300 | [diff] [blame] | 2961 | cx231xx_info("No ACK after %d msec -GPIO I2C failed!", |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2962 | nInit * 10); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2963 | |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 2964 | /* |
| 2965 | * readAck |
| 2966 | * through clock stretch, slave has given a SCL signal, |
| 2967 | * so the SDA data can be directly read. |
| 2968 | */ |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2969 | status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2970 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2971 | if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) { |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2972 | dev->gpio_val = gpio_logic_value; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2973 | dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2974 | status = 0; |
| 2975 | } else { |
| 2976 | dev->gpio_val = gpio_logic_value; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2977 | dev->gpio_val |= (1 << dev->board.tuner_sda_gpio); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2978 | } |
| 2979 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2980 | /* read SDA end, set the SCL to output 0, after this operation, |
| 2981 | SDA direction can be changed. */ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2982 | dev->gpio_val = gpio_logic_value; |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2983 | dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio); |
| 2984 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2985 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2986 | |
| 2987 | return status; |
| 2988 | } |
| 2989 | |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2990 | int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev) |
| 2991 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2992 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2993 | |
| 2994 | /* set SDA to ouput */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2995 | dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 2996 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 2997 | |
| 2998 | /* set SCL = 0 (output); set SDA = 0 (output) */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 2999 | dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); |
| 3000 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 3001 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3002 | |
| 3003 | /* set SCL = 1 (output); set SDA = 0 (output) */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3004 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 3005 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3006 | |
| 3007 | /* set SCL = 0 (output); set SDA = 0 (output) */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3008 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 3009 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3010 | |
| 3011 | /* set SDA to input,and then the slave will read data from SDA. */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3012 | dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 3013 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3014 | |
| 3015 | return status; |
| 3016 | } |
| 3017 | |
| 3018 | int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev) |
| 3019 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3020 | int status = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3021 | |
| 3022 | /* set scl to output ; set sda to input */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3023 | dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; |
| 3024 | dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 3025 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3026 | |
| 3027 | /* set scl to output 0; set sda to input */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3028 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 3029 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3030 | |
| 3031 | /* set scl to output 1; set sda to input */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3032 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 3033 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3034 | |
| 3035 | return status; |
| 3036 | } |
| 3037 | |
Mauro Carvalho Chehab | cde4362 | 2009-03-03 13:31:36 -0300 | [diff] [blame] | 3038 | /***************************************************************************** |
| 3039 | * G P I O I2C related functions * |
| 3040 | ******************************************************************************/ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3041 | /* cx231xx_gpio_i2c_read |
| 3042 | * Function to read data from gpio based I2C interface |
| 3043 | */ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 3044 | int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3045 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3046 | int status = 0; |
| 3047 | int i = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3048 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3049 | /* get the lock */ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3050 | mutex_lock(&dev->gpio_i2c_lock); |
| 3051 | |
| 3052 | /* start */ |
| 3053 | status = cx231xx_gpio_i2c_start(dev); |
| 3054 | |
| 3055 | /* write dev_addr */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3056 | status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3057 | |
| 3058 | /* readAck */ |
| 3059 | status = cx231xx_gpio_i2c_read_ack(dev); |
| 3060 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3061 | /* read data */ |
| 3062 | for (i = 0; i < len; i++) { |
| 3063 | /* read data */ |
| 3064 | buf[i] = 0; |
| 3065 | status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3066 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3067 | if ((i + 1) != len) { |
| 3068 | /* only do write ack if we more length */ |
| 3069 | status = cx231xx_gpio_i2c_write_ack(dev); |
| 3070 | } |
| 3071 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3072 | |
| 3073 | /* write NAK - inform reads are complete */ |
| 3074 | status = cx231xx_gpio_i2c_write_nak(dev); |
| 3075 | |
| 3076 | /* write end */ |
| 3077 | status = cx231xx_gpio_i2c_end(dev); |
| 3078 | |
| 3079 | /* release the lock */ |
| 3080 | mutex_unlock(&dev->gpio_i2c_lock); |
| 3081 | |
| 3082 | return status; |
| 3083 | } |
| 3084 | |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3085 | /* cx231xx_gpio_i2c_write |
| 3086 | * Function to write data to gpio based I2C interface |
| 3087 | */ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 3088 | int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3089 | { |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3090 | int status = 0; |
| 3091 | int i = 0; |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3092 | |
| 3093 | /* get the lock */ |
| 3094 | mutex_lock(&dev->gpio_i2c_lock); |
| 3095 | |
| 3096 | /* start */ |
| 3097 | status = cx231xx_gpio_i2c_start(dev); |
| 3098 | |
| 3099 | /* write dev_addr */ |
| 3100 | status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1); |
| 3101 | |
| 3102 | /* read Ack */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3103 | status = cx231xx_gpio_i2c_read_ack(dev); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3104 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3105 | for (i = 0; i < len; i++) { |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3106 | /* Write data */ |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3107 | status = cx231xx_gpio_i2c_write_byte(dev, buf[i]); |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3108 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3109 | /* read Ack */ |
| 3110 | status = cx231xx_gpio_i2c_read_ack(dev); |
| 3111 | } |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3112 | |
Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame] | 3113 | /* write End */ |
Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 3114 | status = cx231xx_gpio_i2c_end(dev); |
| 3115 | |
| 3116 | /* release the lock */ |
| 3117 | mutex_unlock(&dev->gpio_i2c_lock); |
| 3118 | |
| 3119 | return 0; |
| 3120 | } |