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Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001/**********************************************************
2 * Copyright 1998-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26/*
27 * svga3d_reg.h --
28 *
29 * SVGA 3D hardware definitions
30 */
31
32#ifndef _SVGA3D_REG_H_
33#define _SVGA3D_REG_H_
34
35#include "svga_reg.h"
36
Thomas Hellstromd9019492012-11-21 10:17:00 +010037typedef uint32 PPN;
Thomas Hellstromf2a0dcb2014-01-15 10:04:07 +010038typedef __le64 PPN64;
Jakob Bornecrantz632f6112009-12-10 00:19:10 +000039
40/*
41 * 3D Hardware Version
42 *
43 * The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
44 * register. Is set by the host and read by the guest. This lets
45 * us make new guest drivers which are backwards-compatible with old
46 * SVGA hardware revisions. It does not let us support old guest
47 * drivers. Good enough for now.
48 *
49 */
50
51#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
52#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
53#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
54
55typedef enum {
56 SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
57 SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
58 SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
59 SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
60 SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
61 SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +020062 SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
63 SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +000064} SVGA3dHardwareVersion;
65
66/*
67 * Generic Types
68 */
69
70typedef uint32 SVGA3dBool; /* 32-bit Bool definition */
71#define SVGA3D_NUM_CLIPPLANES 6
72#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS 8
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +020073#define SVGA3D_MAX_CONTEXT_IDS 256
74#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
Jakob Bornecrantz632f6112009-12-10 00:19:10 +000075
Thomas Hellstromd9019492012-11-21 10:17:00 +010076#define SVGA3D_NUM_TEXTURE_UNITS 32
77#define SVGA3D_NUM_LIGHTS 8
78
Jakob Bornecrantz632f6112009-12-10 00:19:10 +000079/*
80 * Surface formats.
81 *
82 * If you modify this list, be sure to keep GLUtil.c in sync. It
83 * includes the internal format definition of each surface in
84 * GLUtil_ConvertSurfaceFormat, and it contains a table of
85 * human-readable names in GLUtil_GetFormatName.
86 */
87
88typedef enum SVGA3dSurfaceFormat {
Thomas Hellstromd9019492012-11-21 10:17:00 +010089 SVGA3D_FORMAT_MIN = 0,
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +020090 SVGA3D_FORMAT_INVALID = 0,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +000091
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +020092 SVGA3D_X8R8G8B8 = 1,
93 SVGA3D_A8R8G8B8 = 2,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +000094
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +020095 SVGA3D_R5G6B5 = 3,
96 SVGA3D_X1R5G5B5 = 4,
97 SVGA3D_A1R5G5B5 = 5,
98 SVGA3D_A4R4G4B4 = 6,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +000099
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200100 SVGA3D_Z_D32 = 7,
101 SVGA3D_Z_D16 = 8,
102 SVGA3D_Z_D24S8 = 9,
103 SVGA3D_Z_D15S1 = 10,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000104
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200105 SVGA3D_LUMINANCE8 = 11,
106 SVGA3D_LUMINANCE4_ALPHA4 = 12,
107 SVGA3D_LUMINANCE16 = 13,
108 SVGA3D_LUMINANCE8_ALPHA8 = 14,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000109
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200110 SVGA3D_DXT1 = 15,
111 SVGA3D_DXT2 = 16,
112 SVGA3D_DXT3 = 17,
113 SVGA3D_DXT4 = 18,
114 SVGA3D_DXT5 = 19,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000115
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200116 SVGA3D_BUMPU8V8 = 20,
117 SVGA3D_BUMPL6V5U5 = 21,
118 SVGA3D_BUMPX8L8V8U8 = 22,
119 SVGA3D_BUMPL8V8U8 = 23,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000120
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200121 SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */
122 SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000123
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200124 SVGA3D_A2R10G10B10 = 26,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000125
126 /* signed formats */
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200127 SVGA3D_V8U8 = 27,
128 SVGA3D_Q8W8V8U8 = 28,
129 SVGA3D_CxV8U8 = 29,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000130
131 /* mixed formats */
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200132 SVGA3D_X8L8V8U8 = 30,
133 SVGA3D_A2W10V10U10 = 31,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000134
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200135 SVGA3D_ALPHA8 = 32,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000136
137 /* Single- and dual-component floating point formats */
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200138 SVGA3D_R_S10E5 = 33,
139 SVGA3D_R_S23E8 = 34,
140 SVGA3D_RG_S10E5 = 35,
141 SVGA3D_RG_S23E8 = 36,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000142
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200143 SVGA3D_BUFFER = 37,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000144
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200145 SVGA3D_Z_D24X8 = 38,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000146
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200147 SVGA3D_V16U16 = 39,
148
149 SVGA3D_G16R16 = 40,
150 SVGA3D_A16B16G16R16 = 41,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000151
152 /* Packed Video formats */
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200153 SVGA3D_UYVY = 42,
154 SVGA3D_YUY2 = 43,
155
156 /* Planar video formats */
157 SVGA3D_NV12 = 44,
158
159 /* Video format with alpha */
160 SVGA3D_AYUV = 45,
161
Thomas Hellstromd9019492012-11-21 10:17:00 +0100162 SVGA3D_R32G32B32A32_TYPELESS = 46,
163 SVGA3D_R32G32B32A32_FLOAT = 25,
164 SVGA3D_R32G32B32A32_UINT = 47,
165 SVGA3D_R32G32B32A32_SINT = 48,
166 SVGA3D_R32G32B32_TYPELESS = 49,
167 SVGA3D_R32G32B32_FLOAT = 50,
168 SVGA3D_R32G32B32_UINT = 51,
169 SVGA3D_R32G32B32_SINT = 52,
170 SVGA3D_R16G16B16A16_TYPELESS = 53,
171 SVGA3D_R16G16B16A16_FLOAT = 24,
172 SVGA3D_R16G16B16A16_UNORM = 41,
173 SVGA3D_R16G16B16A16_UINT = 54,
174 SVGA3D_R16G16B16A16_SNORM = 55,
175 SVGA3D_R16G16B16A16_SINT = 56,
176 SVGA3D_R32G32_TYPELESS = 57,
177 SVGA3D_R32G32_FLOAT = 36,
178 SVGA3D_R32G32_UINT = 58,
179 SVGA3D_R32G32_SINT = 59,
180 SVGA3D_R32G8X24_TYPELESS = 60,
181 SVGA3D_D32_FLOAT_S8X24_UINT = 61,
182 SVGA3D_R32_FLOAT_X8X24_TYPELESS = 62,
183 SVGA3D_X32_TYPELESS_G8X24_UINT = 63,
184 SVGA3D_R10G10B10A2_TYPELESS = 64,
185 SVGA3D_R10G10B10A2_UNORM = 26,
186 SVGA3D_R10G10B10A2_UINT = 65,
187 SVGA3D_R11G11B10_FLOAT = 66,
188 SVGA3D_R8G8B8A8_TYPELESS = 67,
189 SVGA3D_R8G8B8A8_UNORM = 68,
190 SVGA3D_R8G8B8A8_UNORM_SRGB = 69,
191 SVGA3D_R8G8B8A8_UINT = 70,
192 SVGA3D_R8G8B8A8_SNORM = 28,
193 SVGA3D_R8G8B8A8_SINT = 71,
194 SVGA3D_R16G16_TYPELESS = 72,
195 SVGA3D_R16G16_FLOAT = 35,
196 SVGA3D_R16G16_UNORM = 40,
197 SVGA3D_R16G16_UINT = 73,
198 SVGA3D_R16G16_SNORM = 39,
199 SVGA3D_R16G16_SINT = 74,
200 SVGA3D_R32_TYPELESS = 75,
201 SVGA3D_D32_FLOAT = 76,
202 SVGA3D_R32_FLOAT = 34,
203 SVGA3D_R32_UINT = 77,
204 SVGA3D_R32_SINT = 78,
205 SVGA3D_R24G8_TYPELESS = 79,
206 SVGA3D_D24_UNORM_S8_UINT = 80,
207 SVGA3D_R24_UNORM_X8_TYPELESS = 81,
208 SVGA3D_X24_TYPELESS_G8_UINT = 82,
209 SVGA3D_R8G8_TYPELESS = 83,
210 SVGA3D_R8G8_UNORM = 84,
211 SVGA3D_R8G8_UINT = 85,
212 SVGA3D_R8G8_SNORM = 27,
213 SVGA3D_R8G8_SINT = 86,
214 SVGA3D_R16_TYPELESS = 87,
215 SVGA3D_R16_FLOAT = 33,
216 SVGA3D_D16_UNORM = 8,
217 SVGA3D_R16_UNORM = 88,
218 SVGA3D_R16_UINT = 89,
219 SVGA3D_R16_SNORM = 90,
220 SVGA3D_R16_SINT = 91,
221 SVGA3D_R8_TYPELESS = 92,
222 SVGA3D_R8_UNORM = 93,
223 SVGA3D_R8_UINT = 94,
224 SVGA3D_R8_SNORM = 95,
225 SVGA3D_R8_SINT = 96,
226 SVGA3D_A8_UNORM = 32,
227 SVGA3D_R1_UNORM = 97,
228 SVGA3D_R9G9B9E5_SHAREDEXP = 98,
229 SVGA3D_R8G8_B8G8_UNORM = 99,
230 SVGA3D_G8R8_G8B8_UNORM = 100,
231 SVGA3D_BC1_TYPELESS = 101,
232 SVGA3D_BC1_UNORM = 15,
233 SVGA3D_BC1_UNORM_SRGB = 102,
234 SVGA3D_BC2_TYPELESS = 103,
235 SVGA3D_BC2_UNORM = 17,
236 SVGA3D_BC2_UNORM_SRGB = 104,
237 SVGA3D_BC3_TYPELESS = 105,
238 SVGA3D_BC3_UNORM = 19,
239 SVGA3D_BC3_UNORM_SRGB = 106,
240 SVGA3D_BC4_TYPELESS = 107,
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200241 SVGA3D_BC4_UNORM = 108,
Thomas Hellstromd9019492012-11-21 10:17:00 +0100242 SVGA3D_BC4_SNORM = 109,
243 SVGA3D_BC5_TYPELESS = 110,
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200244 SVGA3D_BC5_UNORM = 111,
Thomas Hellstromd9019492012-11-21 10:17:00 +0100245 SVGA3D_BC5_SNORM = 112,
246 SVGA3D_B5G6R5_UNORM = 3,
247 SVGA3D_B5G5R5A1_UNORM = 5,
248 SVGA3D_B8G8R8A8_UNORM = 2,
249 SVGA3D_B8G8R8X8_UNORM = 1,
250 SVGA3D_R10G10B10_XR_BIAS_A2_UNORM = 113,
251 SVGA3D_B8G8R8A8_TYPELESS = 114,
252 SVGA3D_B8G8R8A8_UNORM_SRGB = 115,
253 SVGA3D_B8G8R8X8_TYPELESS = 116,
254 SVGA3D_B8G8R8X8_UNORM_SRGB = 117,
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200255
256 /* Advanced D3D9 depth formats. */
257 SVGA3D_Z_DF16 = 118,
258 SVGA3D_Z_DF24 = 119,
259 SVGA3D_Z_D24S8_INT = 120,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000260
Thomas Hellstromd9019492012-11-21 10:17:00 +0100261 /* Planar video formats. */
262 SVGA3D_YV12 = 121,
263
264 /* Shader constant formats. */
265 SVGA3D_SURFACE_SHADERCONST_FLOAT = 122,
266 SVGA3D_SURFACE_SHADERCONST_INT = 123,
267 SVGA3D_SURFACE_SHADERCONST_BOOL = 124,
268
269 SVGA3D_FORMAT_MAX = 125,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000270} SVGA3dSurfaceFormat;
271
272typedef uint32 SVGA3dColor; /* a, r, g, b */
273
274/*
275 * These match the D3DFORMAT_OP definitions used by Direct3D. We need
276 * them so that we can query the host for what the supported surface
277 * operations are (when we're using the D3D backend, in particular),
278 * and so we can send those operations to the guest.
279 */
280typedef enum {
281 SVGA3DFORMAT_OP_TEXTURE = 0x00000001,
282 SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002,
283 SVGA3DFORMAT_OP_CUBETEXTURE = 0x00000004,
284 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008,
285 SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010,
286 SVGA3DFORMAT_OP_ZSTENCIL = 0x00000040,
287 SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080,
288
289/*
290 * This format can be used as a render target if the current display mode
291 * is the same depth if the alpha channel is ignored. e.g. if the device
292 * can render to A8R8G8B8 when the display mode is X8R8G8B8, then the
293 * format op list entry for A8R8G8B8 should have this cap.
294 */
295 SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100,
296
297/*
298 * This format contains DirectDraw support (including Flip). This flag
299 * should not to be set on alpha formats.
300 */
301 SVGA3DFORMAT_OP_DISPLAYMODE = 0x00000400,
302
303/*
304 * The rasterizer can support some level of Direct3D support in this format
305 * and implies that the driver can create a Context in this mode (for some
306 * render target format). When this flag is set, the SVGA3DFORMAT_OP_DISPLAYMODE
307 * flag must also be set.
308 */
309 SVGA3DFORMAT_OP_3DACCELERATION = 0x00000800,
310
311/*
312 * This is set for a private format when the driver has put the bpp in
313 * the structure.
314 */
315 SVGA3DFORMAT_OP_PIXELSIZE = 0x00001000,
316
317/*
318 * Indicates that this format can be converted to any RGB format for which
319 * SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified
320 */
321 SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000,
322
323/*
324 * Indicates that this format can be used to create offscreen plain surfaces.
325 */
326 SVGA3DFORMAT_OP_OFFSCREENPLAIN = 0x00004000,
327
328/*
329 * Indicated that this format can be read as an SRGB texture (meaning that the
330 * sampler will linearize the looked up data)
331 */
332 SVGA3DFORMAT_OP_SRGBREAD = 0x00008000,
333
334/*
335 * Indicates that this format can be used in the bumpmap instructions
336 */
337 SVGA3DFORMAT_OP_BUMPMAP = 0x00010000,
338
339/*
340 * Indicates that this format can be sampled by the displacement map sampler
341 */
342 SVGA3DFORMAT_OP_DMAP = 0x00020000,
343
344/*
345 * Indicates that this format cannot be used with texture filtering
346 */
347 SVGA3DFORMAT_OP_NOFILTER = 0x00040000,
348
349/*
350 * Indicates that format conversions are supported to this RGB format if
351 * SVGA3DFORMAT_OP_CONVERT_TO_ARGB is specified in the source format.
352 */
353 SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000,
354
355/*
356 * Indicated that this format can be written as an SRGB target (meaning that the
357 * pixel pipe will DE-linearize data on output to format)
358 */
359 SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
360
361/*
362 * Indicates that this format cannot be used with alpha blending
363 */
364 SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000,
365
366/*
367 * Indicates that the device can auto-generated sublevels for resources
368 * of this format
369 */
370 SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000,
371
372/*
373 * Indicates that this format can be used by vertex texture sampler
374 */
375 SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
376
377/*
378 * Indicates that this format supports neither texture coordinate wrap
379 * modes, nor mipmapping
380 */
381 SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000
382} SVGA3dFormatOp;
383
384/*
385 * This structure is a conversion of SVGA3DFORMAT_OP_*.
386 * Entries must be located at the same position.
387 */
388typedef union {
389 uint32 value;
390 struct {
391 uint32 texture : 1;
392 uint32 volumeTexture : 1;
393 uint32 cubeTexture : 1;
394 uint32 offscreenRenderTarget : 1;
395 uint32 sameFormatRenderTarget : 1;
396 uint32 unknown1 : 1;
397 uint32 zStencil : 1;
398 uint32 zStencilArbitraryDepth : 1;
399 uint32 sameFormatUpToAlpha : 1;
400 uint32 unknown2 : 1;
401 uint32 displayMode : 1;
402 uint32 acceleration3d : 1;
403 uint32 pixelSize : 1;
404 uint32 convertToARGB : 1;
405 uint32 offscreenPlain : 1;
406 uint32 sRGBRead : 1;
407 uint32 bumpMap : 1;
408 uint32 dmap : 1;
409 uint32 noFilter : 1;
410 uint32 memberOfGroupARGB : 1;
411 uint32 sRGBWrite : 1;
412 uint32 noAlphaBlend : 1;
413 uint32 autoGenMipMap : 1;
414 uint32 vertexTexture : 1;
415 uint32 noTexCoordWrapNorMip : 1;
416 };
417} SVGA3dSurfaceFormatCaps;
418
419/*
420 * SVGA_3D_CMD_SETRENDERSTATE Types. All value types
421 * must fit in a uint32.
422 */
423
424typedef enum {
425 SVGA3D_RS_INVALID = 0,
426 SVGA3D_RS_ZENABLE = 1, /* SVGA3dBool */
427 SVGA3D_RS_ZWRITEENABLE = 2, /* SVGA3dBool */
428 SVGA3D_RS_ALPHATESTENABLE = 3, /* SVGA3dBool */
429 SVGA3D_RS_DITHERENABLE = 4, /* SVGA3dBool */
430 SVGA3D_RS_BLENDENABLE = 5, /* SVGA3dBool */
431 SVGA3D_RS_FOGENABLE = 6, /* SVGA3dBool */
432 SVGA3D_RS_SPECULARENABLE = 7, /* SVGA3dBool */
433 SVGA3D_RS_STENCILENABLE = 8, /* SVGA3dBool */
434 SVGA3D_RS_LIGHTINGENABLE = 9, /* SVGA3dBool */
435 SVGA3D_RS_NORMALIZENORMALS = 10, /* SVGA3dBool */
436 SVGA3D_RS_POINTSPRITEENABLE = 11, /* SVGA3dBool */
437 SVGA3D_RS_POINTSCALEENABLE = 12, /* SVGA3dBool */
438 SVGA3D_RS_STENCILREF = 13, /* uint32 */
439 SVGA3D_RS_STENCILMASK = 14, /* uint32 */
440 SVGA3D_RS_STENCILWRITEMASK = 15, /* uint32 */
441 SVGA3D_RS_FOGSTART = 16, /* float */
442 SVGA3D_RS_FOGEND = 17, /* float */
443 SVGA3D_RS_FOGDENSITY = 18, /* float */
444 SVGA3D_RS_POINTSIZE = 19, /* float */
445 SVGA3D_RS_POINTSIZEMIN = 20, /* float */
446 SVGA3D_RS_POINTSIZEMAX = 21, /* float */
447 SVGA3D_RS_POINTSCALE_A = 22, /* float */
448 SVGA3D_RS_POINTSCALE_B = 23, /* float */
449 SVGA3D_RS_POINTSCALE_C = 24, /* float */
450 SVGA3D_RS_FOGCOLOR = 25, /* SVGA3dColor */
451 SVGA3D_RS_AMBIENT = 26, /* SVGA3dColor */
452 SVGA3D_RS_CLIPPLANEENABLE = 27, /* SVGA3dClipPlanes */
453 SVGA3D_RS_FOGMODE = 28, /* SVGA3dFogMode */
454 SVGA3D_RS_FILLMODE = 29, /* SVGA3dFillMode */
455 SVGA3D_RS_SHADEMODE = 30, /* SVGA3dShadeMode */
456 SVGA3D_RS_LINEPATTERN = 31, /* SVGA3dLinePattern */
457 SVGA3D_RS_SRCBLEND = 32, /* SVGA3dBlendOp */
458 SVGA3D_RS_DSTBLEND = 33, /* SVGA3dBlendOp */
459 SVGA3D_RS_BLENDEQUATION = 34, /* SVGA3dBlendEquation */
460 SVGA3D_RS_CULLMODE = 35, /* SVGA3dFace */
461 SVGA3D_RS_ZFUNC = 36, /* SVGA3dCmpFunc */
462 SVGA3D_RS_ALPHAFUNC = 37, /* SVGA3dCmpFunc */
463 SVGA3D_RS_STENCILFUNC = 38, /* SVGA3dCmpFunc */
464 SVGA3D_RS_STENCILFAIL = 39, /* SVGA3dStencilOp */
465 SVGA3D_RS_STENCILZFAIL = 40, /* SVGA3dStencilOp */
466 SVGA3D_RS_STENCILPASS = 41, /* SVGA3dStencilOp */
467 SVGA3D_RS_ALPHAREF = 42, /* float (0.0 .. 1.0) */
468 SVGA3D_RS_FRONTWINDING = 43, /* SVGA3dFrontWinding */
469 SVGA3D_RS_COORDINATETYPE = 44, /* SVGA3dCoordinateType */
470 SVGA3D_RS_ZBIAS = 45, /* float */
471 SVGA3D_RS_RANGEFOGENABLE = 46, /* SVGA3dBool */
472 SVGA3D_RS_COLORWRITEENABLE = 47, /* SVGA3dColorMask */
473 SVGA3D_RS_VERTEXMATERIALENABLE = 48, /* SVGA3dBool */
474 SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49, /* SVGA3dVertexMaterial */
475 SVGA3D_RS_SPECULARMATERIALSOURCE = 50, /* SVGA3dVertexMaterial */
476 SVGA3D_RS_AMBIENTMATERIALSOURCE = 51, /* SVGA3dVertexMaterial */
477 SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52, /* SVGA3dVertexMaterial */
478 SVGA3D_RS_TEXTUREFACTOR = 53, /* SVGA3dColor */
479 SVGA3D_RS_LOCALVIEWER = 54, /* SVGA3dBool */
480 SVGA3D_RS_SCISSORTESTENABLE = 55, /* SVGA3dBool */
481 SVGA3D_RS_BLENDCOLOR = 56, /* SVGA3dColor */
482 SVGA3D_RS_STENCILENABLE2SIDED = 57, /* SVGA3dBool */
483 SVGA3D_RS_CCWSTENCILFUNC = 58, /* SVGA3dCmpFunc */
484 SVGA3D_RS_CCWSTENCILFAIL = 59, /* SVGA3dStencilOp */
485 SVGA3D_RS_CCWSTENCILZFAIL = 60, /* SVGA3dStencilOp */
486 SVGA3D_RS_CCWSTENCILPASS = 61, /* SVGA3dStencilOp */
487 SVGA3D_RS_VERTEXBLEND = 62, /* SVGA3dVertexBlendFlags */
488 SVGA3D_RS_SLOPESCALEDEPTHBIAS = 63, /* float */
489 SVGA3D_RS_DEPTHBIAS = 64, /* float */
490
491
492 /*
493 * Output Gamma Level
494 *
495 * Output gamma effects the gamma curve of colors that are output from the
496 * rendering pipeline. A value of 1.0 specifies a linear color space. If the
497 * value is <= 0.0, gamma correction is ignored and linear color space is
498 * used.
499 */
500
501 SVGA3D_RS_OUTPUTGAMMA = 65, /* float */
502 SVGA3D_RS_ZVISIBLE = 66, /* SVGA3dBool */
503 SVGA3D_RS_LASTPIXEL = 67, /* SVGA3dBool */
504 SVGA3D_RS_CLIPPING = 68, /* SVGA3dBool */
505 SVGA3D_RS_WRAP0 = 69, /* SVGA3dWrapFlags */
506 SVGA3D_RS_WRAP1 = 70, /* SVGA3dWrapFlags */
507 SVGA3D_RS_WRAP2 = 71, /* SVGA3dWrapFlags */
508 SVGA3D_RS_WRAP3 = 72, /* SVGA3dWrapFlags */
509 SVGA3D_RS_WRAP4 = 73, /* SVGA3dWrapFlags */
510 SVGA3D_RS_WRAP5 = 74, /* SVGA3dWrapFlags */
511 SVGA3D_RS_WRAP6 = 75, /* SVGA3dWrapFlags */
512 SVGA3D_RS_WRAP7 = 76, /* SVGA3dWrapFlags */
513 SVGA3D_RS_WRAP8 = 77, /* SVGA3dWrapFlags */
514 SVGA3D_RS_WRAP9 = 78, /* SVGA3dWrapFlags */
515 SVGA3D_RS_WRAP10 = 79, /* SVGA3dWrapFlags */
516 SVGA3D_RS_WRAP11 = 80, /* SVGA3dWrapFlags */
517 SVGA3D_RS_WRAP12 = 81, /* SVGA3dWrapFlags */
518 SVGA3D_RS_WRAP13 = 82, /* SVGA3dWrapFlags */
519 SVGA3D_RS_WRAP14 = 83, /* SVGA3dWrapFlags */
520 SVGA3D_RS_WRAP15 = 84, /* SVGA3dWrapFlags */
521 SVGA3D_RS_MULTISAMPLEANTIALIAS = 85, /* SVGA3dBool */
522 SVGA3D_RS_MULTISAMPLEMASK = 86, /* uint32 */
523 SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87, /* SVGA3dBool */
524 SVGA3D_RS_TWEENFACTOR = 88, /* float */
525 SVGA3D_RS_ANTIALIASEDLINEENABLE = 89, /* SVGA3dBool */
526 SVGA3D_RS_COLORWRITEENABLE1 = 90, /* SVGA3dColorMask */
527 SVGA3D_RS_COLORWRITEENABLE2 = 91, /* SVGA3dColorMask */
528 SVGA3D_RS_COLORWRITEENABLE3 = 92, /* SVGA3dColorMask */
529 SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93, /* SVGA3dBool */
530 SVGA3D_RS_SRCBLENDALPHA = 94, /* SVGA3dBlendOp */
531 SVGA3D_RS_DSTBLENDALPHA = 95, /* SVGA3dBlendOp */
532 SVGA3D_RS_BLENDEQUATIONALPHA = 96, /* SVGA3dBlendEquation */
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200533 SVGA3D_RS_TRANSPARENCYANTIALIAS = 97, /* SVGA3dTransparencyAntialiasType */
534 SVGA3D_RS_LINEAA = 98, /* SVGA3dBool */
535 SVGA3D_RS_LINEWIDTH = 99, /* float */
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000536 SVGA3D_RS_MAX
537} SVGA3dRenderStateName;
538
539typedef enum {
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200540 SVGA3D_TRANSPARENCYANTIALIAS_NORMAL = 0,
541 SVGA3D_TRANSPARENCYANTIALIAS_ALPHATOCOVERAGE = 1,
542 SVGA3D_TRANSPARENCYANTIALIAS_SUPERSAMPLE = 2,
543 SVGA3D_TRANSPARENCYANTIALIAS_MAX
544} SVGA3dTransparencyAntialiasType;
545
546typedef enum {
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000547 SVGA3D_VERTEXMATERIAL_NONE = 0, /* Use the value in the current material */
548 SVGA3D_VERTEXMATERIAL_DIFFUSE = 1, /* Use the value in the diffuse component */
549 SVGA3D_VERTEXMATERIAL_SPECULAR = 2, /* Use the value in the specular component */
550} SVGA3dVertexMaterial;
551
552typedef enum {
553 SVGA3D_FILLMODE_INVALID = 0,
554 SVGA3D_FILLMODE_POINT = 1,
555 SVGA3D_FILLMODE_LINE = 2,
556 SVGA3D_FILLMODE_FILL = 3,
557 SVGA3D_FILLMODE_MAX
558} SVGA3dFillModeType;
559
560
561typedef
562union {
563 struct {
564 uint16 mode; /* SVGA3dFillModeType */
565 uint16 face; /* SVGA3dFace */
566 };
567 uint32 uintValue;
568} SVGA3dFillMode;
569
570typedef enum {
571 SVGA3D_SHADEMODE_INVALID = 0,
572 SVGA3D_SHADEMODE_FLAT = 1,
573 SVGA3D_SHADEMODE_SMOOTH = 2,
574 SVGA3D_SHADEMODE_PHONG = 3, /* Not supported */
575 SVGA3D_SHADEMODE_MAX
576} SVGA3dShadeMode;
577
578typedef
579union {
580 struct {
581 uint16 repeat;
582 uint16 pattern;
583 };
584 uint32 uintValue;
585} SVGA3dLinePattern;
586
587typedef enum {
588 SVGA3D_BLENDOP_INVALID = 0,
589 SVGA3D_BLENDOP_ZERO = 1,
590 SVGA3D_BLENDOP_ONE = 2,
591 SVGA3D_BLENDOP_SRCCOLOR = 3,
592 SVGA3D_BLENDOP_INVSRCCOLOR = 4,
593 SVGA3D_BLENDOP_SRCALPHA = 5,
594 SVGA3D_BLENDOP_INVSRCALPHA = 6,
595 SVGA3D_BLENDOP_DESTALPHA = 7,
596 SVGA3D_BLENDOP_INVDESTALPHA = 8,
597 SVGA3D_BLENDOP_DESTCOLOR = 9,
598 SVGA3D_BLENDOP_INVDESTCOLOR = 10,
599 SVGA3D_BLENDOP_SRCALPHASAT = 11,
600 SVGA3D_BLENDOP_BLENDFACTOR = 12,
601 SVGA3D_BLENDOP_INVBLENDFACTOR = 13,
602 SVGA3D_BLENDOP_MAX
603} SVGA3dBlendOp;
604
605typedef enum {
606 SVGA3D_BLENDEQ_INVALID = 0,
607 SVGA3D_BLENDEQ_ADD = 1,
608 SVGA3D_BLENDEQ_SUBTRACT = 2,
609 SVGA3D_BLENDEQ_REVSUBTRACT = 3,
610 SVGA3D_BLENDEQ_MINIMUM = 4,
611 SVGA3D_BLENDEQ_MAXIMUM = 5,
612 SVGA3D_BLENDEQ_MAX
613} SVGA3dBlendEquation;
614
615typedef enum {
616 SVGA3D_FRONTWINDING_INVALID = 0,
617 SVGA3D_FRONTWINDING_CW = 1,
618 SVGA3D_FRONTWINDING_CCW = 2,
619 SVGA3D_FRONTWINDING_MAX
620} SVGA3dFrontWinding;
621
622typedef enum {
623 SVGA3D_FACE_INVALID = 0,
624 SVGA3D_FACE_NONE = 1,
625 SVGA3D_FACE_FRONT = 2,
626 SVGA3D_FACE_BACK = 3,
627 SVGA3D_FACE_FRONT_BACK = 4,
628 SVGA3D_FACE_MAX
629} SVGA3dFace;
630
631/*
632 * The order and the values should not be changed
633 */
634
635typedef enum {
636 SVGA3D_CMP_INVALID = 0,
637 SVGA3D_CMP_NEVER = 1,
638 SVGA3D_CMP_LESS = 2,
639 SVGA3D_CMP_EQUAL = 3,
640 SVGA3D_CMP_LESSEQUAL = 4,
641 SVGA3D_CMP_GREATER = 5,
642 SVGA3D_CMP_NOTEQUAL = 6,
643 SVGA3D_CMP_GREATEREQUAL = 7,
644 SVGA3D_CMP_ALWAYS = 8,
645 SVGA3D_CMP_MAX
646} SVGA3dCmpFunc;
647
648/*
649 * SVGA3D_FOGFUNC_* specifies the fog equation, or PER_VERTEX which allows
650 * the fog factor to be specified in the alpha component of the specular
651 * (a.k.a. secondary) vertex color.
652 */
653typedef enum {
654 SVGA3D_FOGFUNC_INVALID = 0,
655 SVGA3D_FOGFUNC_EXP = 1,
656 SVGA3D_FOGFUNC_EXP2 = 2,
657 SVGA3D_FOGFUNC_LINEAR = 3,
658 SVGA3D_FOGFUNC_PER_VERTEX = 4
659} SVGA3dFogFunction;
660
661/*
662 * SVGA3D_FOGTYPE_* specifies if fog factors are computed on a per-vertex
663 * or per-pixel basis.
664 */
665typedef enum {
666 SVGA3D_FOGTYPE_INVALID = 0,
667 SVGA3D_FOGTYPE_VERTEX = 1,
668 SVGA3D_FOGTYPE_PIXEL = 2,
669 SVGA3D_FOGTYPE_MAX = 3
670} SVGA3dFogType;
671
672/*
673 * SVGA3D_FOGBASE_* selects depth or range-based fog. Depth-based fog is
674 * computed using the eye Z value of each pixel (or vertex), whereas range-
675 * based fog is computed using the actual distance (range) to the eye.
676 */
677typedef enum {
678 SVGA3D_FOGBASE_INVALID = 0,
679 SVGA3D_FOGBASE_DEPTHBASED = 1,
680 SVGA3D_FOGBASE_RANGEBASED = 2,
681 SVGA3D_FOGBASE_MAX = 3
682} SVGA3dFogBase;
683
684typedef enum {
685 SVGA3D_STENCILOP_INVALID = 0,
686 SVGA3D_STENCILOP_KEEP = 1,
687 SVGA3D_STENCILOP_ZERO = 2,
688 SVGA3D_STENCILOP_REPLACE = 3,
689 SVGA3D_STENCILOP_INCRSAT = 4,
690 SVGA3D_STENCILOP_DECRSAT = 5,
691 SVGA3D_STENCILOP_INVERT = 6,
692 SVGA3D_STENCILOP_INCR = 7,
693 SVGA3D_STENCILOP_DECR = 8,
694 SVGA3D_STENCILOP_MAX
695} SVGA3dStencilOp;
696
697typedef enum {
698 SVGA3D_CLIPPLANE_0 = (1 << 0),
699 SVGA3D_CLIPPLANE_1 = (1 << 1),
700 SVGA3D_CLIPPLANE_2 = (1 << 2),
701 SVGA3D_CLIPPLANE_3 = (1 << 3),
702 SVGA3D_CLIPPLANE_4 = (1 << 4),
703 SVGA3D_CLIPPLANE_5 = (1 << 5),
704} SVGA3dClipPlanes;
705
706typedef enum {
707 SVGA3D_CLEAR_COLOR = 0x1,
708 SVGA3D_CLEAR_DEPTH = 0x2,
709 SVGA3D_CLEAR_STENCIL = 0x4
710} SVGA3dClearFlag;
711
712typedef enum {
713 SVGA3D_RT_DEPTH = 0,
714 SVGA3D_RT_STENCIL = 1,
715 SVGA3D_RT_COLOR0 = 2,
716 SVGA3D_RT_COLOR1 = 3,
717 SVGA3D_RT_COLOR2 = 4,
718 SVGA3D_RT_COLOR3 = 5,
719 SVGA3D_RT_COLOR4 = 6,
720 SVGA3D_RT_COLOR5 = 7,
721 SVGA3D_RT_COLOR6 = 8,
722 SVGA3D_RT_COLOR7 = 9,
723 SVGA3D_RT_MAX,
724 SVGA3D_RT_INVALID = ((uint32)-1),
725} SVGA3dRenderTargetType;
726
727#define SVGA3D_MAX_RT_COLOR (SVGA3D_RT_COLOR7 - SVGA3D_RT_COLOR0 + 1)
728
729typedef
730union {
731 struct {
732 uint32 red : 1;
733 uint32 green : 1;
734 uint32 blue : 1;
735 uint32 alpha : 1;
736 };
737 uint32 uintValue;
738} SVGA3dColorMask;
739
740typedef enum {
741 SVGA3D_VBLEND_DISABLE = 0,
742 SVGA3D_VBLEND_1WEIGHT = 1,
743 SVGA3D_VBLEND_2WEIGHT = 2,
744 SVGA3D_VBLEND_3WEIGHT = 3,
745} SVGA3dVertexBlendFlags;
746
747typedef enum {
748 SVGA3D_WRAPCOORD_0 = 1 << 0,
749 SVGA3D_WRAPCOORD_1 = 1 << 1,
750 SVGA3D_WRAPCOORD_2 = 1 << 2,
751 SVGA3D_WRAPCOORD_3 = 1 << 3,
752 SVGA3D_WRAPCOORD_ALL = 0xF,
753} SVGA3dWrapFlags;
754
755/*
756 * SVGA_3D_CMD_TEXTURESTATE Types. All value types
757 * must fit in a uint32.
758 */
759
760typedef enum {
761 SVGA3D_TS_INVALID = 0,
762 SVGA3D_TS_BIND_TEXTURE = 1, /* SVGA3dSurfaceId */
763 SVGA3D_TS_COLOROP = 2, /* SVGA3dTextureCombiner */
764 SVGA3D_TS_COLORARG1 = 3, /* SVGA3dTextureArgData */
765 SVGA3D_TS_COLORARG2 = 4, /* SVGA3dTextureArgData */
766 SVGA3D_TS_ALPHAOP = 5, /* SVGA3dTextureCombiner */
767 SVGA3D_TS_ALPHAARG1 = 6, /* SVGA3dTextureArgData */
768 SVGA3D_TS_ALPHAARG2 = 7, /* SVGA3dTextureArgData */
769 SVGA3D_TS_ADDRESSU = 8, /* SVGA3dTextureAddress */
770 SVGA3D_TS_ADDRESSV = 9, /* SVGA3dTextureAddress */
771 SVGA3D_TS_MIPFILTER = 10, /* SVGA3dTextureFilter */
772 SVGA3D_TS_MAGFILTER = 11, /* SVGA3dTextureFilter */
773 SVGA3D_TS_MINFILTER = 12, /* SVGA3dTextureFilter */
774 SVGA3D_TS_BORDERCOLOR = 13, /* SVGA3dColor */
775 SVGA3D_TS_TEXCOORDINDEX = 14, /* uint32 */
776 SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15, /* SVGA3dTexTransformFlags */
777 SVGA3D_TS_TEXCOORDGEN = 16, /* SVGA3dTextureCoordGen */
778 SVGA3D_TS_BUMPENVMAT00 = 17, /* float */
779 SVGA3D_TS_BUMPENVMAT01 = 18, /* float */
780 SVGA3D_TS_BUMPENVMAT10 = 19, /* float */
781 SVGA3D_TS_BUMPENVMAT11 = 20, /* float */
782 SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21, /* uint32 */
783 SVGA3D_TS_TEXTURE_LOD_BIAS = 22, /* float */
784 SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23, /* uint32 */
785 SVGA3D_TS_ADDRESSW = 24, /* SVGA3dTextureAddress */
786
787
788 /*
789 * Sampler Gamma Level
790 *
791 * Sampler gamma effects the color of samples taken from the sampler. A
792 * value of 1.0 will produce linear samples. If the value is <= 0.0 the
793 * gamma value is ignored and a linear space is used.
794 */
795
796 SVGA3D_TS_GAMMA = 25, /* float */
797 SVGA3D_TS_BUMPENVLSCALE = 26, /* float */
798 SVGA3D_TS_BUMPENVLOFFSET = 27, /* float */
799 SVGA3D_TS_COLORARG0 = 28, /* SVGA3dTextureArgData */
800 SVGA3D_TS_ALPHAARG0 = 29, /* SVGA3dTextureArgData */
801 SVGA3D_TS_MAX
802} SVGA3dTextureStateName;
803
804typedef enum {
805 SVGA3D_TC_INVALID = 0,
806 SVGA3D_TC_DISABLE = 1,
807 SVGA3D_TC_SELECTARG1 = 2,
808 SVGA3D_TC_SELECTARG2 = 3,
809 SVGA3D_TC_MODULATE = 4,
810 SVGA3D_TC_ADD = 5,
811 SVGA3D_TC_ADDSIGNED = 6,
812 SVGA3D_TC_SUBTRACT = 7,
813 SVGA3D_TC_BLENDTEXTUREALPHA = 8,
814 SVGA3D_TC_BLENDDIFFUSEALPHA = 9,
815 SVGA3D_TC_BLENDCURRENTALPHA = 10,
816 SVGA3D_TC_BLENDFACTORALPHA = 11,
817 SVGA3D_TC_MODULATE2X = 12,
818 SVGA3D_TC_MODULATE4X = 13,
819 SVGA3D_TC_DSDT = 14,
820 SVGA3D_TC_DOTPRODUCT3 = 15,
821 SVGA3D_TC_BLENDTEXTUREALPHAPM = 16,
822 SVGA3D_TC_ADDSIGNED2X = 17,
823 SVGA3D_TC_ADDSMOOTH = 18,
824 SVGA3D_TC_PREMODULATE = 19,
825 SVGA3D_TC_MODULATEALPHA_ADDCOLOR = 20,
826 SVGA3D_TC_MODULATECOLOR_ADDALPHA = 21,
827 SVGA3D_TC_MODULATEINVALPHA_ADDCOLOR = 22,
828 SVGA3D_TC_MODULATEINVCOLOR_ADDALPHA = 23,
829 SVGA3D_TC_BUMPENVMAPLUMINANCE = 24,
830 SVGA3D_TC_MULTIPLYADD = 25,
831 SVGA3D_TC_LERP = 26,
832 SVGA3D_TC_MAX
833} SVGA3dTextureCombiner;
834
835#define SVGA3D_TC_CAP_BIT(svga3d_tc_op) (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0)
836
837typedef enum {
838 SVGA3D_TEX_ADDRESS_INVALID = 0,
839 SVGA3D_TEX_ADDRESS_WRAP = 1,
840 SVGA3D_TEX_ADDRESS_MIRROR = 2,
841 SVGA3D_TEX_ADDRESS_CLAMP = 3,
842 SVGA3D_TEX_ADDRESS_BORDER = 4,
843 SVGA3D_TEX_ADDRESS_MIRRORONCE = 5,
844 SVGA3D_TEX_ADDRESS_EDGE = 6,
845 SVGA3D_TEX_ADDRESS_MAX
846} SVGA3dTextureAddress;
847
848/*
849 * SVGA3D_TEX_FILTER_NONE as the minification filter means mipmapping is
850 * disabled, and the rasterizer should use the magnification filter instead.
851 */
852typedef enum {
853 SVGA3D_TEX_FILTER_NONE = 0,
854 SVGA3D_TEX_FILTER_NEAREST = 1,
855 SVGA3D_TEX_FILTER_LINEAR = 2,
856 SVGA3D_TEX_FILTER_ANISOTROPIC = 3,
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200857 SVGA3D_TEX_FILTER_FLATCUBIC = 4, /* Deprecated, not implemented */
858 SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5, /* Deprecated, not implemented */
859 SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6, /* Not currently implemented */
860 SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7, /* Not currently implemented */
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000861 SVGA3D_TEX_FILTER_MAX
862} SVGA3dTextureFilter;
863
864typedef enum {
865 SVGA3D_TEX_TRANSFORM_OFF = 0,
866 SVGA3D_TEX_TRANSFORM_S = (1 << 0),
867 SVGA3D_TEX_TRANSFORM_T = (1 << 1),
868 SVGA3D_TEX_TRANSFORM_R = (1 << 2),
869 SVGA3D_TEX_TRANSFORM_Q = (1 << 3),
870 SVGA3D_TEX_PROJECTED = (1 << 15),
871} SVGA3dTexTransformFlags;
872
873typedef enum {
874 SVGA3D_TEXCOORD_GEN_OFF = 0,
875 SVGA3D_TEXCOORD_GEN_EYE_POSITION = 1,
876 SVGA3D_TEXCOORD_GEN_EYE_NORMAL = 2,
877 SVGA3D_TEXCOORD_GEN_REFLECTIONVECTOR = 3,
878 SVGA3D_TEXCOORD_GEN_SPHERE = 4,
879 SVGA3D_TEXCOORD_GEN_MAX
880} SVGA3dTextureCoordGen;
881
882/*
883 * Texture argument constants for texture combiner
884 */
885typedef enum {
886 SVGA3D_TA_INVALID = 0,
887 SVGA3D_TA_CONSTANT = 1,
888 SVGA3D_TA_PREVIOUS = 2,
889 SVGA3D_TA_DIFFUSE = 3,
890 SVGA3D_TA_TEXTURE = 4,
891 SVGA3D_TA_SPECULAR = 5,
892 SVGA3D_TA_MAX
893} SVGA3dTextureArgData;
894
895#define SVGA3D_TM_MASK_LEN 4
896
897/* Modifiers for texture argument constants defined above. */
898typedef enum {
899 SVGA3D_TM_NONE = 0,
900 SVGA3D_TM_ALPHA = (1 << SVGA3D_TM_MASK_LEN),
901 SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN),
902} SVGA3dTextureArgModifier;
903
904#define SVGA3D_INVALID_ID ((uint32)-1)
905#define SVGA3D_MAX_CLIP_PLANES 6
906
907/*
908 * This is the limit to the number of fixed-function texture
909 * transforms and texture coordinates we can support. It does *not*
910 * correspond to the number of texture image units (samplers) we
911 * support!
912 */
913#define SVGA3D_MAX_TEXTURE_COORDS 8
914
915/*
916 * Vertex declarations
917 *
918 * Notes:
919 *
920 * SVGA3D_DECLUSAGE_POSITIONT is for pre-transformed vertices. If you
921 * draw with any POSITIONT vertex arrays, the programmable vertex
922 * pipeline will be implicitly disabled. Drawing will take place as if
923 * no vertex shader was bound.
924 */
925
926typedef enum {
927 SVGA3D_DECLUSAGE_POSITION = 0,
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200928 SVGA3D_DECLUSAGE_BLENDWEIGHT, /* 1 */
929 SVGA3D_DECLUSAGE_BLENDINDICES, /* 2 */
930 SVGA3D_DECLUSAGE_NORMAL, /* 3 */
931 SVGA3D_DECLUSAGE_PSIZE, /* 4 */
932 SVGA3D_DECLUSAGE_TEXCOORD, /* 5 */
933 SVGA3D_DECLUSAGE_TANGENT, /* 6 */
934 SVGA3D_DECLUSAGE_BINORMAL, /* 7 */
935 SVGA3D_DECLUSAGE_TESSFACTOR, /* 8 */
936 SVGA3D_DECLUSAGE_POSITIONT, /* 9 */
937 SVGA3D_DECLUSAGE_COLOR, /* 10 */
938 SVGA3D_DECLUSAGE_FOG, /* 11 */
939 SVGA3D_DECLUSAGE_DEPTH, /* 12 */
940 SVGA3D_DECLUSAGE_SAMPLE, /* 13 */
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000941 SVGA3D_DECLUSAGE_MAX
942} SVGA3dDeclUsage;
943
944typedef enum {
945 SVGA3D_DECLMETHOD_DEFAULT = 0,
946 SVGA3D_DECLMETHOD_PARTIALU,
947 SVGA3D_DECLMETHOD_PARTIALV,
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200948 SVGA3D_DECLMETHOD_CROSSUV, /* Normal */
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000949 SVGA3D_DECLMETHOD_UV,
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +0200950 SVGA3D_DECLMETHOD_LOOKUP, /* Lookup a displacement map */
951 SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED, /* Lookup a pre-sampled displacement map */
Jakob Bornecrantz632f6112009-12-10 00:19:10 +0000952} SVGA3dDeclMethod;
953
954typedef enum {
955 SVGA3D_DECLTYPE_FLOAT1 = 0,
956 SVGA3D_DECLTYPE_FLOAT2 = 1,
957 SVGA3D_DECLTYPE_FLOAT3 = 2,
958 SVGA3D_DECLTYPE_FLOAT4 = 3,
959 SVGA3D_DECLTYPE_D3DCOLOR = 4,
960 SVGA3D_DECLTYPE_UBYTE4 = 5,
961 SVGA3D_DECLTYPE_SHORT2 = 6,
962 SVGA3D_DECLTYPE_SHORT4 = 7,
963 SVGA3D_DECLTYPE_UBYTE4N = 8,
964 SVGA3D_DECLTYPE_SHORT2N = 9,
965 SVGA3D_DECLTYPE_SHORT4N = 10,
966 SVGA3D_DECLTYPE_USHORT2N = 11,
967 SVGA3D_DECLTYPE_USHORT4N = 12,
968 SVGA3D_DECLTYPE_UDEC3 = 13,
969 SVGA3D_DECLTYPE_DEC3N = 14,
970 SVGA3D_DECLTYPE_FLOAT16_2 = 15,
971 SVGA3D_DECLTYPE_FLOAT16_4 = 16,
972 SVGA3D_DECLTYPE_MAX,
973} SVGA3dDeclType;
974
975/*
976 * This structure is used for the divisor for geometry instancing;
977 * it's a direct translation of the Direct3D equivalent.
978 */
979typedef union {
980 struct {
981 /*
982 * For index data, this number represents the number of instances to draw.
983 * For instance data, this number represents the number of
984 * instances/vertex in this stream
985 */
986 uint32 count : 30;
987
988 /*
989 * This is 1 if this is supposed to be the data that is repeated for
990 * every instance.
991 */
992 uint32 indexedData : 1;
993
994 /*
995 * This is 1 if this is supposed to be the per-instance data.
996 */
997 uint32 instanceData : 1;
998 };
999
1000 uint32 value;
1001} SVGA3dVertexDivisor;
1002
1003typedef enum {
1004 SVGA3D_PRIMITIVE_INVALID = 0,
1005 SVGA3D_PRIMITIVE_TRIANGLELIST = 1,
1006 SVGA3D_PRIMITIVE_POINTLIST = 2,
1007 SVGA3D_PRIMITIVE_LINELIST = 3,
1008 SVGA3D_PRIMITIVE_LINESTRIP = 4,
1009 SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5,
1010 SVGA3D_PRIMITIVE_TRIANGLEFAN = 6,
1011 SVGA3D_PRIMITIVE_MAX
1012} SVGA3dPrimitiveType;
1013
1014typedef enum {
1015 SVGA3D_COORDINATE_INVALID = 0,
1016 SVGA3D_COORDINATE_LEFTHANDED = 1,
1017 SVGA3D_COORDINATE_RIGHTHANDED = 2,
1018 SVGA3D_COORDINATE_MAX
1019} SVGA3dCoordinateType;
1020
1021typedef enum {
1022 SVGA3D_TRANSFORM_INVALID = 0,
1023 SVGA3D_TRANSFORM_WORLD = 1,
1024 SVGA3D_TRANSFORM_VIEW = 2,
1025 SVGA3D_TRANSFORM_PROJECTION = 3,
1026 SVGA3D_TRANSFORM_TEXTURE0 = 4,
1027 SVGA3D_TRANSFORM_TEXTURE1 = 5,
1028 SVGA3D_TRANSFORM_TEXTURE2 = 6,
1029 SVGA3D_TRANSFORM_TEXTURE3 = 7,
1030 SVGA3D_TRANSFORM_TEXTURE4 = 8,
1031 SVGA3D_TRANSFORM_TEXTURE5 = 9,
1032 SVGA3D_TRANSFORM_TEXTURE6 = 10,
1033 SVGA3D_TRANSFORM_TEXTURE7 = 11,
1034 SVGA3D_TRANSFORM_WORLD1 = 12,
1035 SVGA3D_TRANSFORM_WORLD2 = 13,
1036 SVGA3D_TRANSFORM_WORLD3 = 14,
1037 SVGA3D_TRANSFORM_MAX
1038} SVGA3dTransformType;
1039
1040typedef enum {
1041 SVGA3D_LIGHTTYPE_INVALID = 0,
1042 SVGA3D_LIGHTTYPE_POINT = 1,
1043 SVGA3D_LIGHTTYPE_SPOT1 = 2, /* 1-cone, in degrees */
1044 SVGA3D_LIGHTTYPE_SPOT2 = 3, /* 2-cone, in radians */
1045 SVGA3D_LIGHTTYPE_DIRECTIONAL = 4,
1046 SVGA3D_LIGHTTYPE_MAX
1047} SVGA3dLightType;
1048
1049typedef enum {
1050 SVGA3D_CUBEFACE_POSX = 0,
1051 SVGA3D_CUBEFACE_NEGX = 1,
1052 SVGA3D_CUBEFACE_POSY = 2,
1053 SVGA3D_CUBEFACE_NEGY = 3,
1054 SVGA3D_CUBEFACE_POSZ = 4,
1055 SVGA3D_CUBEFACE_NEGZ = 5,
1056} SVGA3dCubeFace;
1057
1058typedef enum {
Thomas Hellstromd9019492012-11-21 10:17:00 +01001059 SVGA3D_SHADERTYPE_INVALID = 0,
1060 SVGA3D_SHADERTYPE_MIN = 1,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001061 SVGA3D_SHADERTYPE_VS = 1,
1062 SVGA3D_SHADERTYPE_PS = 2,
Thomas Hellstromd9019492012-11-21 10:17:00 +01001063 SVGA3D_SHADERTYPE_MAX = 3,
1064 SVGA3D_SHADERTYPE_GS = 3,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001065} SVGA3dShaderType;
1066
Thomas Hellstromd9019492012-11-21 10:17:00 +01001067#define SVGA3D_NUM_SHADERTYPE (SVGA3D_SHADERTYPE_MAX - SVGA3D_SHADERTYPE_MIN)
1068
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001069typedef enum {
1070 SVGA3D_CONST_TYPE_FLOAT = 0,
1071 SVGA3D_CONST_TYPE_INT = 1,
1072 SVGA3D_CONST_TYPE_BOOL = 2,
Thomas Hellstromd9019492012-11-21 10:17:00 +01001073 SVGA3D_CONST_TYPE_MAX
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001074} SVGA3dShaderConstType;
1075
1076#define SVGA3D_MAX_SURFACE_FACES 6
1077
1078typedef enum {
1079 SVGA3D_STRETCH_BLT_POINT = 0,
1080 SVGA3D_STRETCH_BLT_LINEAR = 1,
1081 SVGA3D_STRETCH_BLT_MAX
1082} SVGA3dStretchBltMode;
1083
1084typedef enum {
1085 SVGA3D_QUERYTYPE_OCCLUSION = 0,
1086 SVGA3D_QUERYTYPE_MAX
1087} SVGA3dQueryType;
1088
1089typedef enum {
1090 SVGA3D_QUERYSTATE_PENDING = 0, /* Waiting on the host (set by guest) */
1091 SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully (set by host) */
1092 SVGA3D_QUERYSTATE_FAILED = 2, /* Completed unsuccessfully (set by host) */
1093 SVGA3D_QUERYSTATE_NEW = 3, /* Never submitted (For guest use only) */
1094} SVGA3dQueryState;
1095
1096typedef enum {
1097 SVGA3D_WRITE_HOST_VRAM = 1,
1098 SVGA3D_READ_HOST_VRAM = 2,
1099} SVGA3dTransferType;
1100
1101/*
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +02001102 * The maximum number of vertex arrays we're guaranteed to support in
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001103 * SVGA_3D_CMD_DRAWPRIMITIVES.
1104 */
1105#define SVGA3D_MAX_VERTEX_ARRAYS 32
1106
1107/*
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +02001108 * The maximum number of primitive ranges we're guaranteed to support
1109 * in SVGA_3D_CMD_DRAWPRIMITIVES.
1110 */
1111#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32
1112
1113/*
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001114 * Identifiers for commands in the command FIFO.
1115 *
1116 * IDs between 1000 and 1039 (inclusive) were used by obsolete versions of
1117 * the SVGA3D protocol and remain reserved; they should not be used in the
1118 * future.
1119 *
1120 * IDs between 1040 and 1999 (inclusive) are available for use by the
1121 * current SVGA3D protocol.
1122 *
1123 * FIFO clients other than SVGA3D should stay below 1000, or at 2000
1124 * and up.
1125 */
1126
1127#define SVGA_3D_CMD_LEGACY_BASE 1000
1128#define SVGA_3D_CMD_BASE 1040
1129
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +02001130#define SVGA_3D_CMD_SURFACE_DEFINE SVGA_3D_CMD_BASE + 0 /* Deprecated */
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001131#define SVGA_3D_CMD_SURFACE_DESTROY SVGA_3D_CMD_BASE + 1
1132#define SVGA_3D_CMD_SURFACE_COPY SVGA_3D_CMD_BASE + 2
1133#define SVGA_3D_CMD_SURFACE_STRETCHBLT SVGA_3D_CMD_BASE + 3
1134#define SVGA_3D_CMD_SURFACE_DMA SVGA_3D_CMD_BASE + 4
1135#define SVGA_3D_CMD_CONTEXT_DEFINE SVGA_3D_CMD_BASE + 5
1136#define SVGA_3D_CMD_CONTEXT_DESTROY SVGA_3D_CMD_BASE + 6
1137#define SVGA_3D_CMD_SETTRANSFORM SVGA_3D_CMD_BASE + 7
1138#define SVGA_3D_CMD_SETZRANGE SVGA_3D_CMD_BASE + 8
1139#define SVGA_3D_CMD_SETRENDERSTATE SVGA_3D_CMD_BASE + 9
1140#define SVGA_3D_CMD_SETRENDERTARGET SVGA_3D_CMD_BASE + 10
1141#define SVGA_3D_CMD_SETTEXTURESTATE SVGA_3D_CMD_BASE + 11
1142#define SVGA_3D_CMD_SETMATERIAL SVGA_3D_CMD_BASE + 12
1143#define SVGA_3D_CMD_SETLIGHTDATA SVGA_3D_CMD_BASE + 13
1144#define SVGA_3D_CMD_SETLIGHTENABLED SVGA_3D_CMD_BASE + 14
1145#define SVGA_3D_CMD_SETVIEWPORT SVGA_3D_CMD_BASE + 15
1146#define SVGA_3D_CMD_SETCLIPPLANE SVGA_3D_CMD_BASE + 16
1147#define SVGA_3D_CMD_CLEAR SVGA_3D_CMD_BASE + 17
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +02001148#define SVGA_3D_CMD_PRESENT SVGA_3D_CMD_BASE + 18 /* Deprecated */
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001149#define SVGA_3D_CMD_SHADER_DEFINE SVGA_3D_CMD_BASE + 19
1150#define SVGA_3D_CMD_SHADER_DESTROY SVGA_3D_CMD_BASE + 20
1151#define SVGA_3D_CMD_SET_SHADER SVGA_3D_CMD_BASE + 21
1152#define SVGA_3D_CMD_SET_SHADER_CONST SVGA_3D_CMD_BASE + 22
1153#define SVGA_3D_CMD_DRAW_PRIMITIVES SVGA_3D_CMD_BASE + 23
1154#define SVGA_3D_CMD_SETSCISSORRECT SVGA_3D_CMD_BASE + 24
1155#define SVGA_3D_CMD_BEGIN_QUERY SVGA_3D_CMD_BASE + 25
1156#define SVGA_3D_CMD_END_QUERY SVGA_3D_CMD_BASE + 26
1157#define SVGA_3D_CMD_WAIT_FOR_QUERY SVGA_3D_CMD_BASE + 27
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +02001158#define SVGA_3D_CMD_PRESENT_READBACK SVGA_3D_CMD_BASE + 28 /* Deprecated */
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001159#define SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN SVGA_3D_CMD_BASE + 29
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +02001160#define SVGA_3D_CMD_SURFACE_DEFINE_V2 SVGA_3D_CMD_BASE + 30
1161#define SVGA_3D_CMD_GENERATE_MIPMAPS SVGA_3D_CMD_BASE + 31
1162#define SVGA_3D_CMD_ACTIVATE_SURFACE SVGA_3D_CMD_BASE + 40
1163#define SVGA_3D_CMD_DEACTIVATE_SURFACE SVGA_3D_CMD_BASE + 41
Thomas Hellstromd9019492012-11-21 10:17:00 +01001164#define SVGA_3D_CMD_SCREEN_DMA 1082
1165#define SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE 1083
1166#define SVGA_3D_CMD_OPEN_CONTEXT_SURFACE 1084
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001167
Thomas Hellstromd9019492012-11-21 10:17:00 +01001168#define SVGA_3D_CMD_LOGICOPS_BITBLT 1085
1169#define SVGA_3D_CMD_LOGICOPS_TRANSBLT 1086
1170#define SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1087
1171#define SVGA_3D_CMD_LOGICOPS_COLORFILL 1088
1172#define SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1089
1173#define SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1090
1174
1175#define SVGA_3D_CMD_SET_OTABLE_BASE 1091
1176#define SVGA_3D_CMD_READBACK_OTABLE 1092
1177
1178#define SVGA_3D_CMD_DEFINE_GB_MOB 1093
1179#define SVGA_3D_CMD_DESTROY_GB_MOB 1094
1180#define SVGA_3D_CMD_REDEFINE_GB_MOB 1095
1181#define SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING 1096
1182
1183#define SVGA_3D_CMD_DEFINE_GB_SURFACE 1097
1184#define SVGA_3D_CMD_DESTROY_GB_SURFACE 1098
1185#define SVGA_3D_CMD_BIND_GB_SURFACE 1099
1186#define SVGA_3D_CMD_COND_BIND_GB_SURFACE 1100
1187#define SVGA_3D_CMD_UPDATE_GB_IMAGE 1101
1188#define SVGA_3D_CMD_UPDATE_GB_SURFACE 1102
1189#define SVGA_3D_CMD_READBACK_GB_IMAGE 1103
1190#define SVGA_3D_CMD_READBACK_GB_SURFACE 1104
1191#define SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105
1192#define SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106
1193
1194#define SVGA_3D_CMD_DEFINE_GB_CONTEXT 1107
1195#define SVGA_3D_CMD_DESTROY_GB_CONTEXT 1108
1196#define SVGA_3D_CMD_BIND_GB_CONTEXT 1109
1197#define SVGA_3D_CMD_READBACK_GB_CONTEXT 1110
1198#define SVGA_3D_CMD_INVALIDATE_GB_CONTEXT 1111
1199
1200#define SVGA_3D_CMD_DEFINE_GB_SHADER 1112
1201#define SVGA_3D_CMD_DESTROY_GB_SHADER 1113
1202#define SVGA_3D_CMD_BIND_GB_SHADER 1114
1203
Thomas Hellstromf2a0dcb2014-01-15 10:04:07 +01001204#define SVGA_3D_CMD_SET_OTABLE_BASE64 1115
Thomas Hellstromd9019492012-11-21 10:17:00 +01001205
1206#define SVGA_3D_CMD_BEGIN_GB_QUERY 1116
1207#define SVGA_3D_CMD_END_GB_QUERY 1117
1208#define SVGA_3D_CMD_WAIT_FOR_GB_QUERY 1118
1209
1210#define SVGA_3D_CMD_NOP 1119
1211
1212#define SVGA_3D_CMD_ENABLE_GART 1120
1213#define SVGA_3D_CMD_DISABLE_GART 1121
1214#define SVGA_3D_CMD_MAP_MOB_INTO_GART 1122
1215#define SVGA_3D_CMD_UNMAP_GART_RANGE 1123
1216
1217#define SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124
1218#define SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125
1219#define SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126
1220#define SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127
1221
1222#define SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL 1128
1223#define SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL 1129
1224
1225#define SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE 1130
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01001226#define SVGA_3D_CMD_GB_SCREEN_DMA 1131
1227#define SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH 1132
1228#define SVGA_3D_CMD_GB_MOB_FENCE 1133
1229#define SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134
Thomas Hellstromf2a0dcb2014-01-15 10:04:07 +01001230#define SVGA_3D_CMD_DEFINE_GB_MOB64 1135
1231#define SVGA_3D_CMD_REDEFINE_GB_MOB64 1136
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01001232#define SVGA_3D_CMD_NOP_ERROR 1137
1233
1234#define SVGA_3D_CMD_RESERVED1 1138
1235#define SVGA_3D_CMD_RESERVED2 1139
1236#define SVGA_3D_CMD_RESERVED3 1140
1237#define SVGA_3D_CMD_RESERVED4 1141
1238#define SVGA_3D_CMD_RESERVED5 1142
Thomas Hellstromf2a0dcb2014-01-15 10:04:07 +01001239
1240#define SVGA_3D_CMD_MAX 1142
Thomas Hellstromd9019492012-11-21 10:17:00 +01001241#define SVGA_3D_CMD_FUTURE_MAX 3000
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001242
1243/*
1244 * Common substructures used in multiple FIFO commands:
1245 */
1246
1247typedef struct {
1248 union {
1249 struct {
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +02001250 uint16 function; /* SVGA3dFogFunction */
1251 uint8 type; /* SVGA3dFogType */
1252 uint8 base; /* SVGA3dFogBase */
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001253 };
1254 uint32 uintValue;
1255 };
1256} SVGA3dFogMode;
1257
1258/*
1259 * Uniquely identify one image (a 1D/2D/3D array) from a surface. This
1260 * is a surface ID as well as face/mipmap indices.
1261 */
1262
1263typedef
1264struct SVGA3dSurfaceImageId {
1265 uint32 sid;
1266 uint32 face;
1267 uint32 mipmap;
1268} SVGA3dSurfaceImageId;
1269
1270typedef
1271struct SVGA3dGuestImage {
1272 SVGAGuestPtr ptr;
1273
1274 /*
1275 * A note on interpretation of pitch: This value of pitch is the
1276 * number of bytes between vertically adjacent image
1277 * blocks. Normally this is the number of bytes between the first
1278 * pixel of two adjacent scanlines. With compressed textures,
1279 * however, this may represent the number of bytes between
1280 * compression blocks rather than between rows of pixels.
1281 *
1282 * XXX: Compressed textures currently must be tightly packed in guest memory.
1283 *
1284 * If the image is 1-dimensional, pitch is ignored.
1285 *
1286 * If 'pitch' is zero, the SVGA3D device calculates a pitch value
1287 * assuming each row of blocks is tightly packed.
1288 */
1289 uint32 pitch;
1290} SVGA3dGuestImage;
1291
1292
1293/*
1294 * FIFO command format definitions:
1295 */
1296
1297/*
1298 * The data size header following cmdNum for every 3d command
1299 */
1300typedef
1301struct {
1302 uint32 id;
1303 uint32 size;
1304} SVGA3dCmdHeader;
1305
1306/*
1307 * A surface is a hierarchy of host VRAM surfaces: 1D, 2D, or 3D, with
1308 * optional mipmaps and cube faces.
1309 */
1310
1311typedef
1312struct {
1313 uint32 width;
1314 uint32 height;
1315 uint32 depth;
1316} SVGA3dSize;
1317
1318typedef enum {
1319 SVGA3D_SURFACE_CUBEMAP = (1 << 0),
1320 SVGA3D_SURFACE_HINT_STATIC = (1 << 1),
1321 SVGA3D_SURFACE_HINT_DYNAMIC = (1 << 2),
1322 SVGA3D_SURFACE_HINT_INDEXBUFFER = (1 << 3),
1323 SVGA3D_SURFACE_HINT_VERTEXBUFFER = (1 << 4),
1324 SVGA3D_SURFACE_HINT_TEXTURE = (1 << 5),
1325 SVGA3D_SURFACE_HINT_RENDERTARGET = (1 << 6),
1326 SVGA3D_SURFACE_HINT_DEPTHSTENCIL = (1 << 7),
1327 SVGA3D_SURFACE_HINT_WRITEONLY = (1 << 8),
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +02001328 SVGA3D_SURFACE_MASKABLE_ANTIALIAS = (1 << 9),
1329 SVGA3D_SURFACE_AUTOGENMIPMAPS = (1 << 10),
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001330} SVGA3dSurfaceFlags;
1331
1332typedef
1333struct {
1334 uint32 numMipLevels;
1335} SVGA3dSurfaceFace;
1336
1337typedef
1338struct {
1339 uint32 sid;
1340 SVGA3dSurfaceFlags surfaceFlags;
1341 SVGA3dSurfaceFormat format;
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +02001342 /*
1343 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
1344 * structures must have the same value of numMipLevels field.
1345 * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
1346 * numMipLevels set to 0.
1347 */
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001348 SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
1349 /*
1350 * Followed by an SVGA3dSize structure for each mip level in each face.
1351 *
1352 * A note on surface sizes: Sizes are always specified in pixels,
1353 * even if the true surface size is not a multiple of the minimum
1354 * block size of the surface's format. For example, a 3x3x1 DXT1
1355 * compressed texture would actually be stored as a 4x4x1 image in
1356 * memory.
1357 */
1358} SVGA3dCmdDefineSurface; /* SVGA_3D_CMD_SURFACE_DEFINE */
1359
1360typedef
1361struct {
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +02001362 uint32 sid;
1363 SVGA3dSurfaceFlags surfaceFlags;
1364 SVGA3dSurfaceFormat format;
1365 /*
1366 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
1367 * structures must have the same value of numMipLevels field.
1368 * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
1369 * numMipLevels set to 0.
1370 */
1371 SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
1372 uint32 multisampleCount;
1373 SVGA3dTextureFilter autogenFilter;
1374 /*
1375 * Followed by an SVGA3dSize structure for each mip level in each face.
1376 *
1377 * A note on surface sizes: Sizes are always specified in pixels,
1378 * even if the true surface size is not a multiple of the minimum
1379 * block size of the surface's format. For example, a 3x3x1 DXT1
1380 * compressed texture would actually be stored as a 4x4x1 image in
1381 * memory.
1382 */
1383} SVGA3dCmdDefineSurface_v2; /* SVGA_3D_CMD_SURFACE_DEFINE_V2 */
1384
1385typedef
1386struct {
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001387 uint32 sid;
1388} SVGA3dCmdDestroySurface; /* SVGA_3D_CMD_SURFACE_DESTROY */
1389
1390typedef
1391struct {
1392 uint32 cid;
1393} SVGA3dCmdDefineContext; /* SVGA_3D_CMD_CONTEXT_DEFINE */
1394
1395typedef
1396struct {
1397 uint32 cid;
1398} SVGA3dCmdDestroyContext; /* SVGA_3D_CMD_CONTEXT_DESTROY */
1399
1400typedef
1401struct {
1402 uint32 cid;
1403 SVGA3dClearFlag clearFlag;
1404 uint32 color;
1405 float depth;
1406 uint32 stencil;
1407 /* Followed by variable number of SVGA3dRect structures */
1408} SVGA3dCmdClear; /* SVGA_3D_CMD_CLEAR */
1409
1410typedef
1411struct SVGA3dCopyRect {
1412 uint32 x;
1413 uint32 y;
1414 uint32 w;
1415 uint32 h;
1416 uint32 srcx;
1417 uint32 srcy;
1418} SVGA3dCopyRect;
1419
1420typedef
1421struct SVGA3dCopyBox {
1422 uint32 x;
1423 uint32 y;
1424 uint32 z;
1425 uint32 w;
1426 uint32 h;
1427 uint32 d;
1428 uint32 srcx;
1429 uint32 srcy;
1430 uint32 srcz;
1431} SVGA3dCopyBox;
1432
1433typedef
1434struct {
1435 uint32 x;
1436 uint32 y;
1437 uint32 w;
1438 uint32 h;
1439} SVGA3dRect;
1440
1441typedef
1442struct {
1443 uint32 x;
1444 uint32 y;
1445 uint32 z;
1446 uint32 w;
1447 uint32 h;
1448 uint32 d;
1449} SVGA3dBox;
1450
1451typedef
1452struct {
1453 uint32 x;
1454 uint32 y;
1455 uint32 z;
1456} SVGA3dPoint;
1457
1458typedef
1459struct {
1460 SVGA3dLightType type;
1461 SVGA3dBool inWorldSpace;
1462 float diffuse[4];
1463 float specular[4];
1464 float ambient[4];
1465 float position[4];
1466 float direction[4];
1467 float range;
1468 float falloff;
1469 float attenuation0;
1470 float attenuation1;
1471 float attenuation2;
1472 float theta;
1473 float phi;
1474} SVGA3dLightData;
1475
1476typedef
1477struct {
1478 uint32 sid;
1479 /* Followed by variable number of SVGA3dCopyRect structures */
1480} SVGA3dCmdPresent; /* SVGA_3D_CMD_PRESENT */
1481
1482typedef
1483struct {
1484 SVGA3dRenderStateName state;
1485 union {
1486 uint32 uintValue;
1487 float floatValue;
1488 };
1489} SVGA3dRenderState;
1490
1491typedef
1492struct {
1493 uint32 cid;
1494 /* Followed by variable number of SVGA3dRenderState structures */
1495} SVGA3dCmdSetRenderState; /* SVGA_3D_CMD_SETRENDERSTATE */
1496
1497typedef
1498struct {
1499 uint32 cid;
1500 SVGA3dRenderTargetType type;
1501 SVGA3dSurfaceImageId target;
1502} SVGA3dCmdSetRenderTarget; /* SVGA_3D_CMD_SETRENDERTARGET */
1503
1504typedef
1505struct {
1506 SVGA3dSurfaceImageId src;
1507 SVGA3dSurfaceImageId dest;
1508 /* Followed by variable number of SVGA3dCopyBox structures */
1509} SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
1510
1511typedef
1512struct {
1513 SVGA3dSurfaceImageId src;
1514 SVGA3dSurfaceImageId dest;
1515 SVGA3dBox boxSrc;
1516 SVGA3dBox boxDest;
1517 SVGA3dStretchBltMode mode;
1518} SVGA3dCmdSurfaceStretchBlt; /* SVGA_3D_CMD_SURFACE_STRETCHBLT */
1519
1520typedef
1521struct {
1522 /*
1523 * If the discard flag is present in a surface DMA operation, the host may
1524 * discard the contents of the current mipmap level and face of the target
1525 * surface before applying the surface DMA contents.
1526 */
1527 uint32 discard : 1;
1528
1529 /*
1530 * If the unsynchronized flag is present, the host may perform this upload
1531 * without syncing to pending reads on this surface.
1532 */
1533 uint32 unsynchronized : 1;
1534
1535 /*
1536 * Guests *MUST* set the reserved bits to 0 before submitting the command
1537 * suffix as future flags may occupy these bits.
1538 */
1539 uint32 reserved : 30;
1540} SVGA3dSurfaceDMAFlags;
1541
1542typedef
1543struct {
1544 SVGA3dGuestImage guest;
1545 SVGA3dSurfaceImageId host;
1546 SVGA3dTransferType transfer;
1547 /*
1548 * Followed by variable number of SVGA3dCopyBox structures. For consistency
1549 * in all clipping logic and coordinate translation, we define the
1550 * "source" in each copyBox as the guest image and the
1551 * "destination" as the host image, regardless of transfer
1552 * direction.
1553 *
1554 * For efficiency, the SVGA3D device is free to copy more data than
1555 * specified. For example, it may round copy boxes outwards such
1556 * that they lie on particular alignment boundaries.
1557 */
1558} SVGA3dCmdSurfaceDMA; /* SVGA_3D_CMD_SURFACE_DMA */
1559
1560/*
1561 * SVGA3dCmdSurfaceDMASuffix --
1562 *
1563 * This is a command suffix that will appear after a SurfaceDMA command in
1564 * the FIFO. It contains some extra information that hosts may use to
1565 * optimize performance or protect the guest. This suffix exists to preserve
1566 * backwards compatibility while also allowing for new functionality to be
1567 * implemented.
1568 */
1569
1570typedef
1571struct {
1572 uint32 suffixSize;
1573
1574 /*
1575 * The maximum offset is used to determine the maximum offset from the
1576 * guestPtr base address that will be accessed or written to during this
1577 * surfaceDMA. If the suffix is supported, the host will respect this
1578 * boundary while performing surface DMAs.
1579 *
1580 * Defaults to MAX_UINT32
1581 */
1582 uint32 maximumOffset;
1583
1584 /*
1585 * A set of flags that describes optimizations that the host may perform
1586 * while performing this surface DMA operation. The guest should never rely
1587 * on behaviour that is different when these flags are set for correctness.
1588 *
1589 * Defaults to 0
1590 */
1591 SVGA3dSurfaceDMAFlags flags;
1592} SVGA3dCmdSurfaceDMASuffix;
1593
1594/*
1595 * SVGA_3D_CMD_DRAW_PRIMITIVES --
1596 *
1597 * This command is the SVGA3D device's generic drawing entry point.
1598 * It can draw multiple ranges of primitives, optionally using an
1599 * index buffer, using an arbitrary collection of vertex buffers.
1600 *
1601 * Each SVGA3dVertexDecl defines a distinct vertex array to bind
1602 * during this draw call. The declarations specify which surface
1603 * the vertex data lives in, what that vertex data is used for,
1604 * and how to interpret it.
1605 *
1606 * Each SVGA3dPrimitiveRange defines a collection of primitives
1607 * to render using the same vertex arrays. An index buffer is
1608 * optional.
1609 */
1610
1611typedef
1612struct {
1613 /*
1614 * A range hint is an optional specification for the range of indices
1615 * in an SVGA3dArray that will be used. If 'last' is zero, it is assumed
1616 * that the entire array will be used.
1617 *
1618 * These are only hints. The SVGA3D device may use them for
1619 * performance optimization if possible, but it's also allowed to
1620 * ignore these values.
1621 */
1622 uint32 first;
1623 uint32 last;
1624} SVGA3dArrayRangeHint;
1625
1626typedef
1627struct {
1628 /*
1629 * Define the origin and shape of a vertex or index array. Both
1630 * 'offset' and 'stride' are in bytes. The provided surface will be
1631 * reinterpreted as a flat array of bytes in the same format used
1632 * by surface DMA operations. To avoid unnecessary conversions, the
1633 * surface should be created with the SVGA3D_BUFFER format.
1634 *
1635 * Index 0 in the array starts 'offset' bytes into the surface.
1636 * Index 1 begins at byte 'offset + stride', etc. Array indices may
1637 * not be negative.
1638 */
1639 uint32 surfaceId;
1640 uint32 offset;
1641 uint32 stride;
1642} SVGA3dArray;
1643
1644typedef
1645struct {
1646 /*
1647 * Describe a vertex array's data type, and define how it is to be
1648 * used by the fixed function pipeline or the vertex shader. It
1649 * isn't useful to have two VertexDecls with the same
1650 * VertexArrayIdentity in one draw call.
1651 */
1652 SVGA3dDeclType type;
1653 SVGA3dDeclMethod method;
1654 SVGA3dDeclUsage usage;
1655 uint32 usageIndex;
1656} SVGA3dVertexArrayIdentity;
1657
1658typedef
1659struct {
1660 SVGA3dVertexArrayIdentity identity;
1661 SVGA3dArray array;
1662 SVGA3dArrayRangeHint rangeHint;
1663} SVGA3dVertexDecl;
1664
1665typedef
1666struct {
1667 /*
1668 * Define a group of primitives to render, from sequential indices.
1669 *
1670 * The value of 'primitiveType' and 'primitiveCount' imply the
1671 * total number of vertices that will be rendered.
1672 */
1673 SVGA3dPrimitiveType primType;
1674 uint32 primitiveCount;
1675
1676 /*
1677 * Optional index buffer. If indexArray.surfaceId is
1678 * SVGA3D_INVALID_ID, we render without an index buffer. Rendering
1679 * without an index buffer is identical to rendering with an index
1680 * buffer containing the sequence [0, 1, 2, 3, ...].
1681 *
1682 * If an index buffer is in use, indexWidth specifies the width in
1683 * bytes of each index value. It must be less than or equal to
1684 * indexArray.stride.
1685 *
1686 * (Currently, the SVGA3D device requires index buffers to be tightly
1687 * packed. In other words, indexWidth == indexArray.stride)
1688 */
1689 SVGA3dArray indexArray;
1690 uint32 indexWidth;
1691
1692 /*
1693 * Optional index bias. This number is added to all indices from
1694 * indexArray before they are used as vertex array indices. This
1695 * can be used in multiple ways:
1696 *
1697 * - When not using an indexArray, this bias can be used to
1698 * specify where in the vertex arrays to begin rendering.
1699 *
1700 * - A positive number here is equivalent to increasing the
1701 * offset in each vertex array.
1702 *
1703 * - A negative number can be used to render using a small
1704 * vertex array and an index buffer that contains large
1705 * values. This may be used by some applications that
1706 * crop a vertex buffer without modifying their index
1707 * buffer.
1708 *
1709 * Note that rendering with a negative bias value may be slower and
1710 * use more memory than rendering with a positive or zero bias.
1711 */
1712 int32 indexBias;
1713} SVGA3dPrimitiveRange;
1714
1715typedef
1716struct {
1717 uint32 cid;
1718 uint32 numVertexDecls;
1719 uint32 numRanges;
1720
1721 /*
1722 * There are two variable size arrays after the
1723 * SVGA3dCmdDrawPrimitives structure. In order,
1724 * they are:
1725 *
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +02001726 * 1. SVGA3dVertexDecl, quantity 'numVertexDecls', but no more than
1727 * SVGA3D_MAX_VERTEX_ARRAYS;
1728 * 2. SVGA3dPrimitiveRange, quantity 'numRanges', but no more than
1729 * SVGA3D_MAX_DRAW_PRIMITIVE_RANGES;
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001730 * 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +02001731 * the frequency divisor for the corresponding vertex decl).
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001732 */
1733} SVGA3dCmdDrawPrimitives; /* SVGA_3D_CMD_DRAWPRIMITIVES */
1734
1735typedef
1736struct {
1737 uint32 stage;
1738 SVGA3dTextureStateName name;
1739 union {
1740 uint32 value;
1741 float floatValue;
1742 };
1743} SVGA3dTextureState;
1744
1745typedef
1746struct {
1747 uint32 cid;
1748 /* Followed by variable number of SVGA3dTextureState structures */
1749} SVGA3dCmdSetTextureState; /* SVGA_3D_CMD_SETTEXTURESTATE */
1750
1751typedef
1752struct {
1753 uint32 cid;
1754 SVGA3dTransformType type;
1755 float matrix[16];
1756} SVGA3dCmdSetTransform; /* SVGA_3D_CMD_SETTRANSFORM */
1757
1758typedef
1759struct {
1760 float min;
1761 float max;
1762} SVGA3dZRange;
1763
1764typedef
1765struct {
1766 uint32 cid;
1767 SVGA3dZRange zRange;
1768} SVGA3dCmdSetZRange; /* SVGA_3D_CMD_SETZRANGE */
1769
1770typedef
1771struct {
1772 float diffuse[4];
1773 float ambient[4];
1774 float specular[4];
1775 float emissive[4];
1776 float shininess;
1777} SVGA3dMaterial;
1778
1779typedef
1780struct {
1781 uint32 cid;
1782 SVGA3dFace face;
1783 SVGA3dMaterial material;
1784} SVGA3dCmdSetMaterial; /* SVGA_3D_CMD_SETMATERIAL */
1785
1786typedef
1787struct {
1788 uint32 cid;
1789 uint32 index;
1790 SVGA3dLightData data;
1791} SVGA3dCmdSetLightData; /* SVGA_3D_CMD_SETLIGHTDATA */
1792
1793typedef
1794struct {
1795 uint32 cid;
1796 uint32 index;
1797 uint32 enabled;
1798} SVGA3dCmdSetLightEnabled; /* SVGA_3D_CMD_SETLIGHTENABLED */
1799
1800typedef
1801struct {
1802 uint32 cid;
1803 SVGA3dRect rect;
1804} SVGA3dCmdSetViewport; /* SVGA_3D_CMD_SETVIEWPORT */
1805
1806typedef
1807struct {
1808 uint32 cid;
1809 SVGA3dRect rect;
1810} SVGA3dCmdSetScissorRect; /* SVGA_3D_CMD_SETSCISSORRECT */
1811
1812typedef
1813struct {
1814 uint32 cid;
1815 uint32 index;
1816 float plane[4];
1817} SVGA3dCmdSetClipPlane; /* SVGA_3D_CMD_SETCLIPPLANE */
1818
1819typedef
1820struct {
1821 uint32 cid;
1822 uint32 shid;
1823 SVGA3dShaderType type;
1824 /* Followed by variable number of DWORDs for shader bycode */
1825} SVGA3dCmdDefineShader; /* SVGA_3D_CMD_SHADER_DEFINE */
1826
1827typedef
1828struct {
1829 uint32 cid;
1830 uint32 shid;
1831 SVGA3dShaderType type;
1832} SVGA3dCmdDestroyShader; /* SVGA_3D_CMD_SHADER_DESTROY */
1833
1834typedef
1835struct {
1836 uint32 cid;
1837 uint32 reg; /* register number */
1838 SVGA3dShaderType type;
1839 SVGA3dShaderConstType ctype;
1840 uint32 values[4];
1841} SVGA3dCmdSetShaderConst; /* SVGA_3D_CMD_SET_SHADER_CONST */
1842
1843typedef
1844struct {
1845 uint32 cid;
1846 SVGA3dShaderType type;
1847 uint32 shid;
1848} SVGA3dCmdSetShader; /* SVGA_3D_CMD_SET_SHADER */
1849
1850typedef
1851struct {
1852 uint32 cid;
1853 SVGA3dQueryType type;
1854} SVGA3dCmdBeginQuery; /* SVGA_3D_CMD_BEGIN_QUERY */
1855
1856typedef
1857struct {
1858 uint32 cid;
1859 SVGA3dQueryType type;
1860 SVGAGuestPtr guestResult; /* Points to an SVGA3dQueryResult structure */
1861} SVGA3dCmdEndQuery; /* SVGA_3D_CMD_END_QUERY */
1862
1863typedef
1864struct {
1865 uint32 cid; /* Same parameters passed to END_QUERY */
1866 SVGA3dQueryType type;
1867 SVGAGuestPtr guestResult;
1868} SVGA3dCmdWaitForQuery; /* SVGA_3D_CMD_WAIT_FOR_QUERY */
1869
1870typedef
1871struct {
1872 uint32 totalSize; /* Set by guest before query is ended. */
1873 SVGA3dQueryState state; /* Set by host or guest. See SVGA3dQueryState. */
1874 union { /* Set by host on exit from PENDING state */
1875 uint32 result32;
1876 };
1877} SVGA3dQueryResult;
1878
1879/*
1880 * SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN --
1881 *
1882 * This is a blit from an SVGA3D surface to a Screen Object. Just
1883 * like GMR-to-screen blits, this blit may be directed at a
1884 * specific screen or to the virtual coordinate space.
1885 *
1886 * The blit copies from a rectangular region of an SVGA3D surface
1887 * image to a rectangular region of a screen or screens.
1888 *
1889 * This command takes an optional variable-length list of clipping
1890 * rectangles after the body of the command. If no rectangles are
1891 * specified, there is no clipping region. The entire destRect is
1892 * drawn to. If one or more rectangles are included, they describe
1893 * a clipping region. The clip rectangle coordinates are measured
1894 * relative to the top-left corner of destRect.
1895 *
1896 * This clipping region serves multiple purposes:
1897 *
1898 * - It can be used to perform an irregularly shaped blit more
1899 * efficiently than by issuing many separate blit commands.
1900 *
1901 * - It is equivalent to allowing blits with non-integer
1902 * source coordinates. You could blit just one half-pixel
1903 * of a source, for example, by specifying a larger
1904 * destination rectangle than you need, then removing
1905 * part of it using a clip rectangle.
1906 *
1907 * Availability:
1908 * SVGA_FIFO_CAP_SCREEN_OBJECT
1909 *
1910 * Limitations:
1911 *
1912 * - Currently, no backend supports blits from a mipmap or face
1913 * other than the first one.
1914 */
1915
1916typedef
1917struct {
1918 SVGA3dSurfaceImageId srcImage;
1919 SVGASignedRect srcRect;
1920 uint32 destScreenId; /* Screen ID or SVGA_ID_INVALID for virt. coords */
1921 SVGASignedRect destRect; /* Supports scaling if src/rest different size */
1922 /* Clipping: zero or more SVGASignedRects follow */
1923} SVGA3dCmdBlitSurfaceToScreen; /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */
1924
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +02001925typedef
1926struct {
1927 uint32 sid;
1928 SVGA3dTextureFilter filter;
1929} SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */
1930
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00001931
1932/*
Thomas Hellstromd9019492012-11-21 10:17:00 +01001933 * Guest-backed surface definitions.
1934 */
1935
1936typedef uint32 SVGAMobId;
1937
1938typedef enum SVGAMobFormat {
1939 SVGA3D_MOBFMT_INVALID = SVGA3D_INVALID_ID,
1940 SVGA3D_MOBFMT_PTDEPTH_0 = 0,
1941 SVGA3D_MOBFMT_PTDEPTH_1 = 1,
1942 SVGA3D_MOBFMT_PTDEPTH_2 = 2,
1943 SVGA3D_MOBFMT_RANGE = 3,
Thomas Hellstromf2a0dcb2014-01-15 10:04:07 +01001944 SVGA3D_MOBFMT_PTDEPTH64_0 = 4,
1945 SVGA3D_MOBFMT_PTDEPTH64_1 = 5,
1946 SVGA3D_MOBFMT_PTDEPTH64_2 = 6,
Thomas Hellstromd9019492012-11-21 10:17:00 +01001947 SVGA3D_MOBFMT_MAX,
1948} SVGAMobFormat;
1949
1950/*
1951 * Sizes of opaque types.
1952 */
1953
1954#define SVGA3D_OTABLE_MOB_ENTRY_SIZE 16
1955#define SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE 8
1956#define SVGA3D_OTABLE_SURFACE_ENTRY_SIZE 64
1957#define SVGA3D_OTABLE_SHADER_ENTRY_SIZE 16
Thomas Hellstrom7cba9062014-01-09 11:03:18 +01001958#define SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE 64
Thomas Hellstromd9019492012-11-21 10:17:00 +01001959#define SVGA3D_CONTEXT_DATA_SIZE 16384
1960
1961/*
1962 * SVGA3dCmdSetOTableBase --
1963 *
1964 * This command allows the guest to specify the base PPN of the
1965 * specified object table.
1966 */
1967
1968typedef enum {
Thomas Hellstrom7cba9062014-01-09 11:03:18 +01001969 SVGA_OTABLE_MOB = 0,
1970 SVGA_OTABLE_MIN = 0,
1971 SVGA_OTABLE_SURFACE = 1,
1972 SVGA_OTABLE_CONTEXT = 2,
1973 SVGA_OTABLE_SHADER = 3,
1974 SVGA_OTABLE_SCREEN_TARGET = 4,
1975 SVGA_OTABLE_DX9_MAX = 5,
1976 SVGA_OTABLE_MAX = 8
Thomas Hellstromd9019492012-11-21 10:17:00 +01001977} SVGAOTableType;
1978
1979typedef
1980struct {
1981 SVGAOTableType type;
1982 PPN baseAddress;
1983 uint32 sizeInBytes;
1984 uint32 validSizeInBytes;
1985 SVGAMobFormat ptDepth;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01001986} __packed
Thomas Hellstrom96b43622014-01-16 21:20:21 +01001987SVGA3dCmdSetOTableBase; /* SVGA_3D_CMD_SET_OTABLE_BASE */
Thomas Hellstromd9019492012-11-21 10:17:00 +01001988
1989typedef
1990struct {
1991 SVGAOTableType type;
Thomas Hellstromf2a0dcb2014-01-15 10:04:07 +01001992 PPN64 baseAddress;
1993 uint32 sizeInBytes;
1994 uint32 validSizeInBytes;
1995 SVGAMobFormat ptDepth;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01001996} __packed
Thomas Hellstrom96b43622014-01-16 21:20:21 +01001997SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */
Thomas Hellstromf2a0dcb2014-01-15 10:04:07 +01001998
1999typedef
2000struct {
2001 SVGAOTableType type;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002002} __packed
Thomas Hellstrom96b43622014-01-16 21:20:21 +01002003SVGA3dCmdReadbackOTable; /* SVGA_3D_CMD_READBACK_OTABLE */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002004
2005/*
2006 * Define a memory object (Mob) in the OTable.
2007 */
2008
2009typedef
2010struct SVGA3dCmdDefineGBMob {
2011 SVGAMobId mobid;
2012 SVGAMobFormat ptDepth;
2013 PPN base;
2014 uint32 sizeInBytes;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002015} __packed
Thomas Hellstrom96b43622014-01-16 21:20:21 +01002016SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002017
2018
2019/*
2020 * Destroys an object in the OTable.
2021 */
2022
2023typedef
2024struct SVGA3dCmdDestroyGBMob {
2025 SVGAMobId mobid;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002026} __packed
Thomas Hellstrom96b43622014-01-16 21:20:21 +01002027SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002028
2029/*
2030 * Redefine an object in the OTable.
2031 */
2032
2033typedef
2034struct SVGA3dCmdRedefineGBMob {
2035 SVGAMobId mobid;
2036 SVGAMobFormat ptDepth;
2037 PPN base;
2038 uint32 sizeInBytes;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002039} __packed
Thomas Hellstrom96b43622014-01-16 21:20:21 +01002040SVGA3dCmdRedefineGBMob; /* SVGA_3D_CMD_REDEFINE_GB_MOB */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002041
2042/*
Thomas Hellstromf2a0dcb2014-01-15 10:04:07 +01002043 * Define a memory object (Mob) in the OTable with a PPN64 base.
2044 */
2045
2046typedef
2047struct SVGA3dCmdDefineGBMob64 {
2048 SVGAMobId mobid;
2049 SVGAMobFormat ptDepth;
2050 PPN64 base;
2051 uint32 sizeInBytes;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002052} __packed
Thomas Hellstromf2a0dcb2014-01-15 10:04:07 +01002053SVGA3dCmdDefineGBMob64; /* SVGA_3D_CMD_DEFINE_GB_MOB64 */
2054
2055/*
2056 * Redefine an object in the OTable with PPN64 base.
2057 */
2058
2059typedef
2060struct SVGA3dCmdRedefineGBMob64 {
2061 SVGAMobId mobid;
2062 SVGAMobFormat ptDepth;
2063 PPN64 base;
2064 uint32 sizeInBytes;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002065} __packed
Thomas Hellstromf2a0dcb2014-01-15 10:04:07 +01002066SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */
2067
2068/*
Thomas Hellstromd9019492012-11-21 10:17:00 +01002069 * Notification that the page tables have been modified.
2070 */
2071
2072typedef
2073struct SVGA3dCmdUpdateGBMobMapping {
2074 SVGAMobId mobid;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002075} __packed
Thomas Hellstrom96b43622014-01-16 21:20:21 +01002076SVGA3dCmdUpdateGBMobMapping; /* SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002077
2078/*
2079 * Define a guest-backed surface.
2080 */
2081
2082typedef
2083struct SVGA3dCmdDefineGBSurface {
2084 uint32 sid;
2085 SVGA3dSurfaceFlags surfaceFlags;
2086 SVGA3dSurfaceFormat format;
2087 uint32 numMipLevels;
2088 uint32 multisampleCount;
2089 SVGA3dTextureFilter autogenFilter;
2090 SVGA3dSize size;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002091} __packed
2092SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002093
2094/*
2095 * Destroy a guest-backed surface.
2096 */
2097
2098typedef
2099struct SVGA3dCmdDestroyGBSurface {
2100 uint32 sid;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002101} __packed
2102SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002103
2104/*
2105 * Bind a guest-backed surface to an object.
2106 */
2107
2108typedef
2109struct SVGA3dCmdBindGBSurface {
2110 uint32 sid;
2111 SVGAMobId mobid;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002112} __packed
2113SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002114
2115/*
2116 * Conditionally bind a mob to a guest backed surface if testMobid
2117 * matches the currently bound mob. Optionally issue a readback on
2118 * the surface while it is still bound to the old mobid if the mobid
2119 * is changed by this command.
2120 */
2121
2122#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_READBACK (1 << 0)
2123
2124typedef
2125struct{
2126 uint32 sid;
2127 SVGAMobId testMobid;
2128 SVGAMobId mobid;
2129 uint32 flags;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002130} __packed
Thomas Hellstromd9019492012-11-21 10:17:00 +01002131SVGA3dCmdCondBindGBSurface; /* SVGA_3D_CMD_COND_BIND_GB_SURFACE */
2132
2133/*
2134 * Update an image in a guest-backed surface.
2135 * (Inform the device that the guest-contents have been updated.)
2136 */
2137
2138typedef
2139struct SVGA3dCmdUpdateGBImage {
2140 SVGA3dSurfaceImageId image;
2141 SVGA3dBox box;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002142} __packed
2143SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002144
2145/*
2146 * Update an entire guest-backed surface.
2147 * (Inform the device that the guest-contents have been updated.)
2148 */
2149
2150typedef
2151struct SVGA3dCmdUpdateGBSurface {
2152 uint32 sid;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002153} __packed
2154SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002155
2156/*
2157 * Readback an image in a guest-backed surface.
2158 * (Request the device to flush the dirty contents into the guest.)
2159 */
2160
2161typedef
2162struct SVGA3dCmdReadbackGBImage {
2163 SVGA3dSurfaceImageId image;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002164} __packed
2165SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE*/
Thomas Hellstromd9019492012-11-21 10:17:00 +01002166
2167/*
2168 * Readback an entire guest-backed surface.
2169 * (Request the device to flush the dirty contents into the guest.)
2170 */
2171
2172typedef
2173struct SVGA3dCmdReadbackGBSurface {
2174 uint32 sid;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002175} __packed
2176SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002177
2178/*
2179 * Readback a sub rect of an image in a guest-backed surface. After
2180 * issuing this command the driver is required to issue an update call
2181 * of the same region before issuing any other commands that reference
2182 * this surface or rendering is not guaranteed.
2183 */
2184
2185typedef
2186struct SVGA3dCmdReadbackGBImagePartial {
2187 SVGA3dSurfaceImageId image;
2188 SVGA3dBox box;
2189 uint32 invertBox;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002190} __packed
Thomas Hellstromd9019492012-11-21 10:17:00 +01002191SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */
2192
2193/*
2194 * Invalidate an image in a guest-backed surface.
2195 * (Notify the device that the contents can be lost.)
2196 */
2197
2198typedef
2199struct SVGA3dCmdInvalidateGBImage {
2200 SVGA3dSurfaceImageId image;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002201} __packed
2202SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002203
2204/*
2205 * Invalidate an entire guest-backed surface.
2206 * (Notify the device that the contents if all images can be lost.)
2207 */
2208
2209typedef
2210struct SVGA3dCmdInvalidateGBSurface {
2211 uint32 sid;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002212} __packed
2213SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002214
2215/*
2216 * Invalidate a sub rect of an image in a guest-backed surface. After
2217 * issuing this command the driver is required to issue an update call
2218 * of the same region before issuing any other commands that reference
2219 * this surface or rendering is not guaranteed.
2220 */
2221
2222typedef
2223struct SVGA3dCmdInvalidateGBImagePartial {
2224 SVGA3dSurfaceImageId image;
2225 SVGA3dBox box;
2226 uint32 invertBox;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002227} __packed
Thomas Hellstromd9019492012-11-21 10:17:00 +01002228SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */
2229
2230/*
2231 * Define a guest-backed context.
2232 */
2233
2234typedef
2235struct SVGA3dCmdDefineGBContext {
2236 uint32 cid;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002237} __packed
2238SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002239
2240/*
2241 * Destroy a guest-backed context.
2242 */
2243
2244typedef
2245struct SVGA3dCmdDestroyGBContext {
2246 uint32 cid;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002247} __packed
2248SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002249
2250/*
2251 * Bind a guest-backed context.
2252 *
2253 * validContents should be set to 0 for new contexts,
2254 * and 1 if this is an old context which is getting paged
2255 * back on to the device.
2256 *
2257 * For new contexts, it is recommended that the driver
2258 * issue commands to initialize all interesting state
2259 * prior to rendering.
2260 */
2261
2262typedef
2263struct SVGA3dCmdBindGBContext {
2264 uint32 cid;
2265 SVGAMobId mobid;
2266 uint32 validContents;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002267} __packed
2268SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002269
2270/*
2271 * Readback a guest-backed context.
2272 * (Request that the device flush the contents back into guest memory.)
2273 */
2274
2275typedef
2276struct SVGA3dCmdReadbackGBContext {
2277 uint32 cid;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002278} __packed
2279SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002280
2281/*
2282 * Invalidate a guest-backed context.
2283 */
2284typedef
2285struct SVGA3dCmdInvalidateGBContext {
2286 uint32 cid;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002287} __packed
2288SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002289
2290/*
2291 * Define a guest-backed shader.
2292 */
2293
2294typedef
2295struct SVGA3dCmdDefineGBShader {
2296 uint32 shid;
2297 SVGA3dShaderType type;
2298 uint32 sizeInBytes;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002299} __packed
2300SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002301
2302/*
2303 * Bind a guest-backed shader.
2304 */
2305
2306typedef struct SVGA3dCmdBindGBShader {
2307 uint32 shid;
2308 SVGAMobId mobid;
2309 uint32 offsetInBytes;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002310} __packed
2311SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002312
2313/*
2314 * Destroy a guest-backed shader.
2315 */
2316
2317typedef struct SVGA3dCmdDestroyGBShader {
2318 uint32 shid;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002319} __packed
2320SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002321
Thomas Hellstromd9019492012-11-21 10:17:00 +01002322typedef
2323struct {
2324 uint32 cid;
2325 uint32 regStart;
2326 SVGA3dShaderType shaderType;
2327 SVGA3dShaderConstType constType;
2328
2329 /*
2330 * Followed by a variable number of shader constants.
2331 *
2332 * Note that FLOAT and INT constants are 4-dwords in length, while
2333 * BOOL constants are 1-dword in length.
2334 */
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002335} __packed
2336SVGA3dCmdSetGBShaderConstInline;
Thomas Hellstromd9019492012-11-21 10:17:00 +01002337/* SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE */
2338
2339typedef
2340struct {
2341 uint32 cid;
2342 SVGA3dQueryType type;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002343} __packed
2344SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002345
2346typedef
2347struct {
2348 uint32 cid;
2349 SVGA3dQueryType type;
2350 SVGAMobId mobid;
2351 uint32 offset;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002352} __packed
2353SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002354
2355
2356/*
2357 * SVGA_3D_CMD_WAIT_FOR_GB_QUERY --
2358 *
2359 * The semantics of this command are identical to the
2360 * SVGA_3D_CMD_WAIT_FOR_QUERY except that the results are written
2361 * to a Mob instead of a GMR.
2362 */
2363
2364typedef
2365struct {
2366 uint32 cid;
2367 SVGA3dQueryType type;
2368 SVGAMobId mobid;
2369 uint32 offset;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002370} __packed
2371SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002372
2373typedef
2374struct {
2375 SVGAMobId mobid;
2376 uint32 fbOffset;
2377 uint32 initalized;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002378} __packed
Thomas Hellstromd9019492012-11-21 10:17:00 +01002379SVGA3dCmdEnableGart; /* SVGA_3D_CMD_ENABLE_GART */
2380
2381typedef
2382struct {
2383 SVGAMobId mobid;
2384 uint32 gartOffset;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002385} __packed
Thomas Hellstromd9019492012-11-21 10:17:00 +01002386SVGA3dCmdMapMobIntoGart; /* SVGA_3D_CMD_MAP_MOB_INTO_GART */
2387
2388
2389typedef
2390struct {
2391 uint32 gartOffset;
2392 uint32 numPages;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002393} __packed
Thomas Hellstromd9019492012-11-21 10:17:00 +01002394SVGA3dCmdUnmapGartRange; /* SVGA_3D_CMD_UNMAP_GART_RANGE */
2395
2396
2397/*
2398 * Screen Targets
2399 */
2400#define SVGA_STFLAG_PRIMARY (1 << 0)
2401
2402typedef
2403struct {
2404 uint32 stid;
2405 uint32 width;
2406 uint32 height;
2407 int32 xRoot;
2408 int32 yRoot;
2409 uint32 flags;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002410} __packed
Thomas Hellstromd9019492012-11-21 10:17:00 +01002411SVGA3dCmdDefineGBScreenTarget; /* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET */
2412
2413typedef
2414struct {
2415 uint32 stid;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002416} __packed
Thomas Hellstromd9019492012-11-21 10:17:00 +01002417SVGA3dCmdDestroyGBScreenTarget; /* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET */
2418
2419typedef
2420struct {
2421 uint32 stid;
2422 SVGA3dSurfaceImageId image;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002423} __packed
Thomas Hellstromd9019492012-11-21 10:17:00 +01002424SVGA3dCmdBindGBScreenTarget; /* SVGA_3D_CMD_BIND_GB_SCREENTARGET */
2425
2426typedef
2427struct {
2428 uint32 stid;
2429 SVGA3dBox box;
Thomas Hellstrom36e952c2014-02-12 13:19:36 +01002430} __packed
Thomas Hellstromd9019492012-11-21 10:17:00 +01002431SVGA3dCmdUpdateGBScreenTarget; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET */
2432
2433/*
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00002434 * Capability query index.
2435 *
2436 * Notes:
2437 *
2438 * 1. SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
2439 * fixed-function texture units available. Each of these units
2440 * work in both FFP and Shader modes, and they support texture
2441 * transforms and texture coordinates. The host may have additional
2442 * texture image units that are only usable with shaders.
2443 *
2444 * 2. The BUFFER_FORMAT capabilities are deprecated, and they always
2445 * return TRUE. Even on physical hardware that does not support
2446 * these formats natively, the SVGA3D device will provide an emulation
2447 * which should be invisible to the guest OS.
2448 *
2449 * In general, the SVGA3D device should support any operation on
2450 * any surface format, it just may perform some of these
2451 * operations in software depending on the capabilities of the
2452 * available physical hardware.
2453 *
2454 * XXX: In the future, we will add capabilities that describe in
2455 * detail what formats are supported in hardware for what kinds
2456 * of operations.
2457 */
2458
2459typedef enum {
2460 SVGA3D_DEVCAP_3D = 0,
2461 SVGA3D_DEVCAP_MAX_LIGHTS = 1,
2462 SVGA3D_DEVCAP_MAX_TEXTURES = 2, /* See note (1) */
2463 SVGA3D_DEVCAP_MAX_CLIP_PLANES = 3,
2464 SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = 4,
2465 SVGA3D_DEVCAP_VERTEX_SHADER = 5,
2466 SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = 6,
2467 SVGA3D_DEVCAP_FRAGMENT_SHADER = 7,
2468 SVGA3D_DEVCAP_MAX_RENDER_TARGETS = 8,
2469 SVGA3D_DEVCAP_S23E8_TEXTURES = 9,
2470 SVGA3D_DEVCAP_S10E5_TEXTURES = 10,
2471 SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = 11,
2472 SVGA3D_DEVCAP_D16_BUFFER_FORMAT = 12, /* See note (2) */
2473 SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = 13, /* See note (2) */
2474 SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = 14, /* See note (2) */
2475 SVGA3D_DEVCAP_QUERY_TYPES = 15,
2476 SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = 16,
2477 SVGA3D_DEVCAP_MAX_POINT_SIZE = 17,
2478 SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = 18,
2479 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = 19,
2480 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = 20,
2481 SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = 21,
2482 SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = 22,
2483 SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = 23,
2484 SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = 24,
2485 SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = 25,
2486 SVGA3D_DEVCAP_MAX_VERTEX_INDEX = 26,
2487 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = 27,
2488 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = 28,
2489 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = 29,
2490 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = 30,
2491 SVGA3D_DEVCAP_TEXTURE_OPS = 31,
2492 SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = 32,
2493 SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = 33,
2494 SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = 34,
2495 SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = 35,
2496 SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = 36,
2497 SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = 37,
2498 SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = 38,
2499 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = 39,
2500 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = 40,
2501 SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = 41,
2502 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = 42,
2503 SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = 43,
2504 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = 44,
2505 SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = 45,
2506 SVGA3D_DEVCAP_SURFACEFMT_DXT1 = 46,
2507 SVGA3D_DEVCAP_SURFACEFMT_DXT2 = 47,
2508 SVGA3D_DEVCAP_SURFACEFMT_DXT3 = 48,
2509 SVGA3D_DEVCAP_SURFACEFMT_DXT4 = 49,
2510 SVGA3D_DEVCAP_SURFACEFMT_DXT5 = 50,
2511 SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = 51,
2512 SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = 52,
2513 SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = 53,
2514 SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = 54,
2515 SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = 55,
2516 SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = 56,
2517 SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = 57,
2518 SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = 58,
2519 SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = 59,
2520 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = 60,
2521 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = 61,
2522 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = 63,
2523
2524 /*
2525 * Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
2526 * render targets. This does no include the depth or stencil targets.
2527 */
2528 SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = 64,
2529
2530 SVGA3D_DEVCAP_SURFACEFMT_V16U16 = 65,
2531 SVGA3D_DEVCAP_SURFACEFMT_G16R16 = 66,
2532 SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = 67,
2533 SVGA3D_DEVCAP_SURFACEFMT_UYVY = 68,
2534 SVGA3D_DEVCAP_SURFACEFMT_YUY2 = 69,
Jakob Bornecrantz8d3713e2011-10-04 20:13:12 +02002535 SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = 70,
2536 SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = 71,
2537 SVGA3D_DEVCAP_ALPHATOCOVERAGE = 72,
2538 SVGA3D_DEVCAP_SUPERSAMPLE = 73,
2539 SVGA3D_DEVCAP_AUTOGENMIPMAPS = 74,
2540 SVGA3D_DEVCAP_SURFACEFMT_NV12 = 75,
2541 SVGA3D_DEVCAP_SURFACEFMT_AYUV = 76,
2542
2543 /*
2544 * This is the maximum number of SVGA context IDs that the guest
2545 * can define using SVGA_3D_CMD_CONTEXT_DEFINE.
2546 */
2547 SVGA3D_DEVCAP_MAX_CONTEXT_IDS = 77,
2548
2549 /*
2550 * This is the maximum number of SVGA surface IDs that the guest
2551 * can define using SVGA_3D_CMD_SURFACE_DEFINE*.
2552 */
2553 SVGA3D_DEVCAP_MAX_SURFACE_IDS = 78,
2554
2555 SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = 79,
2556 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = 80,
2557 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = 81,
2558
2559 SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = 82,
2560 SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = 83,
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00002561
2562 /*
Thomas Hellstromd9019492012-11-21 10:17:00 +01002563 * Deprecated.
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00002564 */
Thomas Hellstromd9019492012-11-21 10:17:00 +01002565 SVGA3D_DEVCAP_VGPU10 = 84,
2566
2567 /*
2568 * This contains several SVGA_3D_CAPS_VIDEO_DECODE elements
2569 * ored together, one for every type of video decoding supported.
2570 */
2571 SVGA3D_DEVCAP_VIDEO_DECODE = 85,
2572
2573 /*
2574 * This contains several SVGA_3D_CAPS_VIDEO_PROCESS elements
2575 * ored together, one for every type of video processing supported.
2576 */
2577 SVGA3D_DEVCAP_VIDEO_PROCESS = 86,
2578
2579 SVGA3D_DEVCAP_LINE_AA = 87, /* boolean */
2580 SVGA3D_DEVCAP_LINE_STIPPLE = 88, /* boolean */
2581 SVGA3D_DEVCAP_MAX_LINE_WIDTH = 89, /* float */
2582 SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH = 90, /* float */
2583
2584 SVGA3D_DEVCAP_SURFACEFMT_YV12 = 91,
2585
2586 /*
2587 * Does the host support the SVGA logic ops commands?
2588 */
2589 SVGA3D_DEVCAP_LOGICOPS = 92,
2590
2591 /*
2592 * What support does the host have for screen targets?
2593 *
2594 * See the SVGA3D_SCREENTARGET_CAP bits below.
2595 */
2596 SVGA3D_DEVCAP_SCREENTARGETS = 93,
2597
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00002598 SVGA3D_DEVCAP_MAX /* This must be the last index. */
2599} SVGA3dDevCapIndex;
2600
2601typedef union {
2602 Bool b;
2603 uint32 u;
2604 int32 i;
2605 float f;
2606} SVGA3dDevCapResult;
2607
Thomas Hellstroma6fc9552014-01-31 10:21:10 +01002608typedef enum {
2609 SVGA3DCAPS_RECORD_UNKNOWN = 0,
2610 SVGA3DCAPS_RECORD_DEVCAPS_MIN = 0x100,
2611 SVGA3DCAPS_RECORD_DEVCAPS = 0x100,
2612 SVGA3DCAPS_RECORD_DEVCAPS_MAX = 0x1ff,
2613} SVGA3dCapsRecordType;
2614
2615typedef
2616struct SVGA3dCapsRecordHeader {
2617 uint32 length;
2618 SVGA3dCapsRecordType type;
2619}
2620SVGA3dCapsRecordHeader;
2621
2622typedef
2623struct SVGA3dCapsRecord {
2624 SVGA3dCapsRecordHeader header;
2625 uint32 data[1];
2626}
2627SVGA3dCapsRecord;
2628
2629
2630typedef uint32 SVGA3dCapPair[2];
2631
Jakob Bornecrantz632f6112009-12-10 00:19:10 +00002632#endif /* _SVGA3D_REG_H_ */