Blame - sound/soc/codecs/wm5100.h - kernel/msm-4.9

Mark Brown

6d4baf0

2011-09-20 15:44:21 +0100

[diff] [blame^]

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/*

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* wm5100.h -- WM5100 ALSA SoC Audio driver

*

*

* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>

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*

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*

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* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License version 2 as

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* published by the Free Software Foundation.

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*/

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#ifndef WM5100_ASOC_H

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#define WM5100_ASOC_H

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#include <sound/soc.h>

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#define WM5100_CLK_AIF1 1

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#define WM5100_CLK_AIF2 2

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#define WM5100_CLK_AIF3 3

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#define WM5100_CLK_SYSCLK 4

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#define WM5100_CLK_ASYNCCLK 5

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#define WM5100_CLK_32KHZ 6

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#define WM5100_CLK_OPCLK 7

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#define WM5100_CLKSRC_MCLK1 0

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#define WM5100_CLKSRC_MCLK2 1

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#define WM5100_CLKSRC_SYSCLK 2

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#define WM5100_CLKSRC_FLL1 4

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#define WM5100_CLKSRC_FLL2 5

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#define WM5100_CLKSRC_AIF1BCLK 8

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#define WM5100_CLKSRC_AIF2BCLK 9

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#define WM5100_CLKSRC_AIF3BCLK 10

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#define WM5100_CLKSRC_ASYNCCLK 0x100

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#define WM5100_FLL1 1

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#define WM5100_FLL2 2

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#define WM5100_FLL_SRC_MCLK1 0x0

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#define WM5100_FLL_SRC_MCLK2 0x1

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#define WM5100_FLL_SRC_FLL1 0x4

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#define WM5100_FLL_SRC_FLL2 0x5

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#define WM5100_FLL_SRC_AIF1BCLK 0x8

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#define WM5100_FLL_SRC_AIF2BCLK 0x9

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#define WM5100_FLL_SRC_AIF3BCLK 0xa

/*

* Register values.

*/

#define WM5100_SOFTWARE_RESET 0x00

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#define WM5100_DEVICE_REVISION 0x01

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#define WM5100_CTRL_IF_1 0x10

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#define WM5100_TONE_GENERATOR_1 0x20

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#define WM5100_PWM_DRIVE_1 0x30

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#define WM5100_PWM_DRIVE_2 0x31

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#define WM5100_PWM_DRIVE_3 0x32

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#define WM5100_CLOCKING_1 0x100

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#define WM5100_CLOCKING_3 0x101

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#define WM5100_CLOCKING_4 0x102

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#define WM5100_CLOCKING_5 0x103

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#define WM5100_CLOCKING_6 0x104

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#define WM5100_CLOCKING_7 0x107

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#define WM5100_CLOCKING_8 0x108

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#define WM5100_ASRC_ENABLE 0x120

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#define WM5100_ASRC_STATUS 0x121

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#define WM5100_ASRC_RATE1 0x122

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#define WM5100_ISRC_1_CTRL_1 0x141

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#define WM5100_ISRC_1_CTRL_2 0x142

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#define WM5100_ISRC_2_CTRL1 0x143

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#define WM5100_ISRC_2_CTRL_2 0x144

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#define WM5100_FLL1_CONTROL_1 0x182

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#define WM5100_FLL1_CONTROL_2 0x183

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#define WM5100_FLL1_CONTROL_3 0x184

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#define WM5100_FLL1_CONTROL_5 0x186

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#define WM5100_FLL1_CONTROL_6 0x187

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#define WM5100_FLL1_EFS_1 0x188

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#define WM5100_FLL2_CONTROL_1 0x1A2

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#define WM5100_FLL2_CONTROL_2 0x1A3

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#define WM5100_FLL2_CONTROL_3 0x1A4

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#define WM5100_FLL2_CONTROL_5 0x1A6

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#define WM5100_FLL2_CONTROL_6 0x1A7

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#define WM5100_FLL2_EFS_1 0x1A8

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#define WM5100_MIC_CHARGE_PUMP_1 0x200

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#define WM5100_MIC_CHARGE_PUMP_2 0x201

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#define WM5100_HP_CHARGE_PUMP_1 0x202

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#define WM5100_LDO1_CONTROL 0x211

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#define WM5100_MIC_BIAS_CTRL_1 0x215

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#define WM5100_MIC_BIAS_CTRL_2 0x216

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#define WM5100_MIC_BIAS_CTRL_3 0x217

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#define WM5100_ACCESSORY_DETECT_MODE_1 0x280

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#define WM5100_HEADPHONE_DETECT_1 0x288

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#define WM5100_HEADPHONE_DETECT_2 0x289

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#define WM5100_MIC_DETECT_1 0x290

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#define WM5100_MIC_DETECT_2 0x291

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#define WM5100_MIC_DETECT_3 0x292

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#define WM5100_INPUT_ENABLES 0x301

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#define WM5100_INPUT_ENABLES_STATUS 0x302

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#define WM5100_IN1L_CONTROL 0x310

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#define WM5100_IN1R_CONTROL 0x311

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#define WM5100_IN2L_CONTROL 0x312

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#define WM5100_IN2R_CONTROL 0x313

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#define WM5100_IN3L_CONTROL 0x314

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#define WM5100_IN3R_CONTROL 0x315

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#define WM5100_IN4L_CONTROL 0x316

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#define WM5100_IN4R_CONTROL 0x317

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#define WM5100_RXANC_SRC 0x318

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#define WM5100_INPUT_VOLUME_RAMP 0x319

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#define WM5100_ADC_DIGITAL_VOLUME_1L 0x320

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#define WM5100_ADC_DIGITAL_VOLUME_1R 0x321

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#define WM5100_ADC_DIGITAL_VOLUME_2L 0x322

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#define WM5100_ADC_DIGITAL_VOLUME_2R 0x323

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#define WM5100_ADC_DIGITAL_VOLUME_3L 0x324

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#define WM5100_ADC_DIGITAL_VOLUME_3R 0x325

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#define WM5100_ADC_DIGITAL_VOLUME_4L 0x326

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#define WM5100_ADC_DIGITAL_VOLUME_4R 0x327

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#define WM5100_OUTPUT_ENABLES_2 0x401

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#define WM5100_OUTPUT_STATUS_1 0x402

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#define WM5100_OUTPUT_STATUS_2 0x403

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#define WM5100_CHANNEL_ENABLES_1 0x408

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#define WM5100_OUT_VOLUME_1L 0x410

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#define WM5100_OUT_VOLUME_1R 0x411

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#define WM5100_DAC_VOLUME_LIMIT_1L 0x412

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#define WM5100_DAC_VOLUME_LIMIT_1R 0x413

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#define WM5100_OUT_VOLUME_2L 0x414

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#define WM5100_OUT_VOLUME_2R 0x415

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#define WM5100_DAC_VOLUME_LIMIT_2L 0x416

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#define WM5100_DAC_VOLUME_LIMIT_2R 0x417

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#define WM5100_OUT_VOLUME_3L 0x418

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#define WM5100_OUT_VOLUME_3R 0x419

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#define WM5100_DAC_VOLUME_LIMIT_3L 0x41A

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#define WM5100_DAC_VOLUME_LIMIT_3R 0x41B

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#define WM5100_OUT_VOLUME_4L 0x41C

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#define WM5100_OUT_VOLUME_4R 0x41D

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#define WM5100_DAC_VOLUME_LIMIT_5L 0x41E

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#define WM5100_DAC_VOLUME_LIMIT_5R 0x41F

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#define WM5100_DAC_VOLUME_LIMIT_6L 0x420

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#define WM5100_DAC_VOLUME_LIMIT_6R 0x421

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#define WM5100_DAC_AEC_CONTROL_1 0x440

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#define WM5100_OUTPUT_VOLUME_RAMP 0x441

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#define WM5100_DAC_DIGITAL_VOLUME_1L 0x480

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#define WM5100_DAC_DIGITAL_VOLUME_1R 0x481

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#define WM5100_DAC_DIGITAL_VOLUME_2L 0x482

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#define WM5100_DAC_DIGITAL_VOLUME_2R 0x483

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#define WM5100_DAC_DIGITAL_VOLUME_3L 0x484

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#define WM5100_DAC_DIGITAL_VOLUME_3R 0x485

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#define WM5100_DAC_DIGITAL_VOLUME_4L 0x486

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#define WM5100_DAC_DIGITAL_VOLUME_4R 0x487

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#define WM5100_DAC_DIGITAL_VOLUME_5L 0x488

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#define WM5100_DAC_DIGITAL_VOLUME_5R 0x489

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#define WM5100_DAC_DIGITAL_VOLUME_6L 0x48A

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#define WM5100_DAC_DIGITAL_VOLUME_6R 0x48B

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#define WM5100_PDM_SPK1_CTRL_1 0x4C0

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#define WM5100_PDM_SPK1_CTRL_2 0x4C1

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#define WM5100_PDM_SPK2_CTRL_1 0x4C2

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#define WM5100_PDM_SPK2_CTRL_2 0x4C3

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#define WM5100_AUDIO_IF_1_1 0x500

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#define WM5100_AUDIO_IF_1_2 0x501

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#define WM5100_AUDIO_IF_1_3 0x502

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#define WM5100_AUDIO_IF_1_4 0x503

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#define WM5100_AUDIO_IF_1_5 0x504

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#define WM5100_AUDIO_IF_1_6 0x505

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#define WM5100_AUDIO_IF_1_7 0x506

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#define WM5100_AUDIO_IF_1_8 0x507

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#define WM5100_AUDIO_IF_1_9 0x508

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#define WM5100_AUDIO_IF_1_10 0x509

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#define WM5100_AUDIO_IF_1_11 0x50A

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#define WM5100_AUDIO_IF_1_12 0x50B

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#define WM5100_AUDIO_IF_1_13 0x50C

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#define WM5100_AUDIO_IF_1_14 0x50D

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#define WM5100_AUDIO_IF_1_15 0x50E

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#define WM5100_AUDIO_IF_1_16 0x50F

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#define WM5100_AUDIO_IF_1_17 0x510

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#define WM5100_AUDIO_IF_1_18 0x511

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#define WM5100_AUDIO_IF_1_19 0x512

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#define WM5100_AUDIO_IF_1_20 0x513

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#define WM5100_AUDIO_IF_1_21 0x514

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#define WM5100_AUDIO_IF_1_22 0x515

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#define WM5100_AUDIO_IF_1_23 0x516

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#define WM5100_AUDIO_IF_1_24 0x517

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#define WM5100_AUDIO_IF_1_25 0x518

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#define WM5100_AUDIO_IF_1_26 0x519

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#define WM5100_AUDIO_IF_1_27 0x51A

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#define WM5100_AUDIO_IF_2_1 0x540

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#define WM5100_AUDIO_IF_2_2 0x541

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#define WM5100_AUDIO_IF_2_3 0x542

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#define WM5100_AUDIO_IF_2_4 0x543

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#define WM5100_AUDIO_IF_2_5 0x544

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#define WM5100_AUDIO_IF_2_6 0x545

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#define WM5100_AUDIO_IF_2_7 0x546

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#define WM5100_AUDIO_IF_2_8 0x547

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#define WM5100_AUDIO_IF_2_9 0x548

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#define WM5100_AUDIO_IF_2_10 0x549

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#define WM5100_AUDIO_IF_2_11 0x54A

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#define WM5100_AUDIO_IF_2_18 0x551

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#define WM5100_AUDIO_IF_2_19 0x552

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#define WM5100_AUDIO_IF_2_26 0x559

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#define WM5100_AUDIO_IF_2_27 0x55A

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#define WM5100_AUDIO_IF_3_1 0x580

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#define WM5100_AUDIO_IF_3_2 0x581

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#define WM5100_AUDIO_IF_3_3 0x582

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#define WM5100_AUDIO_IF_3_4 0x583

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#define WM5100_AUDIO_IF_3_5 0x584

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#define WM5100_AUDIO_IF_3_6 0x585

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#define WM5100_AUDIO_IF_3_7 0x586

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#define WM5100_AUDIO_IF_3_8 0x587

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#define WM5100_AUDIO_IF_3_9 0x588

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#define WM5100_AUDIO_IF_3_10 0x589

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#define WM5100_AUDIO_IF_3_11 0x58A

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#define WM5100_AUDIO_IF_3_18 0x591

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#define WM5100_AUDIO_IF_3_19 0x592

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#define WM5100_AUDIO_IF_3_26 0x599

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#define WM5100_AUDIO_IF_3_27 0x59A

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#define WM5100_PWM1MIX_INPUT_1_SOURCE 0x640

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#define WM5100_PWM1MIX_INPUT_1_VOLUME 0x641

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#define WM5100_PWM1MIX_INPUT_2_SOURCE 0x642

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#define WM5100_PWM1MIX_INPUT_2_VOLUME 0x643

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#define WM5100_PWM1MIX_INPUT_3_SOURCE 0x644

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#define WM5100_PWM1MIX_INPUT_3_VOLUME 0x645

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#define WM5100_PWM1MIX_INPUT_4_SOURCE 0x646

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#define WM5100_PWM1MIX_INPUT_4_VOLUME 0x647

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#define WM5100_PWM2MIX_INPUT_1_SOURCE 0x648

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#define WM5100_PWM2MIX_INPUT_1_VOLUME 0x649

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#define WM5100_PWM2MIX_INPUT_2_SOURCE 0x64A

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#define WM5100_PWM2MIX_INPUT_2_VOLUME 0x64B

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#define WM5100_PWM2MIX_INPUT_3_SOURCE 0x64C

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#define WM5100_PWM2MIX_INPUT_3_VOLUME 0x64D

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#define WM5100_PWM2MIX_INPUT_4_SOURCE 0x64E

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#define WM5100_PWM2MIX_INPUT_4_VOLUME 0x64F

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#define WM5100_OUT1LMIX_INPUT_1_SOURCE 0x680

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#define WM5100_OUT1LMIX_INPUT_1_VOLUME 0x681

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#define WM5100_OUT1LMIX_INPUT_2_SOURCE 0x682

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#define WM5100_OUT1LMIX_INPUT_2_VOLUME 0x683

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#define WM5100_OUT1LMIX_INPUT_3_SOURCE 0x684

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#define WM5100_OUT1LMIX_INPUT_3_VOLUME 0x685

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#define WM5100_OUT1LMIX_INPUT_4_SOURCE 0x686

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#define WM5100_OUT1LMIX_INPUT_4_VOLUME 0x687

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#define WM5100_OUT1RMIX_INPUT_1_SOURCE 0x688

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#define WM5100_OUT1RMIX_INPUT_1_VOLUME 0x689

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#define WM5100_OUT1RMIX_INPUT_2_SOURCE 0x68A

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#define WM5100_OUT1RMIX_INPUT_2_VOLUME 0x68B

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#define WM5100_OUT1RMIX_INPUT_3_SOURCE 0x68C

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#define WM5100_OUT1RMIX_INPUT_3_VOLUME 0x68D

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#define WM5100_OUT1RMIX_INPUT_4_SOURCE 0x68E

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#define WM5100_OUT1RMIX_INPUT_4_VOLUME 0x68F

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#define WM5100_OUT2LMIX_INPUT_1_SOURCE 0x690

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#define WM5100_OUT2LMIX_INPUT_1_VOLUME 0x691

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#define WM5100_OUT2LMIX_INPUT_2_SOURCE 0x692

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#define WM5100_OUT2LMIX_INPUT_2_VOLUME 0x693

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#define WM5100_OUT2LMIX_INPUT_3_SOURCE 0x694

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#define WM5100_OUT2LMIX_INPUT_3_VOLUME 0x695

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#define WM5100_OUT2LMIX_INPUT_4_SOURCE 0x696

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#define WM5100_OUT2LMIX_INPUT_4_VOLUME 0x697

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#define WM5100_OUT2RMIX_INPUT_1_SOURCE 0x698

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#define WM5100_OUT2RMIX_INPUT_1_VOLUME 0x699

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#define WM5100_OUT2RMIX_INPUT_2_SOURCE 0x69A

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#define WM5100_OUT2RMIX_INPUT_2_VOLUME 0x69B

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#define WM5100_OUT2RMIX_INPUT_3_SOURCE 0x69C

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#define WM5100_OUT2RMIX_INPUT_3_VOLUME 0x69D

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#define WM5100_OUT2RMIX_INPUT_4_SOURCE 0x69E

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#define WM5100_OUT2RMIX_INPUT_4_VOLUME 0x69F

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#define WM5100_OUT3LMIX_INPUT_1_SOURCE 0x6A0

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#define WM5100_OUT3LMIX_INPUT_1_VOLUME 0x6A1

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#define WM5100_OUT3LMIX_INPUT_2_SOURCE 0x6A2

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#define WM5100_OUT3LMIX_INPUT_2_VOLUME 0x6A3

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#define WM5100_OUT3LMIX_INPUT_3_SOURCE 0x6A4

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#define WM5100_OUT3LMIX_INPUT_3_VOLUME 0x6A5

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#define WM5100_OUT3LMIX_INPUT_4_SOURCE 0x6A6

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#define WM5100_OUT3LMIX_INPUT_4_VOLUME 0x6A7

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#define WM5100_OUT3RMIX_INPUT_1_SOURCE 0x6A8

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#define WM5100_OUT3RMIX_INPUT_1_VOLUME 0x6A9

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#define WM5100_OUT3RMIX_INPUT_2_SOURCE 0x6AA

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#define WM5100_OUT3RMIX_INPUT_2_VOLUME 0x6AB

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#define WM5100_OUT3RMIX_INPUT_3_SOURCE 0x6AC

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#define WM5100_OUT3RMIX_INPUT_3_VOLUME 0x6AD

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#define WM5100_OUT3RMIX_INPUT_4_SOURCE 0x6AE

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#define WM5100_OUT3RMIX_INPUT_4_VOLUME 0x6AF

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#define WM5100_OUT4LMIX_INPUT_1_SOURCE 0x6B0

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#define WM5100_OUT4LMIX_INPUT_1_VOLUME 0x6B1

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#define WM5100_OUT4LMIX_INPUT_2_SOURCE 0x6B2

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#define WM5100_OUT4LMIX_INPUT_2_VOLUME 0x6B3

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#define WM5100_OUT4LMIX_INPUT_3_SOURCE 0x6B4

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#define WM5100_OUT4LMIX_INPUT_3_VOLUME 0x6B5

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#define WM5100_OUT4LMIX_INPUT_4_SOURCE 0x6B6

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#define WM5100_OUT4LMIX_INPUT_4_VOLUME 0x6B7

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#define WM5100_OUT4RMIX_INPUT_1_SOURCE 0x6B8

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#define WM5100_OUT4RMIX_INPUT_1_VOLUME 0x6B9

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#define WM5100_OUT4RMIX_INPUT_2_SOURCE 0x6BA

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#define WM5100_OUT4RMIX_INPUT_2_VOLUME 0x6BB

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#define WM5100_OUT4RMIX_INPUT_3_SOURCE 0x6BC

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#define WM5100_OUT4RMIX_INPUT_3_VOLUME 0x6BD

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#define WM5100_OUT4RMIX_INPUT_4_SOURCE 0x6BE

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#define WM5100_OUT4RMIX_INPUT_4_VOLUME 0x6BF

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#define WM5100_OUT5LMIX_INPUT_1_SOURCE 0x6C0

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#define WM5100_OUT5LMIX_INPUT_1_VOLUME 0x6C1

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#define WM5100_OUT5LMIX_INPUT_2_SOURCE 0x6C2

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#define WM5100_OUT5LMIX_INPUT_2_VOLUME 0x6C3

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#define WM5100_OUT5LMIX_INPUT_3_SOURCE 0x6C4

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#define WM5100_OUT5LMIX_INPUT_3_VOLUME 0x6C5

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#define WM5100_OUT5LMIX_INPUT_4_SOURCE 0x6C6

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#define WM5100_OUT5LMIX_INPUT_4_VOLUME 0x6C7

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#define WM5100_OUT5RMIX_INPUT_1_SOURCE 0x6C8

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#define WM5100_OUT5RMIX_INPUT_1_VOLUME 0x6C9

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#define WM5100_OUT5RMIX_INPUT_2_SOURCE 0x6CA

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#define WM5100_OUT5RMIX_INPUT_2_VOLUME 0x6CB

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#define WM5100_OUT5RMIX_INPUT_3_SOURCE 0x6CC

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#define WM5100_OUT5RMIX_INPUT_3_VOLUME 0x6CD

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#define WM5100_OUT5RMIX_INPUT_4_SOURCE 0x6CE

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#define WM5100_OUT5RMIX_INPUT_4_VOLUME 0x6CF

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#define WM5100_OUT6LMIX_INPUT_1_SOURCE 0x6D0

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#define WM5100_OUT6LMIX_INPUT_1_VOLUME 0x6D1

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#define WM5100_OUT6LMIX_INPUT_2_SOURCE 0x6D2

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#define WM5100_OUT6LMIX_INPUT_2_VOLUME 0x6D3

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#define WM5100_OUT6LMIX_INPUT_3_SOURCE 0x6D4

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#define WM5100_OUT6LMIX_INPUT_3_VOLUME 0x6D5

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#define WM5100_OUT6LMIX_INPUT_4_SOURCE 0x6D6

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#define WM5100_OUT6LMIX_INPUT_4_VOLUME 0x6D7

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#define WM5100_OUT6RMIX_INPUT_1_SOURCE 0x6D8

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#define WM5100_OUT6RMIX_INPUT_1_VOLUME 0x6D9

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#define WM5100_OUT6RMIX_INPUT_2_SOURCE 0x6DA

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#define WM5100_OUT6RMIX_INPUT_2_VOLUME 0x6DB

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#define WM5100_OUT6RMIX_INPUT_3_SOURCE 0x6DC

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#define WM5100_OUT6RMIX_INPUT_3_VOLUME 0x6DD

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#define WM5100_OUT6RMIX_INPUT_4_SOURCE 0x6DE

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#define WM5100_OUT6RMIX_INPUT_4_VOLUME 0x6DF

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#define WM5100_AIF1TX1MIX_INPUT_1_SOURCE 0x700

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#define WM5100_AIF1TX1MIX_INPUT_1_VOLUME 0x701

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#define WM5100_AIF1TX1MIX_INPUT_2_SOURCE 0x702

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#define WM5100_AIF1TX1MIX_INPUT_2_VOLUME 0x703

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#define WM5100_AIF1TX1MIX_INPUT_3_SOURCE 0x704

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#define WM5100_AIF1TX1MIX_INPUT_3_VOLUME 0x705

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#define WM5100_AIF1TX1MIX_INPUT_4_SOURCE 0x706

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#define WM5100_AIF1TX1MIX_INPUT_4_VOLUME 0x707

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#define WM5100_AIF1TX2MIX_INPUT_1_SOURCE 0x708

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#define WM5100_AIF1TX2MIX_INPUT_1_VOLUME 0x709

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#define WM5100_AIF1TX2MIX_INPUT_2_SOURCE 0x70A

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#define WM5100_AIF1TX2MIX_INPUT_2_VOLUME 0x70B

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#define WM5100_AIF1TX2MIX_INPUT_3_SOURCE 0x70C

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#define WM5100_AIF1TX2MIX_INPUT_3_VOLUME 0x70D

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#define WM5100_AIF1TX2MIX_INPUT_4_SOURCE 0x70E

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#define WM5100_AIF1TX2MIX_INPUT_4_VOLUME 0x70F

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#define WM5100_AIF1TX3MIX_INPUT_1_SOURCE 0x710

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#define WM5100_AIF1TX3MIX_INPUT_1_VOLUME 0x711

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#define WM5100_AIF1TX3MIX_INPUT_2_SOURCE 0x712

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#define WM5100_AIF1TX3MIX_INPUT_2_VOLUME 0x713

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#define WM5100_AIF1TX3MIX_INPUT_3_SOURCE 0x714

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#define WM5100_AIF1TX3MIX_INPUT_3_VOLUME 0x715

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#define WM5100_AIF1TX3MIX_INPUT_4_SOURCE 0x716

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#define WM5100_AIF1TX3MIX_INPUT_4_VOLUME 0x717

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#define WM5100_AIF1TX4MIX_INPUT_1_SOURCE 0x718

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#define WM5100_AIF1TX4MIX_INPUT_1_VOLUME 0x719

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#define WM5100_AIF1TX4MIX_INPUT_2_SOURCE 0x71A

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#define WM5100_AIF1TX4MIX_INPUT_2_VOLUME 0x71B

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#define WM5100_AIF1TX4MIX_INPUT_3_SOURCE 0x71C

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#define WM5100_AIF1TX4MIX_INPUT_3_VOLUME 0x71D

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#define WM5100_AIF1TX4MIX_INPUT_4_SOURCE 0x71E

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#define WM5100_AIF1TX4MIX_INPUT_4_VOLUME 0x71F

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#define WM5100_AIF1TX5MIX_INPUT_1_SOURCE 0x720

359

#define WM5100_AIF1TX5MIX_INPUT_1_VOLUME 0x721

360

#define WM5100_AIF1TX5MIX_INPUT_2_SOURCE 0x722

361

#define WM5100_AIF1TX5MIX_INPUT_2_VOLUME 0x723

362

#define WM5100_AIF1TX5MIX_INPUT_3_SOURCE 0x724

363

#define WM5100_AIF1TX5MIX_INPUT_3_VOLUME 0x725

364

#define WM5100_AIF1TX5MIX_INPUT_4_SOURCE 0x726

365

#define WM5100_AIF1TX5MIX_INPUT_4_VOLUME 0x727

366

#define WM5100_AIF1TX6MIX_INPUT_1_SOURCE 0x728

367

#define WM5100_AIF1TX6MIX_INPUT_1_VOLUME 0x729

368

#define WM5100_AIF1TX6MIX_INPUT_2_SOURCE 0x72A

369

#define WM5100_AIF1TX6MIX_INPUT_2_VOLUME 0x72B

370

#define WM5100_AIF1TX6MIX_INPUT_3_SOURCE 0x72C

371

#define WM5100_AIF1TX6MIX_INPUT_3_VOLUME 0x72D

372

#define WM5100_AIF1TX6MIX_INPUT_4_SOURCE 0x72E

373

#define WM5100_AIF1TX6MIX_INPUT_4_VOLUME 0x72F

374

#define WM5100_AIF1TX7MIX_INPUT_1_SOURCE 0x730

375

#define WM5100_AIF1TX7MIX_INPUT_1_VOLUME 0x731

376

#define WM5100_AIF1TX7MIX_INPUT_2_SOURCE 0x732

377

#define WM5100_AIF1TX7MIX_INPUT_2_VOLUME 0x733

378

#define WM5100_AIF1TX7MIX_INPUT_3_SOURCE 0x734

379

#define WM5100_AIF1TX7MIX_INPUT_3_VOLUME 0x735

380

#define WM5100_AIF1TX7MIX_INPUT_4_SOURCE 0x736

381

#define WM5100_AIF1TX7MIX_INPUT_4_VOLUME 0x737

382

#define WM5100_AIF1TX8MIX_INPUT_1_SOURCE 0x738

383

#define WM5100_AIF1TX8MIX_INPUT_1_VOLUME 0x739

384

#define WM5100_AIF1TX8MIX_INPUT_2_SOURCE 0x73A

385

#define WM5100_AIF1TX8MIX_INPUT_2_VOLUME 0x73B

386

#define WM5100_AIF1TX8MIX_INPUT_3_SOURCE 0x73C

387

#define WM5100_AIF1TX8MIX_INPUT_3_VOLUME 0x73D

388

#define WM5100_AIF1TX8MIX_INPUT_4_SOURCE 0x73E

389

#define WM5100_AIF1TX8MIX_INPUT_4_VOLUME 0x73F

390

#define WM5100_AIF2TX1MIX_INPUT_1_SOURCE 0x740

391

#define WM5100_AIF2TX1MIX_INPUT_1_VOLUME 0x741

392

#define WM5100_AIF2TX1MIX_INPUT_2_SOURCE 0x742

393

#define WM5100_AIF2TX1MIX_INPUT_2_VOLUME 0x743

394

#define WM5100_AIF2TX1MIX_INPUT_3_SOURCE 0x744

395

#define WM5100_AIF2TX1MIX_INPUT_3_VOLUME 0x745

396

#define WM5100_AIF2TX1MIX_INPUT_4_SOURCE 0x746

397

#define WM5100_AIF2TX1MIX_INPUT_4_VOLUME 0x747

398

#define WM5100_AIF2TX2MIX_INPUT_1_SOURCE 0x748

399

#define WM5100_AIF2TX2MIX_INPUT_1_VOLUME 0x749

400

#define WM5100_AIF2TX2MIX_INPUT_2_SOURCE 0x74A

401

#define WM5100_AIF2TX2MIX_INPUT_2_VOLUME 0x74B

402

#define WM5100_AIF2TX2MIX_INPUT_3_SOURCE 0x74C

403

#define WM5100_AIF2TX2MIX_INPUT_3_VOLUME 0x74D

404

#define WM5100_AIF2TX2MIX_INPUT_4_SOURCE 0x74E

405

#define WM5100_AIF2TX2MIX_INPUT_4_VOLUME 0x74F

406

#define WM5100_AIF3TX1MIX_INPUT_1_SOURCE 0x780

407

#define WM5100_AIF3TX1MIX_INPUT_1_VOLUME 0x781

408

#define WM5100_AIF3TX1MIX_INPUT_2_SOURCE 0x782

409

#define WM5100_AIF3TX1MIX_INPUT_2_VOLUME 0x783

410

#define WM5100_AIF3TX1MIX_INPUT_3_SOURCE 0x784

411

#define WM5100_AIF3TX1MIX_INPUT_3_VOLUME 0x785

412

#define WM5100_AIF3TX1MIX_INPUT_4_SOURCE 0x786

413

#define WM5100_AIF3TX1MIX_INPUT_4_VOLUME 0x787

414

#define WM5100_AIF3TX2MIX_INPUT_1_SOURCE 0x788

415

#define WM5100_AIF3TX2MIX_INPUT_1_VOLUME 0x789

416

#define WM5100_AIF3TX2MIX_INPUT_2_SOURCE 0x78A

417

#define WM5100_AIF3TX2MIX_INPUT_2_VOLUME 0x78B

418

#define WM5100_AIF3TX2MIX_INPUT_3_SOURCE 0x78C

419

#define WM5100_AIF3TX2MIX_INPUT_3_VOLUME 0x78D

420

#define WM5100_AIF3TX2MIX_INPUT_4_SOURCE 0x78E

421

#define WM5100_AIF3TX2MIX_INPUT_4_VOLUME 0x78F

422

#define WM5100_EQ1MIX_INPUT_1_SOURCE 0x880

423

#define WM5100_EQ1MIX_INPUT_1_VOLUME 0x881

424

#define WM5100_EQ1MIX_INPUT_2_SOURCE 0x882

425

#define WM5100_EQ1MIX_INPUT_2_VOLUME 0x883

426

#define WM5100_EQ1MIX_INPUT_3_SOURCE 0x884

427

#define WM5100_EQ1MIX_INPUT_3_VOLUME 0x885

428

#define WM5100_EQ1MIX_INPUT_4_SOURCE 0x886

429

#define WM5100_EQ1MIX_INPUT_4_VOLUME 0x887

430

#define WM5100_EQ2MIX_INPUT_1_SOURCE 0x888

431

#define WM5100_EQ2MIX_INPUT_1_VOLUME 0x889

432

#define WM5100_EQ2MIX_INPUT_2_SOURCE 0x88A

433

#define WM5100_EQ2MIX_INPUT_2_VOLUME 0x88B

434

#define WM5100_EQ2MIX_INPUT_3_SOURCE 0x88C

435

#define WM5100_EQ2MIX_INPUT_3_VOLUME 0x88D

436

#define WM5100_EQ2MIX_INPUT_4_SOURCE 0x88E

437

#define WM5100_EQ2MIX_INPUT_4_VOLUME 0x88F

438

#define WM5100_EQ3MIX_INPUT_1_SOURCE 0x890

439

#define WM5100_EQ3MIX_INPUT_1_VOLUME 0x891

440

#define WM5100_EQ3MIX_INPUT_2_SOURCE 0x892

441

#define WM5100_EQ3MIX_INPUT_2_VOLUME 0x893

442

#define WM5100_EQ3MIX_INPUT_3_SOURCE 0x894

443

#define WM5100_EQ3MIX_INPUT_3_VOLUME 0x895

444

#define WM5100_EQ3MIX_INPUT_4_SOURCE 0x896

445

#define WM5100_EQ3MIX_INPUT_4_VOLUME 0x897

446

#define WM5100_EQ4MIX_INPUT_1_SOURCE 0x898

447

#define WM5100_EQ4MIX_INPUT_1_VOLUME 0x899

448

#define WM5100_EQ4MIX_INPUT_2_SOURCE 0x89A

449

#define WM5100_EQ4MIX_INPUT_2_VOLUME 0x89B

450

#define WM5100_EQ4MIX_INPUT_3_SOURCE 0x89C

451

#define WM5100_EQ4MIX_INPUT_3_VOLUME 0x89D

452

#define WM5100_EQ4MIX_INPUT_4_SOURCE 0x89E

453

#define WM5100_EQ4MIX_INPUT_4_VOLUME 0x89F

454

#define WM5100_DRC1LMIX_INPUT_1_SOURCE 0x8C0

455

#define WM5100_DRC1LMIX_INPUT_1_VOLUME 0x8C1

456

#define WM5100_DRC1LMIX_INPUT_2_SOURCE 0x8C2

457

#define WM5100_DRC1LMIX_INPUT_2_VOLUME 0x8C3

458

#define WM5100_DRC1LMIX_INPUT_3_SOURCE 0x8C4

459

#define WM5100_DRC1LMIX_INPUT_3_VOLUME 0x8C5

460

#define WM5100_DRC1LMIX_INPUT_4_SOURCE 0x8C6

461

#define WM5100_DRC1LMIX_INPUT_4_VOLUME 0x8C7

462

#define WM5100_DRC1RMIX_INPUT_1_SOURCE 0x8C8

463

#define WM5100_DRC1RMIX_INPUT_1_VOLUME 0x8C9

464

#define WM5100_DRC1RMIX_INPUT_2_SOURCE 0x8CA

465

#define WM5100_DRC1RMIX_INPUT_2_VOLUME 0x8CB

466

#define WM5100_DRC1RMIX_INPUT_3_SOURCE 0x8CC

467

#define WM5100_DRC1RMIX_INPUT_3_VOLUME 0x8CD

468

#define WM5100_DRC1RMIX_INPUT_4_SOURCE 0x8CE

469

#define WM5100_DRC1RMIX_INPUT_4_VOLUME 0x8CF

470

#define WM5100_HPLP1MIX_INPUT_1_SOURCE 0x900

471

#define WM5100_HPLP1MIX_INPUT_1_VOLUME 0x901

472

#define WM5100_HPLP1MIX_INPUT_2_SOURCE 0x902

473

#define WM5100_HPLP1MIX_INPUT_2_VOLUME 0x903

474

#define WM5100_HPLP1MIX_INPUT_3_SOURCE 0x904

475

#define WM5100_HPLP1MIX_INPUT_3_VOLUME 0x905

476

#define WM5100_HPLP1MIX_INPUT_4_SOURCE 0x906

477

#define WM5100_HPLP1MIX_INPUT_4_VOLUME 0x907

478

#define WM5100_HPLP2MIX_INPUT_1_SOURCE 0x908

479

#define WM5100_HPLP2MIX_INPUT_1_VOLUME 0x909

480

#define WM5100_HPLP2MIX_INPUT_2_SOURCE 0x90A

481

#define WM5100_HPLP2MIX_INPUT_2_VOLUME 0x90B

482

#define WM5100_HPLP2MIX_INPUT_3_SOURCE 0x90C

483

#define WM5100_HPLP2MIX_INPUT_3_VOLUME 0x90D

484

#define WM5100_HPLP2MIX_INPUT_4_SOURCE 0x90E

485

#define WM5100_HPLP2MIX_INPUT_4_VOLUME 0x90F

486

#define WM5100_HPLP3MIX_INPUT_1_SOURCE 0x910

487

#define WM5100_HPLP3MIX_INPUT_1_VOLUME 0x911

488

#define WM5100_HPLP3MIX_INPUT_2_SOURCE 0x912

489

#define WM5100_HPLP3MIX_INPUT_2_VOLUME 0x913

490

#define WM5100_HPLP3MIX_INPUT_3_SOURCE 0x914

491

#define WM5100_HPLP3MIX_INPUT_3_VOLUME 0x915

492

#define WM5100_HPLP3MIX_INPUT_4_SOURCE 0x916

493

#define WM5100_HPLP3MIX_INPUT_4_VOLUME 0x917

494

#define WM5100_HPLP4MIX_INPUT_1_SOURCE 0x918

495

#define WM5100_HPLP4MIX_INPUT_1_VOLUME 0x919

496

#define WM5100_HPLP4MIX_INPUT_2_SOURCE 0x91A

497

#define WM5100_HPLP4MIX_INPUT_2_VOLUME 0x91B

498

#define WM5100_HPLP4MIX_INPUT_3_SOURCE 0x91C

499

#define WM5100_HPLP4MIX_INPUT_3_VOLUME 0x91D

500

#define WM5100_HPLP4MIX_INPUT_4_SOURCE 0x91E

501

#define WM5100_HPLP4MIX_INPUT_4_VOLUME 0x91F

502

#define WM5100_DSP1LMIX_INPUT_1_SOURCE 0x940

503

#define WM5100_DSP1LMIX_INPUT_1_VOLUME 0x941

504

#define WM5100_DSP1LMIX_INPUT_2_SOURCE 0x942

505

#define WM5100_DSP1LMIX_INPUT_2_VOLUME 0x943

506

#define WM5100_DSP1LMIX_INPUT_3_SOURCE 0x944

507

#define WM5100_DSP1LMIX_INPUT_3_VOLUME 0x945

508

#define WM5100_DSP1LMIX_INPUT_4_SOURCE 0x946

509

#define WM5100_DSP1LMIX_INPUT_4_VOLUME 0x947

510

#define WM5100_DSP1RMIX_INPUT_1_SOURCE 0x948

511

#define WM5100_DSP1RMIX_INPUT_1_VOLUME 0x949

512

#define WM5100_DSP1RMIX_INPUT_2_SOURCE 0x94A

513

#define WM5100_DSP1RMIX_INPUT_2_VOLUME 0x94B

514

#define WM5100_DSP1RMIX_INPUT_3_SOURCE 0x94C

515

#define WM5100_DSP1RMIX_INPUT_3_VOLUME 0x94D

516

#define WM5100_DSP1RMIX_INPUT_4_SOURCE 0x94E

517

#define WM5100_DSP1RMIX_INPUT_4_VOLUME 0x94F

518

#define WM5100_DSP1AUX1MIX_INPUT_1_SOURCE 0x950

519

#define WM5100_DSP1AUX2MIX_INPUT_1_SOURCE 0x958

520

#define WM5100_DSP1AUX3MIX_INPUT_1_SOURCE 0x960

521

#define WM5100_DSP1AUX4MIX_INPUT_1_SOURCE 0x968

522

#define WM5100_DSP1AUX5MIX_INPUT_1_SOURCE 0x970

523

#define WM5100_DSP1AUX6MIX_INPUT_1_SOURCE 0x978

524

#define WM5100_DSP2LMIX_INPUT_1_SOURCE 0x980

525

#define WM5100_DSP2LMIX_INPUT_1_VOLUME 0x981

526

#define WM5100_DSP2LMIX_INPUT_2_SOURCE 0x982

527

#define WM5100_DSP2LMIX_INPUT_2_VOLUME 0x983

528

#define WM5100_DSP2LMIX_INPUT_3_SOURCE 0x984

529

#define WM5100_DSP2LMIX_INPUT_3_VOLUME 0x985

530

#define WM5100_DSP2LMIX_INPUT_4_SOURCE 0x986

531

#define WM5100_DSP2LMIX_INPUT_4_VOLUME 0x987

532

#define WM5100_DSP2RMIX_INPUT_1_SOURCE 0x988

533

#define WM5100_DSP2RMIX_INPUT_1_VOLUME 0x989

534

#define WM5100_DSP2RMIX_INPUT_2_SOURCE 0x98A

535

#define WM5100_DSP2RMIX_INPUT_2_VOLUME 0x98B

536

#define WM5100_DSP2RMIX_INPUT_3_SOURCE 0x98C

537

#define WM5100_DSP2RMIX_INPUT_3_VOLUME 0x98D

538

#define WM5100_DSP2RMIX_INPUT_4_SOURCE 0x98E

539

#define WM5100_DSP2RMIX_INPUT_4_VOLUME 0x98F

540

#define WM5100_DSP2AUX1MIX_INPUT_1_SOURCE 0x990

541

#define WM5100_DSP2AUX2MIX_INPUT_1_SOURCE 0x998

542

#define WM5100_DSP2AUX3MIX_INPUT_1_SOURCE 0x9A0

543

#define WM5100_DSP2AUX4MIX_INPUT_1_SOURCE 0x9A8

544

#define WM5100_DSP2AUX5MIX_INPUT_1_SOURCE 0x9B0

545

#define WM5100_DSP2AUX6MIX_INPUT_1_SOURCE 0x9B8

546

#define WM5100_DSP3LMIX_INPUT_1_SOURCE 0x9C0

547

#define WM5100_DSP3LMIX_INPUT_1_VOLUME 0x9C1

548

#define WM5100_DSP3LMIX_INPUT_2_SOURCE 0x9C2

549

#define WM5100_DSP3LMIX_INPUT_2_VOLUME 0x9C3

550

#define WM5100_DSP3LMIX_INPUT_3_SOURCE 0x9C4

551

#define WM5100_DSP3LMIX_INPUT_3_VOLUME 0x9C5

552

#define WM5100_DSP3LMIX_INPUT_4_SOURCE 0x9C6

553

#define WM5100_DSP3LMIX_INPUT_4_VOLUME 0x9C7

554

#define WM5100_DSP3RMIX_INPUT_1_SOURCE 0x9C8

555

#define WM5100_DSP3RMIX_INPUT_1_VOLUME 0x9C9

556

#define WM5100_DSP3RMIX_INPUT_2_SOURCE 0x9CA

557

#define WM5100_DSP3RMIX_INPUT_2_VOLUME 0x9CB

558

#define WM5100_DSP3RMIX_INPUT_3_SOURCE 0x9CC

559

#define WM5100_DSP3RMIX_INPUT_3_VOLUME 0x9CD

560

#define WM5100_DSP3RMIX_INPUT_4_SOURCE 0x9CE

561

#define WM5100_DSP3RMIX_INPUT_4_VOLUME 0x9CF

562

#define WM5100_DSP3AUX1MIX_INPUT_1_SOURCE 0x9D0

563

#define WM5100_DSP3AUX2MIX_INPUT_1_SOURCE 0x9D8

564

#define WM5100_DSP3AUX3MIX_INPUT_1_SOURCE 0x9E0

565

#define WM5100_DSP3AUX4MIX_INPUT_1_SOURCE 0x9E8

566

#define WM5100_DSP3AUX5MIX_INPUT_1_SOURCE 0x9F0

567

#define WM5100_DSP3AUX6MIX_INPUT_1_SOURCE 0x9F8

568

#define WM5100_ASRC1LMIX_INPUT_1_SOURCE 0xA80

569

#define WM5100_ASRC1RMIX_INPUT_1_SOURCE 0xA88

570

#define WM5100_ASRC2LMIX_INPUT_1_SOURCE 0xA90

571

#define WM5100_ASRC2RMIX_INPUT_1_SOURCE 0xA98

572

#define WM5100_ISRC1DEC1MIX_INPUT_1_SOURCE 0xB00

573

#define WM5100_ISRC1DEC2MIX_INPUT_1_SOURCE 0xB08

574

#define WM5100_ISRC1DEC3MIX_INPUT_1_SOURCE 0xB10

575

#define WM5100_ISRC1DEC4MIX_INPUT_1_SOURCE 0xB18

576

#define WM5100_ISRC1INT1MIX_INPUT_1_SOURCE 0xB20

577

#define WM5100_ISRC1INT2MIX_INPUT_1_SOURCE 0xB28

578

#define WM5100_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30

579

#define WM5100_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38

580

#define WM5100_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40

581

#define WM5100_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48

582

#define WM5100_ISRC2DEC3MIX_INPUT_1_SOURCE 0xB50

583

#define WM5100_ISRC2DEC4MIX_INPUT_1_SOURCE 0xB58

584

#define WM5100_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60

585

#define WM5100_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68

586

#define WM5100_ISRC2INT3MIX_INPUT_1_SOURCE 0xB70

587

#define WM5100_ISRC2INT4MIX_INPUT_1_SOURCE 0xB78

588

#define WM5100_GPIO_CTRL_1 0xC00

589

#define WM5100_GPIO_CTRL_2 0xC01

590

#define WM5100_GPIO_CTRL_3 0xC02

591

#define WM5100_GPIO_CTRL_4 0xC03

592

#define WM5100_GPIO_CTRL_5 0xC04

593

#define WM5100_GPIO_CTRL_6 0xC05

594

#define WM5100_MISC_PAD_CTRL_1 0xC23

595

#define WM5100_MISC_PAD_CTRL_2 0xC24

596

#define WM5100_MISC_PAD_CTRL_3 0xC25

597

#define WM5100_MISC_PAD_CTRL_4 0xC26

598

#define WM5100_MISC_PAD_CTRL_5 0xC27

599

#define WM5100_MISC_GPIO_1 0xC28

600

#define WM5100_INTERRUPT_STATUS_1 0xD00

601

#define WM5100_INTERRUPT_STATUS_2 0xD01

602

#define WM5100_INTERRUPT_STATUS_3 0xD02

603

#define WM5100_INTERRUPT_STATUS_4 0xD03

604

#define WM5100_INTERRUPT_RAW_STATUS_2 0xD04

605

#define WM5100_INTERRUPT_RAW_STATUS_3 0xD05

606

#define WM5100_INTERRUPT_RAW_STATUS_4 0xD06

607

#define WM5100_INTERRUPT_STATUS_1_MASK 0xD07

608

#define WM5100_INTERRUPT_STATUS_2_MASK 0xD08

609

#define WM5100_INTERRUPT_STATUS_3_MASK 0xD09

610

#define WM5100_INTERRUPT_STATUS_4_MASK 0xD0A

611

#define WM5100_INTERRUPT_CONTROL 0xD1F

612

#define WM5100_IRQ_DEBOUNCE_1 0xD20

613

#define WM5100_IRQ_DEBOUNCE_2 0xD21

614

#define WM5100_FX_CTRL 0xE00

615

#define WM5100_EQ1_1 0xE10

616

#define WM5100_EQ1_2 0xE11

617

#define WM5100_EQ1_3 0xE12

618

#define WM5100_EQ1_4 0xE13

619

#define WM5100_EQ1_5 0xE14

620

#define WM5100_EQ1_6 0xE15

621

#define WM5100_EQ1_7 0xE16

622

#define WM5100_EQ1_8 0xE17

623

#define WM5100_EQ1_9 0xE18

624

#define WM5100_EQ1_10 0xE19

625

#define WM5100_EQ1_11 0xE1A

626

#define WM5100_EQ1_12 0xE1B

627

#define WM5100_EQ1_13 0xE1C

628

#define WM5100_EQ1_14 0xE1D

629

#define WM5100_EQ1_15 0xE1E

630

#define WM5100_EQ1_16 0xE1F

631

#define WM5100_EQ1_17 0xE20

632

#define WM5100_EQ1_18 0xE21

633

#define WM5100_EQ1_19 0xE22

634

#define WM5100_EQ1_20 0xE23

635

#define WM5100_EQ2_1 0xE26

636

#define WM5100_EQ2_2 0xE27

637

#define WM5100_EQ2_3 0xE28

638

#define WM5100_EQ2_4 0xE29

639

#define WM5100_EQ2_5 0xE2A

640

#define WM5100_EQ2_6 0xE2B

641

#define WM5100_EQ2_7 0xE2C

642

#define WM5100_EQ2_8 0xE2D

643

#define WM5100_EQ2_9 0xE2E

644

#define WM5100_EQ2_10 0xE2F

645

#define WM5100_EQ2_11 0xE30

646

#define WM5100_EQ2_12 0xE31

647

#define WM5100_EQ2_13 0xE32

648

#define WM5100_EQ2_14 0xE33

649

#define WM5100_EQ2_15 0xE34

650

#define WM5100_EQ2_16 0xE35

651

#define WM5100_EQ2_17 0xE36

652

#define WM5100_EQ2_18 0xE37

653

#define WM5100_EQ2_19 0xE38

654

#define WM5100_EQ2_20 0xE39

655

#define WM5100_EQ3_1 0xE3C

656

#define WM5100_EQ3_2 0xE3D

657

#define WM5100_EQ3_3 0xE3E

658

#define WM5100_EQ3_4 0xE3F

659

#define WM5100_EQ3_5 0xE40

660

#define WM5100_EQ3_6 0xE41

661

#define WM5100_EQ3_7 0xE42

662

#define WM5100_EQ3_8 0xE43

663

#define WM5100_EQ3_9 0xE44

664

#define WM5100_EQ3_10 0xE45

665

#define WM5100_EQ3_11 0xE46

666

#define WM5100_EQ3_12 0xE47

667

#define WM5100_EQ3_13 0xE48

668

#define WM5100_EQ3_14 0xE49

669

#define WM5100_EQ3_15 0xE4A

670

#define WM5100_EQ3_16 0xE4B

671

#define WM5100_EQ3_17 0xE4C

672

#define WM5100_EQ3_18 0xE4D

673

#define WM5100_EQ3_19 0xE4E

674

#define WM5100_EQ3_20 0xE4F

675

#define WM5100_EQ4_1 0xE52

676

#define WM5100_EQ4_2 0xE53

677

#define WM5100_EQ4_3 0xE54

678

#define WM5100_EQ4_4 0xE55

679

#define WM5100_EQ4_5 0xE56

680

#define WM5100_EQ4_6 0xE57

681

#define WM5100_EQ4_7 0xE58

682

#define WM5100_EQ4_8 0xE59

683

#define WM5100_EQ4_9 0xE5A

684

#define WM5100_EQ4_10 0xE5B

685

#define WM5100_EQ4_11 0xE5C

686

#define WM5100_EQ4_12 0xE5D

687

#define WM5100_EQ4_13 0xE5E

688

#define WM5100_EQ4_14 0xE5F

689

#define WM5100_EQ4_15 0xE60

690

#define WM5100_EQ4_16 0xE61

691

#define WM5100_EQ4_17 0xE62

692

#define WM5100_EQ4_18 0xE63

693

#define WM5100_EQ4_19 0xE64

694

#define WM5100_EQ4_20 0xE65

695

#define WM5100_DRC1_CTRL1 0xE80

696

#define WM5100_DRC1_CTRL2 0xE81

697

#define WM5100_DRC1_CTRL3 0xE82

698

#define WM5100_DRC1_CTRL4 0xE83

699

#define WM5100_DRC1_CTRL5 0xE84

700

#define WM5100_HPLPF1_1 0xEC0

701

#define WM5100_HPLPF1_2 0xEC1

702

#define WM5100_HPLPF2_1 0xEC4

703

#define WM5100_HPLPF2_2 0xEC5

704

#define WM5100_HPLPF3_1 0xEC8

705

#define WM5100_HPLPF3_2 0xEC9

706

#define WM5100_HPLPF4_1 0xECC

707

#define WM5100_HPLPF4_2 0xECD

708

#define WM5100_DSP1_DM_0 0x4000

709

#define WM5100_DSP1_DM_1 0x4001

710

#define WM5100_DSP1_DM_2 0x4002

711

#define WM5100_DSP1_DM_3 0x4003

712

#define WM5100_DSP1_DM_508 0x41FC

713

#define WM5100_DSP1_DM_509 0x41FD

714

#define WM5100_DSP1_DM_510 0x41FE

715

#define WM5100_DSP1_DM_511 0x41FF

716

#define WM5100_DSP1_PM_0 0x4800

717

#define WM5100_DSP1_PM_1 0x4801

718

#define WM5100_DSP1_PM_2 0x4802

719

#define WM5100_DSP1_PM_3 0x4803

720

#define WM5100_DSP1_PM_4 0x4804

721

#define WM5100_DSP1_PM_5 0x4805

722

#define WM5100_DSP1_PM_1530 0x4DFA

723

#define WM5100_DSP1_PM_1531 0x4DFB

724

#define WM5100_DSP1_PM_1532 0x4DFC

725

#define WM5100_DSP1_PM_1533 0x4DFD

726

#define WM5100_DSP1_PM_1534 0x4DFE

727

#define WM5100_DSP1_PM_1535 0x4DFF

728

#define WM5100_DSP1_ZM_0 0x5000

729

#define WM5100_DSP1_ZM_1 0x5001

730

#define WM5100_DSP1_ZM_2 0x5002

731

#define WM5100_DSP1_ZM_3 0x5003

732

#define WM5100_DSP1_ZM_2044 0x57FC

733

#define WM5100_DSP1_ZM_2045 0x57FD

734

#define WM5100_DSP1_ZM_2046 0x57FE

735

#define WM5100_DSP1_ZM_2047 0x57FF

736

#define WM5100_DSP2_DM_0 0x6000

737

#define WM5100_DSP2_DM_1 0x6001

738

#define WM5100_DSP2_DM_2 0x6002

739

#define WM5100_DSP2_DM_3 0x6003

740

#define WM5100_DSP2_DM_508 0x61FC

741

#define WM5100_DSP2_DM_509 0x61FD

742

#define WM5100_DSP2_DM_510 0x61FE

743

#define WM5100_DSP2_DM_511 0x61FF

744

#define WM5100_DSP2_PM_0 0x6800

745

#define WM5100_DSP2_PM_1 0x6801

746

#define WM5100_DSP2_PM_2 0x6802

747

#define WM5100_DSP2_PM_3 0x6803

748

#define WM5100_DSP2_PM_4 0x6804

749

#define WM5100_DSP2_PM_5 0x6805

750

#define WM5100_DSP2_PM_1530 0x6DFA

751

#define WM5100_DSP2_PM_1531 0x6DFB

752

#define WM5100_DSP2_PM_1532 0x6DFC

753

#define WM5100_DSP2_PM_1533 0x6DFD

754

#define WM5100_DSP2_PM_1534 0x6DFE

755

#define WM5100_DSP2_PM_1535 0x6DFF

756

#define WM5100_DSP2_ZM_0 0x7000

757

#define WM5100_DSP2_ZM_1 0x7001

758

#define WM5100_DSP2_ZM_2 0x7002

759

#define WM5100_DSP2_ZM_3 0x7003

760

#define WM5100_DSP2_ZM_2044 0x77FC

761

#define WM5100_DSP2_ZM_2045 0x77FD

762

#define WM5100_DSP2_ZM_2046 0x77FE

763

#define WM5100_DSP2_ZM_2047 0x77FF

764

#define WM5100_DSP3_DM_0 0x8000

765

#define WM5100_DSP3_DM_1 0x8001

766

#define WM5100_DSP3_DM_2 0x8002

767

#define WM5100_DSP3_DM_3 0x8003

768

#define WM5100_DSP3_DM_508 0x81FC

769

#define WM5100_DSP3_DM_509 0x81FD

770

#define WM5100_DSP3_DM_510 0x81FE

771

#define WM5100_DSP3_DM_511 0x81FF

772

#define WM5100_DSP3_PM_0 0x8800

773

#define WM5100_DSP3_PM_1 0x8801

774

#define WM5100_DSP3_PM_2 0x8802

775

#define WM5100_DSP3_PM_3 0x8803

776

#define WM5100_DSP3_PM_4 0x8804

777

#define WM5100_DSP3_PM_5 0x8805

778

#define WM5100_DSP3_PM_1530 0x8DFA

779

#define WM5100_DSP3_PM_1531 0x8DFB

780

#define WM5100_DSP3_PM_1532 0x8DFC

781

#define WM5100_DSP3_PM_1533 0x8DFD

782

#define WM5100_DSP3_PM_1534 0x8DFE

783

#define WM5100_DSP3_PM_1535 0x8DFF

784

#define WM5100_DSP3_ZM_0 0x9000

785

#define WM5100_DSP3_ZM_1 0x9001

786

#define WM5100_DSP3_ZM_2 0x9002

787

#define WM5100_DSP3_ZM_3 0x9003

788

#define WM5100_DSP3_ZM_2044 0x97FC

789

#define WM5100_DSP3_ZM_2045 0x97FD

790

#define WM5100_DSP3_ZM_2046 0x97FE

791

#define WM5100_DSP3_ZM_2047 0x97FF

792

793

#define WM5100_REGISTER_COUNT 1435

794

#define WM5100_MAX_REGISTER 0x97FF

/*

* Field Definitions.

*/

/*

* R0 (0x00) - software reset

802

*/

803

#define WM5100_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */

804

#define WM5100_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */

805

#define WM5100_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */

806

807

/*

808

* R1 (0x01) - Device Revision

809

*/

810

#define WM5100_DEVICE_REVISION_MASK 0x000F /* DEVICE_REVISION - [3:0] */

811

#define WM5100_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [3:0] */

812

#define WM5100_DEVICE_REVISION_WIDTH 4 /* DEVICE_REVISION - [3:0] */

813

814

/*

815

* R16 (0x10) - Ctrl IF 1

816

*/

817

#define WM5100_AUTO_INC 0x0001 /* AUTO_INC */

818

#define WM5100_AUTO_INC_MASK 0x0001 /* AUTO_INC */

819

#define WM5100_AUTO_INC_SHIFT 0 /* AUTO_INC */

820

#define WM5100_AUTO_INC_WIDTH 1 /* AUTO_INC */

821

822

/*

823

* R32 (0x20) - Tone Generator 1

824

*/

825

#define WM5100_TONE_RATE_MASK 0x3000 /* TONE_RATE - [13:12] */

826

#define WM5100_TONE_RATE_SHIFT 12 /* TONE_RATE - [13:12] */

827

#define WM5100_TONE_RATE_WIDTH 2 /* TONE_RATE - [13:12] */

828

#define WM5100_TONE_OFFSET_MASK 0x0300 /* TONE_OFFSET - [9:8] */

829

#define WM5100_TONE_OFFSET_SHIFT 8 /* TONE_OFFSET - [9:8] */

830

#define WM5100_TONE_OFFSET_WIDTH 2 /* TONE_OFFSET - [9:8] */

831

#define WM5100_TONE2_ENA 0x0002 /* TONE2_ENA */

832

#define WM5100_TONE2_ENA_MASK 0x0002 /* TONE2_ENA */

833

#define WM5100_TONE2_ENA_SHIFT 1 /* TONE2_ENA */

834

#define WM5100_TONE2_ENA_WIDTH 1 /* TONE2_ENA */

835

#define WM5100_TONE1_ENA 0x0001 /* TONE1_ENA */

836

#define WM5100_TONE1_ENA_MASK 0x0001 /* TONE1_ENA */

837

#define WM5100_TONE1_ENA_SHIFT 0 /* TONE1_ENA */

838

#define WM5100_TONE1_ENA_WIDTH 1 /* TONE1_ENA */

839

840

/*

841

* R48 (0x30) - PWM Drive 1

842

*/

843

#define WM5100_PWM_RATE_MASK 0x3000 /* PWM_RATE - [13:12] */

844

#define WM5100_PWM_RATE_SHIFT 12 /* PWM_RATE - [13:12] */

845

#define WM5100_PWM_RATE_WIDTH 2 /* PWM_RATE - [13:12] */

846

#define WM5100_PWM_CLK_SEL_MASK 0x0300 /* PWM_CLK_SEL - [9:8] */

847

#define WM5100_PWM_CLK_SEL_SHIFT 8 /* PWM_CLK_SEL - [9:8] */

848

#define WM5100_PWM_CLK_SEL_WIDTH 2 /* PWM_CLK_SEL - [9:8] */

849

#define WM5100_PWM2_OVD 0x0020 /* PWM2_OVD */

850

#define WM5100_PWM2_OVD_MASK 0x0020 /* PWM2_OVD */

851

#define WM5100_PWM2_OVD_SHIFT 5 /* PWM2_OVD */

852

#define WM5100_PWM2_OVD_WIDTH 1 /* PWM2_OVD */

853

#define WM5100_PWM1_OVD 0x0010 /* PWM1_OVD */

854

#define WM5100_PWM1_OVD_MASK 0x0010 /* PWM1_OVD */

855

#define WM5100_PWM1_OVD_SHIFT 4 /* PWM1_OVD */

856

#define WM5100_PWM1_OVD_WIDTH 1 /* PWM1_OVD */

857

#define WM5100_PWM2_ENA 0x0002 /* PWM2_ENA */

858

#define WM5100_PWM2_ENA_MASK 0x0002 /* PWM2_ENA */

859

#define WM5100_PWM2_ENA_SHIFT 1 /* PWM2_ENA */

860

#define WM5100_PWM2_ENA_WIDTH 1 /* PWM2_ENA */

861

#define WM5100_PWM1_ENA 0x0001 /* PWM1_ENA */

862

#define WM5100_PWM1_ENA_MASK 0x0001 /* PWM1_ENA */

863

#define WM5100_PWM1_ENA_SHIFT 0 /* PWM1_ENA */

864

#define WM5100_PWM1_ENA_WIDTH 1 /* PWM1_ENA */

865

866

/*

867

* R49 (0x31) - PWM Drive 2

868

*/

869

#define WM5100_PWM1_LVL_MASK 0x03FF /* PWM1_LVL - [9:0] */

870

#define WM5100_PWM1_LVL_SHIFT 0 /* PWM1_LVL - [9:0] */

871

#define WM5100_PWM1_LVL_WIDTH 10 /* PWM1_LVL - [9:0] */

872

873

/*

874

* R50 (0x32) - PWM Drive 3

875

*/

876

#define WM5100_PWM2_LVL_MASK 0x03FF /* PWM2_LVL - [9:0] */

877

#define WM5100_PWM2_LVL_SHIFT 0 /* PWM2_LVL - [9:0] */

878

#define WM5100_PWM2_LVL_WIDTH 10 /* PWM2_LVL - [9:0] */

879

880

/*

881

* R256 (0x100) - Clocking 1

882

*/

883

#define WM5100_CLK_32K_SRC_MASK 0x000F /* CLK_32K_SRC - [3:0] */

884

#define WM5100_CLK_32K_SRC_SHIFT 0 /* CLK_32K_SRC - [3:0] */

885

#define WM5100_CLK_32K_SRC_WIDTH 4 /* CLK_32K_SRC - [3:0] */

886

887

/*

888

* R257 (0x101) - Clocking 3

889

*/

890

#define WM5100_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */

891

#define WM5100_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */

892

#define WM5100_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */

893

#define WM5100_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */

894

#define WM5100_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */

895

#define WM5100_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */

896

#define WM5100_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */

897

#define WM5100_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */

898

#define WM5100_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */

899

#define WM5100_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */

900

901

/*

902

* R258 (0x102) - Clocking 4

903

*/

904

#define WM5100_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */

905

#define WM5100_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */

906

#define WM5100_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */

907

908

/*

909

* R259 (0x103) - Clocking 5

910

*/

911

#define WM5100_SAMPLE_RATE_2_MASK 0x001F /* SAMPLE_RATE_2 - [4:0] */

912

#define WM5100_SAMPLE_RATE_2_SHIFT 0 /* SAMPLE_RATE_2 - [4:0] */

913

#define WM5100_SAMPLE_RATE_2_WIDTH 5 /* SAMPLE_RATE_2 - [4:0] */

914

915

/*

916

* R260 (0x104) - Clocking 6

917

*/

918

#define WM5100_SAMPLE_RATE_3_MASK 0x001F /* SAMPLE_RATE_3 - [4:0] */

919

#define WM5100_SAMPLE_RATE_3_SHIFT 0 /* SAMPLE_RATE_3 - [4:0] */

920

#define WM5100_SAMPLE_RATE_3_WIDTH 5 /* SAMPLE_RATE_3 - [4:0] */

921

922

/*

923

* R263 (0x107) - Clocking 7

924

*/

925

#define WM5100_ASYNC_CLK_FREQ_MASK 0x0700 /* ASYNC_CLK_FREQ - [10:8] */

926

#define WM5100_ASYNC_CLK_FREQ_SHIFT 8 /* ASYNC_CLK_FREQ - [10:8] */

927

#define WM5100_ASYNC_CLK_FREQ_WIDTH 3 /* ASYNC_CLK_FREQ - [10:8] */

928

#define WM5100_ASYNC_CLK_ENA 0x0040 /* ASYNC_CLK_ENA */

929

#define WM5100_ASYNC_CLK_ENA_MASK 0x0040 /* ASYNC_CLK_ENA */

930

#define WM5100_ASYNC_CLK_ENA_SHIFT 6 /* ASYNC_CLK_ENA */

931

#define WM5100_ASYNC_CLK_ENA_WIDTH 1 /* ASYNC_CLK_ENA */

932

#define WM5100_ASYNC_CLK_SRC_MASK 0x000F /* ASYNC_CLK_SRC - [3:0] */

933

#define WM5100_ASYNC_CLK_SRC_SHIFT 0 /* ASYNC_CLK_SRC - [3:0] */

934

#define WM5100_ASYNC_CLK_SRC_WIDTH 4 /* ASYNC_CLK_SRC - [3:0] */

935

936

/*

937

* R264 (0x108) - Clocking 8

938

*/

939

#define WM5100_ASYNC_SAMPLE_RATE_MASK 0x001F /* ASYNC_SAMPLE_RATE - [4:0] */

940

#define WM5100_ASYNC_SAMPLE_RATE_SHIFT 0 /* ASYNC_SAMPLE_RATE - [4:0] */

941

#define WM5100_ASYNC_SAMPLE_RATE_WIDTH 5 /* ASYNC_SAMPLE_RATE - [4:0] */

942

943

/*

944

* R288 (0x120) - ASRC_ENABLE

945

*/

946

#define WM5100_ASRC2L_ENA 0x0008 /* ASRC2L_ENA */

947

#define WM5100_ASRC2L_ENA_MASK 0x0008 /* ASRC2L_ENA */

948

#define WM5100_ASRC2L_ENA_SHIFT 3 /* ASRC2L_ENA */

949

#define WM5100_ASRC2L_ENA_WIDTH 1 /* ASRC2L_ENA */

950

#define WM5100_ASRC2R_ENA 0x0004 /* ASRC2R_ENA */

951

#define WM5100_ASRC2R_ENA_MASK 0x0004 /* ASRC2R_ENA */

952

#define WM5100_ASRC2R_ENA_SHIFT 2 /* ASRC2R_ENA */

953

#define WM5100_ASRC2R_ENA_WIDTH 1 /* ASRC2R_ENA */

954

#define WM5100_ASRC1L_ENA 0x0002 /* ASRC1L_ENA */

955

#define WM5100_ASRC1L_ENA_MASK 0x0002 /* ASRC1L_ENA */

956

#define WM5100_ASRC1L_ENA_SHIFT 1 /* ASRC1L_ENA */

957

#define WM5100_ASRC1L_ENA_WIDTH 1 /* ASRC1L_ENA */

958

#define WM5100_ASRC1R_ENA 0x0001 /* ASRC1R_ENA */

959

#define WM5100_ASRC1R_ENA_MASK 0x0001 /* ASRC1R_ENA */

960

#define WM5100_ASRC1R_ENA_SHIFT 0 /* ASRC1R_ENA */

961

#define WM5100_ASRC1R_ENA_WIDTH 1 /* ASRC1R_ENA */

962

963

/*

964

* R289 (0x121) - ASRC_STATUS

965

*/

966

#define WM5100_ASRC2L_ENA_STS 0x0008 /* ASRC2L_ENA_STS */

967

#define WM5100_ASRC2L_ENA_STS_MASK 0x0008 /* ASRC2L_ENA_STS */

968

#define WM5100_ASRC2L_ENA_STS_SHIFT 3 /* ASRC2L_ENA_STS */

969

#define WM5100_ASRC2L_ENA_STS_WIDTH 1 /* ASRC2L_ENA_STS */

970

#define WM5100_ASRC2R_ENA_STS 0x0004 /* ASRC2R_ENA_STS */

971

#define WM5100_ASRC2R_ENA_STS_MASK 0x0004 /* ASRC2R_ENA_STS */

972

#define WM5100_ASRC2R_ENA_STS_SHIFT 2 /* ASRC2R_ENA_STS */

973

#define WM5100_ASRC2R_ENA_STS_WIDTH 1 /* ASRC2R_ENA_STS */

974

#define WM5100_ASRC1L_ENA_STS 0x0002 /* ASRC1L_ENA_STS */

975

#define WM5100_ASRC1L_ENA_STS_MASK 0x0002 /* ASRC1L_ENA_STS */

976

#define WM5100_ASRC1L_ENA_STS_SHIFT 1 /* ASRC1L_ENA_STS */

977

#define WM5100_ASRC1L_ENA_STS_WIDTH 1 /* ASRC1L_ENA_STS */

978

#define WM5100_ASRC1R_ENA_STS 0x0001 /* ASRC1R_ENA_STS */

979

#define WM5100_ASRC1R_ENA_STS_MASK 0x0001 /* ASRC1R_ENA_STS */

980

#define WM5100_ASRC1R_ENA_STS_SHIFT 0 /* ASRC1R_ENA_STS */

981

#define WM5100_ASRC1R_ENA_STS_WIDTH 1 /* ASRC1R_ENA_STS */

982

983

/*

984

* R290 (0x122) - ASRC_RATE1

985

*/

986

#define WM5100_ASRC_RATE1_MASK 0x0006 /* ASRC_RATE1 - [2:1] */

987

#define WM5100_ASRC_RATE1_SHIFT 1 /* ASRC_RATE1 - [2:1] */

988

#define WM5100_ASRC_RATE1_WIDTH 2 /* ASRC_RATE1 - [2:1] */

989

990

/*

991

* R321 (0x141) - ISRC 1 CTRL 1

992

*/

993

#define WM5100_ISRC1_DFS_ENA 0x2000 /* ISRC1_DFS_ENA */

994

#define WM5100_ISRC1_DFS_ENA_MASK 0x2000 /* ISRC1_DFS_ENA */

995

#define WM5100_ISRC1_DFS_ENA_SHIFT 13 /* ISRC1_DFS_ENA */

996

#define WM5100_ISRC1_DFS_ENA_WIDTH 1 /* ISRC1_DFS_ENA */

997

#define WM5100_ISRC1_CLK_SEL_MASK 0x0300 /* ISRC1_CLK_SEL - [9:8] */

998

#define WM5100_ISRC1_CLK_SEL_SHIFT 8 /* ISRC1_CLK_SEL - [9:8] */

999

#define WM5100_ISRC1_CLK_SEL_WIDTH 2 /* ISRC1_CLK_SEL - [9:8] */

1000

#define WM5100_ISRC1_FSH_MASK 0x000C /* ISRC1_FSH - [3:2] */

1001

#define WM5100_ISRC1_FSH_SHIFT 2 /* ISRC1_FSH - [3:2] */

1002

#define WM5100_ISRC1_FSH_WIDTH 2 /* ISRC1_FSH - [3:2] */

1003

#define WM5100_ISRC1_FSL_MASK 0x0003 /* ISRC1_FSL - [1:0] */

1004

#define WM5100_ISRC1_FSL_SHIFT 0 /* ISRC1_FSL - [1:0] */

1005

#define WM5100_ISRC1_FSL_WIDTH 2 /* ISRC1_FSL - [1:0] */

1006

1007

/*

1008

* R322 (0x142) - ISRC 1 CTRL 2

1009

*/

1010

#define WM5100_ISRC1_INT1_ENA 0x8000 /* ISRC1_INT1_ENA */

1011

#define WM5100_ISRC1_INT1_ENA_MASK 0x8000 /* ISRC1_INT1_ENA */

1012

#define WM5100_ISRC1_INT1_ENA_SHIFT 15 /* ISRC1_INT1_ENA */

1013

#define WM5100_ISRC1_INT1_ENA_WIDTH 1 /* ISRC1_INT1_ENA */

1014

#define WM5100_ISRC1_INT2_ENA 0x4000 /* ISRC1_INT2_ENA */

1015

#define WM5100_ISRC1_INT2_ENA_MASK 0x4000 /* ISRC1_INT2_ENA */

1016

#define WM5100_ISRC1_INT2_ENA_SHIFT 14 /* ISRC1_INT2_ENA */

1017

#define WM5100_ISRC1_INT2_ENA_WIDTH 1 /* ISRC1_INT2_ENA */

1018

#define WM5100_ISRC1_INT3_ENA 0x2000 /* ISRC1_INT3_ENA */

1019

#define WM5100_ISRC1_INT3_ENA_MASK 0x2000 /* ISRC1_INT3_ENA */

1020

#define WM5100_ISRC1_INT3_ENA_SHIFT 13 /* ISRC1_INT3_ENA */

1021

#define WM5100_ISRC1_INT3_ENA_WIDTH 1 /* ISRC1_INT3_ENA */

1022

#define WM5100_ISRC1_INT4_ENA 0x1000 /* ISRC1_INT4_ENA */

1023

#define WM5100_ISRC1_INT4_ENA_MASK 0x1000 /* ISRC1_INT4_ENA */

1024

#define WM5100_ISRC1_INT4_ENA_SHIFT 12 /* ISRC1_INT4_ENA */

1025

#define WM5100_ISRC1_INT4_ENA_WIDTH 1 /* ISRC1_INT4_ENA */

1026

#define WM5100_ISRC1_DEC1_ENA 0x0200 /* ISRC1_DEC1_ENA */

1027

#define WM5100_ISRC1_DEC1_ENA_MASK 0x0200 /* ISRC1_DEC1_ENA */

1028

#define WM5100_ISRC1_DEC1_ENA_SHIFT 9 /* ISRC1_DEC1_ENA */

1029

#define WM5100_ISRC1_DEC1_ENA_WIDTH 1 /* ISRC1_DEC1_ENA */

1030

#define WM5100_ISRC1_DEC2_ENA 0x0100 /* ISRC1_DEC2_ENA */

1031

#define WM5100_ISRC1_DEC2_ENA_MASK 0x0100 /* ISRC1_DEC2_ENA */

1032

#define WM5100_ISRC1_DEC2_ENA_SHIFT 8 /* ISRC1_DEC2_ENA */

1033

#define WM5100_ISRC1_DEC2_ENA_WIDTH 1 /* ISRC1_DEC2_ENA */

1034

#define WM5100_ISRC1_DEC3_ENA 0x0080 /* ISRC1_DEC3_ENA */

1035

#define WM5100_ISRC1_DEC3_ENA_MASK 0x0080 /* ISRC1_DEC3_ENA */

1036

#define WM5100_ISRC1_DEC3_ENA_SHIFT 7 /* ISRC1_DEC3_ENA */

1037

#define WM5100_ISRC1_DEC3_ENA_WIDTH 1 /* ISRC1_DEC3_ENA */

1038

#define WM5100_ISRC1_DEC4_ENA 0x0040 /* ISRC1_DEC4_ENA */

1039

#define WM5100_ISRC1_DEC4_ENA_MASK 0x0040 /* ISRC1_DEC4_ENA */

1040

#define WM5100_ISRC1_DEC4_ENA_SHIFT 6 /* ISRC1_DEC4_ENA */

1041

#define WM5100_ISRC1_DEC4_ENA_WIDTH 1 /* ISRC1_DEC4_ENA */

1042

#define WM5100_ISRC1_NOTCH_ENA 0x0001 /* ISRC1_NOTCH_ENA */

1043

#define WM5100_ISRC1_NOTCH_ENA_MASK 0x0001 /* ISRC1_NOTCH_ENA */

1044

#define WM5100_ISRC1_NOTCH_ENA_SHIFT 0 /* ISRC1_NOTCH_ENA */

1045

#define WM5100_ISRC1_NOTCH_ENA_WIDTH 1 /* ISRC1_NOTCH_ENA */

1046

1047

/*

1048

* R323 (0x143) - ISRC 2 CTRL1

1049

*/

1050

#define WM5100_ISRC2_DFS_ENA 0x2000 /* ISRC2_DFS_ENA */

1051

#define WM5100_ISRC2_DFS_ENA_MASK 0x2000 /* ISRC2_DFS_ENA */

1052

#define WM5100_ISRC2_DFS_ENA_SHIFT 13 /* ISRC2_DFS_ENA */

1053

#define WM5100_ISRC2_DFS_ENA_WIDTH 1 /* ISRC2_DFS_ENA */

1054

#define WM5100_ISRC2_CLK_SEL_MASK 0x0300 /* ISRC2_CLK_SEL - [9:8] */

1055

#define WM5100_ISRC2_CLK_SEL_SHIFT 8 /* ISRC2_CLK_SEL - [9:8] */

1056

#define WM5100_ISRC2_CLK_SEL_WIDTH 2 /* ISRC2_CLK_SEL - [9:8] */

1057

#define WM5100_ISRC2_FSH_MASK 0x000C /* ISRC2_FSH - [3:2] */

1058

#define WM5100_ISRC2_FSH_SHIFT 2 /* ISRC2_FSH - [3:2] */

1059

#define WM5100_ISRC2_FSH_WIDTH 2 /* ISRC2_FSH - [3:2] */

1060

#define WM5100_ISRC2_FSL_MASK 0x0003 /* ISRC2_FSL - [1:0] */

1061

#define WM5100_ISRC2_FSL_SHIFT 0 /* ISRC2_FSL - [1:0] */

1062

#define WM5100_ISRC2_FSL_WIDTH 2 /* ISRC2_FSL - [1:0] */

1063

1064

/*

1065

* R324 (0x144) - ISRC 2 CTRL 2

1066

*/

1067

#define WM5100_ISRC2_INT1_ENA 0x8000 /* ISRC2_INT1_ENA */

1068

#define WM5100_ISRC2_INT1_ENA_MASK 0x8000 /* ISRC2_INT1_ENA */

1069

#define WM5100_ISRC2_INT1_ENA_SHIFT 15 /* ISRC2_INT1_ENA */

1070

#define WM5100_ISRC2_INT1_ENA_WIDTH 1 /* ISRC2_INT1_ENA */

1071

#define WM5100_ISRC2_INT2_ENA 0x4000 /* ISRC2_INT2_ENA */

1072

#define WM5100_ISRC2_INT2_ENA_MASK 0x4000 /* ISRC2_INT2_ENA */

1073

#define WM5100_ISRC2_INT2_ENA_SHIFT 14 /* ISRC2_INT2_ENA */

1074

#define WM5100_ISRC2_INT2_ENA_WIDTH 1 /* ISRC2_INT2_ENA */

1075

#define WM5100_ISRC2_INT3_ENA 0x2000 /* ISRC2_INT3_ENA */

1076

#define WM5100_ISRC2_INT3_ENA_MASK 0x2000 /* ISRC2_INT3_ENA */

1077

#define WM5100_ISRC2_INT3_ENA_SHIFT 13 /* ISRC2_INT3_ENA */

1078

#define WM5100_ISRC2_INT3_ENA_WIDTH 1 /* ISRC2_INT3_ENA */

1079

#define WM5100_ISRC2_INT4_ENA 0x1000 /* ISRC2_INT4_ENA */

1080

#define WM5100_ISRC2_INT4_ENA_MASK 0x1000 /* ISRC2_INT4_ENA */

1081

#define WM5100_ISRC2_INT4_ENA_SHIFT 12 /* ISRC2_INT4_ENA */

1082

#define WM5100_ISRC2_INT4_ENA_WIDTH 1 /* ISRC2_INT4_ENA */

1083

#define WM5100_ISRC2_DEC1_ENA 0x0200 /* ISRC2_DEC1_ENA */

1084

#define WM5100_ISRC2_DEC1_ENA_MASK 0x0200 /* ISRC2_DEC1_ENA */

1085

#define WM5100_ISRC2_DEC1_ENA_SHIFT 9 /* ISRC2_DEC1_ENA */

1086

#define WM5100_ISRC2_DEC1_ENA_WIDTH 1 /* ISRC2_DEC1_ENA */

1087

#define WM5100_ISRC2_DEC2_ENA 0x0100 /* ISRC2_DEC2_ENA */

1088

#define WM5100_ISRC2_DEC2_ENA_MASK 0x0100 /* ISRC2_DEC2_ENA */

1089

#define WM5100_ISRC2_DEC2_ENA_SHIFT 8 /* ISRC2_DEC2_ENA */

1090

#define WM5100_ISRC2_DEC2_ENA_WIDTH 1 /* ISRC2_DEC2_ENA */

1091

#define WM5100_ISRC2_DEC3_ENA 0x0080 /* ISRC2_DEC3_ENA */

1092

#define WM5100_ISRC2_DEC3_ENA_MASK 0x0080 /* ISRC2_DEC3_ENA */

1093

#define WM5100_ISRC2_DEC3_ENA_SHIFT 7 /* ISRC2_DEC3_ENA */

1094

#define WM5100_ISRC2_DEC3_ENA_WIDTH 1 /* ISRC2_DEC3_ENA */

1095

#define WM5100_ISRC2_DEC4_ENA 0x0040 /* ISRC2_DEC4_ENA */

1096

#define WM5100_ISRC2_DEC4_ENA_MASK 0x0040 /* ISRC2_DEC4_ENA */

1097

#define WM5100_ISRC2_DEC4_ENA_SHIFT 6 /* ISRC2_DEC4_ENA */

1098

#define WM5100_ISRC2_DEC4_ENA_WIDTH 1 /* ISRC2_DEC4_ENA */

1099

#define WM5100_ISRC2_NOTCH_ENA 0x0001 /* ISRC2_NOTCH_ENA */

1100

#define WM5100_ISRC2_NOTCH_ENA_MASK 0x0001 /* ISRC2_NOTCH_ENA */

1101

#define WM5100_ISRC2_NOTCH_ENA_SHIFT 0 /* ISRC2_NOTCH_ENA */

1102

#define WM5100_ISRC2_NOTCH_ENA_WIDTH 1 /* ISRC2_NOTCH_ENA */

1103

1104

/*

1105

* R386 (0x182) - FLL1 Control 1

1106

*/

1107

#define WM5100_FLL1_ENA 0x0001 /* FLL1_ENA */

1108

#define WM5100_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */

1109

#define WM5100_FLL1_ENA_SHIFT 0 /* FLL1_ENA */

1110

#define WM5100_FLL1_ENA_WIDTH 1 /* FLL1_ENA */

1111

1112

/*

1113

* R387 (0x183) - FLL1 Control 2

1114

*/

1115

#define WM5100_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */

1116

#define WM5100_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */

1117

#define WM5100_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */

1118

#define WM5100_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */

1119

#define WM5100_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */

1120

#define WM5100_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */

1121

1122

/*

1123

* R388 (0x184) - FLL1 Control 3

1124

*/

1125

#define WM5100_FLL1_THETA_MASK 0xFFFF /* FLL1_THETA - [15:0] */

1126

#define WM5100_FLL1_THETA_SHIFT 0 /* FLL1_THETA - [15:0] */

1127

#define WM5100_FLL1_THETA_WIDTH 16 /* FLL1_THETA - [15:0] */

1128

1129

/*

1130

* R390 (0x186) - FLL1 Control 5

1131

*/

1132

#define WM5100_FLL1_N_MASK 0x03FF /* FLL1_N - [9:0] */

1133

#define WM5100_FLL1_N_SHIFT 0 /* FLL1_N - [9:0] */

1134

#define WM5100_FLL1_N_WIDTH 10 /* FLL1_N - [9:0] */

1135

1136

/*

1137

* R391 (0x187) - FLL1 Control 6

1138

*/

1139

#define WM5100_FLL1_REFCLK_DIV_MASK 0x00C0 /* FLL1_REFCLK_DIV - [7:6] */

1140

#define WM5100_FLL1_REFCLK_DIV_SHIFT 6 /* FLL1_REFCLK_DIV - [7:6] */

1141

#define WM5100_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [7:6] */

1142

#define WM5100_FLL1_REFCLK_SRC_MASK 0x000F /* FLL1_REFCLK_SRC - [3:0] */

1143

#define WM5100_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [3:0] */

1144

#define WM5100_FLL1_REFCLK_SRC_WIDTH 4 /* FLL1_REFCLK_SRC - [3:0] */

1145

1146

/*

1147

* R392 (0x188) - FLL1 EFS 1

1148

*/

1149

#define WM5100_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */

1150

#define WM5100_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */

1151

#define WM5100_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */

1152

1153

/*

1154

* R418 (0x1A2) - FLL2 Control 1

1155

*/

1156

#define WM5100_FLL2_ENA 0x0001 /* FLL2_ENA */

1157

#define WM5100_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */

1158

#define WM5100_FLL2_ENA_SHIFT 0 /* FLL2_ENA */

1159

#define WM5100_FLL2_ENA_WIDTH 1 /* FLL2_ENA */

1160

1161

/*

1162

* R419 (0x1A3) - FLL2 Control 2

1163

*/

1164

#define WM5100_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */

1165

#define WM5100_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */

1166

#define WM5100_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */

1167

#define WM5100_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */

1168

#define WM5100_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */

1169

#define WM5100_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */

1170

1171

/*

1172

* R420 (0x1A4) - FLL2 Control 3

1173

*/

1174

#define WM5100_FLL2_THETA_MASK 0xFFFF /* FLL2_THETA - [15:0] */

1175

#define WM5100_FLL2_THETA_SHIFT 0 /* FLL2_THETA - [15:0] */

1176

#define WM5100_FLL2_THETA_WIDTH 16 /* FLL2_THETA - [15:0] */

1177

1178

/*

1179

* R422 (0x1A6) - FLL2 Control 5

1180

*/

1181

#define WM5100_FLL2_N_MASK 0x03FF /* FLL2_N - [9:0] */

1182

#define WM5100_FLL2_N_SHIFT 0 /* FLL2_N - [9:0] */

1183

#define WM5100_FLL2_N_WIDTH 10 /* FLL2_N - [9:0] */

1184

1185

/*

1186

* R423 (0x1A7) - FLL2 Control 6

1187

*/

1188

#define WM5100_FLL2_REFCLK_DIV_MASK 0x00C0 /* FLL2_REFCLK_DIV - [7:6] */

1189

#define WM5100_FLL2_REFCLK_DIV_SHIFT 6 /* FLL2_REFCLK_DIV - [7:6] */

1190

#define WM5100_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [7:6] */

1191

#define WM5100_FLL2_REFCLK_SRC_MASK 0x000F /* FLL2_REFCLK_SRC - [3:0] */

1192

#define WM5100_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [3:0] */

1193

#define WM5100_FLL2_REFCLK_SRC_WIDTH 4 /* FLL2_REFCLK_SRC - [3:0] */

1194

1195

/*

1196

* R424 (0x1A8) - FLL2 EFS 1

1197

*/

1198

#define WM5100_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */

1199

#define WM5100_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */

1200

#define WM5100_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */

1201

1202

/*

1203

* R512 (0x200) - Mic Charge Pump 1

1204

*/

1205

#define WM5100_CP2_BYPASS 0x0020 /* CP2_BYPASS */

1206

#define WM5100_CP2_BYPASS_MASK 0x0020 /* CP2_BYPASS */

1207

#define WM5100_CP2_BYPASS_SHIFT 5 /* CP2_BYPASS */

1208

#define WM5100_CP2_BYPASS_WIDTH 1 /* CP2_BYPASS */

1209

#define WM5100_CP2_ENA 0x0001 /* CP2_ENA */

1210

#define WM5100_CP2_ENA_MASK 0x0001 /* CP2_ENA */

1211

#define WM5100_CP2_ENA_SHIFT 0 /* CP2_ENA */

1212

#define WM5100_CP2_ENA_WIDTH 1 /* CP2_ENA */

1213

1214

/*

1215

* R513 (0x201) - Mic Charge Pump 2

1216

*/

1217

#define WM5100_LDO2_VSEL_MASK 0xF800 /* LDO2_VSEL - [15:11] */

1218

#define WM5100_LDO2_VSEL_SHIFT 11 /* LDO2_VSEL - [15:11] */

1219

#define WM5100_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [15:11] */

1220

1221

/*

1222

* R514 (0x202) - HP Charge Pump 1

1223

*/

1224

#define WM5100_CP1_ENA 0x0001 /* CP1_ENA */

1225

#define WM5100_CP1_ENA_MASK 0x0001 /* CP1_ENA */

1226

#define WM5100_CP1_ENA_SHIFT 0 /* CP1_ENA */

1227

#define WM5100_CP1_ENA_WIDTH 1 /* CP1_ENA */

1228

1229

/*

1230

* R529 (0x211) - LDO1 Control

1231

*/

1232

#define WM5100_LDO1_BYPASS 0x0002 /* LDO1_BYPASS */

1233

#define WM5100_LDO1_BYPASS_MASK 0x0002 /* LDO1_BYPASS */

1234

#define WM5100_LDO1_BYPASS_SHIFT 1 /* LDO1_BYPASS */

1235

#define WM5100_LDO1_BYPASS_WIDTH 1 /* LDO1_BYPASS */

1236

1237

/*

1238

* R533 (0x215) - Mic Bias Ctrl 1

1239

*/

1240

#define WM5100_MICB1_DISCH 0x0040 /* MICB1_DISCH */

1241

#define WM5100_MICB1_DISCH_MASK 0x0040 /* MICB1_DISCH */

1242

#define WM5100_MICB1_DISCH_SHIFT 6 /* MICB1_DISCH */

1243

#define WM5100_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */

1244

#define WM5100_MICB1_RATE 0x0020 /* MICB1_RATE */

1245

#define WM5100_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */

1246

#define WM5100_MICB1_RATE_SHIFT 5 /* MICB1_RATE */

1247

#define WM5100_MICB1_RATE_WIDTH 1 /* MICB1_RATE */

1248

#define WM5100_MICB1_LVL_MASK 0x001C /* MICB1_LVL - [4:2] */

1249

#define WM5100_MICB1_LVL_SHIFT 2 /* MICB1_LVL - [4:2] */

1250

#define WM5100_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [4:2] */

1251

#define WM5100_MICB1_BYPASS 0x0002 /* MICB1_BYPASS */

1252

#define WM5100_MICB1_BYPASS_MASK 0x0002 /* MICB1_BYPASS */

1253

#define WM5100_MICB1_BYPASS_SHIFT 1 /* MICB1_BYPASS */

1254

#define WM5100_MICB1_BYPASS_WIDTH 1 /* MICB1_BYPASS */

1255

#define WM5100_MICB1_ENA 0x0001 /* MICB1_ENA */

1256

#define WM5100_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */

1257

#define WM5100_MICB1_ENA_SHIFT 0 /* MICB1_ENA */

1258

#define WM5100_MICB1_ENA_WIDTH 1 /* MICB1_ENA */

1259

1260

/*

1261

* R534 (0x216) - Mic Bias Ctrl 2

1262

*/

1263

#define WM5100_MICB2_DISCH 0x0040 /* MICB2_DISCH */

1264

#define WM5100_MICB2_DISCH_MASK 0x0040 /* MICB2_DISCH */

1265

#define WM5100_MICB2_DISCH_SHIFT 6 /* MICB2_DISCH */

1266

#define WM5100_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */

1267

#define WM5100_MICB2_RATE 0x0020 /* MICB2_RATE */

1268

#define WM5100_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */

1269

#define WM5100_MICB2_RATE_SHIFT 5 /* MICB2_RATE */

1270

#define WM5100_MICB2_RATE_WIDTH 1 /* MICB2_RATE */

1271

#define WM5100_MICB2_LVL_MASK 0x001C /* MICB2_LVL - [4:2] */

1272

#define WM5100_MICB2_LVL_SHIFT 2 /* MICB2_LVL - [4:2] */

1273

#define WM5100_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [4:2] */

1274

#define WM5100_MICB2_BYPASS 0x0002 /* MICB2_BYPASS */

1275

#define WM5100_MICB2_BYPASS_MASK 0x0002 /* MICB2_BYPASS */

1276

#define WM5100_MICB2_BYPASS_SHIFT 1 /* MICB2_BYPASS */

1277

#define WM5100_MICB2_BYPASS_WIDTH 1 /* MICB2_BYPASS */

1278

#define WM5100_MICB2_ENA 0x0001 /* MICB2_ENA */

1279

#define WM5100_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */

1280

#define WM5100_MICB2_ENA_SHIFT 0 /* MICB2_ENA */

1281

#define WM5100_MICB2_ENA_WIDTH 1 /* MICB2_ENA */

1282

1283

/*

1284

* R535 (0x217) - Mic Bias Ctrl 3

1285

*/

1286

#define WM5100_MICB3_DISCH 0x0040 /* MICB3_DISCH */

1287

#define WM5100_MICB3_DISCH_MASK 0x0040 /* MICB3_DISCH */

1288

#define WM5100_MICB3_DISCH_SHIFT 6 /* MICB3_DISCH */

1289

#define WM5100_MICB3_DISCH_WIDTH 1 /* MICB3_DISCH */

1290

#define WM5100_MICB3_RATE 0x0020 /* MICB3_RATE */

1291

#define WM5100_MICB3_RATE_MASK 0x0020 /* MICB3_RATE */

1292

#define WM5100_MICB3_RATE_SHIFT 5 /* MICB3_RATE */

1293

#define WM5100_MICB3_RATE_WIDTH 1 /* MICB3_RATE */

1294

#define WM5100_MICB3_LVL_MASK 0x001C /* MICB3_LVL - [4:2] */

1295

#define WM5100_MICB3_LVL_SHIFT 2 /* MICB3_LVL - [4:2] */

1296

#define WM5100_MICB3_LVL_WIDTH 3 /* MICB3_LVL - [4:2] */

1297

#define WM5100_MICB3_BYPASS 0x0002 /* MICB3_BYPASS */

1298

#define WM5100_MICB3_BYPASS_MASK 0x0002 /* MICB3_BYPASS */

1299

#define WM5100_MICB3_BYPASS_SHIFT 1 /* MICB3_BYPASS */

1300

#define WM5100_MICB3_BYPASS_WIDTH 1 /* MICB3_BYPASS */

1301

#define WM5100_MICB3_ENA 0x0001 /* MICB3_ENA */

1302

#define WM5100_MICB3_ENA_MASK 0x0001 /* MICB3_ENA */

1303

#define WM5100_MICB3_ENA_SHIFT 0 /* MICB3_ENA */

1304

#define WM5100_MICB3_ENA_WIDTH 1 /* MICB3_ENA */

1305

1306

/*

1307

* R640 (0x280) - Accessory Detect Mode 1

1308

*/

1309

#define WM5100_ACCDET_BIAS_SRC_MASK 0xC000 /* ACCDET_BIAS_SRC - [15:14] */

1310

#define WM5100_ACCDET_BIAS_SRC_SHIFT 14 /* ACCDET_BIAS_SRC - [15:14] */

1311

#define WM5100_ACCDET_BIAS_SRC_WIDTH 2 /* ACCDET_BIAS_SRC - [15:14] */

1312

#define WM5100_ACCDET_SRC 0x2000 /* ACCDET_SRC */

1313

#define WM5100_ACCDET_SRC_MASK 0x2000 /* ACCDET_SRC */

1314

#define WM5100_ACCDET_SRC_SHIFT 13 /* ACCDET_SRC */

1315

#define WM5100_ACCDET_SRC_WIDTH 1 /* ACCDET_SRC */

1316

#define WM5100_ACCDET_MODE_MASK 0x0003 /* ACCDET_MODE - [1:0] */

1317

#define WM5100_ACCDET_MODE_SHIFT 0 /* ACCDET_MODE - [1:0] */

1318

#define WM5100_ACCDET_MODE_WIDTH 2 /* ACCDET_MODE - [1:0] */

1319

1320

/*

1321

* R648 (0x288) - Headphone Detect 1

1322

*/

1323

#define WM5100_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */

1324

#define WM5100_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */

1325

#define WM5100_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */

1326

#define WM5100_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */

1327

#define WM5100_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */

1328

#define WM5100_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */

1329

#define WM5100_HP_STEP_SIZE 0x0002 /* HP_STEP_SIZE */

1330

#define WM5100_HP_STEP_SIZE_MASK 0x0002 /* HP_STEP_SIZE */

1331

#define WM5100_HP_STEP_SIZE_SHIFT 1 /* HP_STEP_SIZE */

1332

#define WM5100_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */

1333

#define WM5100_HP_POLL 0x0001 /* HP_POLL */

1334

#define WM5100_HP_POLL_MASK 0x0001 /* HP_POLL */

1335

#define WM5100_HP_POLL_SHIFT 0 /* HP_POLL */

1336

#define WM5100_HP_POLL_WIDTH 1 /* HP_POLL */

1337

1338

/*

1339

* R649 (0x289) - Headphone Detect 2

1340

*/

1341

#define WM5100_HP_DONE 0x0080 /* HP_DONE */

1342

#define WM5100_HP_DONE_MASK 0x0080 /* HP_DONE */

1343

#define WM5100_HP_DONE_SHIFT 7 /* HP_DONE */

1344

#define WM5100_HP_DONE_WIDTH 1 /* HP_DONE */

1345

#define WM5100_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */

1346

#define WM5100_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */

1347

#define WM5100_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */

1348

1349

/*

1350

* R656 (0x290) - Mic Detect 1

1351

*/

1352

#define WM5100_ACCDET_BIAS_STARTTIME_MASK 0xF000 /* ACCDET_BIAS_STARTTIME - [15:12] */

1353

#define WM5100_ACCDET_BIAS_STARTTIME_SHIFT 12 /* ACCDET_BIAS_STARTTIME - [15:12] */

1354

#define WM5100_ACCDET_BIAS_STARTTIME_WIDTH 4 /* ACCDET_BIAS_STARTTIME - [15:12] */

1355

#define WM5100_ACCDET_RATE_MASK 0x0F00 /* ACCDET_RATE - [11:8] */

1356

#define WM5100_ACCDET_RATE_SHIFT 8 /* ACCDET_RATE - [11:8] */

1357

#define WM5100_ACCDET_RATE_WIDTH 4 /* ACCDET_RATE - [11:8] */

1358

#define WM5100_ACCDET_DBTIME 0x0002 /* ACCDET_DBTIME */

1359

#define WM5100_ACCDET_DBTIME_MASK 0x0002 /* ACCDET_DBTIME */

1360

#define WM5100_ACCDET_DBTIME_SHIFT 1 /* ACCDET_DBTIME */

1361

#define WM5100_ACCDET_DBTIME_WIDTH 1 /* ACCDET_DBTIME */

1362

#define WM5100_ACCDET_ENA 0x0001 /* ACCDET_ENA */

1363

#define WM5100_ACCDET_ENA_MASK 0x0001 /* ACCDET_ENA */

1364

#define WM5100_ACCDET_ENA_SHIFT 0 /* ACCDET_ENA */

1365

#define WM5100_ACCDET_ENA_WIDTH 1 /* ACCDET_ENA */

1366

1367

/*

1368

* R657 (0x291) - Mic Detect 2

1369

*/

1370

#define WM5100_ACCDET_LVL_SEL_MASK 0x00FF /* ACCDET_LVL_SEL - [7:0] */

1371

#define WM5100_ACCDET_LVL_SEL_SHIFT 0 /* ACCDET_LVL_SEL - [7:0] */

1372

#define WM5100_ACCDET_LVL_SEL_WIDTH 8 /* ACCDET_LVL_SEL - [7:0] */

1373

1374

/*

1375

* R658 (0x292) - Mic Detect 3

1376

*/

1377

#define WM5100_ACCDET_LVL_MASK 0x07FC /* ACCDET_LVL - [10:2] */

1378

#define WM5100_ACCDET_LVL_SHIFT 2 /* ACCDET_LVL - [10:2] */

1379

#define WM5100_ACCDET_LVL_WIDTH 9 /* ACCDET_LVL - [10:2] */

1380

#define WM5100_ACCDET_VALID 0x0002 /* ACCDET_VALID */

1381

#define WM5100_ACCDET_VALID_MASK 0x0002 /* ACCDET_VALID */

1382

#define WM5100_ACCDET_VALID_SHIFT 1 /* ACCDET_VALID */

1383

#define WM5100_ACCDET_VALID_WIDTH 1 /* ACCDET_VALID */

1384

#define WM5100_ACCDET_STS 0x0001 /* ACCDET_STS */

1385

#define WM5100_ACCDET_STS_MASK 0x0001 /* ACCDET_STS */

1386

#define WM5100_ACCDET_STS_SHIFT 0 /* ACCDET_STS */

1387

#define WM5100_ACCDET_STS_WIDTH 1 /* ACCDET_STS */

1388

1389

/*

1390

* R769 (0x301) - Input Enables

1391

*/

1392

#define WM5100_IN4L_ENA 0x0080 /* IN4L_ENA */

1393

#define WM5100_IN4L_ENA_MASK 0x0080 /* IN4L_ENA */

1394

#define WM5100_IN4L_ENA_SHIFT 7 /* IN4L_ENA */

1395

#define WM5100_IN4L_ENA_WIDTH 1 /* IN4L_ENA */

1396

#define WM5100_IN4R_ENA 0x0040 /* IN4R_ENA */

1397

#define WM5100_IN4R_ENA_MASK 0x0040 /* IN4R_ENA */

1398

#define WM5100_IN4R_ENA_SHIFT 6 /* IN4R_ENA */

1399

#define WM5100_IN4R_ENA_WIDTH 1 /* IN4R_ENA */

1400

#define WM5100_IN3L_ENA 0x0020 /* IN3L_ENA */

1401

#define WM5100_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */

1402

#define WM5100_IN3L_ENA_SHIFT 5 /* IN3L_ENA */

1403

#define WM5100_IN3L_ENA_WIDTH 1 /* IN3L_ENA */

1404

#define WM5100_IN3R_ENA 0x0010 /* IN3R_ENA */

1405

#define WM5100_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */

1406

#define WM5100_IN3R_ENA_SHIFT 4 /* IN3R_ENA */

1407

#define WM5100_IN3R_ENA_WIDTH 1 /* IN3R_ENA */

1408

#define WM5100_IN2L_ENA 0x0008 /* IN2L_ENA */

1409

#define WM5100_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */

1410

#define WM5100_IN2L_ENA_SHIFT 3 /* IN2L_ENA */

1411

#define WM5100_IN2L_ENA_WIDTH 1 /* IN2L_ENA */

1412

#define WM5100_IN2R_ENA 0x0004 /* IN2R_ENA */

1413

#define WM5100_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */

1414

#define WM5100_IN2R_ENA_SHIFT 2 /* IN2R_ENA */

1415

#define WM5100_IN2R_ENA_WIDTH 1 /* IN2R_ENA */

1416

#define WM5100_IN1L_ENA 0x0002 /* IN1L_ENA */

1417

#define WM5100_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */

1418

#define WM5100_IN1L_ENA_SHIFT 1 /* IN1L_ENA */

1419

#define WM5100_IN1L_ENA_WIDTH 1 /* IN1L_ENA */

1420

#define WM5100_IN1R_ENA 0x0001 /* IN1R_ENA */

1421

#define WM5100_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */

1422

#define WM5100_IN1R_ENA_SHIFT 0 /* IN1R_ENA */

1423

#define WM5100_IN1R_ENA_WIDTH 1 /* IN1R_ENA */

1424

1425

/*

1426

* R770 (0x302) - Input Enables Status

1427

*/

1428

#define WM5100_IN4L_ENA_STS 0x0080 /* IN4L_ENA_STS */

1429

#define WM5100_IN4L_ENA_STS_MASK 0x0080 /* IN4L_ENA_STS */

1430

#define WM5100_IN4L_ENA_STS_SHIFT 7 /* IN4L_ENA_STS */

1431

#define WM5100_IN4L_ENA_STS_WIDTH 1 /* IN4L_ENA_STS */

1432

#define WM5100_IN4R_ENA_STS 0x0040 /* IN4R_ENA_STS */

1433

#define WM5100_IN4R_ENA_STS_MASK 0x0040 /* IN4R_ENA_STS */

1434

#define WM5100_IN4R_ENA_STS_SHIFT 6 /* IN4R_ENA_STS */

1435

#define WM5100_IN4R_ENA_STS_WIDTH 1 /* IN4R_ENA_STS */

1436

#define WM5100_IN3L_ENA_STS 0x0020 /* IN3L_ENA_STS */

1437

#define WM5100_IN3L_ENA_STS_MASK 0x0020 /* IN3L_ENA_STS */

1438

#define WM5100_IN3L_ENA_STS_SHIFT 5 /* IN3L_ENA_STS */

1439

#define WM5100_IN3L_ENA_STS_WIDTH 1 /* IN3L_ENA_STS */

1440

#define WM5100_IN3R_ENA_STS 0x0010 /* IN3R_ENA_STS */

1441

#define WM5100_IN3R_ENA_STS_MASK 0x0010 /* IN3R_ENA_STS */

1442

#define WM5100_IN3R_ENA_STS_SHIFT 4 /* IN3R_ENA_STS */

1443

#define WM5100_IN3R_ENA_STS_WIDTH 1 /* IN3R_ENA_STS */

1444

#define WM5100_IN2L_ENA_STS 0x0008 /* IN2L_ENA_STS */

1445

#define WM5100_IN2L_ENA_STS_MASK 0x0008 /* IN2L_ENA_STS */

1446

#define WM5100_IN2L_ENA_STS_SHIFT 3 /* IN2L_ENA_STS */

1447

#define WM5100_IN2L_ENA_STS_WIDTH 1 /* IN2L_ENA_STS */

1448

#define WM5100_IN2R_ENA_STS 0x0004 /* IN2R_ENA_STS */

1449

#define WM5100_IN2R_ENA_STS_MASK 0x0004 /* IN2R_ENA_STS */

1450

#define WM5100_IN2R_ENA_STS_SHIFT 2 /* IN2R_ENA_STS */

1451

#define WM5100_IN2R_ENA_STS_WIDTH 1 /* IN2R_ENA_STS */

1452

#define WM5100_IN1L_ENA_STS 0x0002 /* IN1L_ENA_STS */

1453

#define WM5100_IN1L_ENA_STS_MASK 0x0002 /* IN1L_ENA_STS */

1454

#define WM5100_IN1L_ENA_STS_SHIFT 1 /* IN1L_ENA_STS */

1455

#define WM5100_IN1L_ENA_STS_WIDTH 1 /* IN1L_ENA_STS */

1456

#define WM5100_IN1R_ENA_STS 0x0001 /* IN1R_ENA_STS */

1457

#define WM5100_IN1R_ENA_STS_MASK 0x0001 /* IN1R_ENA_STS */

1458

#define WM5100_IN1R_ENA_STS_SHIFT 0 /* IN1R_ENA_STS */

1459

#define WM5100_IN1R_ENA_STS_WIDTH 1 /* IN1R_ENA_STS */

1460

1461

/*

1462

* R784 (0x310) - IN1L Control

1463

*/

1464

#define WM5100_IN_RATE_MASK 0xC000 /* IN_RATE - [15:14] */

1465

#define WM5100_IN_RATE_SHIFT 14 /* IN_RATE - [15:14] */

1466

#define WM5100_IN_RATE_WIDTH 2 /* IN_RATE - [15:14] */

1467

#define WM5100_IN1_OSR 0x2000 /* IN1_OSR */

1468

#define WM5100_IN1_OSR_MASK 0x2000 /* IN1_OSR */

1469

#define WM5100_IN1_OSR_SHIFT 13 /* IN1_OSR */

1470

#define WM5100_IN1_OSR_WIDTH 1 /* IN1_OSR */

1471

#define WM5100_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */

1472

#define WM5100_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */

1473

#define WM5100_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */

1474

#define WM5100_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */

1475

#define WM5100_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */

1476

#define WM5100_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */

1477

#define WM5100_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */

1478

#define WM5100_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */

1479

#define WM5100_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */

1480

1481

/*

1482

* R785 (0x311) - IN1R Control

1483

*/

1484

#define WM5100_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */

1485

#define WM5100_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */

1486

#define WM5100_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */

1487

1488

/*

1489

* R786 (0x312) - IN2L Control

1490

*/

1491

#define WM5100_IN2_OSR 0x2000 /* IN2_OSR */

1492

#define WM5100_IN2_OSR_MASK 0x2000 /* IN2_OSR */

1493

#define WM5100_IN2_OSR_SHIFT 13 /* IN2_OSR */

1494

#define WM5100_IN2_OSR_WIDTH 1 /* IN2_OSR */

1495

#define WM5100_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */

1496

#define WM5100_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */

1497

#define WM5100_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */

1498

#define WM5100_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */

1499

#define WM5100_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */

1500

#define WM5100_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */

1501

#define WM5100_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */

1502

#define WM5100_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */

1503

#define WM5100_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */

1504

1505

/*

1506

* R787 (0x313) - IN2R Control

1507

*/

1508

#define WM5100_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */

1509

#define WM5100_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */

1510

#define WM5100_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */

1511

1512

/*

1513

* R788 (0x314) - IN3L Control

1514

*/

1515

#define WM5100_IN3_OSR 0x2000 /* IN3_OSR */

1516

#define WM5100_IN3_OSR_MASK 0x2000 /* IN3_OSR */

1517

#define WM5100_IN3_OSR_SHIFT 13 /* IN3_OSR */

1518

#define WM5100_IN3_OSR_WIDTH 1 /* IN3_OSR */

1519

#define WM5100_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */

1520

#define WM5100_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */

1521

#define WM5100_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */

1522

#define WM5100_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */

1523

#define WM5100_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */

1524

#define WM5100_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */

1525

#define WM5100_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */

1526

#define WM5100_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */

1527

#define WM5100_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */

1528

1529

/*

1530

* R789 (0x315) - IN3R Control

1531

*/

1532

#define WM5100_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */

1533

#define WM5100_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */

1534

#define WM5100_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */

1535

1536

/*

1537

* R790 (0x316) - IN4L Control

1538

*/

1539

#define WM5100_IN4_OSR 0x2000 /* IN4_OSR */

1540

#define WM5100_IN4_OSR_MASK 0x2000 /* IN4_OSR */

1541

#define WM5100_IN4_OSR_SHIFT 13 /* IN4_OSR */

1542

#define WM5100_IN4_OSR_WIDTH 1 /* IN4_OSR */

1543

#define WM5100_IN4_DMIC_SUP_MASK 0x1800 /* IN4_DMIC_SUP - [12:11] */

1544

#define WM5100_IN4_DMIC_SUP_SHIFT 11 /* IN4_DMIC_SUP - [12:11] */

1545

#define WM5100_IN4_DMIC_SUP_WIDTH 2 /* IN4_DMIC_SUP - [12:11] */

1546

#define WM5100_IN4_MODE_MASK 0x0600 /* IN4_MODE - [10:9] */

1547

#define WM5100_IN4_MODE_SHIFT 9 /* IN4_MODE - [10:9] */

1548

#define WM5100_IN4_MODE_WIDTH 2 /* IN4_MODE - [10:9] */

1549

#define WM5100_IN4L_PGA_VOL_MASK 0x00FE /* IN4L_PGA_VOL - [7:1] */

1550

#define WM5100_IN4L_PGA_VOL_SHIFT 1 /* IN4L_PGA_VOL - [7:1] */

1551

#define WM5100_IN4L_PGA_VOL_WIDTH 7 /* IN4L_PGA_VOL - [7:1] */

1552

1553

/*

1554

* R791 (0x317) - IN4R Control

1555

*/

1556

#define WM5100_IN4R_PGA_VOL_MASK 0x00FE /* IN4R_PGA_VOL - [7:1] */

1557

#define WM5100_IN4R_PGA_VOL_SHIFT 1 /* IN4R_PGA_VOL - [7:1] */

1558

#define WM5100_IN4R_PGA_VOL_WIDTH 7 /* IN4R_PGA_VOL - [7:1] */

1559

1560

/*

1561

* R792 (0x318) - RXANC_SRC

1562

*/

1563

#define WM5100_IN_RXANC_SEL_MASK 0x0007 /* IN_RXANC_SEL - [2:0] */

1564

#define WM5100_IN_RXANC_SEL_SHIFT 0 /* IN_RXANC_SEL - [2:0] */

1565

#define WM5100_IN_RXANC_SEL_WIDTH 3 /* IN_RXANC_SEL - [2:0] */

1566

1567

/*

1568

* R793 (0x319) - Input Volume Ramp

1569

*/

1570

#define WM5100_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */

1571

#define WM5100_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */

1572

#define WM5100_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */

1573

#define WM5100_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */

1574

#define WM5100_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */

1575

#define WM5100_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */

1576

1577

/*

1578

* R800 (0x320) - ADC Digital Volume 1L

1579

*/

1580

#define WM5100_IN_VU 0x0200 /* IN_VU */

1581

#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */

1582

#define WM5100_IN_VU_SHIFT 9 /* IN_VU */

1583

#define WM5100_IN_VU_WIDTH 1 /* IN_VU */

1584

#define WM5100_IN1L_MUTE 0x0100 /* IN1L_MUTE */

1585

#define WM5100_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */

1586

#define WM5100_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */

1587

#define WM5100_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */

1588

#define WM5100_IN1L_VOL_MASK 0x00FF /* IN1L_VOL - [7:0] */

1589

#define WM5100_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [7:0] */

1590

#define WM5100_IN1L_VOL_WIDTH 8 /* IN1L_VOL - [7:0] */

1591

1592

/*

1593

* R801 (0x321) - ADC Digital Volume 1R

1594

*/

1595

#define WM5100_IN_VU 0x0200 /* IN_VU */

1596

#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */

1597

#define WM5100_IN_VU_SHIFT 9 /* IN_VU */

1598

#define WM5100_IN_VU_WIDTH 1 /* IN_VU */

1599

#define WM5100_IN1R_MUTE 0x0100 /* IN1R_MUTE */

1600

#define WM5100_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */

1601

#define WM5100_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */

1602

#define WM5100_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */

1603

#define WM5100_IN1R_VOL_MASK 0x00FF /* IN1R_VOL - [7:0] */

1604

#define WM5100_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [7:0] */

1605

#define WM5100_IN1R_VOL_WIDTH 8 /* IN1R_VOL - [7:0] */

1606

1607

/*

1608

* R802 (0x322) - ADC Digital Volume 2L

1609

*/

1610

#define WM5100_IN_VU 0x0200 /* IN_VU */

1611

#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */

1612

#define WM5100_IN_VU_SHIFT 9 /* IN_VU */

1613

#define WM5100_IN_VU_WIDTH 1 /* IN_VU */

1614

#define WM5100_IN2L_MUTE 0x0100 /* IN2L_MUTE */

1615

#define WM5100_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */

1616

#define WM5100_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */

1617

#define WM5100_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */

1618

#define WM5100_IN2L_VOL_MASK 0x00FF /* IN2L_VOL - [7:0] */

1619

#define WM5100_IN2L_VOL_SHIFT 0 /* IN2L_VOL - [7:0] */

1620

#define WM5100_IN2L_VOL_WIDTH 8 /* IN2L_VOL - [7:0] */

1621

1622

/*

1623

* R803 (0x323) - ADC Digital Volume 2R

1624

*/

1625

#define WM5100_IN_VU 0x0200 /* IN_VU */

1626

#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */

1627

#define WM5100_IN_VU_SHIFT 9 /* IN_VU */

1628

#define WM5100_IN_VU_WIDTH 1 /* IN_VU */

1629

#define WM5100_IN2R_MUTE 0x0100 /* IN2R_MUTE */

1630

#define WM5100_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */

1631

#define WM5100_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */

1632

#define WM5100_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */

1633

#define WM5100_IN2R_VOL_MASK 0x00FF /* IN2R_VOL - [7:0] */

1634

#define WM5100_IN2R_VOL_SHIFT 0 /* IN2R_VOL - [7:0] */

1635

#define WM5100_IN2R_VOL_WIDTH 8 /* IN2R_VOL - [7:0] */

1636

1637

/*

1638

* R804 (0x324) - ADC Digital Volume 3L

1639

*/

1640

#define WM5100_IN_VU 0x0200 /* IN_VU */

1641

#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */

1642

#define WM5100_IN_VU_SHIFT 9 /* IN_VU */

1643

#define WM5100_IN_VU_WIDTH 1 /* IN_VU */

1644

#define WM5100_IN3L_MUTE 0x0100 /* IN3L_MUTE */

1645

#define WM5100_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */

1646

#define WM5100_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */

1647

#define WM5100_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */

1648

#define WM5100_IN3L_VOL_MASK 0x00FF /* IN3L_VOL - [7:0] */

1649

#define WM5100_IN3L_VOL_SHIFT 0 /* IN3L_VOL - [7:0] */

1650

#define WM5100_IN3L_VOL_WIDTH 8 /* IN3L_VOL - [7:0] */

1651

1652

/*

1653

* R805 (0x325) - ADC Digital Volume 3R

1654

*/

1655

#define WM5100_IN_VU 0x0200 /* IN_VU */

1656

#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */

1657

#define WM5100_IN_VU_SHIFT 9 /* IN_VU */

1658

#define WM5100_IN_VU_WIDTH 1 /* IN_VU */

1659

#define WM5100_IN3R_MUTE 0x0100 /* IN3R_MUTE */

1660

#define WM5100_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */

1661

#define WM5100_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */

1662

#define WM5100_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */

1663

#define WM5100_IN3R_VOL_MASK 0x00FF /* IN3R_VOL - [7:0] */

1664

#define WM5100_IN3R_VOL_SHIFT 0 /* IN3R_VOL - [7:0] */

1665

#define WM5100_IN3R_VOL_WIDTH 8 /* IN3R_VOL - [7:0] */

1666

1667

/*

1668

* R806 (0x326) - ADC Digital Volume 4L

1669

*/

1670

#define WM5100_IN_VU 0x0200 /* IN_VU */

1671

#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */

1672

#define WM5100_IN_VU_SHIFT 9 /* IN_VU */

1673

#define WM5100_IN_VU_WIDTH 1 /* IN_VU */

1674

#define WM5100_IN4L_MUTE 0x0100 /* IN4L_MUTE */

1675

#define WM5100_IN4L_MUTE_MASK 0x0100 /* IN4L_MUTE */

1676

#define WM5100_IN4L_MUTE_SHIFT 8 /* IN4L_MUTE */

1677

#define WM5100_IN4L_MUTE_WIDTH 1 /* IN4L_MUTE */

1678

#define WM5100_IN4L_VOL_MASK 0x00FF /* IN4L_VOL - [7:0] */

1679

#define WM5100_IN4L_VOL_SHIFT 0 /* IN4L_VOL - [7:0] */

1680

#define WM5100_IN4L_VOL_WIDTH 8 /* IN4L_VOL - [7:0] */

1681

1682

/*

1683

* R807 (0x327) - ADC Digital Volume 4R

1684

*/

1685

#define WM5100_IN_VU 0x0200 /* IN_VU */

1686

#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */

1687

#define WM5100_IN_VU_SHIFT 9 /* IN_VU */

1688

#define WM5100_IN_VU_WIDTH 1 /* IN_VU */

1689

#define WM5100_IN4R_MUTE 0x0100 /* IN4R_MUTE */

1690

#define WM5100_IN4R_MUTE_MASK 0x0100 /* IN4R_MUTE */

1691

#define WM5100_IN4R_MUTE_SHIFT 8 /* IN4R_MUTE */

1692

#define WM5100_IN4R_MUTE_WIDTH 1 /* IN4R_MUTE */

1693

#define WM5100_IN4R_VOL_MASK 0x00FF /* IN4R_VOL - [7:0] */

1694

#define WM5100_IN4R_VOL_SHIFT 0 /* IN4R_VOL - [7:0] */

1695

#define WM5100_IN4R_VOL_WIDTH 8 /* IN4R_VOL - [7:0] */

1696

1697

/*

1698

* R1025 (0x401) - Output Enables 2

1699

*/

1700

#define WM5100_OUT6L_ENA 0x0800 /* OUT6L_ENA */

1701

#define WM5100_OUT6L_ENA_MASK 0x0800 /* OUT6L_ENA */

1702

#define WM5100_OUT6L_ENA_SHIFT 11 /* OUT6L_ENA */

1703

#define WM5100_OUT6L_ENA_WIDTH 1 /* OUT6L_ENA */

1704

#define WM5100_OUT6R_ENA 0x0400 /* OUT6R_ENA */

1705

#define WM5100_OUT6R_ENA_MASK 0x0400 /* OUT6R_ENA */

1706

#define WM5100_OUT6R_ENA_SHIFT 10 /* OUT6R_ENA */

1707

#define WM5100_OUT6R_ENA_WIDTH 1 /* OUT6R_ENA */

1708

#define WM5100_OUT5L_ENA 0x0200 /* OUT5L_ENA */

1709

#define WM5100_OUT5L_ENA_MASK 0x0200 /* OUT5L_ENA */

1710

#define WM5100_OUT5L_ENA_SHIFT 9 /* OUT5L_ENA */

1711

#define WM5100_OUT5L_ENA_WIDTH 1 /* OUT5L_ENA */

1712

#define WM5100_OUT5R_ENA 0x0100 /* OUT5R_ENA */

1713

#define WM5100_OUT5R_ENA_MASK 0x0100 /* OUT5R_ENA */

1714

#define WM5100_OUT5R_ENA_SHIFT 8 /* OUT5R_ENA */

1715

#define WM5100_OUT5R_ENA_WIDTH 1 /* OUT5R_ENA */

1716

#define WM5100_OUT4L_ENA 0x0080 /* OUT4L_ENA */

1717

#define WM5100_OUT4L_ENA_MASK 0x0080 /* OUT4L_ENA */

1718

#define WM5100_OUT4L_ENA_SHIFT 7 /* OUT4L_ENA */

1719

#define WM5100_OUT4L_ENA_WIDTH 1 /* OUT4L_ENA */

1720

#define WM5100_OUT4R_ENA 0x0040 /* OUT4R_ENA */

1721

#define WM5100_OUT4R_ENA_MASK 0x0040 /* OUT4R_ENA */

1722

#define WM5100_OUT4R_ENA_SHIFT 6 /* OUT4R_ENA */

1723

#define WM5100_OUT4R_ENA_WIDTH 1 /* OUT4R_ENA */

1724

1725

/*

1726

* R1026 (0x402) - Output Status 1

1727

*/

1728

#define WM5100_OUT3L_ENA_STS 0x0020 /* OUT3L_ENA_STS */

1729

#define WM5100_OUT3L_ENA_STS_MASK 0x0020 /* OUT3L_ENA_STS */

1730

#define WM5100_OUT3L_ENA_STS_SHIFT 5 /* OUT3L_ENA_STS */

1731

#define WM5100_OUT3L_ENA_STS_WIDTH 1 /* OUT3L_ENA_STS */

1732

#define WM5100_OUT3R_ENA_STS 0x0010 /* OUT3R_ENA_STS */

1733

#define WM5100_OUT3R_ENA_STS_MASK 0x0010 /* OUT3R_ENA_STS */

1734

#define WM5100_OUT3R_ENA_STS_SHIFT 4 /* OUT3R_ENA_STS */

1735

#define WM5100_OUT3R_ENA_STS_WIDTH 1 /* OUT3R_ENA_STS */

1736

#define WM5100_OUT2L_ENA_STS 0x0008 /* OUT2L_ENA_STS */

1737

#define WM5100_OUT2L_ENA_STS_MASK 0x0008 /* OUT2L_ENA_STS */

1738

#define WM5100_OUT2L_ENA_STS_SHIFT 3 /* OUT2L_ENA_STS */

1739

#define WM5100_OUT2L_ENA_STS_WIDTH 1 /* OUT2L_ENA_STS */

1740

#define WM5100_OUT2R_ENA_STS 0x0004 /* OUT2R_ENA_STS */

1741

#define WM5100_OUT2R_ENA_STS_MASK 0x0004 /* OUT2R_ENA_STS */

1742

#define WM5100_OUT2R_ENA_STS_SHIFT 2 /* OUT2R_ENA_STS */

1743

#define WM5100_OUT2R_ENA_STS_WIDTH 1 /* OUT2R_ENA_STS */

1744

#define WM5100_OUT1L_ENA_STS 0x0002 /* OUT1L_ENA_STS */

1745

#define WM5100_OUT1L_ENA_STS_MASK 0x0002 /* OUT1L_ENA_STS */

1746

#define WM5100_OUT1L_ENA_STS_SHIFT 1 /* OUT1L_ENA_STS */

1747

#define WM5100_OUT1L_ENA_STS_WIDTH 1 /* OUT1L_ENA_STS */

1748

#define WM5100_OUT1R_ENA_STS 0x0001 /* OUT1R_ENA_STS */

1749

#define WM5100_OUT1R_ENA_STS_MASK 0x0001 /* OUT1R_ENA_STS */

1750

#define WM5100_OUT1R_ENA_STS_SHIFT 0 /* OUT1R_ENA_STS */

1751

#define WM5100_OUT1R_ENA_STS_WIDTH 1 /* OUT1R_ENA_STS */

1752

1753

/*

1754

* R1027 (0x403) - Output Status 2

1755

*/

1756

#define WM5100_OUT6L_ENA_STS 0x0800 /* OUT6L_ENA_STS */

1757

#define WM5100_OUT6L_ENA_STS_MASK 0x0800 /* OUT6L_ENA_STS */

1758

#define WM5100_OUT6L_ENA_STS_SHIFT 11 /* OUT6L_ENA_STS */

1759

#define WM5100_OUT6L_ENA_STS_WIDTH 1 /* OUT6L_ENA_STS */

1760

#define WM5100_OUT6R_ENA_STS 0x0400 /* OUT6R_ENA_STS */

1761

#define WM5100_OUT6R_ENA_STS_MASK 0x0400 /* OUT6R_ENA_STS */

1762

#define WM5100_OUT6R_ENA_STS_SHIFT 10 /* OUT6R_ENA_STS */

1763

#define WM5100_OUT6R_ENA_STS_WIDTH 1 /* OUT6R_ENA_STS */

1764

#define WM5100_OUT5L_ENA_STS 0x0200 /* OUT5L_ENA_STS */

1765

#define WM5100_OUT5L_ENA_STS_MASK 0x0200 /* OUT5L_ENA_STS */

1766

#define WM5100_OUT5L_ENA_STS_SHIFT 9 /* OUT5L_ENA_STS */

1767

#define WM5100_OUT5L_ENA_STS_WIDTH 1 /* OUT5L_ENA_STS */

1768

#define WM5100_OUT5R_ENA_STS 0x0100 /* OUT5R_ENA_STS */

1769

#define WM5100_OUT5R_ENA_STS_MASK 0x0100 /* OUT5R_ENA_STS */

1770

#define WM5100_OUT5R_ENA_STS_SHIFT 8 /* OUT5R_ENA_STS */

1771

#define WM5100_OUT5R_ENA_STS_WIDTH 1 /* OUT5R_ENA_STS */

1772

#define WM5100_OUT4L_ENA_STS 0x0080 /* OUT4L_ENA_STS */

1773

#define WM5100_OUT4L_ENA_STS_MASK 0x0080 /* OUT4L_ENA_STS */

1774

#define WM5100_OUT4L_ENA_STS_SHIFT 7 /* OUT4L_ENA_STS */

1775

#define WM5100_OUT4L_ENA_STS_WIDTH 1 /* OUT4L_ENA_STS */

1776

#define WM5100_OUT4R_ENA_STS 0x0040 /* OUT4R_ENA_STS */

1777

#define WM5100_OUT4R_ENA_STS_MASK 0x0040 /* OUT4R_ENA_STS */

1778

#define WM5100_OUT4R_ENA_STS_SHIFT 6 /* OUT4R_ENA_STS */

1779

#define WM5100_OUT4R_ENA_STS_WIDTH 1 /* OUT4R_ENA_STS */

1780

1781

/*

1782

* R1032 (0x408) - Channel Enables 1

1783

*/

1784

#define WM5100_HP3L_ENA 0x0020 /* HP3L_ENA */

1785

#define WM5100_HP3L_ENA_MASK 0x0020 /* HP3L_ENA */

1786

#define WM5100_HP3L_ENA_SHIFT 5 /* HP3L_ENA */

1787

#define WM5100_HP3L_ENA_WIDTH 1 /* HP3L_ENA */

1788

#define WM5100_HP3R_ENA 0x0010 /* HP3R_ENA */

1789

#define WM5100_HP3R_ENA_MASK 0x0010 /* HP3R_ENA */

1790

#define WM5100_HP3R_ENA_SHIFT 4 /* HP3R_ENA */

1791

#define WM5100_HP3R_ENA_WIDTH 1 /* HP3R_ENA */

1792

#define WM5100_HP2L_ENA 0x0008 /* HP2L_ENA */

1793

#define WM5100_HP2L_ENA_MASK 0x0008 /* HP2L_ENA */

1794

#define WM5100_HP2L_ENA_SHIFT 3 /* HP2L_ENA */

1795

#define WM5100_HP2L_ENA_WIDTH 1 /* HP2L_ENA */

1796

#define WM5100_HP2R_ENA 0x0004 /* HP2R_ENA */

1797

#define WM5100_HP2R_ENA_MASK 0x0004 /* HP2R_ENA */

1798

#define WM5100_HP2R_ENA_SHIFT 2 /* HP2R_ENA */

1799

#define WM5100_HP2R_ENA_WIDTH 1 /* HP2R_ENA */

1800

#define WM5100_HP1L_ENA 0x0002 /* HP1L_ENA */

1801

#define WM5100_HP1L_ENA_MASK 0x0002 /* HP1L_ENA */

1802

#define WM5100_HP1L_ENA_SHIFT 1 /* HP1L_ENA */

1803

#define WM5100_HP1L_ENA_WIDTH 1 /* HP1L_ENA */

1804

#define WM5100_HP1R_ENA 0x0001 /* HP1R_ENA */

1805

#define WM5100_HP1R_ENA_MASK 0x0001 /* HP1R_ENA */

1806

#define WM5100_HP1R_ENA_SHIFT 0 /* HP1R_ENA */

1807

#define WM5100_HP1R_ENA_WIDTH 1 /* HP1R_ENA */

1808

1809

/*

1810

* R1040 (0x410) - Out Volume 1L

1811

*/

1812

#define WM5100_OUT_RATE_MASK 0xC000 /* OUT_RATE - [15:14] */

1813

#define WM5100_OUT_RATE_SHIFT 14 /* OUT_RATE - [15:14] */

1814

#define WM5100_OUT_RATE_WIDTH 2 /* OUT_RATE - [15:14] */

1815

#define WM5100_OUT1_OSR 0x2000 /* OUT1_OSR */

1816

#define WM5100_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */

1817

#define WM5100_OUT1_OSR_SHIFT 13 /* OUT1_OSR */

1818

#define WM5100_OUT1_OSR_WIDTH 1 /* OUT1_OSR */

1819

#define WM5100_OUT1_MONO 0x1000 /* OUT1_MONO */

1820

#define WM5100_OUT1_MONO_MASK 0x1000 /* OUT1_MONO */

1821

#define WM5100_OUT1_MONO_SHIFT 12 /* OUT1_MONO */

1822

#define WM5100_OUT1_MONO_WIDTH 1 /* OUT1_MONO */

1823

#define WM5100_OUT1L_ANC_SRC 0x0800 /* OUT1L_ANC_SRC */

1824

#define WM5100_OUT1L_ANC_SRC_MASK 0x0800 /* OUT1L_ANC_SRC */

1825

#define WM5100_OUT1L_ANC_SRC_SHIFT 11 /* OUT1L_ANC_SRC */

1826

#define WM5100_OUT1L_ANC_SRC_WIDTH 1 /* OUT1L_ANC_SRC */

1827

#define WM5100_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */

1828

#define WM5100_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */

1829

#define WM5100_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */

1830

1831

/*

1832

* R1041 (0x411) - Out Volume 1R

1833

*/

1834

#define WM5100_OUT1R_ANC_SRC 0x0800 /* OUT1R_ANC_SRC */

1835

#define WM5100_OUT1R_ANC_SRC_MASK 0x0800 /* OUT1R_ANC_SRC */

1836

#define WM5100_OUT1R_ANC_SRC_SHIFT 11 /* OUT1R_ANC_SRC */

1837

#define WM5100_OUT1R_ANC_SRC_WIDTH 1 /* OUT1R_ANC_SRC */

1838

#define WM5100_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */

1839

#define WM5100_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */

1840

#define WM5100_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */

1841

1842

/*

1843

* R1042 (0x412) - DAC Volume Limit 1L

1844

*/

1845

#define WM5100_OUT1L_VOL_LIM_MASK 0x00FF /* OUT1L_VOL_LIM - [7:0] */

1846

#define WM5100_OUT1L_VOL_LIM_SHIFT 0 /* OUT1L_VOL_LIM - [7:0] */

1847

#define WM5100_OUT1L_VOL_LIM_WIDTH 8 /* OUT1L_VOL_LIM - [7:0] */

1848

1849

/*

1850

* R1043 (0x413) - DAC Volume Limit 1R

1851

*/

1852

#define WM5100_OUT1R_VOL_LIM_MASK 0x00FF /* OUT1R_VOL_LIM - [7:0] */

1853

#define WM5100_OUT1R_VOL_LIM_SHIFT 0 /* OUT1R_VOL_LIM - [7:0] */

1854

#define WM5100_OUT1R_VOL_LIM_WIDTH 8 /* OUT1R_VOL_LIM - [7:0] */

1855

1856

/*

1857

* R1044 (0x414) - Out Volume 2L

1858

*/

1859

#define WM5100_OUT2_OSR 0x2000 /* OUT2_OSR */

1860

#define WM5100_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */

1861

#define WM5100_OUT2_OSR_SHIFT 13 /* OUT2_OSR */

1862

#define WM5100_OUT2_OSR_WIDTH 1 /* OUT2_OSR */

1863

#define WM5100_OUT2_MONO 0x1000 /* OUT2_MONO */

1864

#define WM5100_OUT2_MONO_MASK 0x1000 /* OUT2_MONO */

1865

#define WM5100_OUT2_MONO_SHIFT 12 /* OUT2_MONO */

1866

#define WM5100_OUT2_MONO_WIDTH 1 /* OUT2_MONO */

1867

#define WM5100_OUT2L_ANC_SRC 0x0800 /* OUT2L_ANC_SRC */

1868

#define WM5100_OUT2L_ANC_SRC_MASK 0x0800 /* OUT2L_ANC_SRC */

1869

#define WM5100_OUT2L_ANC_SRC_SHIFT 11 /* OUT2L_ANC_SRC */

1870

#define WM5100_OUT2L_ANC_SRC_WIDTH 1 /* OUT2L_ANC_SRC */

1871

#define WM5100_OUT2L_PGA_VOL_MASK 0x00FE /* OUT2L_PGA_VOL - [7:1] */

1872

#define WM5100_OUT2L_PGA_VOL_SHIFT 1 /* OUT2L_PGA_VOL - [7:1] */

1873

#define WM5100_OUT2L_PGA_VOL_WIDTH 7 /* OUT2L_PGA_VOL - [7:1] */

1874

1875

/*

1876

* R1045 (0x415) - Out Volume 2R

1877

*/

1878

#define WM5100_OUT2R_ANC_SRC 0x0800 /* OUT2R_ANC_SRC */

1879

#define WM5100_OUT2R_ANC_SRC_MASK 0x0800 /* OUT2R_ANC_SRC */

1880

#define WM5100_OUT2R_ANC_SRC_SHIFT 11 /* OUT2R_ANC_SRC */

1881

#define WM5100_OUT2R_ANC_SRC_WIDTH 1 /* OUT2R_ANC_SRC */

1882

#define WM5100_OUT2R_PGA_VOL_MASK 0x00FE /* OUT2R_PGA_VOL - [7:1] */

1883

#define WM5100_OUT2R_PGA_VOL_SHIFT 1 /* OUT2R_PGA_VOL - [7:1] */

1884

#define WM5100_OUT2R_PGA_VOL_WIDTH 7 /* OUT2R_PGA_VOL - [7:1] */

1885

1886

/*

1887

* R1046 (0x416) - DAC Volume Limit 2L

1888

*/

1889

#define WM5100_OUT2L_VOL_LIM_MASK 0x00FF /* OUT2L_VOL_LIM - [7:0] */

1890

#define WM5100_OUT2L_VOL_LIM_SHIFT 0 /* OUT2L_VOL_LIM - [7:0] */

1891

#define WM5100_OUT2L_VOL_LIM_WIDTH 8 /* OUT2L_VOL_LIM - [7:0] */

1892

1893

/*

1894

* R1047 (0x417) - DAC Volume Limit 2R

1895

*/

1896

#define WM5100_OUT2R_VOL_LIM_MASK 0x00FF /* OUT2R_VOL_LIM - [7:0] */

1897

#define WM5100_OUT2R_VOL_LIM_SHIFT 0 /* OUT2R_VOL_LIM - [7:0] */

1898

#define WM5100_OUT2R_VOL_LIM_WIDTH 8 /* OUT2R_VOL_LIM - [7:0] */

1899

1900

/*

1901

* R1048 (0x418) - Out Volume 3L

1902

*/

1903

#define WM5100_OUT3_OSR 0x2000 /* OUT3_OSR */

1904

#define WM5100_OUT3_OSR_MASK 0x2000 /* OUT3_OSR */

1905

#define WM5100_OUT3_OSR_SHIFT 13 /* OUT3_OSR */

1906

#define WM5100_OUT3_OSR_WIDTH 1 /* OUT3_OSR */

1907

#define WM5100_OUT3_MONO 0x1000 /* OUT3_MONO */

1908

#define WM5100_OUT3_MONO_MASK 0x1000 /* OUT3_MONO */

1909

#define WM5100_OUT3_MONO_SHIFT 12 /* OUT3_MONO */

1910

#define WM5100_OUT3_MONO_WIDTH 1 /* OUT3_MONO */

1911

#define WM5100_OUT3L_ANC_SRC 0x0800 /* OUT3L_ANC_SRC */

1912

#define WM5100_OUT3L_ANC_SRC_MASK 0x0800 /* OUT3L_ANC_SRC */

1913

#define WM5100_OUT3L_ANC_SRC_SHIFT 11 /* OUT3L_ANC_SRC */

1914

#define WM5100_OUT3L_ANC_SRC_WIDTH 1 /* OUT3L_ANC_SRC */

1915

#define WM5100_OUT3L_PGA_VOL_MASK 0x00FE /* OUT3L_PGA_VOL - [7:1] */

1916

#define WM5100_OUT3L_PGA_VOL_SHIFT 1 /* OUT3L_PGA_VOL - [7:1] */

1917

#define WM5100_OUT3L_PGA_VOL_WIDTH 7 /* OUT3L_PGA_VOL - [7:1] */

1918

1919

/*

1920

* R1049 (0x419) - Out Volume 3R

1921

*/

1922

#define WM5100_OUT3R_ANC_SRC 0x0800 /* OUT3R_ANC_SRC */

1923

#define WM5100_OUT3R_ANC_SRC_MASK 0x0800 /* OUT3R_ANC_SRC */

1924

#define WM5100_OUT3R_ANC_SRC_SHIFT 11 /* OUT3R_ANC_SRC */

1925

#define WM5100_OUT3R_ANC_SRC_WIDTH 1 /* OUT3R_ANC_SRC */

1926

#define WM5100_OUT3R_PGA_VOL_MASK 0x00FE /* OUT3R_PGA_VOL - [7:1] */

1927

#define WM5100_OUT3R_PGA_VOL_SHIFT 1 /* OUT3R_PGA_VOL - [7:1] */

1928

#define WM5100_OUT3R_PGA_VOL_WIDTH 7 /* OUT3R_PGA_VOL - [7:1] */

1929

1930

/*

1931

* R1050 (0x41A) - DAC Volume Limit 3L

1932

*/

1933

#define WM5100_OUT3L_VOL_LIM_MASK 0x00FF /* OUT3L_VOL_LIM - [7:0] */

1934

#define WM5100_OUT3L_VOL_LIM_SHIFT 0 /* OUT3L_VOL_LIM - [7:0] */

1935

#define WM5100_OUT3L_VOL_LIM_WIDTH 8 /* OUT3L_VOL_LIM - [7:0] */

1936

1937

/*

1938

* R1051 (0x41B) - DAC Volume Limit 3R

1939

*/

1940

#define WM5100_OUT3R_VOL_LIM_MASK 0x00FF /* OUT3R_VOL_LIM - [7:0] */

1941

#define WM5100_OUT3R_VOL_LIM_SHIFT 0 /* OUT3R_VOL_LIM - [7:0] */

1942

#define WM5100_OUT3R_VOL_LIM_WIDTH 8 /* OUT3R_VOL_LIM - [7:0] */

1943

1944

/*

1945

* R1052 (0x41C) - Out Volume 4L

1946

*/

1947

#define WM5100_OUT4_OSR 0x2000 /* OUT4_OSR */

1948

#define WM5100_OUT4_OSR_MASK 0x2000 /* OUT4_OSR */

1949

#define WM5100_OUT4_OSR_SHIFT 13 /* OUT4_OSR */

1950

#define WM5100_OUT4_OSR_WIDTH 1 /* OUT4_OSR */

1951

#define WM5100_OUT4L_ANC_SRC 0x0800 /* OUT4L_ANC_SRC */

1952

#define WM5100_OUT4L_ANC_SRC_MASK 0x0800 /* OUT4L_ANC_SRC */

1953

#define WM5100_OUT4L_ANC_SRC_SHIFT 11 /* OUT4L_ANC_SRC */

1954

#define WM5100_OUT4L_ANC_SRC_WIDTH 1 /* OUT4L_ANC_SRC */

1955

#define WM5100_OUT4L_VOL_LIM_MASK 0x00FF /* OUT4L_VOL_LIM - [7:0] */

1956

#define WM5100_OUT4L_VOL_LIM_SHIFT 0 /* OUT4L_VOL_LIM - [7:0] */

1957

#define WM5100_OUT4L_VOL_LIM_WIDTH 8 /* OUT4L_VOL_LIM - [7:0] */

1958

1959

/*

1960

* R1053 (0x41D) - Out Volume 4R

1961

*/

1962

#define WM5100_OUT4R_ANC_SRC 0x0800 /* OUT4R_ANC_SRC */

1963

#define WM5100_OUT4R_ANC_SRC_MASK 0x0800 /* OUT4R_ANC_SRC */

1964

#define WM5100_OUT4R_ANC_SRC_SHIFT 11 /* OUT4R_ANC_SRC */

1965

#define WM5100_OUT4R_ANC_SRC_WIDTH 1 /* OUT4R_ANC_SRC */

1966

#define WM5100_OUT4R_VOL_LIM_MASK 0x00FF /* OUT4R_VOL_LIM - [7:0] */

1967

#define WM5100_OUT4R_VOL_LIM_SHIFT 0 /* OUT4R_VOL_LIM - [7:0] */

1968

#define WM5100_OUT4R_VOL_LIM_WIDTH 8 /* OUT4R_VOL_LIM - [7:0] */

1969

1970

/*

1971

* R1054 (0x41E) - DAC Volume Limit 5L

1972

*/

1973

#define WM5100_OUT5_OSR 0x2000 /* OUT5_OSR */

1974

#define WM5100_OUT5_OSR_MASK 0x2000 /* OUT5_OSR */

1975

#define WM5100_OUT5_OSR_SHIFT 13 /* OUT5_OSR */

1976

#define WM5100_OUT5_OSR_WIDTH 1 /* OUT5_OSR */

1977

#define WM5100_OUT5L_ANC_SRC 0x0800 /* OUT5L_ANC_SRC */

1978

#define WM5100_OUT5L_ANC_SRC_MASK 0x0800 /* OUT5L_ANC_SRC */

1979

#define WM5100_OUT5L_ANC_SRC_SHIFT 11 /* OUT5L_ANC_SRC */

1980

#define WM5100_OUT5L_ANC_SRC_WIDTH 1 /* OUT5L_ANC_SRC */

1981

#define WM5100_OUT5L_VOL_LIM_MASK 0x00FF /* OUT5L_VOL_LIM - [7:0] */

1982

#define WM5100_OUT5L_VOL_LIM_SHIFT 0 /* OUT5L_VOL_LIM - [7:0] */

1983

#define WM5100_OUT5L_VOL_LIM_WIDTH 8 /* OUT5L_VOL_LIM - [7:0] */

1984

1985

/*

1986

* R1055 (0x41F) - DAC Volume Limit 5R

1987

*/

1988

#define WM5100_OUT5R_ANC_SRC 0x0800 /* OUT5R_ANC_SRC */

1989

#define WM5100_OUT5R_ANC_SRC_MASK 0x0800 /* OUT5R_ANC_SRC */

1990

#define WM5100_OUT5R_ANC_SRC_SHIFT 11 /* OUT5R_ANC_SRC */

1991

#define WM5100_OUT5R_ANC_SRC_WIDTH 1 /* OUT5R_ANC_SRC */

1992

#define WM5100_OUT5R_VOL_LIM_MASK 0x00FF /* OUT5R_VOL_LIM - [7:0] */

1993

#define WM5100_OUT5R_VOL_LIM_SHIFT 0 /* OUT5R_VOL_LIM - [7:0] */

1994

#define WM5100_OUT5R_VOL_LIM_WIDTH 8 /* OUT5R_VOL_LIM - [7:0] */

1995

1996

/*

1997

* R1056 (0x420) - DAC Volume Limit 6L

1998

*/

1999

#define WM5100_OUT6_OSR 0x2000 /* OUT6_OSR */

2000

#define WM5100_OUT6_OSR_MASK 0x2000 /* OUT6_OSR */

2001

#define WM5100_OUT6_OSR_SHIFT 13 /* OUT6_OSR */

2002

#define WM5100_OUT6_OSR_WIDTH 1 /* OUT6_OSR */

2003

#define WM5100_OUT6L_ANC_SRC 0x0800 /* OUT6L_ANC_SRC */

2004

#define WM5100_OUT6L_ANC_SRC_MASK 0x0800 /* OUT6L_ANC_SRC */

2005

#define WM5100_OUT6L_ANC_SRC_SHIFT 11 /* OUT6L_ANC_SRC */

2006

#define WM5100_OUT6L_ANC_SRC_WIDTH 1 /* OUT6L_ANC_SRC */

2007

#define WM5100_OUT6L_VOL_LIM_MASK 0x00FF /* OUT6L_VOL_LIM - [7:0] */

2008

#define WM5100_OUT6L_VOL_LIM_SHIFT 0 /* OUT6L_VOL_LIM - [7:0] */

2009

#define WM5100_OUT6L_VOL_LIM_WIDTH 8 /* OUT6L_VOL_LIM - [7:0] */

2010

2011

/*

2012

* R1057 (0x421) - DAC Volume Limit 6R

2013

*/

2014

#define WM5100_OUT6R_ANC_SRC 0x0800 /* OUT6R_ANC_SRC */

2015

#define WM5100_OUT6R_ANC_SRC_MASK 0x0800 /* OUT6R_ANC_SRC */

2016

#define WM5100_OUT6R_ANC_SRC_SHIFT 11 /* OUT6R_ANC_SRC */

2017

#define WM5100_OUT6R_ANC_SRC_WIDTH 1 /* OUT6R_ANC_SRC */

2018

#define WM5100_OUT6R_VOL_LIM_MASK 0x00FF /* OUT6R_VOL_LIM - [7:0] */

2019

#define WM5100_OUT6R_VOL_LIM_SHIFT 0 /* OUT6R_VOL_LIM - [7:0] */

2020

#define WM5100_OUT6R_VOL_LIM_WIDTH 8 /* OUT6R_VOL_LIM - [7:0] */

2021

2022

/*

2023

* R1088 (0x440) - DAC AEC Control 1

2024

*/

2025

#define WM5100_AEC_LOOPBACK_SRC_MASK 0x003C /* AEC_LOOPBACK_SRC - [5:2] */

2026

#define WM5100_AEC_LOOPBACK_SRC_SHIFT 2 /* AEC_LOOPBACK_SRC - [5:2] */

2027

#define WM5100_AEC_LOOPBACK_SRC_WIDTH 4 /* AEC_LOOPBACK_SRC - [5:2] */

2028

#define WM5100_AEC_ENA_STS 0x0002 /* AEC_ENA_STS */

2029

#define WM5100_AEC_ENA_STS_MASK 0x0002 /* AEC_ENA_STS */

2030

#define WM5100_AEC_ENA_STS_SHIFT 1 /* AEC_ENA_STS */

2031

#define WM5100_AEC_ENA_STS_WIDTH 1 /* AEC_ENA_STS */

2032

#define WM5100_AEC_LOOPBACK_ENA 0x0001 /* AEC_LOOPBACK_ENA */

2033

#define WM5100_AEC_LOOPBACK_ENA_MASK 0x0001 /* AEC_LOOPBACK_ENA */

2034

#define WM5100_AEC_LOOPBACK_ENA_SHIFT 0 /* AEC_LOOPBACK_ENA */

2035

#define WM5100_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */

2036

2037

/*

2038

* R1089 (0x441) - Output Volume Ramp

2039

*/

2040

#define WM5100_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */

2041

#define WM5100_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */

2042

#define WM5100_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */

2043

#define WM5100_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */

2044

#define WM5100_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */

2045

#define WM5100_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */

2046

2047

/*

2048

* R1152 (0x480) - DAC Digital Volume 1L

2049

*/

2050

#define WM5100_OUT_VU 0x0200 /* OUT_VU */

2051

#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */

2052

#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */

2053

#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */

2054

#define WM5100_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */

2055

#define WM5100_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */

2056

#define WM5100_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */

2057

#define WM5100_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */

2058

#define WM5100_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */

2059

#define WM5100_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */

2060

#define WM5100_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */

2061

2062

/*

2063

* R1153 (0x481) - DAC Digital Volume 1R

2064

*/

2065

#define WM5100_OUT_VU 0x0200 /* OUT_VU */

2066

#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */

2067

#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */

2068

#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */

2069

#define WM5100_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */

2070

#define WM5100_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */

2071

#define WM5100_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */

2072

#define WM5100_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */

2073

#define WM5100_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */

2074

#define WM5100_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */

2075

#define WM5100_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */

2076

2077

/*

2078

* R1154 (0x482) - DAC Digital Volume 2L

2079

*/

2080

#define WM5100_OUT_VU 0x0200 /* OUT_VU */

2081

#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */

2082

#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */

2083

#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */

2084

#define WM5100_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */

2085

#define WM5100_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */

2086

#define WM5100_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */

2087

#define WM5100_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */

2088

#define WM5100_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */

2089

#define WM5100_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */

2090

#define WM5100_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */

2091

2092

/*

2093

* R1155 (0x483) - DAC Digital Volume 2R

2094

*/

2095

#define WM5100_OUT_VU 0x0200 /* OUT_VU */

2096

#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */

2097

#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */

2098

#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */

2099

#define WM5100_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */

2100

#define WM5100_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */

2101

#define WM5100_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */

2102

#define WM5100_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */

2103

#define WM5100_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */

2104

#define WM5100_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */

2105

#define WM5100_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */

2106

2107

/*

2108

* R1156 (0x484) - DAC Digital Volume 3L

2109

*/

2110

#define WM5100_OUT_VU 0x0200 /* OUT_VU */

2111

#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */

2112

#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */

2113

#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */

2114

#define WM5100_OUT3L_MUTE 0x0100 /* OUT3L_MUTE */

2115

#define WM5100_OUT3L_MUTE_MASK 0x0100 /* OUT3L_MUTE */

2116

#define WM5100_OUT3L_MUTE_SHIFT 8 /* OUT3L_MUTE */

2117

#define WM5100_OUT3L_MUTE_WIDTH 1 /* OUT3L_MUTE */

2118

#define WM5100_OUT3L_VOL_MASK 0x00FF /* OUT3L_VOL - [7:0] */

2119

#define WM5100_OUT3L_VOL_SHIFT 0 /* OUT3L_VOL - [7:0] */

2120

#define WM5100_OUT3L_VOL_WIDTH 8 /* OUT3L_VOL - [7:0] */

2121

2122

/*

2123

* R1157 (0x485) - DAC Digital Volume 3R

2124

*/

2125

#define WM5100_OUT_VU 0x0200 /* OUT_VU */

2126

#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */

2127

#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */

2128

#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */

2129

#define WM5100_OUT3R_MUTE 0x0100 /* OUT3R_MUTE */

2130

#define WM5100_OUT3R_MUTE_MASK 0x0100 /* OUT3R_MUTE */

2131

#define WM5100_OUT3R_MUTE_SHIFT 8 /* OUT3R_MUTE */

2132

#define WM5100_OUT3R_MUTE_WIDTH 1 /* OUT3R_MUTE */

2133

#define WM5100_OUT3R_VOL_MASK 0x00FF /* OUT3R_VOL - [7:0] */

2134

#define WM5100_OUT3R_VOL_SHIFT 0 /* OUT3R_VOL - [7:0] */

2135

#define WM5100_OUT3R_VOL_WIDTH 8 /* OUT3R_VOL - [7:0] */

2136

2137

/*

2138

* R1158 (0x486) - DAC Digital Volume 4L

2139

*/

2140

#define WM5100_OUT_VU 0x0200 /* OUT_VU */

2141

#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */

2142

#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */

2143

#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */

2144

#define WM5100_OUT4L_MUTE 0x0100 /* OUT4L_MUTE */

2145

#define WM5100_OUT4L_MUTE_MASK 0x0100 /* OUT4L_MUTE */

2146

#define WM5100_OUT4L_MUTE_SHIFT 8 /* OUT4L_MUTE */

2147

#define WM5100_OUT4L_MUTE_WIDTH 1 /* OUT4L_MUTE */

2148

#define WM5100_OUT4L_VOL_MASK 0x00FF /* OUT4L_VOL - [7:0] */

2149

#define WM5100_OUT4L_VOL_SHIFT 0 /* OUT4L_VOL - [7:0] */

2150

#define WM5100_OUT4L_VOL_WIDTH 8 /* OUT4L_VOL - [7:0] */

2151

2152

/*

2153

* R1159 (0x487) - DAC Digital Volume 4R

2154

*/

2155

#define WM5100_OUT_VU 0x0200 /* OUT_VU */

2156

#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */

2157

#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */

2158

#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */

2159

#define WM5100_OUT4R_MUTE 0x0100 /* OUT4R_MUTE */

2160

#define WM5100_OUT4R_MUTE_MASK 0x0100 /* OUT4R_MUTE */

2161

#define WM5100_OUT4R_MUTE_SHIFT 8 /* OUT4R_MUTE */

2162

#define WM5100_OUT4R_MUTE_WIDTH 1 /* OUT4R_MUTE */

2163

#define WM5100_OUT4R_VOL_MASK 0x00FF /* OUT4R_VOL - [7:0] */

2164

#define WM5100_OUT4R_VOL_SHIFT 0 /* OUT4R_VOL - [7:0] */

2165

#define WM5100_OUT4R_VOL_WIDTH 8 /* OUT4R_VOL - [7:0] */

2166

2167

/*

2168

* R1160 (0x488) - DAC Digital Volume 5L

2169

*/

2170

#define WM5100_OUT_VU 0x0200 /* OUT_VU */

2171

#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */

2172

#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */

2173

#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */

2174

#define WM5100_OUT5L_MUTE 0x0100 /* OUT5L_MUTE */

2175

#define WM5100_OUT5L_MUTE_MASK 0x0100 /* OUT5L_MUTE */

2176

#define WM5100_OUT5L_MUTE_SHIFT 8 /* OUT5L_MUTE */

2177

#define WM5100_OUT5L_MUTE_WIDTH 1 /* OUT5L_MUTE */

2178

#define WM5100_OUT5L_VOL_MASK 0x00FF /* OUT5L_VOL - [7:0] */

2179

#define WM5100_OUT5L_VOL_SHIFT 0 /* OUT5L_VOL - [7:0] */

2180

#define WM5100_OUT5L_VOL_WIDTH 8 /* OUT5L_VOL - [7:0] */

2181

2182

/*

2183

* R1161 (0x489) - DAC Digital Volume 5R

2184

*/

2185

#define WM5100_OUT_VU 0x0200 /* OUT_VU */

2186

#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */

2187

#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */

2188

#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */

2189

#define WM5100_OUT5R_MUTE 0x0100 /* OUT5R_MUTE */

2190

#define WM5100_OUT5R_MUTE_MASK 0x0100 /* OUT5R_MUTE */

2191

#define WM5100_OUT5R_MUTE_SHIFT 8 /* OUT5R_MUTE */

2192

#define WM5100_OUT5R_MUTE_WIDTH 1 /* OUT5R_MUTE */

2193

#define WM5100_OUT5R_VOL_MASK 0x00FF /* OUT5R_VOL - [7:0] */

2194

#define WM5100_OUT5R_VOL_SHIFT 0 /* OUT5R_VOL - [7:0] */

2195

#define WM5100_OUT5R_VOL_WIDTH 8 /* OUT5R_VOL - [7:0] */

2196

2197

/*

2198

* R1162 (0x48A) - DAC Digital Volume 6L

2199

*/

2200

#define WM5100_OUT_VU 0x0200 /* OUT_VU */

2201

#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */

2202

#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */

2203

#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */

2204

#define WM5100_OUT6L_MUTE 0x0100 /* OUT6L_MUTE */

2205

#define WM5100_OUT6L_MUTE_MASK 0x0100 /* OUT6L_MUTE */

2206

#define WM5100_OUT6L_MUTE_SHIFT 8 /* OUT6L_MUTE */

2207

#define WM5100_OUT6L_MUTE_WIDTH 1 /* OUT6L_MUTE */

2208

#define WM5100_OUT6L_VOL_MASK 0x00FF /* OUT6L_VOL - [7:0] */

2209

#define WM5100_OUT6L_VOL_SHIFT 0 /* OUT6L_VOL - [7:0] */

2210

#define WM5100_OUT6L_VOL_WIDTH 8 /* OUT6L_VOL - [7:0] */

2211

2212

/*

2213

* R1163 (0x48B) - DAC Digital Volume 6R

2214

*/

2215

#define WM5100_OUT_VU 0x0200 /* OUT_VU */

2216

#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */

2217

#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */

2218

#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */

2219

#define WM5100_OUT6R_MUTE 0x0100 /* OUT6R_MUTE */

2220

#define WM5100_OUT6R_MUTE_MASK 0x0100 /* OUT6R_MUTE */

2221

#define WM5100_OUT6R_MUTE_SHIFT 8 /* OUT6R_MUTE */

2222

#define WM5100_OUT6R_MUTE_WIDTH 1 /* OUT6R_MUTE */

2223

#define WM5100_OUT6R_VOL_MASK 0x00FF /* OUT6R_VOL - [7:0] */

2224

#define WM5100_OUT6R_VOL_SHIFT 0 /* OUT6R_VOL - [7:0] */

2225

#define WM5100_OUT6R_VOL_WIDTH 8 /* OUT6R_VOL - [7:0] */

2226

2227

/*

2228

* R1216 (0x4C0) - PDM SPK1 CTRL 1

2229

*/

2230

#define WM5100_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */

2231

#define WM5100_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */

2232

#define WM5100_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */

2233

#define WM5100_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */

2234

#define WM5100_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */

2235

#define WM5100_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */

2236

#define WM5100_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */

2237

#define WM5100_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */

2238

#define WM5100_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */

2239

#define WM5100_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */

2240

#define WM5100_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */

2241

#define WM5100_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */

2242

#define WM5100_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */

2243

#define WM5100_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */

2244

#define WM5100_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */

2245

2246

/*

2247

* R1217 (0x4C1) - PDM SPK1 CTRL 2

2248

*/

2249

#define WM5100_SPK1_FMT 0x0001 /* SPK1_FMT */

2250

#define WM5100_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */

2251

#define WM5100_SPK1_FMT_SHIFT 0 /* SPK1_FMT */

2252

#define WM5100_SPK1_FMT_WIDTH 1 /* SPK1_FMT */

2253

2254

/*

2255

* R1218 (0x4C2) - PDM SPK2 CTRL 1

2256

*/

2257

#define WM5100_SPK2R_MUTE 0x2000 /* SPK2R_MUTE */

2258

#define WM5100_SPK2R_MUTE_MASK 0x2000 /* SPK2R_MUTE */

2259

#define WM5100_SPK2R_MUTE_SHIFT 13 /* SPK2R_MUTE */

2260

#define WM5100_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */

2261

#define WM5100_SPK2L_MUTE 0x1000 /* SPK2L_MUTE */

2262

#define WM5100_SPK2L_MUTE_MASK 0x1000 /* SPK2L_MUTE */

2263

#define WM5100_SPK2L_MUTE_SHIFT 12 /* SPK2L_MUTE */

2264

#define WM5100_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */

2265

#define WM5100_SPK2_MUTE_ENDIAN 0x0100 /* SPK2_MUTE_ENDIAN */

2266

#define WM5100_SPK2_MUTE_ENDIAN_MASK 0x0100 /* SPK2_MUTE_ENDIAN */

2267

#define WM5100_SPK2_MUTE_ENDIAN_SHIFT 8 /* SPK2_MUTE_ENDIAN */

2268

#define WM5100_SPK2_MUTE_ENDIAN_WIDTH 1 /* SPK2_MUTE_ENDIAN */

2269

#define WM5100_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */

2270

#define WM5100_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */

2271

#define WM5100_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */

2272

2273

/*

2274

* R1219 (0x4C3) - PDM SPK2 CTRL 2

2275

*/

2276

#define WM5100_SPK2_FMT 0x0001 /* SPK2_FMT */

2277

#define WM5100_SPK2_FMT_MASK 0x0001 /* SPK2_FMT */

2278

#define WM5100_SPK2_FMT_SHIFT 0 /* SPK2_FMT */

2279

#define WM5100_SPK2_FMT_WIDTH 1 /* SPK2_FMT */

2280

2281

/*

2282

* R1280 (0x500) - Audio IF 1_1

2283

*/

2284

#define WM5100_AIF1_BCLK_INV 0x0080 /* AIF1_BCLK_INV */

2285

#define WM5100_AIF1_BCLK_INV_MASK 0x0080 /* AIF1_BCLK_INV */

2286

#define WM5100_AIF1_BCLK_INV_SHIFT 7 /* AIF1_BCLK_INV */

2287

#define WM5100_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */

2288

#define WM5100_AIF1_BCLK_FRC 0x0040 /* AIF1_BCLK_FRC */

2289

#define WM5100_AIF1_BCLK_FRC_MASK 0x0040 /* AIF1_BCLK_FRC */

2290

#define WM5100_AIF1_BCLK_FRC_SHIFT 6 /* AIF1_BCLK_FRC */

2291

#define WM5100_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */

2292

#define WM5100_AIF1_BCLK_MSTR 0x0020 /* AIF1_BCLK_MSTR */

2293

#define WM5100_AIF1_BCLK_MSTR_MASK 0x0020 /* AIF1_BCLK_MSTR */

2294

#define WM5100_AIF1_BCLK_MSTR_SHIFT 5 /* AIF1_BCLK_MSTR */

2295

#define WM5100_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */

2296

#define WM5100_AIF1_BCLK_FREQ_MASK 0x001F /* AIF1_BCLK_FREQ - [4:0] */

2297

#define WM5100_AIF1_BCLK_FREQ_SHIFT 0 /* AIF1_BCLK_FREQ - [4:0] */

2298

#define WM5100_AIF1_BCLK_FREQ_WIDTH 5 /* AIF1_BCLK_FREQ - [4:0] */

2299

2300

/*

2301

* R1281 (0x501) - Audio IF 1_2

2302

*/

2303

#define WM5100_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */

2304

#define WM5100_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */

2305

#define WM5100_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */

2306

#define WM5100_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */

2307

#define WM5100_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */

2308

#define WM5100_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */

2309

#define WM5100_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */

2310

#define WM5100_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */

2311

#define WM5100_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */

2312

#define WM5100_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */

2313

#define WM5100_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */

2314

#define WM5100_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */

2315

#define WM5100_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */

2316

#define WM5100_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */

2317

#define WM5100_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */

2318

#define WM5100_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */

2319

#define WM5100_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */

2320

#define WM5100_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */

2321

#define WM5100_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */

2322

#define WM5100_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */

2323

2324

/*

2325

* R1282 (0x502) - Audio IF 1_3

2326

*/

2327

#define WM5100_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */

2328

#define WM5100_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */

2329

#define WM5100_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */

2330

#define WM5100_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */

2331

#define WM5100_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */

2332

#define WM5100_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */

2333

#define WM5100_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */

2334

#define WM5100_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */

2335

#define WM5100_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */

2336

#define WM5100_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */

2337

#define WM5100_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */

2338

#define WM5100_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */

2339

2340

/*

2341

* R1283 (0x503) - Audio IF 1_4

2342

*/

2343

#define WM5100_AIF1_TRI 0x0040 /* AIF1_TRI */

2344

#define WM5100_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */

2345

#define WM5100_AIF1_TRI_SHIFT 6 /* AIF1_TRI */

2346

#define WM5100_AIF1_TRI_WIDTH 1 /* AIF1_TRI */

2347

#define WM5100_AIF1_RATE_MASK 0x0003 /* AIF1_RATE - [1:0] */

2348

#define WM5100_AIF1_RATE_SHIFT 0 /* AIF1_RATE - [1:0] */

2349

#define WM5100_AIF1_RATE_WIDTH 2 /* AIF1_RATE - [1:0] */

2350

2351

/*

2352

* R1284 (0x504) - Audio IF 1_5

2353

*/

2354

#define WM5100_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */

2355

#define WM5100_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */

2356

#define WM5100_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */

2357

2358

/*

2359

* R1285 (0x505) - Audio IF 1_6

2360

*/

2361

#define WM5100_AIF1TX_BCPF_MASK 0x1FFF /* AIF1TX_BCPF - [12:0] */

2362

#define WM5100_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [12:0] */

2363

#define WM5100_AIF1TX_BCPF_WIDTH 13 /* AIF1TX_BCPF - [12:0] */

2364

2365

/*

2366

* R1286 (0x506) - Audio IF 1_7

2367

*/

2368

#define WM5100_AIF1RX_BCPF_MASK 0x1FFF /* AIF1RX_BCPF - [12:0] */

2369

#define WM5100_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [12:0] */

2370

#define WM5100_AIF1RX_BCPF_WIDTH 13 /* AIF1RX_BCPF - [12:0] */

2371

2372

/*

2373

* R1287 (0x507) - Audio IF 1_8

2374

*/

2375

#define WM5100_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */

2376

#define WM5100_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */

2377

#define WM5100_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */

2378

#define WM5100_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */

2379

#define WM5100_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */

2380

#define WM5100_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */

2381

2382

/*

2383

* R1288 (0x508) - Audio IF 1_9

2384

*/

2385

#define WM5100_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */

2386

#define WM5100_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */

2387

#define WM5100_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */

2388

#define WM5100_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */

2389

#define WM5100_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */

2390

#define WM5100_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */

2391

2392

/*

2393

* R1289 (0x509) - Audio IF 1_10

2394

*/

2395

#define WM5100_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */

2396

#define WM5100_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */

2397

#define WM5100_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */

2398

2399

/*

2400

* R1290 (0x50A) - Audio IF 1_11

2401

*/

2402

#define WM5100_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */

2403

#define WM5100_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */

2404

#define WM5100_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */

2405

2406

/*

2407

* R1291 (0x50B) - Audio IF 1_12

2408

*/

2409

#define WM5100_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */

2410

#define WM5100_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */

2411

#define WM5100_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */

2412

2413

/*

2414

* R1292 (0x50C) - Audio IF 1_13

2415

*/

2416

#define WM5100_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */

2417

#define WM5100_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */

2418

#define WM5100_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */

2419

2420

/*

2421

* R1293 (0x50D) - Audio IF 1_14

2422

*/

2423

#define WM5100_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */

2424

#define WM5100_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */

2425

#define WM5100_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */

2426

2427

/*

2428

* R1294 (0x50E) - Audio IF 1_15

2429

*/

2430

#define WM5100_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */

2431

#define WM5100_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */

2432

#define WM5100_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */

2433

2434

/*

2435

* R1295 (0x50F) - Audio IF 1_16

2436

*/

2437

#define WM5100_AIF1TX7_SLOT_MASK 0x003F /* AIF1TX7_SLOT - [5:0] */

2438

#define WM5100_AIF1TX7_SLOT_SHIFT 0 /* AIF1TX7_SLOT - [5:0] */

2439

#define WM5100_AIF1TX7_SLOT_WIDTH 6 /* AIF1TX7_SLOT - [5:0] */

2440

2441

/*

2442

* R1296 (0x510) - Audio IF 1_17

2443

*/

2444

#define WM5100_AIF1TX8_SLOT_MASK 0x003F /* AIF1TX8_SLOT - [5:0] */

2445

#define WM5100_AIF1TX8_SLOT_SHIFT 0 /* AIF1TX8_SLOT - [5:0] */

2446

#define WM5100_AIF1TX8_SLOT_WIDTH 6 /* AIF1TX8_SLOT - [5:0] */

2447

2448

/*

2449

* R1297 (0x511) - Audio IF 1_18

2450

*/

2451

#define WM5100_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */

2452

#define WM5100_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */

2453

#define WM5100_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */

2454

2455

/*

2456

* R1298 (0x512) - Audio IF 1_19

2457

*/

2458

#define WM5100_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */

2459

#define WM5100_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */

2460

#define WM5100_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */

2461

2462

/*

2463

* R1299 (0x513) - Audio IF 1_20

2464

*/

2465

#define WM5100_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */

2466

#define WM5100_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */

2467

#define WM5100_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */

2468

2469

/*

2470

* R1300 (0x514) - Audio IF 1_21

2471

*/

2472

#define WM5100_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */

2473

#define WM5100_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */

2474

#define WM5100_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */

2475

2476

/*

2477

* R1301 (0x515) - Audio IF 1_22

2478

*/

2479

#define WM5100_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */

2480

#define WM5100_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */

2481

#define WM5100_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */

2482

2483

/*

2484

* R1302 (0x516) - Audio IF 1_23

2485

*/

2486

#define WM5100_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */

2487

#define WM5100_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */

2488

#define WM5100_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */

2489

2490

/*

2491

* R1303 (0x517) - Audio IF 1_24

2492

*/

2493

#define WM5100_AIF1RX7_SLOT_MASK 0x003F /* AIF1RX7_SLOT - [5:0] */

2494

#define WM5100_AIF1RX7_SLOT_SHIFT 0 /* AIF1RX7_SLOT - [5:0] */

2495

#define WM5100_AIF1RX7_SLOT_WIDTH 6 /* AIF1RX7_SLOT - [5:0] */

2496

2497

/*

2498

* R1304 (0x518) - Audio IF 1_25

2499

*/

2500

#define WM5100_AIF1RX8_SLOT_MASK 0x003F /* AIF1RX8_SLOT - [5:0] */

2501

#define WM5100_AIF1RX8_SLOT_SHIFT 0 /* AIF1RX8_SLOT - [5:0] */

2502

#define WM5100_AIF1RX8_SLOT_WIDTH 6 /* AIF1RX8_SLOT - [5:0] */

2503

2504

/*

2505

* R1305 (0x519) - Audio IF 1_26

2506

*/

2507

#define WM5100_AIF1TX8_ENA 0x0080 /* AIF1TX8_ENA */

2508

#define WM5100_AIF1TX8_ENA_MASK 0x0080 /* AIF1TX8_ENA */

2509

#define WM5100_AIF1TX8_ENA_SHIFT 7 /* AIF1TX8_ENA */

2510

#define WM5100_AIF1TX8_ENA_WIDTH 1 /* AIF1TX8_ENA */

2511

#define WM5100_AIF1TX7_ENA 0x0040 /* AIF1TX7_ENA */

2512

#define WM5100_AIF1TX7_ENA_MASK 0x0040 /* AIF1TX7_ENA */

2513

#define WM5100_AIF1TX7_ENA_SHIFT 6 /* AIF1TX7_ENA */

2514

#define WM5100_AIF1TX7_ENA_WIDTH 1 /* AIF1TX7_ENA */

2515

#define WM5100_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */

2516

#define WM5100_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */

2517

#define WM5100_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */

2518

#define WM5100_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */

2519

#define WM5100_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */

2520

#define WM5100_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */

2521

#define WM5100_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */

2522

#define WM5100_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */

2523

#define WM5100_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */

2524

#define WM5100_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */

2525

#define WM5100_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */

2526

#define WM5100_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */

2527

#define WM5100_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */

2528

#define WM5100_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */

2529

#define WM5100_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */

2530

#define WM5100_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */

2531

#define WM5100_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */

2532

#define WM5100_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */

2533

#define WM5100_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */

2534

#define WM5100_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */

2535

#define WM5100_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */

2536

#define WM5100_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */

2537

#define WM5100_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */

2538

#define WM5100_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */

2539

2540

/*

2541

* R1306 (0x51A) - Audio IF 1_27

2542

*/

2543

#define WM5100_AIF1RX8_ENA 0x0080 /* AIF1RX8_ENA */

2544

#define WM5100_AIF1RX8_ENA_MASK 0x0080 /* AIF1RX8_ENA */

2545

#define WM5100_AIF1RX8_ENA_SHIFT 7 /* AIF1RX8_ENA */

2546

#define WM5100_AIF1RX8_ENA_WIDTH 1 /* AIF1RX8_ENA */

2547

#define WM5100_AIF1RX7_ENA 0x0040 /* AIF1RX7_ENA */

2548

#define WM5100_AIF1RX7_ENA_MASK 0x0040 /* AIF1RX7_ENA */

2549

#define WM5100_AIF1RX7_ENA_SHIFT 6 /* AIF1RX7_ENA */

2550

#define WM5100_AIF1RX7_ENA_WIDTH 1 /* AIF1RX7_ENA */

2551

#define WM5100_AIF1RX6_ENA 0x0020 /* AIF1RX6_ENA */

2552

#define WM5100_AIF1RX6_ENA_MASK 0x0020 /* AIF1RX6_ENA */

2553

#define WM5100_AIF1RX6_ENA_SHIFT 5 /* AIF1RX6_ENA */

2554

#define WM5100_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */

2555

#define WM5100_AIF1RX5_ENA 0x0010 /* AIF1RX5_ENA */

2556

#define WM5100_AIF1RX5_ENA_MASK 0x0010 /* AIF1RX5_ENA */

2557

#define WM5100_AIF1RX5_ENA_SHIFT 4 /* AIF1RX5_ENA */

2558

#define WM5100_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */

2559

#define WM5100_AIF1RX4_ENA 0x0008 /* AIF1RX4_ENA */

2560

#define WM5100_AIF1RX4_ENA_MASK 0x0008 /* AIF1RX4_ENA */

2561

#define WM5100_AIF1RX4_ENA_SHIFT 3 /* AIF1RX4_ENA */

2562

#define WM5100_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */

2563

#define WM5100_AIF1RX3_ENA 0x0004 /* AIF1RX3_ENA */

2564

#define WM5100_AIF1RX3_ENA_MASK 0x0004 /* AIF1RX3_ENA */

2565

#define WM5100_AIF1RX3_ENA_SHIFT 2 /* AIF1RX3_ENA */

2566

#define WM5100_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */

2567

#define WM5100_AIF1RX2_ENA 0x0002 /* AIF1RX2_ENA */

2568

#define WM5100_AIF1RX2_ENA_MASK 0x0002 /* AIF1RX2_ENA */

2569

#define WM5100_AIF1RX2_ENA_SHIFT 1 /* AIF1RX2_ENA */

2570

#define WM5100_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */

2571

#define WM5100_AIF1RX1_ENA 0x0001 /* AIF1RX1_ENA */

2572

#define WM5100_AIF1RX1_ENA_MASK 0x0001 /* AIF1RX1_ENA */

2573

#define WM5100_AIF1RX1_ENA_SHIFT 0 /* AIF1RX1_ENA */

2574

#define WM5100_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */

2575

2576

/*

2577

* R1344 (0x540) - Audio IF 2_1

2578

*/

2579

#define WM5100_AIF2_BCLK_INV 0x0080 /* AIF2_BCLK_INV */

2580

#define WM5100_AIF2_BCLK_INV_MASK 0x0080 /* AIF2_BCLK_INV */

2581

#define WM5100_AIF2_BCLK_INV_SHIFT 7 /* AIF2_BCLK_INV */

2582

#define WM5100_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */

2583

#define WM5100_AIF2_BCLK_FRC 0x0040 /* AIF2_BCLK_FRC */

2584

#define WM5100_AIF2_BCLK_FRC_MASK 0x0040 /* AIF2_BCLK_FRC */

2585

#define WM5100_AIF2_BCLK_FRC_SHIFT 6 /* AIF2_BCLK_FRC */

2586

#define WM5100_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */

2587

#define WM5100_AIF2_BCLK_MSTR 0x0020 /* AIF2_BCLK_MSTR */

2588

#define WM5100_AIF2_BCLK_MSTR_MASK 0x0020 /* AIF2_BCLK_MSTR */

2589

#define WM5100_AIF2_BCLK_MSTR_SHIFT 5 /* AIF2_BCLK_MSTR */

2590

#define WM5100_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */

2591

#define WM5100_AIF2_BCLK_FREQ_MASK 0x001F /* AIF2_BCLK_FREQ - [4:0] */

2592

#define WM5100_AIF2_BCLK_FREQ_SHIFT 0 /* AIF2_BCLK_FREQ - [4:0] */

2593

#define WM5100_AIF2_BCLK_FREQ_WIDTH 5 /* AIF2_BCLK_FREQ - [4:0] */

2594

2595

/*

2596

* R1345 (0x541) - Audio IF 2_2

2597

*/

2598

#define WM5100_AIF2TX_DAT_TRI 0x0020 /* AIF2TX_DAT_TRI */

2599

#define WM5100_AIF2TX_DAT_TRI_MASK 0x0020 /* AIF2TX_DAT_TRI */

2600

#define WM5100_AIF2TX_DAT_TRI_SHIFT 5 /* AIF2TX_DAT_TRI */

2601

#define WM5100_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */

2602

#define WM5100_AIF2TX_LRCLK_SRC 0x0008 /* AIF2TX_LRCLK_SRC */

2603

#define WM5100_AIF2TX_LRCLK_SRC_MASK 0x0008 /* AIF2TX_LRCLK_SRC */

2604

#define WM5100_AIF2TX_LRCLK_SRC_SHIFT 3 /* AIF2TX_LRCLK_SRC */

2605

#define WM5100_AIF2TX_LRCLK_SRC_WIDTH 1 /* AIF2TX_LRCLK_SRC */

2606

#define WM5100_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */

2607

#define WM5100_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */

2608

#define WM5100_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */

2609

#define WM5100_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */

2610

#define WM5100_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */

2611

#define WM5100_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */

2612

#define WM5100_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */

2613

#define WM5100_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */

2614

#define WM5100_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */

2615

#define WM5100_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */

2616

#define WM5100_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */

2617

#define WM5100_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */

2618

2619

/*

2620

* R1346 (0x542) - Audio IF 2_3

2621

*/

2622

#define WM5100_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */

2623

#define WM5100_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */

2624

#define WM5100_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */

2625

#define WM5100_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */

2626

#define WM5100_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */

2627

#define WM5100_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */

2628

#define WM5100_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */

2629

#define WM5100_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */

2630

#define WM5100_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */

2631

#define WM5100_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */

2632

#define WM5100_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */

2633

#define WM5100_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */

2634

2635

/*

2636

* R1347 (0x543) - Audio IF 2_4

2637

*/

2638

#define WM5100_AIF2_TRI 0x0040 /* AIF2_TRI */

2639

#define WM5100_AIF2_TRI_MASK 0x0040 /* AIF2_TRI */

2640

#define WM5100_AIF2_TRI_SHIFT 6 /* AIF2_TRI */

2641

#define WM5100_AIF2_TRI_WIDTH 1 /* AIF2_TRI */

2642

#define WM5100_AIF2_RATE_MASK 0x0003 /* AIF2_RATE - [1:0] */

2643

#define WM5100_AIF2_RATE_SHIFT 0 /* AIF2_RATE - [1:0] */

2644

#define WM5100_AIF2_RATE_WIDTH 2 /* AIF2_RATE - [1:0] */

2645

2646

/*

2647

* R1348 (0x544) - Audio IF 2_5

2648

*/

2649

#define WM5100_AIF2_FMT_MASK 0x0007 /* AIF2_FMT - [2:0] */

2650

#define WM5100_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [2:0] */

2651

#define WM5100_AIF2_FMT_WIDTH 3 /* AIF2_FMT - [2:0] */

2652

2653

/*

2654

* R1349 (0x545) - Audio IF 2_6

2655

*/

2656

#define WM5100_AIF2TX_BCPF_MASK 0x1FFF /* AIF2TX_BCPF - [12:0] */

2657

#define WM5100_AIF2TX_BCPF_SHIFT 0 /* AIF2TX_BCPF - [12:0] */

2658

#define WM5100_AIF2TX_BCPF_WIDTH 13 /* AIF2TX_BCPF - [12:0] */

2659

2660

/*

2661

* R1350 (0x546) - Audio IF 2_7

2662

*/

2663

#define WM5100_AIF2RX_BCPF_MASK 0x1FFF /* AIF2RX_BCPF - [12:0] */

2664

#define WM5100_AIF2RX_BCPF_SHIFT 0 /* AIF2RX_BCPF - [12:0] */

2665

#define WM5100_AIF2RX_BCPF_WIDTH 13 /* AIF2RX_BCPF - [12:0] */

2666

2667

/*

2668

* R1351 (0x547) - Audio IF 2_8

2669

*/

2670

#define WM5100_AIF2TX_WL_MASK 0x3F00 /* AIF2TX_WL - [13:8] */

2671

#define WM5100_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [13:8] */

2672

#define WM5100_AIF2TX_WL_WIDTH 6 /* AIF2TX_WL - [13:8] */

2673

#define WM5100_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */

2674

#define WM5100_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */

2675

#define WM5100_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */

2676

2677

/*

2678

* R1352 (0x548) - Audio IF 2_9

2679

*/

2680

#define WM5100_AIF2RX_WL_MASK 0x3F00 /* AIF2RX_WL - [13:8] */

2681

#define WM5100_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [13:8] */

2682

#define WM5100_AIF2RX_WL_WIDTH 6 /* AIF2RX_WL - [13:8] */

2683

#define WM5100_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */

2684

#define WM5100_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */

2685

#define WM5100_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */

2686

2687

/*

2688

* R1353 (0x549) - Audio IF 2_10

2689

*/

2690

#define WM5100_AIF2TX1_SLOT_MASK 0x003F /* AIF2TX1_SLOT - [5:0] */

2691

#define WM5100_AIF2TX1_SLOT_SHIFT 0 /* AIF2TX1_SLOT - [5:0] */

2692

#define WM5100_AIF2TX1_SLOT_WIDTH 6 /* AIF2TX1_SLOT - [5:0] */

2693

2694

/*

2695

* R1354 (0x54A) - Audio IF 2_11

2696

*/

2697

#define WM5100_AIF2TX2_SLOT_MASK 0x003F /* AIF2TX2_SLOT - [5:0] */

2698

#define WM5100_AIF2TX2_SLOT_SHIFT 0 /* AIF2TX2_SLOT - [5:0] */

2699

#define WM5100_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */

2700

2701

/*

2702

* R1361 (0x551) - Audio IF 2_18

2703

*/

2704

#define WM5100_AIF2RX1_SLOT_MASK 0x003F /* AIF2RX1_SLOT - [5:0] */

2705

#define WM5100_AIF2RX1_SLOT_SHIFT 0 /* AIF2RX1_SLOT - [5:0] */

2706

#define WM5100_AIF2RX1_SLOT_WIDTH 6 /* AIF2RX1_SLOT - [5:0] */

2707

2708

/*

2709

* R1362 (0x552) - Audio IF 2_19

2710

*/

2711

#define WM5100_AIF2RX2_SLOT_MASK 0x003F /* AIF2RX2_SLOT - [5:0] */

2712

#define WM5100_AIF2RX2_SLOT_SHIFT 0 /* AIF2RX2_SLOT - [5:0] */

2713

#define WM5100_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */

2714

2715

/*

2716

* R1369 (0x559) - Audio IF 2_26

2717

*/

2718

#define WM5100_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */

2719

#define WM5100_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */

2720

#define WM5100_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */

2721

#define WM5100_AIF2TX2_ENA_WIDTH 1 /* AIF2TX2_ENA */

2722

#define WM5100_AIF2TX1_ENA 0x0001 /* AIF2TX1_ENA */

2723

#define WM5100_AIF2TX1_ENA_MASK 0x0001 /* AIF2TX1_ENA */

2724

#define WM5100_AIF2TX1_ENA_SHIFT 0 /* AIF2TX1_ENA */

2725

#define WM5100_AIF2TX1_ENA_WIDTH 1 /* AIF2TX1_ENA */

2726

2727

/*

2728

* R1370 (0x55A) - Audio IF 2_27

2729

*/

2730

#define WM5100_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */

2731

#define WM5100_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */

2732

#define WM5100_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */

2733

#define WM5100_AIF2RX2_ENA_WIDTH 1 /* AIF2RX2_ENA */

2734

#define WM5100_AIF2RX1_ENA 0x0001 /* AIF2RX1_ENA */

2735

#define WM5100_AIF2RX1_ENA_MASK 0x0001 /* AIF2RX1_ENA */

2736

#define WM5100_AIF2RX1_ENA_SHIFT 0 /* AIF2RX1_ENA */

2737

#define WM5100_AIF2RX1_ENA_WIDTH 1 /* AIF2RX1_ENA */

2738

2739

/*

2740

* R1408 (0x580) - Audio IF 3_1

2741

*/

2742

#define WM5100_AIF3_BCLK_INV 0x0080 /* AIF3_BCLK_INV */

2743

#define WM5100_AIF3_BCLK_INV_MASK 0x0080 /* AIF3_BCLK_INV */

2744

#define WM5100_AIF3_BCLK_INV_SHIFT 7 /* AIF3_BCLK_INV */

2745

#define WM5100_AIF3_BCLK_INV_WIDTH 1 /* AIF3_BCLK_INV */

2746

#define WM5100_AIF3_BCLK_FRC 0x0040 /* AIF3_BCLK_FRC */

2747

#define WM5100_AIF3_BCLK_FRC_MASK 0x0040 /* AIF3_BCLK_FRC */

2748

#define WM5100_AIF3_BCLK_FRC_SHIFT 6 /* AIF3_BCLK_FRC */

2749

#define WM5100_AIF3_BCLK_FRC_WIDTH 1 /* AIF3_BCLK_FRC */

2750

#define WM5100_AIF3_BCLK_MSTR 0x0020 /* AIF3_BCLK_MSTR */

2751

#define WM5100_AIF3_BCLK_MSTR_MASK 0x0020 /* AIF3_BCLK_MSTR */

2752

#define WM5100_AIF3_BCLK_MSTR_SHIFT 5 /* AIF3_BCLK_MSTR */

2753

#define WM5100_AIF3_BCLK_MSTR_WIDTH 1 /* AIF3_BCLK_MSTR */

2754

#define WM5100_AIF3_BCLK_FREQ_MASK 0x001F /* AIF3_BCLK_FREQ - [4:0] */

2755

#define WM5100_AIF3_BCLK_FREQ_SHIFT 0 /* AIF3_BCLK_FREQ - [4:0] */

2756

#define WM5100_AIF3_BCLK_FREQ_WIDTH 5 /* AIF3_BCLK_FREQ - [4:0] */

2757

2758

/*

2759

* R1409 (0x581) - Audio IF 3_2

2760

*/

2761

#define WM5100_AIF3TX_DAT_TRI 0x0020 /* AIF3TX_DAT_TRI */

2762

#define WM5100_AIF3TX_DAT_TRI_MASK 0x0020 /* AIF3TX_DAT_TRI */

2763

#define WM5100_AIF3TX_DAT_TRI_SHIFT 5 /* AIF3TX_DAT_TRI */

2764

#define WM5100_AIF3TX_DAT_TRI_WIDTH 1 /* AIF3TX_DAT_TRI */

2765

#define WM5100_AIF3TX_LRCLK_SRC 0x0008 /* AIF3TX_LRCLK_SRC */

2766

#define WM5100_AIF3TX_LRCLK_SRC_MASK 0x0008 /* AIF3TX_LRCLK_SRC */

2767

#define WM5100_AIF3TX_LRCLK_SRC_SHIFT 3 /* AIF3TX_LRCLK_SRC */

2768

#define WM5100_AIF3TX_LRCLK_SRC_WIDTH 1 /* AIF3TX_LRCLK_SRC */

2769

#define WM5100_AIF3TX_LRCLK_INV 0x0004 /* AIF3TX_LRCLK_INV */

2770

#define WM5100_AIF3TX_LRCLK_INV_MASK 0x0004 /* AIF3TX_LRCLK_INV */

2771

#define WM5100_AIF3TX_LRCLK_INV_SHIFT 2 /* AIF3TX_LRCLK_INV */

2772

#define WM5100_AIF3TX_LRCLK_INV_WIDTH 1 /* AIF3TX_LRCLK_INV */

2773

#define WM5100_AIF3TX_LRCLK_FRC 0x0002 /* AIF3TX_LRCLK_FRC */

2774

#define WM5100_AIF3TX_LRCLK_FRC_MASK 0x0002 /* AIF3TX_LRCLK_FRC */

2775

#define WM5100_AIF3TX_LRCLK_FRC_SHIFT 1 /* AIF3TX_LRCLK_FRC */

2776

#define WM5100_AIF3TX_LRCLK_FRC_WIDTH 1 /* AIF3TX_LRCLK_FRC */

2777

#define WM5100_AIF3TX_LRCLK_MSTR 0x0001 /* AIF3TX_LRCLK_MSTR */

2778

#define WM5100_AIF3TX_LRCLK_MSTR_MASK 0x0001 /* AIF3TX_LRCLK_MSTR */

2779

#define WM5100_AIF3TX_LRCLK_MSTR_SHIFT 0 /* AIF3TX_LRCLK_MSTR */

2780

#define WM5100_AIF3TX_LRCLK_MSTR_WIDTH 1 /* AIF3TX_LRCLK_MSTR */

2781

2782

/*

2783

* R1410 (0x582) - Audio IF 3_3

2784

*/

2785

#define WM5100_AIF3RX_LRCLK_INV 0x0004 /* AIF3RX_LRCLK_INV */

2786

#define WM5100_AIF3RX_LRCLK_INV_MASK 0x0004 /* AIF3RX_LRCLK_INV */

2787

#define WM5100_AIF3RX_LRCLK_INV_SHIFT 2 /* AIF3RX_LRCLK_INV */

2788

#define WM5100_AIF3RX_LRCLK_INV_WIDTH 1 /* AIF3RX_LRCLK_INV */

2789

#define WM5100_AIF3RX_LRCLK_FRC 0x0002 /* AIF3RX_LRCLK_FRC */

2790

#define WM5100_AIF3RX_LRCLK_FRC_MASK 0x0002 /* AIF3RX_LRCLK_FRC */

2791

#define WM5100_AIF3RX_LRCLK_FRC_SHIFT 1 /* AIF3RX_LRCLK_FRC */

2792

#define WM5100_AIF3RX_LRCLK_FRC_WIDTH 1 /* AIF3RX_LRCLK_FRC */

2793

#define WM5100_AIF3RX_LRCLK_MSTR 0x0001 /* AIF3RX_LRCLK_MSTR */

2794

#define WM5100_AIF3RX_LRCLK_MSTR_MASK 0x0001 /* AIF3RX_LRCLK_MSTR */

2795

#define WM5100_AIF3RX_LRCLK_MSTR_SHIFT 0 /* AIF3RX_LRCLK_MSTR */

2796

#define WM5100_AIF3RX_LRCLK_MSTR_WIDTH 1 /* AIF3RX_LRCLK_MSTR */

2797

2798

/*

2799

* R1411 (0x583) - Audio IF 3_4

2800

*/

2801

#define WM5100_AIF3_TRI 0x0040 /* AIF3_TRI */

2802

#define WM5100_AIF3_TRI_MASK 0x0040 /* AIF3_TRI */

2803

#define WM5100_AIF3_TRI_SHIFT 6 /* AIF3_TRI */

2804

#define WM5100_AIF3_TRI_WIDTH 1 /* AIF3_TRI */

2805

#define WM5100_AIF3_RATE_MASK 0x0003 /* AIF3_RATE - [1:0] */

2806

#define WM5100_AIF3_RATE_SHIFT 0 /* AIF3_RATE - [1:0] */

2807

#define WM5100_AIF3_RATE_WIDTH 2 /* AIF3_RATE - [1:0] */

2808

2809

/*

2810

* R1412 (0x584) - Audio IF 3_5

2811

*/

2812

#define WM5100_AIF3_FMT_MASK 0x0007 /* AIF3_FMT - [2:0] */

2813

#define WM5100_AIF3_FMT_SHIFT 0 /* AIF3_FMT - [2:0] */

2814

#define WM5100_AIF3_FMT_WIDTH 3 /* AIF3_FMT - [2:0] */

2815

2816

/*

2817

* R1413 (0x585) - Audio IF 3_6

2818

*/

2819

#define WM5100_AIF3TX_BCPF_MASK 0x1FFF /* AIF3TX_BCPF - [12:0] */

2820

#define WM5100_AIF3TX_BCPF_SHIFT 0 /* AIF3TX_BCPF - [12:0] */

2821

#define WM5100_AIF3TX_BCPF_WIDTH 13 /* AIF3TX_BCPF - [12:0] */

2822

2823

/*

2824

* R1414 (0x586) - Audio IF 3_7

2825

*/

2826

#define WM5100_AIF3RX_BCPF_MASK 0x1FFF /* AIF3RX_BCPF - [12:0] */

2827

#define WM5100_AIF3RX_BCPF_SHIFT 0 /* AIF3RX_BCPF - [12:0] */

2828

#define WM5100_AIF3RX_BCPF_WIDTH 13 /* AIF3RX_BCPF - [12:0] */

2829

2830

/*

2831

* R1415 (0x587) - Audio IF 3_8

2832

*/

2833

#define WM5100_AIF3TX_WL_MASK 0x3F00 /* AIF3TX_WL - [13:8] */

2834

#define WM5100_AIF3TX_WL_SHIFT 8 /* AIF3TX_WL - [13:8] */

2835

#define WM5100_AIF3TX_WL_WIDTH 6 /* AIF3TX_WL - [13:8] */

2836

#define WM5100_AIF3TX_SLOT_LEN_MASK 0x00FF /* AIF3TX_SLOT_LEN - [7:0] */

2837

#define WM5100_AIF3TX_SLOT_LEN_SHIFT 0 /* AIF3TX_SLOT_LEN - [7:0] */

2838

#define WM5100_AIF3TX_SLOT_LEN_WIDTH 8 /* AIF3TX_SLOT_LEN - [7:0] */

2839

2840

/*

2841

* R1416 (0x588) - Audio IF 3_9

2842

*/

2843

#define WM5100_AIF3RX_WL_MASK 0x3F00 /* AIF3RX_WL - [13:8] */

2844

#define WM5100_AIF3RX_WL_SHIFT 8 /* AIF3RX_WL - [13:8] */

2845

#define WM5100_AIF3RX_WL_WIDTH 6 /* AIF3RX_WL - [13:8] */

2846

#define WM5100_AIF3RX_SLOT_LEN_MASK 0x00FF /* AIF3RX_SLOT_LEN - [7:0] */

2847

#define WM5100_AIF3RX_SLOT_LEN_SHIFT 0 /* AIF3RX_SLOT_LEN - [7:0] */

2848

#define WM5100_AIF3RX_SLOT_LEN_WIDTH 8 /* AIF3RX_SLOT_LEN - [7:0] */

2849

2850

/*

2851

* R1417 (0x589) - Audio IF 3_10

2852

*/

2853

#define WM5100_AIF3TX1_SLOT_MASK 0x003F /* AIF3TX1_SLOT - [5:0] */

2854

#define WM5100_AIF3TX1_SLOT_SHIFT 0 /* AIF3TX1_SLOT - [5:0] */

2855

#define WM5100_AIF3TX1_SLOT_WIDTH 6 /* AIF3TX1_SLOT - [5:0] */

2856

2857

/*

2858

* R1418 (0x58A) - Audio IF 3_11

2859

*/

2860

#define WM5100_AIF3TX2_SLOT_MASK 0x003F /* AIF3TX2_SLOT - [5:0] */

2861

#define WM5100_AIF3TX2_SLOT_SHIFT 0 /* AIF3TX2_SLOT - [5:0] */

2862

#define WM5100_AIF3TX2_SLOT_WIDTH 6 /* AIF3TX2_SLOT - [5:0] */

2863

2864

/*

2865

* R1425 (0x591) - Audio IF 3_18

2866

*/

2867

#define WM5100_AIF3RX1_SLOT_MASK 0x003F /* AIF3RX1_SLOT - [5:0] */

2868

#define WM5100_AIF3RX1_SLOT_SHIFT 0 /* AIF3RX1_SLOT - [5:0] */

2869

#define WM5100_AIF3RX1_SLOT_WIDTH 6 /* AIF3RX1_SLOT - [5:0] */

2870

2871

/*

2872

* R1426 (0x592) - Audio IF 3_19

2873

*/

2874

#define WM5100_AIF3RX2_SLOT_MASK 0x003F /* AIF3RX2_SLOT - [5:0] */

2875

#define WM5100_AIF3RX2_SLOT_SHIFT 0 /* AIF3RX2_SLOT - [5:0] */

2876

#define WM5100_AIF3RX2_SLOT_WIDTH 6 /* AIF3RX2_SLOT - [5:0] */

2877

2878

/*

2879

* R1433 (0x599) - Audio IF 3_26

2880

*/

2881

#define WM5100_AIF3TX2_ENA 0x0002 /* AIF3TX2_ENA */

2882

#define WM5100_AIF3TX2_ENA_MASK 0x0002 /* AIF3TX2_ENA */

2883

#define WM5100_AIF3TX2_ENA_SHIFT 1 /* AIF3TX2_ENA */

2884

#define WM5100_AIF3TX2_ENA_WIDTH 1 /* AIF3TX2_ENA */

2885

#define WM5100_AIF3TX1_ENA 0x0001 /* AIF3TX1_ENA */

2886

#define WM5100_AIF3TX1_ENA_MASK 0x0001 /* AIF3TX1_ENA */

2887

#define WM5100_AIF3TX1_ENA_SHIFT 0 /* AIF3TX1_ENA */

2888

#define WM5100_AIF3TX1_ENA_WIDTH 1 /* AIF3TX1_ENA */

2889

2890

/*

2891

* R1434 (0x59A) - Audio IF 3_27

2892

*/

2893

#define WM5100_AIF3RX2_ENA 0x0002 /* AIF3RX2_ENA */

2894

#define WM5100_AIF3RX2_ENA_MASK 0x0002 /* AIF3RX2_ENA */

2895

#define WM5100_AIF3RX2_ENA_SHIFT 1 /* AIF3RX2_ENA */

2896

#define WM5100_AIF3RX2_ENA_WIDTH 1 /* AIF3RX2_ENA */

2897

#define WM5100_AIF3RX1_ENA 0x0001 /* AIF3RX1_ENA */

2898

#define WM5100_AIF3RX1_ENA_MASK 0x0001 /* AIF3RX1_ENA */

2899

#define WM5100_AIF3RX1_ENA_SHIFT 0 /* AIF3RX1_ENA */

2900

#define WM5100_AIF3RX1_ENA_WIDTH 1 /* AIF3RX1_ENA */

2901

2902

#define WM5100_MIXER_VOL_MASK 0x00FE /* MIXER_VOL - [7:1] */

2903

#define WM5100_MIXER_VOL_SHIFT 1 /* MIXER_VOL - [7:1] */

2904

#define WM5100_MIXER_VOL_WIDTH 7 /* MIXER_VOL - [7:1] */

2905

2906

/*

2907

* R3072 (0xC00) - GPIO CTRL 1

2908

*/

2909

#define WM5100_GP1_DIR 0x8000 /* GP1_DIR */

2910

#define WM5100_GP1_DIR_MASK 0x8000 /* GP1_DIR */

2911

#define WM5100_GP1_DIR_SHIFT 15 /* GP1_DIR */

2912

#define WM5100_GP1_DIR_WIDTH 1 /* GP1_DIR */

2913

#define WM5100_GP1_PU 0x4000 /* GP1_PU */

2914

#define WM5100_GP1_PU_MASK 0x4000 /* GP1_PU */

2915

#define WM5100_GP1_PU_SHIFT 14 /* GP1_PU */

2916

#define WM5100_GP1_PU_WIDTH 1 /* GP1_PU */

2917

#define WM5100_GP1_PD 0x2000 /* GP1_PD */

2918

#define WM5100_GP1_PD_MASK 0x2000 /* GP1_PD */

2919

#define WM5100_GP1_PD_SHIFT 13 /* GP1_PD */

2920

#define WM5100_GP1_PD_WIDTH 1 /* GP1_PD */

2921

#define WM5100_GP1_POL 0x0400 /* GP1_POL */

2922

#define WM5100_GP1_POL_MASK 0x0400 /* GP1_POL */

2923

#define WM5100_GP1_POL_SHIFT 10 /* GP1_POL */

2924

#define WM5100_GP1_POL_WIDTH 1 /* GP1_POL */

2925

#define WM5100_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */

2926

#define WM5100_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */

2927

#define WM5100_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */

2928

#define WM5100_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */

2929

#define WM5100_GP1_DB 0x0100 /* GP1_DB */

2930

#define WM5100_GP1_DB_MASK 0x0100 /* GP1_DB */

2931

#define WM5100_GP1_DB_SHIFT 8 /* GP1_DB */

2932

#define WM5100_GP1_DB_WIDTH 1 /* GP1_DB */

2933

#define WM5100_GP1_LVL 0x0040 /* GP1_LVL */

2934

#define WM5100_GP1_LVL_MASK 0x0040 /* GP1_LVL */

2935

#define WM5100_GP1_LVL_SHIFT 6 /* GP1_LVL */

2936

#define WM5100_GP1_LVL_WIDTH 1 /* GP1_LVL */

2937

#define WM5100_GP1_FN_MASK 0x003F /* GP1_FN - [5:0] */

2938

#define WM5100_GP1_FN_SHIFT 0 /* GP1_FN - [5:0] */

2939

#define WM5100_GP1_FN_WIDTH 6 /* GP1_FN - [5:0] */

2940

2941

/*

2942

* R3073 (0xC01) - GPIO CTRL 2

2943

*/

2944

#define WM5100_GP2_DIR 0x8000 /* GP2_DIR */

2945

#define WM5100_GP2_DIR_MASK 0x8000 /* GP2_DIR */

2946

#define WM5100_GP2_DIR_SHIFT 15 /* GP2_DIR */

2947

#define WM5100_GP2_DIR_WIDTH 1 /* GP2_DIR */

2948

#define WM5100_GP2_PU 0x4000 /* GP2_PU */

2949

#define WM5100_GP2_PU_MASK 0x4000 /* GP2_PU */

2950

#define WM5100_GP2_PU_SHIFT 14 /* GP2_PU */

2951

#define WM5100_GP2_PU_WIDTH 1 /* GP2_PU */

2952

#define WM5100_GP2_PD 0x2000 /* GP2_PD */

2953

#define WM5100_GP2_PD_MASK 0x2000 /* GP2_PD */

2954

#define WM5100_GP2_PD_SHIFT 13 /* GP2_PD */

2955

#define WM5100_GP2_PD_WIDTH 1 /* GP2_PD */

2956

#define WM5100_GP2_POL 0x0400 /* GP2_POL */

2957

#define WM5100_GP2_POL_MASK 0x0400 /* GP2_POL */

2958

#define WM5100_GP2_POL_SHIFT 10 /* GP2_POL */

2959

#define WM5100_GP2_POL_WIDTH 1 /* GP2_POL */

2960

#define WM5100_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */

2961

#define WM5100_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */

2962

#define WM5100_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */

2963

#define WM5100_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */

2964

#define WM5100_GP2_DB 0x0100 /* GP2_DB */

2965

#define WM5100_GP2_DB_MASK 0x0100 /* GP2_DB */

2966

#define WM5100_GP2_DB_SHIFT 8 /* GP2_DB */

2967

#define WM5100_GP2_DB_WIDTH 1 /* GP2_DB */

2968

#define WM5100_GP2_LVL 0x0040 /* GP2_LVL */

2969

#define WM5100_GP2_LVL_MASK 0x0040 /* GP2_LVL */

2970

#define WM5100_GP2_LVL_SHIFT 6 /* GP2_LVL */

2971

#define WM5100_GP2_LVL_WIDTH 1 /* GP2_LVL */

2972

#define WM5100_GP2_FN_MASK 0x003F /* GP2_FN - [5:0] */

2973

#define WM5100_GP2_FN_SHIFT 0 /* GP2_FN - [5:0] */

2974

#define WM5100_GP2_FN_WIDTH 6 /* GP2_FN - [5:0] */

2975

2976

/*

2977

* R3074 (0xC02) - GPIO CTRL 3

2978

*/

2979

#define WM5100_GP3_DIR 0x8000 /* GP3_DIR */

2980

#define WM5100_GP3_DIR_MASK 0x8000 /* GP3_DIR */

2981

#define WM5100_GP3_DIR_SHIFT 15 /* GP3_DIR */

2982

#define WM5100_GP3_DIR_WIDTH 1 /* GP3_DIR */

2983

#define WM5100_GP3_PU 0x4000 /* GP3_PU */

2984

#define WM5100_GP3_PU_MASK 0x4000 /* GP3_PU */

2985

#define WM5100_GP3_PU_SHIFT 14 /* GP3_PU */

2986

#define WM5100_GP3_PU_WIDTH 1 /* GP3_PU */

2987

#define WM5100_GP3_PD 0x2000 /* GP3_PD */

2988

#define WM5100_GP3_PD_MASK 0x2000 /* GP3_PD */

2989

#define WM5100_GP3_PD_SHIFT 13 /* GP3_PD */

2990

#define WM5100_GP3_PD_WIDTH 1 /* GP3_PD */

2991

#define WM5100_GP3_POL 0x0400 /* GP3_POL */

2992

#define WM5100_GP3_POL_MASK 0x0400 /* GP3_POL */

2993

#define WM5100_GP3_POL_SHIFT 10 /* GP3_POL */

2994

#define WM5100_GP3_POL_WIDTH 1 /* GP3_POL */

2995

#define WM5100_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */

2996

#define WM5100_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */

2997

#define WM5100_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */

2998

#define WM5100_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */

2999

#define WM5100_GP3_DB 0x0100 /* GP3_DB */

3000

#define WM5100_GP3_DB_MASK 0x0100 /* GP3_DB */

3001

#define WM5100_GP3_DB_SHIFT 8 /* GP3_DB */

3002

#define WM5100_GP3_DB_WIDTH 1 /* GP3_DB */

3003

#define WM5100_GP3_LVL 0x0040 /* GP3_LVL */

3004

#define WM5100_GP3_LVL_MASK 0x0040 /* GP3_LVL */

3005

#define WM5100_GP3_LVL_SHIFT 6 /* GP3_LVL */

3006

#define WM5100_GP3_LVL_WIDTH 1 /* GP3_LVL */

3007

#define WM5100_GP3_FN_MASK 0x003F /* GP3_FN - [5:0] */

3008

#define WM5100_GP3_FN_SHIFT 0 /* GP3_FN - [5:0] */

3009

#define WM5100_GP3_FN_WIDTH 6 /* GP3_FN - [5:0] */

3010

3011

/*

3012

* R3075 (0xC03) - GPIO CTRL 4

3013

*/

3014

#define WM5100_GP4_DIR 0x8000 /* GP4_DIR */

3015

#define WM5100_GP4_DIR_MASK 0x8000 /* GP4_DIR */

3016

#define WM5100_GP4_DIR_SHIFT 15 /* GP4_DIR */

3017

#define WM5100_GP4_DIR_WIDTH 1 /* GP4_DIR */

3018

#define WM5100_GP4_PU 0x4000 /* GP4_PU */

3019

#define WM5100_GP4_PU_MASK 0x4000 /* GP4_PU */

3020

#define WM5100_GP4_PU_SHIFT 14 /* GP4_PU */

3021

#define WM5100_GP4_PU_WIDTH 1 /* GP4_PU */

3022

#define WM5100_GP4_PD 0x2000 /* GP4_PD */

3023

#define WM5100_GP4_PD_MASK 0x2000 /* GP4_PD */

3024

#define WM5100_GP4_PD_SHIFT 13 /* GP4_PD */

3025

#define WM5100_GP4_PD_WIDTH 1 /* GP4_PD */

3026

#define WM5100_GP4_POL 0x0400 /* GP4_POL */

3027

#define WM5100_GP4_POL_MASK 0x0400 /* GP4_POL */

3028

#define WM5100_GP4_POL_SHIFT 10 /* GP4_POL */

3029

#define WM5100_GP4_POL_WIDTH 1 /* GP4_POL */

3030

#define WM5100_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */

3031

#define WM5100_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */

3032

#define WM5100_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */

3033

#define WM5100_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */

3034

#define WM5100_GP4_DB 0x0100 /* GP4_DB */

3035

#define WM5100_GP4_DB_MASK 0x0100 /* GP4_DB */

3036

#define WM5100_GP4_DB_SHIFT 8 /* GP4_DB */

3037

#define WM5100_GP4_DB_WIDTH 1 /* GP4_DB */

3038

#define WM5100_GP4_LVL 0x0040 /* GP4_LVL */

3039

#define WM5100_GP4_LVL_MASK 0x0040 /* GP4_LVL */

3040

#define WM5100_GP4_LVL_SHIFT 6 /* GP4_LVL */

3041

#define WM5100_GP4_LVL_WIDTH 1 /* GP4_LVL */

3042

#define WM5100_GP4_FN_MASK 0x003F /* GP4_FN - [5:0] */

3043

#define WM5100_GP4_FN_SHIFT 0 /* GP4_FN - [5:0] */

3044

#define WM5100_GP4_FN_WIDTH 6 /* GP4_FN - [5:0] */

3045

3046

/*

3047

* R3076 (0xC04) - GPIO CTRL 5

3048

*/

3049

#define WM5100_GP5_DIR 0x8000 /* GP5_DIR */

3050

#define WM5100_GP5_DIR_MASK 0x8000 /* GP5_DIR */

3051

#define WM5100_GP5_DIR_SHIFT 15 /* GP5_DIR */

3052

#define WM5100_GP5_DIR_WIDTH 1 /* GP5_DIR */

3053

#define WM5100_GP5_PU 0x4000 /* GP5_PU */

3054

#define WM5100_GP5_PU_MASK 0x4000 /* GP5_PU */

3055

#define WM5100_GP5_PU_SHIFT 14 /* GP5_PU */

3056

#define WM5100_GP5_PU_WIDTH 1 /* GP5_PU */

3057

#define WM5100_GP5_PD 0x2000 /* GP5_PD */

3058

#define WM5100_GP5_PD_MASK 0x2000 /* GP5_PD */

3059

#define WM5100_GP5_PD_SHIFT 13 /* GP5_PD */

3060

#define WM5100_GP5_PD_WIDTH 1 /* GP5_PD */

3061

#define WM5100_GP5_POL 0x0400 /* GP5_POL */

3062

#define WM5100_GP5_POL_MASK 0x0400 /* GP5_POL */

3063

#define WM5100_GP5_POL_SHIFT 10 /* GP5_POL */

3064

#define WM5100_GP5_POL_WIDTH 1 /* GP5_POL */

3065

#define WM5100_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */

3066

#define WM5100_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */

3067

#define WM5100_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */

3068

#define WM5100_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */

3069

#define WM5100_GP5_DB 0x0100 /* GP5_DB */

3070

#define WM5100_GP5_DB_MASK 0x0100 /* GP5_DB */

3071

#define WM5100_GP5_DB_SHIFT 8 /* GP5_DB */

3072

#define WM5100_GP5_DB_WIDTH 1 /* GP5_DB */

3073

#define WM5100_GP5_LVL 0x0040 /* GP5_LVL */

3074

#define WM5100_GP5_LVL_MASK 0x0040 /* GP5_LVL */

3075

#define WM5100_GP5_LVL_SHIFT 6 /* GP5_LVL */

3076

#define WM5100_GP5_LVL_WIDTH 1 /* GP5_LVL */

3077

#define WM5100_GP5_FN_MASK 0x003F /* GP5_FN - [5:0] */

3078

#define WM5100_GP5_FN_SHIFT 0 /* GP5_FN - [5:0] */

3079

#define WM5100_GP5_FN_WIDTH 6 /* GP5_FN - [5:0] */

3080

3081

/*

3082

* R3077 (0xC05) - GPIO CTRL 6

3083

*/

3084

#define WM5100_GP6_DIR 0x8000 /* GP6_DIR */

3085

#define WM5100_GP6_DIR_MASK 0x8000 /* GP6_DIR */

3086

#define WM5100_GP6_DIR_SHIFT 15 /* GP6_DIR */

3087

#define WM5100_GP6_DIR_WIDTH 1 /* GP6_DIR */

3088

#define WM5100_GP6_PU 0x4000 /* GP6_PU */

3089

#define WM5100_GP6_PU_MASK 0x4000 /* GP6_PU */

3090

#define WM5100_GP6_PU_SHIFT 14 /* GP6_PU */

3091

#define WM5100_GP6_PU_WIDTH 1 /* GP6_PU */

3092

#define WM5100_GP6_PD 0x2000 /* GP6_PD */

3093

#define WM5100_GP6_PD_MASK 0x2000 /* GP6_PD */

3094

#define WM5100_GP6_PD_SHIFT 13 /* GP6_PD */

3095

#define WM5100_GP6_PD_WIDTH 1 /* GP6_PD */

3096

#define WM5100_GP6_POL 0x0400 /* GP6_POL */

3097

#define WM5100_GP6_POL_MASK 0x0400 /* GP6_POL */

3098

#define WM5100_GP6_POL_SHIFT 10 /* GP6_POL */

3099

#define WM5100_GP6_POL_WIDTH 1 /* GP6_POL */

3100

#define WM5100_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */

3101

#define WM5100_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */

3102

#define WM5100_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */

3103

#define WM5100_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */

3104

#define WM5100_GP6_DB 0x0100 /* GP6_DB */

3105

#define WM5100_GP6_DB_MASK 0x0100 /* GP6_DB */

3106

#define WM5100_GP6_DB_SHIFT 8 /* GP6_DB */

3107

#define WM5100_GP6_DB_WIDTH 1 /* GP6_DB */

3108

#define WM5100_GP6_LVL 0x0040 /* GP6_LVL */

3109

#define WM5100_GP6_LVL_MASK 0x0040 /* GP6_LVL */

3110

#define WM5100_GP6_LVL_SHIFT 6 /* GP6_LVL */

3111

#define WM5100_GP6_LVL_WIDTH 1 /* GP6_LVL */

3112

#define WM5100_GP6_FN_MASK 0x003F /* GP6_FN - [5:0] */

3113

#define WM5100_GP6_FN_SHIFT 0 /* GP6_FN - [5:0] */

3114

#define WM5100_GP6_FN_WIDTH 6 /* GP6_FN - [5:0] */

3115

3116

/*

3117

* R3107 (0xC23) - Misc Pad Ctrl 1

3118

*/

3119

#define WM5100_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */

3120

#define WM5100_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */

3121

#define WM5100_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */

3122

#define WM5100_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */

3123

#define WM5100_MCLK2_PD 0x2000 /* MCLK2_PD */

3124

#define WM5100_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */

3125

#define WM5100_MCLK2_PD_SHIFT 13 /* MCLK2_PD */

3126

#define WM5100_MCLK2_PD_WIDTH 1 /* MCLK2_PD */

3127

#define WM5100_MCLK1_PD 0x1000 /* MCLK1_PD */

3128

#define WM5100_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */

3129

#define WM5100_MCLK1_PD_SHIFT 12 /* MCLK1_PD */

3130

#define WM5100_MCLK1_PD_WIDTH 1 /* MCLK1_PD */

3131

#define WM5100_RESET_PU 0x0002 /* RESET_PU */

3132

#define WM5100_RESET_PU_MASK 0x0002 /* RESET_PU */

3133

#define WM5100_RESET_PU_SHIFT 1 /* RESET_PU */

3134

#define WM5100_RESET_PU_WIDTH 1 /* RESET_PU */

3135

#define WM5100_ADDR_PD 0x0001 /* ADDR_PD */

3136

#define WM5100_ADDR_PD_MASK 0x0001 /* ADDR_PD */

3137

#define WM5100_ADDR_PD_SHIFT 0 /* ADDR_PD */

3138

#define WM5100_ADDR_PD_WIDTH 1 /* ADDR_PD */

3139

3140

/*

3141

* R3108 (0xC24) - Misc Pad Ctrl 2

3142

*/

3143

#define WM5100_DMICDAT4_PD 0x0008 /* DMICDAT4_PD */

3144

#define WM5100_DMICDAT4_PD_MASK 0x0008 /* DMICDAT4_PD */

3145

#define WM5100_DMICDAT4_PD_SHIFT 3 /* DMICDAT4_PD */

3146

#define WM5100_DMICDAT4_PD_WIDTH 1 /* DMICDAT4_PD */

3147

#define WM5100_DMICDAT3_PD 0x0004 /* DMICDAT3_PD */

3148

#define WM5100_DMICDAT3_PD_MASK 0x0004 /* DMICDAT3_PD */

3149

#define WM5100_DMICDAT3_PD_SHIFT 2 /* DMICDAT3_PD */

3150

#define WM5100_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */

3151

#define WM5100_DMICDAT2_PD 0x0002 /* DMICDAT2_PD */

3152

#define WM5100_DMICDAT2_PD_MASK 0x0002 /* DMICDAT2_PD */

3153

#define WM5100_DMICDAT2_PD_SHIFT 1 /* DMICDAT2_PD */

3154

#define WM5100_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */

3155

#define WM5100_DMICDAT1_PD 0x0001 /* DMICDAT1_PD */

3156

#define WM5100_DMICDAT1_PD_MASK 0x0001 /* DMICDAT1_PD */

3157

#define WM5100_DMICDAT1_PD_SHIFT 0 /* DMICDAT1_PD */

3158

#define WM5100_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */

3159

3160

/*

3161

* R3109 (0xC25) - Misc Pad Ctrl 3

3162

*/

3163

#define WM5100_AIF1RXLRCLK_PU 0x0020 /* AIF1RXLRCLK_PU */

3164

#define WM5100_AIF1RXLRCLK_PU_MASK 0x0020 /* AIF1RXLRCLK_PU */

3165

#define WM5100_AIF1RXLRCLK_PU_SHIFT 5 /* AIF1RXLRCLK_PU */

3166

#define WM5100_AIF1RXLRCLK_PU_WIDTH 1 /* AIF1RXLRCLK_PU */

3167

#define WM5100_AIF1RXLRCLK_PD 0x0010 /* AIF1RXLRCLK_PD */

3168

#define WM5100_AIF1RXLRCLK_PD_MASK 0x0010 /* AIF1RXLRCLK_PD */

3169

#define WM5100_AIF1RXLRCLK_PD_SHIFT 4 /* AIF1RXLRCLK_PD */

3170

#define WM5100_AIF1RXLRCLK_PD_WIDTH 1 /* AIF1RXLRCLK_PD */

3171

#define WM5100_AIF1BCLK_PU 0x0008 /* AIF1BCLK_PU */

3172

#define WM5100_AIF1BCLK_PU_MASK 0x0008 /* AIF1BCLK_PU */

3173

#define WM5100_AIF1BCLK_PU_SHIFT 3 /* AIF1BCLK_PU */

3174

#define WM5100_AIF1BCLK_PU_WIDTH 1 /* AIF1BCLK_PU */

3175

#define WM5100_AIF1BCLK_PD 0x0004 /* AIF1BCLK_PD */

3176

#define WM5100_AIF1BCLK_PD_MASK 0x0004 /* AIF1BCLK_PD */

3177

#define WM5100_AIF1BCLK_PD_SHIFT 2 /* AIF1BCLK_PD */

3178

#define WM5100_AIF1BCLK_PD_WIDTH 1 /* AIF1BCLK_PD */

3179

#define WM5100_AIF1RXDAT_PU 0x0002 /* AIF1RXDAT_PU */

3180

#define WM5100_AIF1RXDAT_PU_MASK 0x0002 /* AIF1RXDAT_PU */

3181

#define WM5100_AIF1RXDAT_PU_SHIFT 1 /* AIF1RXDAT_PU */

3182

#define WM5100_AIF1RXDAT_PU_WIDTH 1 /* AIF1RXDAT_PU */

3183

#define WM5100_AIF1RXDAT_PD 0x0001 /* AIF1RXDAT_PD */

3184

#define WM5100_AIF1RXDAT_PD_MASK 0x0001 /* AIF1RXDAT_PD */

3185

#define WM5100_AIF1RXDAT_PD_SHIFT 0 /* AIF1RXDAT_PD */

3186

#define WM5100_AIF1RXDAT_PD_WIDTH 1 /* AIF1RXDAT_PD */

3187

3188

/*

3189

* R3110 (0xC26) - Misc Pad Ctrl 4

3190

*/

3191

#define WM5100_AIF2RXLRCLK_PU 0x0020 /* AIF2RXLRCLK_PU */

3192

#define WM5100_AIF2RXLRCLK_PU_MASK 0x0020 /* AIF2RXLRCLK_PU */

3193

#define WM5100_AIF2RXLRCLK_PU_SHIFT 5 /* AIF2RXLRCLK_PU */

3194

#define WM5100_AIF2RXLRCLK_PU_WIDTH 1 /* AIF2RXLRCLK_PU */

3195

#define WM5100_AIF2RXLRCLK_PD 0x0010 /* AIF2RXLRCLK_PD */

3196

#define WM5100_AIF2RXLRCLK_PD_MASK 0x0010 /* AIF2RXLRCLK_PD */

3197

#define WM5100_AIF2RXLRCLK_PD_SHIFT 4 /* AIF2RXLRCLK_PD */

3198

#define WM5100_AIF2RXLRCLK_PD_WIDTH 1 /* AIF2RXLRCLK_PD */

3199

#define WM5100_AIF2BCLK_PU 0x0008 /* AIF2BCLK_PU */

3200

#define WM5100_AIF2BCLK_PU_MASK 0x0008 /* AIF2BCLK_PU */

3201

#define WM5100_AIF2BCLK_PU_SHIFT 3 /* AIF2BCLK_PU */

3202

#define WM5100_AIF2BCLK_PU_WIDTH 1 /* AIF2BCLK_PU */

3203

#define WM5100_AIF2BCLK_PD 0x0004 /* AIF2BCLK_PD */

3204

#define WM5100_AIF2BCLK_PD_MASK 0x0004 /* AIF2BCLK_PD */

3205

#define WM5100_AIF2BCLK_PD_SHIFT 2 /* AIF2BCLK_PD */

3206

#define WM5100_AIF2BCLK_PD_WIDTH 1 /* AIF2BCLK_PD */

3207

#define WM5100_AIF2RXDAT_PU 0x0002 /* AIF2RXDAT_PU */

3208

#define WM5100_AIF2RXDAT_PU_MASK 0x0002 /* AIF2RXDAT_PU */

3209

#define WM5100_AIF2RXDAT_PU_SHIFT 1 /* AIF2RXDAT_PU */

3210

#define WM5100_AIF2RXDAT_PU_WIDTH 1 /* AIF2RXDAT_PU */

3211

#define WM5100_AIF2RXDAT_PD 0x0001 /* AIF2RXDAT_PD */

3212

#define WM5100_AIF2RXDAT_PD_MASK 0x0001 /* AIF2RXDAT_PD */

3213

#define WM5100_AIF2RXDAT_PD_SHIFT 0 /* AIF2RXDAT_PD */

3214

#define WM5100_AIF2RXDAT_PD_WIDTH 1 /* AIF2RXDAT_PD */

3215

3216

/*

3217

* R3111 (0xC27) - Misc Pad Ctrl 5

3218

*/

3219

#define WM5100_AIF3RXLRCLK_PU 0x0020 /* AIF3RXLRCLK_PU */

3220

#define WM5100_AIF3RXLRCLK_PU_MASK 0x0020 /* AIF3RXLRCLK_PU */

3221

#define WM5100_AIF3RXLRCLK_PU_SHIFT 5 /* AIF3RXLRCLK_PU */

3222

#define WM5100_AIF3RXLRCLK_PU_WIDTH 1 /* AIF3RXLRCLK_PU */

3223

#define WM5100_AIF3RXLRCLK_PD 0x0010 /* AIF3RXLRCLK_PD */

3224

#define WM5100_AIF3RXLRCLK_PD_MASK 0x0010 /* AIF3RXLRCLK_PD */

3225

#define WM5100_AIF3RXLRCLK_PD_SHIFT 4 /* AIF3RXLRCLK_PD */

3226

#define WM5100_AIF3RXLRCLK_PD_WIDTH 1 /* AIF3RXLRCLK_PD */

3227

#define WM5100_AIF3BCLK_PU 0x0008 /* AIF3BCLK_PU */

3228

#define WM5100_AIF3BCLK_PU_MASK 0x0008 /* AIF3BCLK_PU */

3229

#define WM5100_AIF3BCLK_PU_SHIFT 3 /* AIF3BCLK_PU */

3230

#define WM5100_AIF3BCLK_PU_WIDTH 1 /* AIF3BCLK_PU */

3231

#define WM5100_AIF3BCLK_PD 0x0004 /* AIF3BCLK_PD */

3232

#define WM5100_AIF3BCLK_PD_MASK 0x0004 /* AIF3BCLK_PD */

3233

#define WM5100_AIF3BCLK_PD_SHIFT 2 /* AIF3BCLK_PD */

3234

#define WM5100_AIF3BCLK_PD_WIDTH 1 /* AIF3BCLK_PD */

3235

#define WM5100_AIF3RXDAT_PU 0x0002 /* AIF3RXDAT_PU */

3236

#define WM5100_AIF3RXDAT_PU_MASK 0x0002 /* AIF3RXDAT_PU */

3237

#define WM5100_AIF3RXDAT_PU_SHIFT 1 /* AIF3RXDAT_PU */

3238

#define WM5100_AIF3RXDAT_PU_WIDTH 1 /* AIF3RXDAT_PU */

3239

#define WM5100_AIF3RXDAT_PD 0x0001 /* AIF3RXDAT_PD */

3240

#define WM5100_AIF3RXDAT_PD_MASK 0x0001 /* AIF3RXDAT_PD */

3241

#define WM5100_AIF3RXDAT_PD_SHIFT 0 /* AIF3RXDAT_PD */

3242

#define WM5100_AIF3RXDAT_PD_WIDTH 1 /* AIF3RXDAT_PD */

3243

3244

/*

3245

* R3112 (0xC28) - Misc GPIO 1

3246

*/

3247

#define WM5100_OPCLK_SEL_MASK 0x0003 /* OPCLK_SEL - [1:0] */

3248

#define WM5100_OPCLK_SEL_SHIFT 0 /* OPCLK_SEL - [1:0] */

3249

#define WM5100_OPCLK_SEL_WIDTH 2 /* OPCLK_SEL - [1:0] */

3250

3251

/*

3252

* R3328 (0xD00) - Interrupt Status 1

3253

*/

3254

#define WM5100_GP6_EINT 0x0020 /* GP6_EINT */

3255

#define WM5100_GP6_EINT_MASK 0x0020 /* GP6_EINT */

3256

#define WM5100_GP6_EINT_SHIFT 5 /* GP6_EINT */

3257

#define WM5100_GP6_EINT_WIDTH 1 /* GP6_EINT */

3258

#define WM5100_GP5_EINT 0x0010 /* GP5_EINT */

3259

#define WM5100_GP5_EINT_MASK 0x0010 /* GP5_EINT */

3260

#define WM5100_GP5_EINT_SHIFT 4 /* GP5_EINT */

3261

#define WM5100_GP5_EINT_WIDTH 1 /* GP5_EINT */

3262

#define WM5100_GP4_EINT 0x0008 /* GP4_EINT */

3263

#define WM5100_GP4_EINT_MASK 0x0008 /* GP4_EINT */

3264

#define WM5100_GP4_EINT_SHIFT 3 /* GP4_EINT */

3265

#define WM5100_GP4_EINT_WIDTH 1 /* GP4_EINT */

3266

#define WM5100_GP3_EINT 0x0004 /* GP3_EINT */

3267

#define WM5100_GP3_EINT_MASK 0x0004 /* GP3_EINT */

3268

#define WM5100_GP3_EINT_SHIFT 2 /* GP3_EINT */

3269

#define WM5100_GP3_EINT_WIDTH 1 /* GP3_EINT */

3270

#define WM5100_GP2_EINT 0x0002 /* GP2_EINT */

3271

#define WM5100_GP2_EINT_MASK 0x0002 /* GP2_EINT */

3272

#define WM5100_GP2_EINT_SHIFT 1 /* GP2_EINT */

3273

#define WM5100_GP2_EINT_WIDTH 1 /* GP2_EINT */

3274

#define WM5100_GP1_EINT 0x0001 /* GP1_EINT */

3275

#define WM5100_GP1_EINT_MASK 0x0001 /* GP1_EINT */

3276

#define WM5100_GP1_EINT_SHIFT 0 /* GP1_EINT */

3277

#define WM5100_GP1_EINT_WIDTH 1 /* GP1_EINT */

3278

3279

/*

3280

* R3329 (0xD01) - Interrupt Status 2

3281

*/

3282

#define WM5100_DSP_IRQ6_EINT 0x0020 /* DSP_IRQ6_EINT */

3283

#define WM5100_DSP_IRQ6_EINT_MASK 0x0020 /* DSP_IRQ6_EINT */

3284

#define WM5100_DSP_IRQ6_EINT_SHIFT 5 /* DSP_IRQ6_EINT */

3285

#define WM5100_DSP_IRQ6_EINT_WIDTH 1 /* DSP_IRQ6_EINT */

3286

#define WM5100_DSP_IRQ5_EINT 0x0010 /* DSP_IRQ5_EINT */

3287

#define WM5100_DSP_IRQ5_EINT_MASK 0x0010 /* DSP_IRQ5_EINT */

3288

#define WM5100_DSP_IRQ5_EINT_SHIFT 4 /* DSP_IRQ5_EINT */

3289

#define WM5100_DSP_IRQ5_EINT_WIDTH 1 /* DSP_IRQ5_EINT */

3290

#define WM5100_DSP_IRQ4_EINT 0x0008 /* DSP_IRQ4_EINT */

3291

#define WM5100_DSP_IRQ4_EINT_MASK 0x0008 /* DSP_IRQ4_EINT */

3292

#define WM5100_DSP_IRQ4_EINT_SHIFT 3 /* DSP_IRQ4_EINT */

3293

#define WM5100_DSP_IRQ4_EINT_WIDTH 1 /* DSP_IRQ4_EINT */

3294

#define WM5100_DSP_IRQ3_EINT 0x0004 /* DSP_IRQ3_EINT */

3295

#define WM5100_DSP_IRQ3_EINT_MASK 0x0004 /* DSP_IRQ3_EINT */

3296

#define WM5100_DSP_IRQ3_EINT_SHIFT 2 /* DSP_IRQ3_EINT */

3297

#define WM5100_DSP_IRQ3_EINT_WIDTH 1 /* DSP_IRQ3_EINT */

3298

#define WM5100_DSP_IRQ2_EINT 0x0002 /* DSP_IRQ2_EINT */

3299

#define WM5100_DSP_IRQ2_EINT_MASK 0x0002 /* DSP_IRQ2_EINT */

3300

#define WM5100_DSP_IRQ2_EINT_SHIFT 1 /* DSP_IRQ2_EINT */

3301

#define WM5100_DSP_IRQ2_EINT_WIDTH 1 /* DSP_IRQ2_EINT */

3302

#define WM5100_DSP_IRQ1_EINT 0x0001 /* DSP_IRQ1_EINT */

3303

#define WM5100_DSP_IRQ1_EINT_MASK 0x0001 /* DSP_IRQ1_EINT */

3304

#define WM5100_DSP_IRQ1_EINT_SHIFT 0 /* DSP_IRQ1_EINT */

3305

#define WM5100_DSP_IRQ1_EINT_WIDTH 1 /* DSP_IRQ1_EINT */

3306

3307

/*

3308

* R3330 (0xD02) - Interrupt Status 3

3309

*/

3310

#define WM5100_SPK_SHUTDOWN_WARN_EINT 0x8000 /* SPK_SHUTDOWN_WARN_EINT */

3311

#define WM5100_SPK_SHUTDOWN_WARN_EINT_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT */

3312

#define WM5100_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT */

3313

#define WM5100_SPK_SHUTDOWN_WARN_EINT_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT */

3314

#define WM5100_SPK_SHUTDOWN_EINT 0x4000 /* SPK_SHUTDOWN_EINT */

3315

#define WM5100_SPK_SHUTDOWN_EINT_MASK 0x4000 /* SPK_SHUTDOWN_EINT */

3316

#define WM5100_SPK_SHUTDOWN_EINT_SHIFT 14 /* SPK_SHUTDOWN_EINT */

3317

#define WM5100_SPK_SHUTDOWN_EINT_WIDTH 1 /* SPK_SHUTDOWN_EINT */

3318

#define WM5100_HPDET_EINT 0x2000 /* HPDET_EINT */

3319

#define WM5100_HPDET_EINT_MASK 0x2000 /* HPDET_EINT */

3320

#define WM5100_HPDET_EINT_SHIFT 13 /* HPDET_EINT */

3321

#define WM5100_HPDET_EINT_WIDTH 1 /* HPDET_EINT */

3322

#define WM5100_ACCDET_EINT 0x1000 /* ACCDET_EINT */

3323

#define WM5100_ACCDET_EINT_MASK 0x1000 /* ACCDET_EINT */

3324

#define WM5100_ACCDET_EINT_SHIFT 12 /* ACCDET_EINT */

3325

#define WM5100_ACCDET_EINT_WIDTH 1 /* ACCDET_EINT */

3326

#define WM5100_DRC_SIG_DET_EINT 0x0200 /* DRC_SIG_DET_EINT */

3327

#define WM5100_DRC_SIG_DET_EINT_MASK 0x0200 /* DRC_SIG_DET_EINT */

3328

#define WM5100_DRC_SIG_DET_EINT_SHIFT 9 /* DRC_SIG_DET_EINT */

3329

#define WM5100_DRC_SIG_DET_EINT_WIDTH 1 /* DRC_SIG_DET_EINT */

3330

#define WM5100_ASRC2_LOCK_EINT 0x0100 /* ASRC2_LOCK_EINT */

3331

#define WM5100_ASRC2_LOCK_EINT_MASK 0x0100 /* ASRC2_LOCK_EINT */

3332

#define WM5100_ASRC2_LOCK_EINT_SHIFT 8 /* ASRC2_LOCK_EINT */

3333

#define WM5100_ASRC2_LOCK_EINT_WIDTH 1 /* ASRC2_LOCK_EINT */

3334

#define WM5100_ASRC1_LOCK_EINT 0x0080 /* ASRC1_LOCK_EINT */

3335

#define WM5100_ASRC1_LOCK_EINT_MASK 0x0080 /* ASRC1_LOCK_EINT */

3336

#define WM5100_ASRC1_LOCK_EINT_SHIFT 7 /* ASRC1_LOCK_EINT */

3337

#define WM5100_ASRC1_LOCK_EINT_WIDTH 1 /* ASRC1_LOCK_EINT */

3338

#define WM5100_FLL2_LOCK_EINT 0x0008 /* FLL2_LOCK_EINT */

3339

#define WM5100_FLL2_LOCK_EINT_MASK 0x0008 /* FLL2_LOCK_EINT */

3340

#define WM5100_FLL2_LOCK_EINT_SHIFT 3 /* FLL2_LOCK_EINT */

3341

#define WM5100_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */

3342

#define WM5100_FLL1_LOCK_EINT 0x0004 /* FLL1_LOCK_EINT */

3343

#define WM5100_FLL1_LOCK_EINT_MASK 0x0004 /* FLL1_LOCK_EINT */

3344

#define WM5100_FLL1_LOCK_EINT_SHIFT 2 /* FLL1_LOCK_EINT */

3345

#define WM5100_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */

3346

#define WM5100_CLKGEN_ERR_EINT 0x0002 /* CLKGEN_ERR_EINT */

3347

#define WM5100_CLKGEN_ERR_EINT_MASK 0x0002 /* CLKGEN_ERR_EINT */

3348

#define WM5100_CLKGEN_ERR_EINT_SHIFT 1 /* CLKGEN_ERR_EINT */

3349

#define WM5100_CLKGEN_ERR_EINT_WIDTH 1 /* CLKGEN_ERR_EINT */

3350

#define WM5100_CLKGEN_ERR_ASYNC_EINT 0x0001 /* CLKGEN_ERR_ASYNC_EINT */

3351

#define WM5100_CLKGEN_ERR_ASYNC_EINT_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT */

3352

#define WM5100_CLKGEN_ERR_ASYNC_EINT_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT */

3353

#define WM5100_CLKGEN_ERR_ASYNC_EINT_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT */

3354

3355

/*

3356

* R3331 (0xD03) - Interrupt Status 4

3357

*/

3358

#define WM5100_AIF3_ERR_EINT 0x2000 /* AIF3_ERR_EINT */

3359

#define WM5100_AIF3_ERR_EINT_MASK 0x2000 /* AIF3_ERR_EINT */

3360

#define WM5100_AIF3_ERR_EINT_SHIFT 13 /* AIF3_ERR_EINT */

3361

#define WM5100_AIF3_ERR_EINT_WIDTH 1 /* AIF3_ERR_EINT */

3362

#define WM5100_AIF2_ERR_EINT 0x1000 /* AIF2_ERR_EINT */

3363

#define WM5100_AIF2_ERR_EINT_MASK 0x1000 /* AIF2_ERR_EINT */

3364

#define WM5100_AIF2_ERR_EINT_SHIFT 12 /* AIF2_ERR_EINT */

3365

#define WM5100_AIF2_ERR_EINT_WIDTH 1 /* AIF2_ERR_EINT */

3366

#define WM5100_AIF1_ERR_EINT 0x0800 /* AIF1_ERR_EINT */

3367

#define WM5100_AIF1_ERR_EINT_MASK 0x0800 /* AIF1_ERR_EINT */

3368

#define WM5100_AIF1_ERR_EINT_SHIFT 11 /* AIF1_ERR_EINT */

3369

#define WM5100_AIF1_ERR_EINT_WIDTH 1 /* AIF1_ERR_EINT */

3370

#define WM5100_CTRLIF_ERR_EINT 0x0400 /* CTRLIF_ERR_EINT */

3371

#define WM5100_CTRLIF_ERR_EINT_MASK 0x0400 /* CTRLIF_ERR_EINT */

3372

#define WM5100_CTRLIF_ERR_EINT_SHIFT 10 /* CTRLIF_ERR_EINT */

3373

#define WM5100_CTRLIF_ERR_EINT_WIDTH 1 /* CTRLIF_ERR_EINT */

3374

#define WM5100_ISRC2_UNDERCLOCKED_EINT 0x0200 /* ISRC2_UNDERCLOCKED_EINT */

3375

#define WM5100_ISRC2_UNDERCLOCKED_EINT_MASK 0x0200 /* ISRC2_UNDERCLOCKED_EINT */

3376

#define WM5100_ISRC2_UNDERCLOCKED_EINT_SHIFT 9 /* ISRC2_UNDERCLOCKED_EINT */

3377

#define WM5100_ISRC2_UNDERCLOCKED_EINT_WIDTH 1 /* ISRC2_UNDERCLOCKED_EINT */

3378

#define WM5100_ISRC1_UNDERCLOCKED_EINT 0x0100 /* ISRC1_UNDERCLOCKED_EINT */

3379

#define WM5100_ISRC1_UNDERCLOCKED_EINT_MASK 0x0100 /* ISRC1_UNDERCLOCKED_EINT */

3380

#define WM5100_ISRC1_UNDERCLOCKED_EINT_SHIFT 8 /* ISRC1_UNDERCLOCKED_EINT */

3381

#define WM5100_ISRC1_UNDERCLOCKED_EINT_WIDTH 1 /* ISRC1_UNDERCLOCKED_EINT */

3382

#define WM5100_FX_UNDERCLOCKED_EINT 0x0080 /* FX_UNDERCLOCKED_EINT */

3383

#define WM5100_FX_UNDERCLOCKED_EINT_MASK 0x0080 /* FX_UNDERCLOCKED_EINT */

3384

#define WM5100_FX_UNDERCLOCKED_EINT_SHIFT 7 /* FX_UNDERCLOCKED_EINT */

3385

#define WM5100_FX_UNDERCLOCKED_EINT_WIDTH 1 /* FX_UNDERCLOCKED_EINT */

3386

#define WM5100_AIF3_UNDERCLOCKED_EINT 0x0040 /* AIF3_UNDERCLOCKED_EINT */

3387

#define WM5100_AIF3_UNDERCLOCKED_EINT_MASK 0x0040 /* AIF3_UNDERCLOCKED_EINT */

3388

#define WM5100_AIF3_UNDERCLOCKED_EINT_SHIFT 6 /* AIF3_UNDERCLOCKED_EINT */

3389

#define WM5100_AIF3_UNDERCLOCKED_EINT_WIDTH 1 /* AIF3_UNDERCLOCKED_EINT */

3390

#define WM5100_AIF2_UNDERCLOCKED_EINT 0x0020 /* AIF2_UNDERCLOCKED_EINT */

3391

#define WM5100_AIF2_UNDERCLOCKED_EINT_MASK 0x0020 /* AIF2_UNDERCLOCKED_EINT */

3392

#define WM5100_AIF2_UNDERCLOCKED_EINT_SHIFT 5 /* AIF2_UNDERCLOCKED_EINT */

3393

#define WM5100_AIF2_UNDERCLOCKED_EINT_WIDTH 1 /* AIF2_UNDERCLOCKED_EINT */

3394

#define WM5100_AIF1_UNDERCLOCKED_EINT 0x0010 /* AIF1_UNDERCLOCKED_EINT */

3395

#define WM5100_AIF1_UNDERCLOCKED_EINT_MASK 0x0010 /* AIF1_UNDERCLOCKED_EINT */

3396

#define WM5100_AIF1_UNDERCLOCKED_EINT_SHIFT 4 /* AIF1_UNDERCLOCKED_EINT */

3397

#define WM5100_AIF1_UNDERCLOCKED_EINT_WIDTH 1 /* AIF1_UNDERCLOCKED_EINT */

3398

#define WM5100_ASRC_UNDERCLOCKED_EINT 0x0008 /* ASRC_UNDERCLOCKED_EINT */

3399

#define WM5100_ASRC_UNDERCLOCKED_EINT_MASK 0x0008 /* ASRC_UNDERCLOCKED_EINT */

3400

#define WM5100_ASRC_UNDERCLOCKED_EINT_SHIFT 3 /* ASRC_UNDERCLOCKED_EINT */

3401

#define WM5100_ASRC_UNDERCLOCKED_EINT_WIDTH 1 /* ASRC_UNDERCLOCKED_EINT */

3402

#define WM5100_DAC_UNDERCLOCKED_EINT 0x0004 /* DAC_UNDERCLOCKED_EINT */

3403

#define WM5100_DAC_UNDERCLOCKED_EINT_MASK 0x0004 /* DAC_UNDERCLOCKED_EINT */

3404

#define WM5100_DAC_UNDERCLOCKED_EINT_SHIFT 2 /* DAC_UNDERCLOCKED_EINT */

3405

#define WM5100_DAC_UNDERCLOCKED_EINT_WIDTH 1 /* DAC_UNDERCLOCKED_EINT */

3406

#define WM5100_ADC_UNDERCLOCKED_EINT 0x0002 /* ADC_UNDERCLOCKED_EINT */

3407

#define WM5100_ADC_UNDERCLOCKED_EINT_MASK 0x0002 /* ADC_UNDERCLOCKED_EINT */

3408

#define WM5100_ADC_UNDERCLOCKED_EINT_SHIFT 1 /* ADC_UNDERCLOCKED_EINT */

3409

#define WM5100_ADC_UNDERCLOCKED_EINT_WIDTH 1 /* ADC_UNDERCLOCKED_EINT */

3410

#define WM5100_MIXER_UNDERCLOCKED_EINT 0x0001 /* MIXER_UNDERCLOCKED_EINT */

3411

#define WM5100_MIXER_UNDERCLOCKED_EINT_MASK 0x0001 /* MIXER_UNDERCLOCKED_EINT */

3412

#define WM5100_MIXER_UNDERCLOCKED_EINT_SHIFT 0 /* MIXER_UNDERCLOCKED_EINT */

3413

#define WM5100_MIXER_UNDERCLOCKED_EINT_WIDTH 1 /* MIXER_UNDERCLOCKED_EINT */

3414

3415

/*

3416

* R3332 (0xD04) - Interrupt Raw Status 2

3417

*/

3418

#define WM5100_DSP_IRQ6_STS 0x0020 /* DSP_IRQ6_STS */

3419

#define WM5100_DSP_IRQ6_STS_MASK 0x0020 /* DSP_IRQ6_STS */

3420

#define WM5100_DSP_IRQ6_STS_SHIFT 5 /* DSP_IRQ6_STS */

3421

#define WM5100_DSP_IRQ6_STS_WIDTH 1 /* DSP_IRQ6_STS */

3422

#define WM5100_DSP_IRQ5_STS 0x0010 /* DSP_IRQ5_STS */

3423

#define WM5100_DSP_IRQ5_STS_MASK 0x0010 /* DSP_IRQ5_STS */

3424

#define WM5100_DSP_IRQ5_STS_SHIFT 4 /* DSP_IRQ5_STS */

3425

#define WM5100_DSP_IRQ5_STS_WIDTH 1 /* DSP_IRQ5_STS */

3426

#define WM5100_DSP_IRQ4_STS 0x0008 /* DSP_IRQ4_STS */

3427

#define WM5100_DSP_IRQ4_STS_MASK 0x0008 /* DSP_IRQ4_STS */

3428

#define WM5100_DSP_IRQ4_STS_SHIFT 3 /* DSP_IRQ4_STS */

3429

#define WM5100_DSP_IRQ4_STS_WIDTH 1 /* DSP_IRQ4_STS */

3430

#define WM5100_DSP_IRQ3_STS 0x0004 /* DSP_IRQ3_STS */

3431

#define WM5100_DSP_IRQ3_STS_MASK 0x0004 /* DSP_IRQ3_STS */

3432

#define WM5100_DSP_IRQ3_STS_SHIFT 2 /* DSP_IRQ3_STS */

3433

#define WM5100_DSP_IRQ3_STS_WIDTH 1 /* DSP_IRQ3_STS */

3434

#define WM5100_DSP_IRQ2_STS 0x0002 /* DSP_IRQ2_STS */

3435

#define WM5100_DSP_IRQ2_STS_MASK 0x0002 /* DSP_IRQ2_STS */

3436

#define WM5100_DSP_IRQ2_STS_SHIFT 1 /* DSP_IRQ2_STS */

3437

#define WM5100_DSP_IRQ2_STS_WIDTH 1 /* DSP_IRQ2_STS */

3438

#define WM5100_DSP_IRQ1_STS 0x0001 /* DSP_IRQ1_STS */

3439

#define WM5100_DSP_IRQ1_STS_MASK 0x0001 /* DSP_IRQ1_STS */

3440

#define WM5100_DSP_IRQ1_STS_SHIFT 0 /* DSP_IRQ1_STS */

3441

#define WM5100_DSP_IRQ1_STS_WIDTH 1 /* DSP_IRQ1_STS */

3442

3443

/*

3444

* R3333 (0xD05) - Interrupt Raw Status 3

3445

*/

3446

#define WM5100_SPK_SHUTDOWN_WARN_STS 0x8000 /* SPK_SHUTDOWN_WARN_STS */

3447

#define WM5100_SPK_SHUTDOWN_WARN_STS_MASK 0x8000 /* SPK_SHUTDOWN_WARN_STS */

3448

#define WM5100_SPK_SHUTDOWN_WARN_STS_SHIFT 15 /* SPK_SHUTDOWN_WARN_STS */

3449

#define WM5100_SPK_SHUTDOWN_WARN_STS_WIDTH 1 /* SPK_SHUTDOWN_WARN_STS */

3450

#define WM5100_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */

3451

#define WM5100_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */

3452

#define WM5100_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */

3453

#define WM5100_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */

3454

#define WM5100_HPDET_STS 0x2000 /* HPDET_STS */

3455

#define WM5100_HPDET_STS_MASK 0x2000 /* HPDET_STS */

3456

#define WM5100_HPDET_STS_SHIFT 13 /* HPDET_STS */

3457

#define WM5100_HPDET_STS_WIDTH 1 /* HPDET_STS */

3458

#define WM5100_DRC_SID_DET_STS 0x0200 /* DRC_SID_DET_STS */

3459

#define WM5100_DRC_SID_DET_STS_MASK 0x0200 /* DRC_SID_DET_STS */

3460

#define WM5100_DRC_SID_DET_STS_SHIFT 9 /* DRC_SID_DET_STS */

3461

#define WM5100_DRC_SID_DET_STS_WIDTH 1 /* DRC_SID_DET_STS */

3462

#define WM5100_ASRC2_LOCK_STS 0x0100 /* ASRC2_LOCK_STS */

3463

#define WM5100_ASRC2_LOCK_STS_MASK 0x0100 /* ASRC2_LOCK_STS */

3464

#define WM5100_ASRC2_LOCK_STS_SHIFT 8 /* ASRC2_LOCK_STS */

3465

#define WM5100_ASRC2_LOCK_STS_WIDTH 1 /* ASRC2_LOCK_STS */

3466

#define WM5100_ASRC1_LOCK_STS 0x0080 /* ASRC1_LOCK_STS */

3467

#define WM5100_ASRC1_LOCK_STS_MASK 0x0080 /* ASRC1_LOCK_STS */

3468

#define WM5100_ASRC1_LOCK_STS_SHIFT 7 /* ASRC1_LOCK_STS */

3469

#define WM5100_ASRC1_LOCK_STS_WIDTH 1 /* ASRC1_LOCK_STS */

3470

#define WM5100_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */

3471

#define WM5100_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */

3472

#define WM5100_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */

3473

#define WM5100_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */

3474

#define WM5100_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */

3475

#define WM5100_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */

3476

#define WM5100_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */

3477

#define WM5100_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */

3478

#define WM5100_CLKGEN_ERR_STS 0x0002 /* CLKGEN_ERR_STS */

3479

#define WM5100_CLKGEN_ERR_STS_MASK 0x0002 /* CLKGEN_ERR_STS */

3480

#define WM5100_CLKGEN_ERR_STS_SHIFT 1 /* CLKGEN_ERR_STS */

3481

#define WM5100_CLKGEN_ERR_STS_WIDTH 1 /* CLKGEN_ERR_STS */

3482

#define WM5100_CLKGEN_ERR_ASYNC_STS 0x0001 /* CLKGEN_ERR_ASYNC_STS */

3483

#define WM5100_CLKGEN_ERR_ASYNC_STS_MASK 0x0001 /* CLKGEN_ERR_ASYNC_STS */

3484

#define WM5100_CLKGEN_ERR_ASYNC_STS_SHIFT 0 /* CLKGEN_ERR_ASYNC_STS */

3485

#define WM5100_CLKGEN_ERR_ASYNC_STS_WIDTH 1 /* CLKGEN_ERR_ASYNC_STS */

3486

3487

/*

3488

* R3334 (0xD06) - Interrupt Raw Status 4

3489

*/

3490

#define WM5100_AIF3_ERR_STS 0x2000 /* AIF3_ERR_STS */

3491

#define WM5100_AIF3_ERR_STS_MASK 0x2000 /* AIF3_ERR_STS */

3492

#define WM5100_AIF3_ERR_STS_SHIFT 13 /* AIF3_ERR_STS */

3493

#define WM5100_AIF3_ERR_STS_WIDTH 1 /* AIF3_ERR_STS */

3494

#define WM5100_AIF2_ERR_STS 0x1000 /* AIF2_ERR_STS */

3495

#define WM5100_AIF2_ERR_STS_MASK 0x1000 /* AIF2_ERR_STS */

3496

#define WM5100_AIF2_ERR_STS_SHIFT 12 /* AIF2_ERR_STS */

3497

#define WM5100_AIF2_ERR_STS_WIDTH 1 /* AIF2_ERR_STS */

3498

#define WM5100_AIF1_ERR_STS 0x0800 /* AIF1_ERR_STS */

3499

#define WM5100_AIF1_ERR_STS_MASK 0x0800 /* AIF1_ERR_STS */

3500

#define WM5100_AIF1_ERR_STS_SHIFT 11 /* AIF1_ERR_STS */

3501

#define WM5100_AIF1_ERR_STS_WIDTH 1 /* AIF1_ERR_STS */

3502

#define WM5100_CTRLIF_ERR_STS 0x0400 /* CTRLIF_ERR_STS */

3503

#define WM5100_CTRLIF_ERR_STS_MASK 0x0400 /* CTRLIF_ERR_STS */

3504

#define WM5100_CTRLIF_ERR_STS_SHIFT 10 /* CTRLIF_ERR_STS */

3505

#define WM5100_CTRLIF_ERR_STS_WIDTH 1 /* CTRLIF_ERR_STS */

3506

#define WM5100_ISRC2_UNDERCLOCKED_STS 0x0200 /* ISRC2_UNDERCLOCKED_STS */

3507

#define WM5100_ISRC2_UNDERCLOCKED_STS_MASK 0x0200 /* ISRC2_UNDERCLOCKED_STS */

3508

#define WM5100_ISRC2_UNDERCLOCKED_STS_SHIFT 9 /* ISRC2_UNDERCLOCKED_STS */

3509

#define WM5100_ISRC2_UNDERCLOCKED_STS_WIDTH 1 /* ISRC2_UNDERCLOCKED_STS */

3510

#define WM5100_ISRC1_UNDERCLOCKED_STS 0x0100 /* ISRC1_UNDERCLOCKED_STS */

3511

#define WM5100_ISRC1_UNDERCLOCKED_STS_MASK 0x0100 /* ISRC1_UNDERCLOCKED_STS */

3512

#define WM5100_ISRC1_UNDERCLOCKED_STS_SHIFT 8 /* ISRC1_UNDERCLOCKED_STS */

3513

#define WM5100_ISRC1_UNDERCLOCKED_STS_WIDTH 1 /* ISRC1_UNDERCLOCKED_STS */

3514

#define WM5100_FX_UNDERCLOCKED_STS 0x0080 /* FX_UNDERCLOCKED_STS */

3515

#define WM5100_FX_UNDERCLOCKED_STS_MASK 0x0080 /* FX_UNDERCLOCKED_STS */

3516

#define WM5100_FX_UNDERCLOCKED_STS_SHIFT 7 /* FX_UNDERCLOCKED_STS */

3517

#define WM5100_FX_UNDERCLOCKED_STS_WIDTH 1 /* FX_UNDERCLOCKED_STS */

3518

#define WM5100_AIF3_UNDERCLOCKED_STS 0x0040 /* AIF3_UNDERCLOCKED_STS */

3519

#define WM5100_AIF3_UNDERCLOCKED_STS_MASK 0x0040 /* AIF3_UNDERCLOCKED_STS */

3520

#define WM5100_AIF3_UNDERCLOCKED_STS_SHIFT 6 /* AIF3_UNDERCLOCKED_STS */

3521

#define WM5100_AIF3_UNDERCLOCKED_STS_WIDTH 1 /* AIF3_UNDERCLOCKED_STS */

3522

#define WM5100_AIF2_UNDERCLOCKED_STS 0x0020 /* AIF2_UNDERCLOCKED_STS */

3523

#define WM5100_AIF2_UNDERCLOCKED_STS_MASK 0x0020 /* AIF2_UNDERCLOCKED_STS */

3524

#define WM5100_AIF2_UNDERCLOCKED_STS_SHIFT 5 /* AIF2_UNDERCLOCKED_STS */

3525

#define WM5100_AIF2_UNDERCLOCKED_STS_WIDTH 1 /* AIF2_UNDERCLOCKED_STS */

3526

#define WM5100_AIF1_UNDERCLOCKED_STS 0x0010 /* AIF1_UNDERCLOCKED_STS */

3527

#define WM5100_AIF1_UNDERCLOCKED_STS_MASK 0x0010 /* AIF1_UNDERCLOCKED_STS */

3528

#define WM5100_AIF1_UNDERCLOCKED_STS_SHIFT 4 /* AIF1_UNDERCLOCKED_STS */

3529

#define WM5100_AIF1_UNDERCLOCKED_STS_WIDTH 1 /* AIF1_UNDERCLOCKED_STS */

3530

#define WM5100_ASRC_UNDERCLOCKED_STS 0x0008 /* ASRC_UNDERCLOCKED_STS */

3531

#define WM5100_ASRC_UNDERCLOCKED_STS_MASK 0x0008 /* ASRC_UNDERCLOCKED_STS */

3532

#define WM5100_ASRC_UNDERCLOCKED_STS_SHIFT 3 /* ASRC_UNDERCLOCKED_STS */

3533

#define WM5100_ASRC_UNDERCLOCKED_STS_WIDTH 1 /* ASRC_UNDERCLOCKED_STS */

3534

#define WM5100_DAC_UNDERCLOCKED_STS 0x0004 /* DAC_UNDERCLOCKED_STS */

3535

#define WM5100_DAC_UNDERCLOCKED_STS_MASK 0x0004 /* DAC_UNDERCLOCKED_STS */

3536

#define WM5100_DAC_UNDERCLOCKED_STS_SHIFT 2 /* DAC_UNDERCLOCKED_STS */

3537

#define WM5100_DAC_UNDERCLOCKED_STS_WIDTH 1 /* DAC_UNDERCLOCKED_STS */

3538

#define WM5100_ADC_UNDERCLOCKED_STS 0x0002 /* ADC_UNDERCLOCKED_STS */

3539

#define WM5100_ADC_UNDERCLOCKED_STS_MASK 0x0002 /* ADC_UNDERCLOCKED_STS */

3540

#define WM5100_ADC_UNDERCLOCKED_STS_SHIFT 1 /* ADC_UNDERCLOCKED_STS */

3541

#define WM5100_ADC_UNDERCLOCKED_STS_WIDTH 1 /* ADC_UNDERCLOCKED_STS */

3542

#define WM5100_MIXER_UNDERCLOCKED_STS 0x0001 /* MIXER_UNDERCLOCKED_STS */

3543

#define WM5100_MIXER_UNDERCLOCKED_STS_MASK 0x0001 /* MIXER_UNDERCLOCKED_STS */

3544

#define WM5100_MIXER_UNDERCLOCKED_STS_SHIFT 0 /* MIXER_UNDERCLOCKED_STS */

3545

#define WM5100_MIXER_UNDERCLOCKED_STS_WIDTH 1 /* MIXER_UNDERCLOCKED_STS */

3546

3547

/*

3548

* R3335 (0xD07) - Interrupt Status 1 Mask

3549

*/

3550

#define WM5100_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */

3551

#define WM5100_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */

3552

#define WM5100_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */

3553

#define WM5100_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */

3554

#define WM5100_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */

3555

#define WM5100_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */

3556

#define WM5100_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */

3557

#define WM5100_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */

3558

#define WM5100_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */

3559

#define WM5100_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */

3560

#define WM5100_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */

3561

#define WM5100_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */

3562

#define WM5100_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */

3563

#define WM5100_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */

3564

#define WM5100_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */

3565

#define WM5100_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */

3566

#define WM5100_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */

3567

#define WM5100_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */

3568

#define WM5100_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */

3569

#define WM5100_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */

3570

#define WM5100_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */

3571

#define WM5100_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */

3572

#define WM5100_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */

3573

#define WM5100_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */

3574

3575

/*

3576

* R3336 (0xD08) - Interrupt Status 2 Mask

3577

*/

3578

#define WM5100_IM_DSP_IRQ6_EINT 0x0020 /* IM_DSP_IRQ6_EINT */

3579

#define WM5100_IM_DSP_IRQ6_EINT_MASK 0x0020 /* IM_DSP_IRQ6_EINT */

3580

#define WM5100_IM_DSP_IRQ6_EINT_SHIFT 5 /* IM_DSP_IRQ6_EINT */

3581

#define WM5100_IM_DSP_IRQ6_EINT_WIDTH 1 /* IM_DSP_IRQ6_EINT */

3582

#define WM5100_IM_DSP_IRQ5_EINT 0x0010 /* IM_DSP_IRQ5_EINT */

3583

#define WM5100_IM_DSP_IRQ5_EINT_MASK 0x0010 /* IM_DSP_IRQ5_EINT */

3584

#define WM5100_IM_DSP_IRQ5_EINT_SHIFT 4 /* IM_DSP_IRQ5_EINT */

3585

#define WM5100_IM_DSP_IRQ5_EINT_WIDTH 1 /* IM_DSP_IRQ5_EINT */

3586

#define WM5100_IM_DSP_IRQ4_EINT 0x0008 /* IM_DSP_IRQ4_EINT */

3587

#define WM5100_IM_DSP_IRQ4_EINT_MASK 0x0008 /* IM_DSP_IRQ4_EINT */

3588

#define WM5100_IM_DSP_IRQ4_EINT_SHIFT 3 /* IM_DSP_IRQ4_EINT */

3589

#define WM5100_IM_DSP_IRQ4_EINT_WIDTH 1 /* IM_DSP_IRQ4_EINT */

3590

#define WM5100_IM_DSP_IRQ3_EINT 0x0004 /* IM_DSP_IRQ3_EINT */

3591

#define WM5100_IM_DSP_IRQ3_EINT_MASK 0x0004 /* IM_DSP_IRQ3_EINT */

3592

#define WM5100_IM_DSP_IRQ3_EINT_SHIFT 2 /* IM_DSP_IRQ3_EINT */

3593

#define WM5100_IM_DSP_IRQ3_EINT_WIDTH 1 /* IM_DSP_IRQ3_EINT */

3594

#define WM5100_IM_DSP_IRQ2_EINT 0x0002 /* IM_DSP_IRQ2_EINT */

3595

#define WM5100_IM_DSP_IRQ2_EINT_MASK 0x0002 /* IM_DSP_IRQ2_EINT */

3596

#define WM5100_IM_DSP_IRQ2_EINT_SHIFT 1 /* IM_DSP_IRQ2_EINT */

3597

#define WM5100_IM_DSP_IRQ2_EINT_WIDTH 1 /* IM_DSP_IRQ2_EINT */

3598

#define WM5100_IM_DSP_IRQ1_EINT 0x0001 /* IM_DSP_IRQ1_EINT */

3599

#define WM5100_IM_DSP_IRQ1_EINT_MASK 0x0001 /* IM_DSP_IRQ1_EINT */

3600

#define WM5100_IM_DSP_IRQ1_EINT_SHIFT 0 /* IM_DSP_IRQ1_EINT */

3601

#define WM5100_IM_DSP_IRQ1_EINT_WIDTH 1 /* IM_DSP_IRQ1_EINT */

3602

3603

/*

3604

* R3337 (0xD09) - Interrupt Status 3 Mask

3605

*/

3606

#define WM5100_IM_SPK_SHUTDOWN_WARN_EINT 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT */

3607

#define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT */

3608

#define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT */

3609

#define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT */

3610

#define WM5100_IM_SPK_SHUTDOWN_EINT 0x4000 /* IM_SPK_SHUTDOWN_EINT */

3611

#define WM5100_IM_SPK_SHUTDOWN_EINT_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT */

3612

#define WM5100_IM_SPK_SHUTDOWN_EINT_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT */

3613

#define WM5100_IM_SPK_SHUTDOWN_EINT_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT */

3614

#define WM5100_IM_HPDET_EINT 0x2000 /* IM_HPDET_EINT */

3615

#define WM5100_IM_HPDET_EINT_MASK 0x2000 /* IM_HPDET_EINT */

3616

#define WM5100_IM_HPDET_EINT_SHIFT 13 /* IM_HPDET_EINT */

3617

#define WM5100_IM_HPDET_EINT_WIDTH 1 /* IM_HPDET_EINT */

3618

#define WM5100_IM_ACCDET_EINT 0x1000 /* IM_ACCDET_EINT */

3619

#define WM5100_IM_ACCDET_EINT_MASK 0x1000 /* IM_ACCDET_EINT */

3620

#define WM5100_IM_ACCDET_EINT_SHIFT 12 /* IM_ACCDET_EINT */

3621

#define WM5100_IM_ACCDET_EINT_WIDTH 1 /* IM_ACCDET_EINT */

3622

#define WM5100_IM_DRC_SIG_DET_EINT 0x0200 /* IM_DRC_SIG_DET_EINT */

3623

#define WM5100_IM_DRC_SIG_DET_EINT_MASK 0x0200 /* IM_DRC_SIG_DET_EINT */

3624

#define WM5100_IM_DRC_SIG_DET_EINT_SHIFT 9 /* IM_DRC_SIG_DET_EINT */

3625

#define WM5100_IM_DRC_SIG_DET_EINT_WIDTH 1 /* IM_DRC_SIG_DET_EINT */

3626

#define WM5100_IM_ASRC2_LOCK_EINT 0x0100 /* IM_ASRC2_LOCK_EINT */

3627

#define WM5100_IM_ASRC2_LOCK_EINT_MASK 0x0100 /* IM_ASRC2_LOCK_EINT */

3628

#define WM5100_IM_ASRC2_LOCK_EINT_SHIFT 8 /* IM_ASRC2_LOCK_EINT */

3629

#define WM5100_IM_ASRC2_LOCK_EINT_WIDTH 1 /* IM_ASRC2_LOCK_EINT */

3630

#define WM5100_IM_ASRC1_LOCK_EINT 0x0080 /* IM_ASRC1_LOCK_EINT */

3631

#define WM5100_IM_ASRC1_LOCK_EINT_MASK 0x0080 /* IM_ASRC1_LOCK_EINT */

3632

#define WM5100_IM_ASRC1_LOCK_EINT_SHIFT 7 /* IM_ASRC1_LOCK_EINT */

3633

#define WM5100_IM_ASRC1_LOCK_EINT_WIDTH 1 /* IM_ASRC1_LOCK_EINT */

3634

#define WM5100_IM_FLL2_LOCK_EINT 0x0008 /* IM_FLL2_LOCK_EINT */

3635

#define WM5100_IM_FLL2_LOCK_EINT_MASK 0x0008 /* IM_FLL2_LOCK_EINT */

3636

#define WM5100_IM_FLL2_LOCK_EINT_SHIFT 3 /* IM_FLL2_LOCK_EINT */

3637

#define WM5100_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */

3638

#define WM5100_IM_FLL1_LOCK_EINT 0x0004 /* IM_FLL1_LOCK_EINT */

3639

#define WM5100_IM_FLL1_LOCK_EINT_MASK 0x0004 /* IM_FLL1_LOCK_EINT */

3640

#define WM5100_IM_FLL1_LOCK_EINT_SHIFT 2 /* IM_FLL1_LOCK_EINT */

3641

#define WM5100_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */

3642

#define WM5100_IM_CLKGEN_ERR_EINT 0x0002 /* IM_CLKGEN_ERR_EINT */

3643

#define WM5100_IM_CLKGEN_ERR_EINT_MASK 0x0002 /* IM_CLKGEN_ERR_EINT */

3644

#define WM5100_IM_CLKGEN_ERR_EINT_SHIFT 1 /* IM_CLKGEN_ERR_EINT */

3645

#define WM5100_IM_CLKGEN_ERR_EINT_WIDTH 1 /* IM_CLKGEN_ERR_EINT */

3646

#define WM5100_IM_CLKGEN_ERR_ASYNC_EINT 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT */

3647

#define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT */

3648

#define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT */

3649

#define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT */

3650

3651

/*

3652

* R3338 (0xD0A) - Interrupt Status 4 Mask

3653

*/

3654

#define WM5100_IM_AIF3_ERR_EINT 0x2000 /* IM_AIF3_ERR_EINT */

3655

#define WM5100_IM_AIF3_ERR_EINT_MASK 0x2000 /* IM_AIF3_ERR_EINT */

3656

#define WM5100_IM_AIF3_ERR_EINT_SHIFT 13 /* IM_AIF3_ERR_EINT */

3657

#define WM5100_IM_AIF3_ERR_EINT_WIDTH 1 /* IM_AIF3_ERR_EINT */

3658

#define WM5100_IM_AIF2_ERR_EINT 0x1000 /* IM_AIF2_ERR_EINT */

3659

#define WM5100_IM_AIF2_ERR_EINT_MASK 0x1000 /* IM_AIF2_ERR_EINT */

3660

#define WM5100_IM_AIF2_ERR_EINT_SHIFT 12 /* IM_AIF2_ERR_EINT */

3661

#define WM5100_IM_AIF2_ERR_EINT_WIDTH 1 /* IM_AIF2_ERR_EINT */

3662

#define WM5100_IM_AIF1_ERR_EINT 0x0800 /* IM_AIF1_ERR_EINT */

3663

#define WM5100_IM_AIF1_ERR_EINT_MASK 0x0800 /* IM_AIF1_ERR_EINT */

3664

#define WM5100_IM_AIF1_ERR_EINT_SHIFT 11 /* IM_AIF1_ERR_EINT */

3665

#define WM5100_IM_AIF1_ERR_EINT_WIDTH 1 /* IM_AIF1_ERR_EINT */

3666

#define WM5100_IM_CTRLIF_ERR_EINT 0x0400 /* IM_CTRLIF_ERR_EINT */

3667

#define WM5100_IM_CTRLIF_ERR_EINT_MASK 0x0400 /* IM_CTRLIF_ERR_EINT */

3668

#define WM5100_IM_CTRLIF_ERR_EINT_SHIFT 10 /* IM_CTRLIF_ERR_EINT */

3669

#define WM5100_IM_CTRLIF_ERR_EINT_WIDTH 1 /* IM_CTRLIF_ERR_EINT */

3670

#define WM5100_IM_ISRC2_UNDERCLOCKED_EINT 0x0200 /* IM_ISRC2_UNDERCLOCKED_EINT */

3671

#define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_MASK 0x0200 /* IM_ISRC2_UNDERCLOCKED_EINT */

3672

#define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_SHIFT 9 /* IM_ISRC2_UNDERCLOCKED_EINT */

3673

#define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ISRC2_UNDERCLOCKED_EINT */

3674

#define WM5100_IM_ISRC1_UNDERCLOCKED_EINT 0x0100 /* IM_ISRC1_UNDERCLOCKED_EINT */

3675

#define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_MASK 0x0100 /* IM_ISRC1_UNDERCLOCKED_EINT */

3676

#define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_SHIFT 8 /* IM_ISRC1_UNDERCLOCKED_EINT */

3677

#define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ISRC1_UNDERCLOCKED_EINT */

3678

#define WM5100_IM_FX_UNDERCLOCKED_EINT 0x0080 /* IM_FX_UNDERCLOCKED_EINT */

3679

#define WM5100_IM_FX_UNDERCLOCKED_EINT_MASK 0x0080 /* IM_FX_UNDERCLOCKED_EINT */

3680

#define WM5100_IM_FX_UNDERCLOCKED_EINT_SHIFT 7 /* IM_FX_UNDERCLOCKED_EINT */

3681

#define WM5100_IM_FX_UNDERCLOCKED_EINT_WIDTH 1 /* IM_FX_UNDERCLOCKED_EINT */

3682

#define WM5100_IM_AIF3_UNDERCLOCKED_EINT 0x0040 /* IM_AIF3_UNDERCLOCKED_EINT */

3683

#define WM5100_IM_AIF3_UNDERCLOCKED_EINT_MASK 0x0040 /* IM_AIF3_UNDERCLOCKED_EINT */

3684

#define WM5100_IM_AIF3_UNDERCLOCKED_EINT_SHIFT 6 /* IM_AIF3_UNDERCLOCKED_EINT */

3685

#define WM5100_IM_AIF3_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF3_UNDERCLOCKED_EINT */

3686

#define WM5100_IM_AIF2_UNDERCLOCKED_EINT 0x0020 /* IM_AIF2_UNDERCLOCKED_EINT */

3687

#define WM5100_IM_AIF2_UNDERCLOCKED_EINT_MASK 0x0020 /* IM_AIF2_UNDERCLOCKED_EINT */

3688

#define WM5100_IM_AIF2_UNDERCLOCKED_EINT_SHIFT 5 /* IM_AIF2_UNDERCLOCKED_EINT */

3689

#define WM5100_IM_AIF2_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF2_UNDERCLOCKED_EINT */

3690

#define WM5100_IM_AIF1_UNDERCLOCKED_EINT 0x0010 /* IM_AIF1_UNDERCLOCKED_EINT */

3691

#define WM5100_IM_AIF1_UNDERCLOCKED_EINT_MASK 0x0010 /* IM_AIF1_UNDERCLOCKED_EINT */

3692

#define WM5100_IM_AIF1_UNDERCLOCKED_EINT_SHIFT 4 /* IM_AIF1_UNDERCLOCKED_EINT */

3693

#define WM5100_IM_AIF1_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF1_UNDERCLOCKED_EINT */

3694

#define WM5100_IM_ASRC_UNDERCLOCKED_EINT 0x0008 /* IM_ASRC_UNDERCLOCKED_EINT */

3695

#define WM5100_IM_ASRC_UNDERCLOCKED_EINT_MASK 0x0008 /* IM_ASRC_UNDERCLOCKED_EINT */

3696

#define WM5100_IM_ASRC_UNDERCLOCKED_EINT_SHIFT 3 /* IM_ASRC_UNDERCLOCKED_EINT */

3697

#define WM5100_IM_ASRC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ASRC_UNDERCLOCKED_EINT */

3698

#define WM5100_IM_DAC_UNDERCLOCKED_EINT 0x0004 /* IM_DAC_UNDERCLOCKED_EINT */

3699

#define WM5100_IM_DAC_UNDERCLOCKED_EINT_MASK 0x0004 /* IM_DAC_UNDERCLOCKED_EINT */

3700

#define WM5100_IM_DAC_UNDERCLOCKED_EINT_SHIFT 2 /* IM_DAC_UNDERCLOCKED_EINT */

3701

#define WM5100_IM_DAC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_DAC_UNDERCLOCKED_EINT */

3702

#define WM5100_IM_ADC_UNDERCLOCKED_EINT 0x0002 /* IM_ADC_UNDERCLOCKED_EINT */

3703

#define WM5100_IM_ADC_UNDERCLOCKED_EINT_MASK 0x0002 /* IM_ADC_UNDERCLOCKED_EINT */

3704

#define WM5100_IM_ADC_UNDERCLOCKED_EINT_SHIFT 1 /* IM_ADC_UNDERCLOCKED_EINT */

3705

#define WM5100_IM_ADC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ADC_UNDERCLOCKED_EINT */

3706

#define WM5100_IM_MIXER_UNDERCLOCKED_EINT 0x0001 /* IM_MIXER_UNDERCLOCKED_EINT */

3707

#define WM5100_IM_MIXER_UNDERCLOCKED_EINT_MASK 0x0001 /* IM_MIXER_UNDERCLOCKED_EINT */

3708

#define WM5100_IM_MIXER_UNDERCLOCKED_EINT_SHIFT 0 /* IM_MIXER_UNDERCLOCKED_EINT */

3709

#define WM5100_IM_MIXER_UNDERCLOCKED_EINT_WIDTH 1 /* IM_MIXER_UNDERCLOCKED_EINT */

3710

3711

/*

3712

* R3359 (0xD1F) - Interrupt Control

3713

*/

3714

#define WM5100_IM_IRQ 0x0001 /* IM_IRQ */

3715

#define WM5100_IM_IRQ_MASK 0x0001 /* IM_IRQ */

3716

#define WM5100_IM_IRQ_SHIFT 0 /* IM_IRQ */

3717

#define WM5100_IM_IRQ_WIDTH 1 /* IM_IRQ */

3718

3719

/*

3720

* R3360 (0xD20) - IRQ Debounce 1

3721

*/

3722

#define WM5100_SPK_SHUTDOWN_WARN_DB 0x0200 /* SPK_SHUTDOWN_WARN_DB */

3723

#define WM5100_SPK_SHUTDOWN_WARN_DB_MASK 0x0200 /* SPK_SHUTDOWN_WARN_DB */

3724

#define WM5100_SPK_SHUTDOWN_WARN_DB_SHIFT 9 /* SPK_SHUTDOWN_WARN_DB */

3725

#define WM5100_SPK_SHUTDOWN_WARN_DB_WIDTH 1 /* SPK_SHUTDOWN_WARN_DB */

3726

#define WM5100_SPK_SHUTDOWN_DB 0x0100 /* SPK_SHUTDOWN_DB */

3727

#define WM5100_SPK_SHUTDOWN_DB_MASK 0x0100 /* SPK_SHUTDOWN_DB */

3728

#define WM5100_SPK_SHUTDOWN_DB_SHIFT 8 /* SPK_SHUTDOWN_DB */

3729

#define WM5100_SPK_SHUTDOWN_DB_WIDTH 1 /* SPK_SHUTDOWN_DB */

3730

#define WM5100_FLL1_LOCK_IRQ_DB 0x0008 /* FLL1_LOCK_IRQ_DB */

3731

#define WM5100_FLL1_LOCK_IRQ_DB_MASK 0x0008 /* FLL1_LOCK_IRQ_DB */

3732

#define WM5100_FLL1_LOCK_IRQ_DB_SHIFT 3 /* FLL1_LOCK_IRQ_DB */

3733

#define WM5100_FLL1_LOCK_IRQ_DB_WIDTH 1 /* FLL1_LOCK_IRQ_DB */

3734

#define WM5100_FLL2_LOCK_IRQ_DB 0x0004 /* FLL2_LOCK_IRQ_DB */

3735

#define WM5100_FLL2_LOCK_IRQ_DB_MASK 0x0004 /* FLL2_LOCK_IRQ_DB */

3736

#define WM5100_FLL2_LOCK_IRQ_DB_SHIFT 2 /* FLL2_LOCK_IRQ_DB */

3737

#define WM5100_FLL2_LOCK_IRQ_DB_WIDTH 1 /* FLL2_LOCK_IRQ_DB */

3738

#define WM5100_CLKGEN_ERR_IRQ_DB 0x0002 /* CLKGEN_ERR_IRQ_DB */

3739

#define WM5100_CLKGEN_ERR_IRQ_DB_MASK 0x0002 /* CLKGEN_ERR_IRQ_DB */

3740

#define WM5100_CLKGEN_ERR_IRQ_DB_SHIFT 1 /* CLKGEN_ERR_IRQ_DB */

3741

#define WM5100_CLKGEN_ERR_IRQ_DB_WIDTH 1 /* CLKGEN_ERR_IRQ_DB */

3742

#define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB 0x0001 /* CLKGEN_ERR_ASYNC_IRQ_DB */

3743

#define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_MASK 0x0001 /* CLKGEN_ERR_ASYNC_IRQ_DB */

3744

#define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_SHIFT 0 /* CLKGEN_ERR_ASYNC_IRQ_DB */

3745

#define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_WIDTH 1 /* CLKGEN_ERR_ASYNC_IRQ_DB */

3746

3747

/*

3748

* R3361 (0xD21) - IRQ Debounce 2

3749

*/

3750

#define WM5100_AIF_ERR_DB 0x0001 /* AIF_ERR_DB */

3751

#define WM5100_AIF_ERR_DB_MASK 0x0001 /* AIF_ERR_DB */

3752

#define WM5100_AIF_ERR_DB_SHIFT 0 /* AIF_ERR_DB */

3753

#define WM5100_AIF_ERR_DB_WIDTH 1 /* AIF_ERR_DB */

3754

3755

/*

3756

* R3584 (0xE00) - FX_Ctrl

3757

*/

3758

#define WM5100_FX_STS_MASK 0xFFC0 /* FX_STS - [15:6] */

3759

#define WM5100_FX_STS_SHIFT 6 /* FX_STS - [15:6] */

3760

#define WM5100_FX_STS_WIDTH 10 /* FX_STS - [15:6] */

3761

#define WM5100_FX_RATE_MASK 0x0003 /* FX_RATE - [1:0] */

3762

#define WM5100_FX_RATE_SHIFT 0 /* FX_RATE - [1:0] */

3763

#define WM5100_FX_RATE_WIDTH 2 /* FX_RATE - [1:0] */

3764

3765

/*

3766

* R3600 (0xE10) - EQ1_1

3767

*/

3768

#define WM5100_EQ1_B1_GAIN_MASK 0xF800 /* EQ1_B1_GAIN - [15:11] */

3769

#define WM5100_EQ1_B1_GAIN_SHIFT 11 /* EQ1_B1_GAIN - [15:11] */

3770

#define WM5100_EQ1_B1_GAIN_WIDTH 5 /* EQ1_B1_GAIN - [15:11] */

3771

#define WM5100_EQ1_B2_GAIN_MASK 0x07C0 /* EQ1_B2_GAIN - [10:6] */

3772

#define WM5100_EQ1_B2_GAIN_SHIFT 6 /* EQ1_B2_GAIN - [10:6] */

3773

#define WM5100_EQ1_B2_GAIN_WIDTH 5 /* EQ1_B2_GAIN - [10:6] */

3774

#define WM5100_EQ1_B3_GAIN_MASK 0x003E /* EQ1_B3_GAIN - [5:1] */

3775

#define WM5100_EQ1_B3_GAIN_SHIFT 1 /* EQ1_B3_GAIN - [5:1] */

3776

#define WM5100_EQ1_B3_GAIN_WIDTH 5 /* EQ1_B3_GAIN - [5:1] */

3777

#define WM5100_EQ1_ENA 0x0001 /* EQ1_ENA */

3778

#define WM5100_EQ1_ENA_MASK 0x0001 /* EQ1_ENA */

3779

#define WM5100_EQ1_ENA_SHIFT 0 /* EQ1_ENA */

3780

#define WM5100_EQ1_ENA_WIDTH 1 /* EQ1_ENA */

3781

3782

/*

3783

* R3601 (0xE11) - EQ1_2

3784

*/

3785

#define WM5100_EQ1_B4_GAIN_MASK 0xF800 /* EQ1_B4_GAIN - [15:11] */

3786

#define WM5100_EQ1_B4_GAIN_SHIFT 11 /* EQ1_B4_GAIN - [15:11] */

3787

#define WM5100_EQ1_B4_GAIN_WIDTH 5 /* EQ1_B4_GAIN - [15:11] */

3788

#define WM5100_EQ1_B5_GAIN_MASK 0x07C0 /* EQ1_B5_GAIN - [10:6] */

3789

#define WM5100_EQ1_B5_GAIN_SHIFT 6 /* EQ1_B5_GAIN - [10:6] */

3790

#define WM5100_EQ1_B5_GAIN_WIDTH 5 /* EQ1_B5_GAIN - [10:6] */

3791

3792

/*

3793

* R3602 (0xE12) - EQ1_3

3794

*/

3795

#define WM5100_EQ1_B1_A_MASK 0xFFFF /* EQ1_B1_A - [15:0] */

3796

#define WM5100_EQ1_B1_A_SHIFT 0 /* EQ1_B1_A - [15:0] */

3797

#define WM5100_EQ1_B1_A_WIDTH 16 /* EQ1_B1_A - [15:0] */

3798

3799

/*

3800

* R3603 (0xE13) - EQ1_4

3801

*/

3802

#define WM5100_EQ1_B1_B_MASK 0xFFFF /* EQ1_B1_B - [15:0] */

3803

#define WM5100_EQ1_B1_B_SHIFT 0 /* EQ1_B1_B - [15:0] */

3804

#define WM5100_EQ1_B1_B_WIDTH 16 /* EQ1_B1_B - [15:0] */

3805

3806

/*

3807

* R3604 (0xE14) - EQ1_5

3808

*/

3809

#define WM5100_EQ1_B1_PG_MASK 0xFFFF /* EQ1_B1_PG - [15:0] */

3810

#define WM5100_EQ1_B1_PG_SHIFT 0 /* EQ1_B1_PG - [15:0] */

3811

#define WM5100_EQ1_B1_PG_WIDTH 16 /* EQ1_B1_PG - [15:0] */

3812

3813

/*

3814

* R3605 (0xE15) - EQ1_6

3815

*/

3816

#define WM5100_EQ1_B2_A_MASK 0xFFFF /* EQ1_B2_A - [15:0] */

3817

#define WM5100_EQ1_B2_A_SHIFT 0 /* EQ1_B2_A - [15:0] */

3818

#define WM5100_EQ1_B2_A_WIDTH 16 /* EQ1_B2_A - [15:0] */

3819

3820

/*

3821

* R3606 (0xE16) - EQ1_7

3822

*/

3823

#define WM5100_EQ1_B2_B_MASK 0xFFFF /* EQ1_B2_B - [15:0] */

3824

#define WM5100_EQ1_B2_B_SHIFT 0 /* EQ1_B2_B - [15:0] */

3825

#define WM5100_EQ1_B2_B_WIDTH 16 /* EQ1_B2_B - [15:0] */

3826

3827

/*

3828

* R3607 (0xE17) - EQ1_8

3829

*/

3830

#define WM5100_EQ1_B2_C_MASK 0xFFFF /* EQ1_B2_C - [15:0] */

3831

#define WM5100_EQ1_B2_C_SHIFT 0 /* EQ1_B2_C - [15:0] */

3832

#define WM5100_EQ1_B2_C_WIDTH 16 /* EQ1_B2_C - [15:0] */

3833

3834

/*

3835

* R3608 (0xE18) - EQ1_9

3836

*/

3837

#define WM5100_EQ1_B2_PG_MASK 0xFFFF /* EQ1_B2_PG - [15:0] */

3838

#define WM5100_EQ1_B2_PG_SHIFT 0 /* EQ1_B2_PG - [15:0] */

3839

#define WM5100_EQ1_B2_PG_WIDTH 16 /* EQ1_B2_PG - [15:0] */

3840

3841

/*

3842

* R3609 (0xE19) - EQ1_10

3843

*/

3844

#define WM5100_EQ1_B3_A_MASK 0xFFFF /* EQ1_B3_A - [15:0] */

3845

#define WM5100_EQ1_B3_A_SHIFT 0 /* EQ1_B3_A - [15:0] */

3846

#define WM5100_EQ1_B3_A_WIDTH 16 /* EQ1_B3_A - [15:0] */

3847

3848

/*

3849

* R3610 (0xE1A) - EQ1_11

3850

*/

3851

#define WM5100_EQ1_B3_B_MASK 0xFFFF /* EQ1_B3_B - [15:0] */

3852

#define WM5100_EQ1_B3_B_SHIFT 0 /* EQ1_B3_B - [15:0] */

3853

#define WM5100_EQ1_B3_B_WIDTH 16 /* EQ1_B3_B - [15:0] */

3854

3855

/*

3856

* R3611 (0xE1B) - EQ1_12

3857

*/

3858

#define WM5100_EQ1_B3_C_MASK 0xFFFF /* EQ1_B3_C - [15:0] */

3859

#define WM5100_EQ1_B3_C_SHIFT 0 /* EQ1_B3_C - [15:0] */

3860

#define WM5100_EQ1_B3_C_WIDTH 16 /* EQ1_B3_C - [15:0] */

3861

3862

/*

3863

* R3612 (0xE1C) - EQ1_13

3864

*/

3865

#define WM5100_EQ1_B3_PG_MASK 0xFFFF /* EQ1_B3_PG - [15:0] */

3866

#define WM5100_EQ1_B3_PG_SHIFT 0 /* EQ1_B3_PG - [15:0] */

3867

#define WM5100_EQ1_B3_PG_WIDTH 16 /* EQ1_B3_PG - [15:0] */

3868

3869

/*

3870

* R3613 (0xE1D) - EQ1_14

3871

*/

3872

#define WM5100_EQ1_B4_A_MASK 0xFFFF /* EQ1_B4_A - [15:0] */

3873

#define WM5100_EQ1_B4_A_SHIFT 0 /* EQ1_B4_A - [15:0] */

3874

#define WM5100_EQ1_B4_A_WIDTH 16 /* EQ1_B4_A - [15:0] */

3875

3876

/*

3877

* R3614 (0xE1E) - EQ1_15

3878

*/

3879

#define WM5100_EQ1_B4_B_MASK 0xFFFF /* EQ1_B4_B - [15:0] */

3880

#define WM5100_EQ1_B4_B_SHIFT 0 /* EQ1_B4_B - [15:0] */

3881

#define WM5100_EQ1_B4_B_WIDTH 16 /* EQ1_B4_B - [15:0] */

3882

3883

/*

3884

* R3615 (0xE1F) - EQ1_16

3885

*/

3886

#define WM5100_EQ1_B4_C_MASK 0xFFFF /* EQ1_B4_C - [15:0] */

3887

#define WM5100_EQ1_B4_C_SHIFT 0 /* EQ1_B4_C - [15:0] */

3888

#define WM5100_EQ1_B4_C_WIDTH 16 /* EQ1_B4_C - [15:0] */

3889

3890

/*

3891

* R3616 (0xE20) - EQ1_17

3892

*/

3893

#define WM5100_EQ1_B4_PG_MASK 0xFFFF /* EQ1_B4_PG - [15:0] */

3894

#define WM5100_EQ1_B4_PG_SHIFT 0 /* EQ1_B4_PG - [15:0] */

3895

#define WM5100_EQ1_B4_PG_WIDTH 16 /* EQ1_B4_PG - [15:0] */

3896

3897

/*

3898

* R3617 (0xE21) - EQ1_18

3899

*/

3900

#define WM5100_EQ1_B5_A_MASK 0xFFFF /* EQ1_B5_A - [15:0] */

3901

#define WM5100_EQ1_B5_A_SHIFT 0 /* EQ1_B5_A - [15:0] */

3902

#define WM5100_EQ1_B5_A_WIDTH 16 /* EQ1_B5_A - [15:0] */

3903

3904

/*

3905

* R3618 (0xE22) - EQ1_19

3906

*/

3907

#define WM5100_EQ1_B5_B_MASK 0xFFFF /* EQ1_B5_B - [15:0] */

3908

#define WM5100_EQ1_B5_B_SHIFT 0 /* EQ1_B5_B - [15:0] */

3909

#define WM5100_EQ1_B5_B_WIDTH 16 /* EQ1_B5_B - [15:0] */

3910

3911

/*

3912

* R3619 (0xE23) - EQ1_20

3913

*/

3914

#define WM5100_EQ1_B5_PG_MASK 0xFFFF /* EQ1_B5_PG - [15:0] */

3915

#define WM5100_EQ1_B5_PG_SHIFT 0 /* EQ1_B5_PG - [15:0] */

3916

#define WM5100_EQ1_B5_PG_WIDTH 16 /* EQ1_B5_PG - [15:0] */

3917

3918

/*

3919

* R3622 (0xE26) - EQ2_1

3920

*/

3921

#define WM5100_EQ2_B1_GAIN_MASK 0xF800 /* EQ2_B1_GAIN - [15:11] */

3922

#define WM5100_EQ2_B1_GAIN_SHIFT 11 /* EQ2_B1_GAIN - [15:11] */

3923

#define WM5100_EQ2_B1_GAIN_WIDTH 5 /* EQ2_B1_GAIN - [15:11] */

3924

#define WM5100_EQ2_B2_GAIN_MASK 0x07C0 /* EQ2_B2_GAIN - [10:6] */

3925

#define WM5100_EQ2_B2_GAIN_SHIFT 6 /* EQ2_B2_GAIN - [10:6] */

3926

#define WM5100_EQ2_B2_GAIN_WIDTH 5 /* EQ2_B2_GAIN - [10:6] */

3927

#define WM5100_EQ2_B3_GAIN_MASK 0x003E /* EQ2_B3_GAIN - [5:1] */

3928

#define WM5100_EQ2_B3_GAIN_SHIFT 1 /* EQ2_B3_GAIN - [5:1] */

3929

#define WM5100_EQ2_B3_GAIN_WIDTH 5 /* EQ2_B3_GAIN - [5:1] */

3930

#define WM5100_EQ2_ENA 0x0001 /* EQ2_ENA */

3931

#define WM5100_EQ2_ENA_MASK 0x0001 /* EQ2_ENA */

3932

#define WM5100_EQ2_ENA_SHIFT 0 /* EQ2_ENA */

3933

#define WM5100_EQ2_ENA_WIDTH 1 /* EQ2_ENA */

3934

3935

/*

3936

* R3623 (0xE27) - EQ2_2

3937

*/

3938

#define WM5100_EQ2_B4_GAIN_MASK 0xF800 /* EQ2_B4_GAIN - [15:11] */

3939

#define WM5100_EQ2_B4_GAIN_SHIFT 11 /* EQ2_B4_GAIN - [15:11] */

3940

#define WM5100_EQ2_B4_GAIN_WIDTH 5 /* EQ2_B4_GAIN - [15:11] */

3941

#define WM5100_EQ2_B5_GAIN_MASK 0x07C0 /* EQ2_B5_GAIN - [10:6] */

3942

#define WM5100_EQ2_B5_GAIN_SHIFT 6 /* EQ2_B5_GAIN - [10:6] */

3943

#define WM5100_EQ2_B5_GAIN_WIDTH 5 /* EQ2_B5_GAIN - [10:6] */

3944

3945

/*

3946

* R3624 (0xE28) - EQ2_3

3947

*/

3948

#define WM5100_EQ2_B1_A_MASK 0xFFFF /* EQ2_B1_A - [15:0] */

3949

#define WM5100_EQ2_B1_A_SHIFT 0 /* EQ2_B1_A - [15:0] */

3950

#define WM5100_EQ2_B1_A_WIDTH 16 /* EQ2_B1_A - [15:0] */

3951

3952

/*

3953

* R3625 (0xE29) - EQ2_4

3954

*/

3955

#define WM5100_EQ2_B1_B_MASK 0xFFFF /* EQ2_B1_B - [15:0] */

3956

#define WM5100_EQ2_B1_B_SHIFT 0 /* EQ2_B1_B - [15:0] */

3957

#define WM5100_EQ2_B1_B_WIDTH 16 /* EQ2_B1_B - [15:0] */

3958

3959

/*

3960

* R3626 (0xE2A) - EQ2_5

3961

*/

3962

#define WM5100_EQ2_B1_PG_MASK 0xFFFF /* EQ2_B1_PG - [15:0] */

3963

#define WM5100_EQ2_B1_PG_SHIFT 0 /* EQ2_B1_PG - [15:0] */

3964

#define WM5100_EQ2_B1_PG_WIDTH 16 /* EQ2_B1_PG - [15:0] */

3965

3966

/*

3967

* R3627 (0xE2B) - EQ2_6

3968

*/

3969

#define WM5100_EQ2_B2_A_MASK 0xFFFF /* EQ2_B2_A - [15:0] */

3970

#define WM5100_EQ2_B2_A_SHIFT 0 /* EQ2_B2_A - [15:0] */

3971

#define WM5100_EQ2_B2_A_WIDTH 16 /* EQ2_B2_A - [15:0] */

3972

3973

/*

3974

* R3628 (0xE2C) - EQ2_7

3975

*/

3976

#define WM5100_EQ2_B2_B_MASK 0xFFFF /* EQ2_B2_B - [15:0] */

3977

#define WM5100_EQ2_B2_B_SHIFT 0 /* EQ2_B2_B - [15:0] */

3978

#define WM5100_EQ2_B2_B_WIDTH 16 /* EQ2_B2_B - [15:0] */

3979

3980

/*

3981

* R3629 (0xE2D) - EQ2_8

3982

*/

3983

#define WM5100_EQ2_B2_C_MASK 0xFFFF /* EQ2_B2_C - [15:0] */

3984

#define WM5100_EQ2_B2_C_SHIFT 0 /* EQ2_B2_C - [15:0] */

3985

#define WM5100_EQ2_B2_C_WIDTH 16 /* EQ2_B2_C - [15:0] */

3986

3987

/*

3988

* R3630 (0xE2E) - EQ2_9

3989

*/

3990

#define WM5100_EQ2_B2_PG_MASK 0xFFFF /* EQ2_B2_PG - [15:0] */

3991

#define WM5100_EQ2_B2_PG_SHIFT 0 /* EQ2_B2_PG - [15:0] */

3992

#define WM5100_EQ2_B2_PG_WIDTH 16 /* EQ2_B2_PG - [15:0] */

3993

3994

/*

3995

* R3631 (0xE2F) - EQ2_10

3996

*/

3997

#define WM5100_EQ2_B3_A_MASK 0xFFFF /* EQ2_B3_A - [15:0] */

3998

#define WM5100_EQ2_B3_A_SHIFT 0 /* EQ2_B3_A - [15:0] */

3999

#define WM5100_EQ2_B3_A_WIDTH 16 /* EQ2_B3_A - [15:0] */

4000

4001

/*

4002

* R3632 (0xE30) - EQ2_11

4003

*/

4004

#define WM5100_EQ2_B3_B_MASK 0xFFFF /* EQ2_B3_B - [15:0] */

4005

#define WM5100_EQ2_B3_B_SHIFT 0 /* EQ2_B3_B - [15:0] */

4006

#define WM5100_EQ2_B3_B_WIDTH 16 /* EQ2_B3_B - [15:0] */

4007

4008

/*

4009

* R3633 (0xE31) - EQ2_12

4010

*/

4011

#define WM5100_EQ2_B3_C_MASK 0xFFFF /* EQ2_B3_C - [15:0] */

4012

#define WM5100_EQ2_B3_C_SHIFT 0 /* EQ2_B3_C - [15:0] */

4013

#define WM5100_EQ2_B3_C_WIDTH 16 /* EQ2_B3_C - [15:0] */

4014

4015

/*

4016

* R3634 (0xE32) - EQ2_13

4017

*/

4018

#define WM5100_EQ2_B3_PG_MASK 0xFFFF /* EQ2_B3_PG - [15:0] */

4019

#define WM5100_EQ2_B3_PG_SHIFT 0 /* EQ2_B3_PG - [15:0] */

4020

#define WM5100_EQ2_B3_PG_WIDTH 16 /* EQ2_B3_PG - [15:0] */

4021

4022

/*

4023

* R3635 (0xE33) - EQ2_14

4024

*/

4025

#define WM5100_EQ2_B4_A_MASK 0xFFFF /* EQ2_B4_A - [15:0] */

4026

#define WM5100_EQ2_B4_A_SHIFT 0 /* EQ2_B4_A - [15:0] */

4027

#define WM5100_EQ2_B4_A_WIDTH 16 /* EQ2_B4_A - [15:0] */

4028

4029

/*

4030

* R3636 (0xE34) - EQ2_15

4031

*/

4032

#define WM5100_EQ2_B4_B_MASK 0xFFFF /* EQ2_B4_B - [15:0] */

4033

#define WM5100_EQ2_B4_B_SHIFT 0 /* EQ2_B4_B - [15:0] */

4034

#define WM5100_EQ2_B4_B_WIDTH 16 /* EQ2_B4_B - [15:0] */

4035

4036

/*

4037

* R3637 (0xE35) - EQ2_16

4038

*/

4039

#define WM5100_EQ2_B4_C_MASK 0xFFFF /* EQ2_B4_C - [15:0] */

4040

#define WM5100_EQ2_B4_C_SHIFT 0 /* EQ2_B4_C - [15:0] */

4041

#define WM5100_EQ2_B4_C_WIDTH 16 /* EQ2_B4_C - [15:0] */

4042

4043

/*

4044

* R3638 (0xE36) - EQ2_17

4045

*/

4046

#define WM5100_EQ2_B4_PG_MASK 0xFFFF /* EQ2_B4_PG - [15:0] */

4047

#define WM5100_EQ2_B4_PG_SHIFT 0 /* EQ2_B4_PG - [15:0] */

4048

#define WM5100_EQ2_B4_PG_WIDTH 16 /* EQ2_B4_PG - [15:0] */

4049

4050

/*

4051

* R3639 (0xE37) - EQ2_18

4052

*/

4053

#define WM5100_EQ2_B5_A_MASK 0xFFFF /* EQ2_B5_A - [15:0] */

4054

#define WM5100_EQ2_B5_A_SHIFT 0 /* EQ2_B5_A - [15:0] */

4055

#define WM5100_EQ2_B5_A_WIDTH 16 /* EQ2_B5_A - [15:0] */

4056

4057

/*

4058

* R3640 (0xE38) - EQ2_19

4059

*/

4060

#define WM5100_EQ2_B5_B_MASK 0xFFFF /* EQ2_B5_B - [15:0] */

4061

#define WM5100_EQ2_B5_B_SHIFT 0 /* EQ2_B5_B - [15:0] */

4062

#define WM5100_EQ2_B5_B_WIDTH 16 /* EQ2_B5_B - [15:0] */

4063

4064

/*

4065

* R3641 (0xE39) - EQ2_20

4066

*/

4067

#define WM5100_EQ2_B5_PG_MASK 0xFFFF /* EQ2_B5_PG - [15:0] */

4068

#define WM5100_EQ2_B5_PG_SHIFT 0 /* EQ2_B5_PG - [15:0] */

4069

#define WM5100_EQ2_B5_PG_WIDTH 16 /* EQ2_B5_PG - [15:0] */

4070

4071

/*

4072

* R3644 (0xE3C) - EQ3_1

4073

*/

4074

#define WM5100_EQ3_B1_GAIN_MASK 0xF800 /* EQ3_B1_GAIN - [15:11] */

4075

#define WM5100_EQ3_B1_GAIN_SHIFT 11 /* EQ3_B1_GAIN - [15:11] */

4076

#define WM5100_EQ3_B1_GAIN_WIDTH 5 /* EQ3_B1_GAIN - [15:11] */

4077

#define WM5100_EQ3_B2_GAIN_MASK 0x07C0 /* EQ3_B2_GAIN - [10:6] */

4078

#define WM5100_EQ3_B2_GAIN_SHIFT 6 /* EQ3_B2_GAIN - [10:6] */

4079

#define WM5100_EQ3_B2_GAIN_WIDTH 5 /* EQ3_B2_GAIN - [10:6] */

4080

#define WM5100_EQ3_B3_GAIN_MASK 0x003E /* EQ3_B3_GAIN - [5:1] */

4081

#define WM5100_EQ3_B3_GAIN_SHIFT 1 /* EQ3_B3_GAIN - [5:1] */

4082

#define WM5100_EQ3_B3_GAIN_WIDTH 5 /* EQ3_B3_GAIN - [5:1] */

4083

#define WM5100_EQ3_ENA 0x0001 /* EQ3_ENA */

4084

#define WM5100_EQ3_ENA_MASK 0x0001 /* EQ3_ENA */

4085

#define WM5100_EQ3_ENA_SHIFT 0 /* EQ3_ENA */

4086

#define WM5100_EQ3_ENA_WIDTH 1 /* EQ3_ENA */

4087

4088

/*

4089

* R3645 (0xE3D) - EQ3_2

4090

*/

4091

#define WM5100_EQ3_B4_GAIN_MASK 0xF800 /* EQ3_B4_GAIN - [15:11] */

4092

#define WM5100_EQ3_B4_GAIN_SHIFT 11 /* EQ3_B4_GAIN - [15:11] */

4093

#define WM5100_EQ3_B4_GAIN_WIDTH 5 /* EQ3_B4_GAIN - [15:11] */

4094

#define WM5100_EQ3_B5_GAIN_MASK 0x07C0 /* EQ3_B5_GAIN - [10:6] */

4095

#define WM5100_EQ3_B5_GAIN_SHIFT 6 /* EQ3_B5_GAIN - [10:6] */

4096

#define WM5100_EQ3_B5_GAIN_WIDTH 5 /* EQ3_B5_GAIN - [10:6] */

4097

4098

/*

4099

* R3646 (0xE3E) - EQ3_3

4100

*/

4101

#define WM5100_EQ3_B1_A_MASK 0xFFFF /* EQ3_B1_A - [15:0] */

4102

#define WM5100_EQ3_B1_A_SHIFT 0 /* EQ3_B1_A - [15:0] */

4103

#define WM5100_EQ3_B1_A_WIDTH 16 /* EQ3_B1_A - [15:0] */

4104

4105

/*

4106

* R3647 (0xE3F) - EQ3_4

4107

*/

4108

#define WM5100_EQ3_B1_B_MASK 0xFFFF /* EQ3_B1_B - [15:0] */

4109

#define WM5100_EQ3_B1_B_SHIFT 0 /* EQ3_B1_B - [15:0] */

4110

#define WM5100_EQ3_B1_B_WIDTH 16 /* EQ3_B1_B - [15:0] */

4111

4112

/*

4113

* R3648 (0xE40) - EQ3_5

4114

*/

4115

#define WM5100_EQ3_B1_PG_MASK 0xFFFF /* EQ3_B1_PG - [15:0] */

4116

#define WM5100_EQ3_B1_PG_SHIFT 0 /* EQ3_B1_PG - [15:0] */

4117

#define WM5100_EQ3_B1_PG_WIDTH 16 /* EQ3_B1_PG - [15:0] */

4118

4119

/*

4120

* R3649 (0xE41) - EQ3_6

4121

*/

4122

#define WM5100_EQ3_B2_A_MASK 0xFFFF /* EQ3_B2_A - [15:0] */

4123

#define WM5100_EQ3_B2_A_SHIFT 0 /* EQ3_B2_A - [15:0] */

4124

#define WM5100_EQ3_B2_A_WIDTH 16 /* EQ3_B2_A - [15:0] */

4125

4126

/*

4127

* R3650 (0xE42) - EQ3_7

4128

*/

4129

#define WM5100_EQ3_B2_B_MASK 0xFFFF /* EQ3_B2_B - [15:0] */

4130

#define WM5100_EQ3_B2_B_SHIFT 0 /* EQ3_B2_B - [15:0] */

4131

#define WM5100_EQ3_B2_B_WIDTH 16 /* EQ3_B2_B - [15:0] */

4132

4133

/*

4134

* R3651 (0xE43) - EQ3_8

4135

*/

4136

#define WM5100_EQ3_B2_C_MASK 0xFFFF /* EQ3_B2_C - [15:0] */

4137

#define WM5100_EQ3_B2_C_SHIFT 0 /* EQ3_B2_C - [15:0] */

4138

#define WM5100_EQ3_B2_C_WIDTH 16 /* EQ3_B2_C - [15:0] */

4139

4140

/*

4141

* R3652 (0xE44) - EQ3_9

4142

*/

4143

#define WM5100_EQ3_B2_PG_MASK 0xFFFF /* EQ3_B2_PG - [15:0] */

4144

#define WM5100_EQ3_B2_PG_SHIFT 0 /* EQ3_B2_PG - [15:0] */

4145

#define WM5100_EQ3_B2_PG_WIDTH 16 /* EQ3_B2_PG - [15:0] */

4146

4147

/*

4148

* R3653 (0xE45) - EQ3_10

4149

*/

4150

#define WM5100_EQ3_B3_A_MASK 0xFFFF /* EQ3_B3_A - [15:0] */

4151

#define WM5100_EQ3_B3_A_SHIFT 0 /* EQ3_B3_A - [15:0] */

4152

#define WM5100_EQ3_B3_A_WIDTH 16 /* EQ3_B3_A - [15:0] */

4153

4154

/*

4155

* R3654 (0xE46) - EQ3_11

4156

*/

4157

#define WM5100_EQ3_B3_B_MASK 0xFFFF /* EQ3_B3_B - [15:0] */

4158

#define WM5100_EQ3_B3_B_SHIFT 0 /* EQ3_B3_B - [15:0] */

4159

#define WM5100_EQ3_B3_B_WIDTH 16 /* EQ3_B3_B - [15:0] */

4160

4161

/*

4162

* R3655 (0xE47) - EQ3_12

4163

*/

4164

#define WM5100_EQ3_B3_C_MASK 0xFFFF /* EQ3_B3_C - [15:0] */

4165

#define WM5100_EQ3_B3_C_SHIFT 0 /* EQ3_B3_C - [15:0] */

4166

#define WM5100_EQ3_B3_C_WIDTH 16 /* EQ3_B3_C - [15:0] */

4167

4168

/*

4169

* R3656 (0xE48) - EQ3_13

4170

*/

4171

#define WM5100_EQ3_B3_PG_MASK 0xFFFF /* EQ3_B3_PG - [15:0] */

4172

#define WM5100_EQ3_B3_PG_SHIFT 0 /* EQ3_B3_PG - [15:0] */

4173

#define WM5100_EQ3_B3_PG_WIDTH 16 /* EQ3_B3_PG - [15:0] */

4174

4175

/*

4176

* R3657 (0xE49) - EQ3_14

4177

*/

4178

#define WM5100_EQ3_B4_A_MASK 0xFFFF /* EQ3_B4_A - [15:0] */

4179

#define WM5100_EQ3_B4_A_SHIFT 0 /* EQ3_B4_A - [15:0] */

4180

#define WM5100_EQ3_B4_A_WIDTH 16 /* EQ3_B4_A - [15:0] */

4181

4182

/*

4183

* R3658 (0xE4A) - EQ3_15

4184

*/

4185

#define WM5100_EQ3_B4_B_MASK 0xFFFF /* EQ3_B4_B - [15:0] */

4186

#define WM5100_EQ3_B4_B_SHIFT 0 /* EQ3_B4_B - [15:0] */

4187

#define WM5100_EQ3_B4_B_WIDTH 16 /* EQ3_B4_B - [15:0] */

4188

4189

/*

4190

* R3659 (0xE4B) - EQ3_16

4191

*/

4192

#define WM5100_EQ3_B4_C_MASK 0xFFFF /* EQ3_B4_C - [15:0] */

4193

#define WM5100_EQ3_B4_C_SHIFT 0 /* EQ3_B4_C - [15:0] */

4194

#define WM5100_EQ3_B4_C_WIDTH 16 /* EQ3_B4_C - [15:0] */

4195

4196

/*

4197

* R3660 (0xE4C) - EQ3_17

4198

*/

4199

#define WM5100_EQ3_B4_PG_MASK 0xFFFF /* EQ3_B4_PG - [15:0] */

4200

#define WM5100_EQ3_B4_PG_SHIFT 0 /* EQ3_B4_PG - [15:0] */

4201

#define WM5100_EQ3_B4_PG_WIDTH 16 /* EQ3_B4_PG - [15:0] */

4202

4203

/*

4204

* R3661 (0xE4D) - EQ3_18

4205

*/

4206

#define WM5100_EQ3_B5_A_MASK 0xFFFF /* EQ3_B5_A - [15:0] */

4207

#define WM5100_EQ3_B5_A_SHIFT 0 /* EQ3_B5_A - [15:0] */

4208

#define WM5100_EQ3_B5_A_WIDTH 16 /* EQ3_B5_A - [15:0] */

4209

4210

/*

4211

* R3662 (0xE4E) - EQ3_19

4212

*/

4213

#define WM5100_EQ3_B5_B_MASK 0xFFFF /* EQ3_B5_B - [15:0] */

4214

#define WM5100_EQ3_B5_B_SHIFT 0 /* EQ3_B5_B - [15:0] */

4215

#define WM5100_EQ3_B5_B_WIDTH 16 /* EQ3_B5_B - [15:0] */

4216

4217

/*

4218

* R3663 (0xE4F) - EQ3_20

4219

*/

4220

#define WM5100_EQ3_B5_PG_MASK 0xFFFF /* EQ3_B5_PG - [15:0] */

4221

#define WM5100_EQ3_B5_PG_SHIFT 0 /* EQ3_B5_PG - [15:0] */

4222

#define WM5100_EQ3_B5_PG_WIDTH 16 /* EQ3_B5_PG - [15:0] */

4223

4224

/*

4225

* R3666 (0xE52) - EQ4_1

4226

*/

4227

#define WM5100_EQ4_B1_GAIN_MASK 0xF800 /* EQ4_B1_GAIN - [15:11] */

4228

#define WM5100_EQ4_B1_GAIN_SHIFT 11 /* EQ4_B1_GAIN - [15:11] */

4229

#define WM5100_EQ4_B1_GAIN_WIDTH 5 /* EQ4_B1_GAIN - [15:11] */

4230

#define WM5100_EQ4_B2_GAIN_MASK 0x07C0 /* EQ4_B2_GAIN - [10:6] */

4231

#define WM5100_EQ4_B2_GAIN_SHIFT 6 /* EQ4_B2_GAIN - [10:6] */

4232

#define WM5100_EQ4_B2_GAIN_WIDTH 5 /* EQ4_B2_GAIN - [10:6] */

4233

#define WM5100_EQ4_B3_GAIN_MASK 0x003E /* EQ4_B3_GAIN - [5:1] */

4234

#define WM5100_EQ4_B3_GAIN_SHIFT 1 /* EQ4_B3_GAIN - [5:1] */

4235

#define WM5100_EQ4_B3_GAIN_WIDTH 5 /* EQ4_B3_GAIN - [5:1] */

4236

#define WM5100_EQ4_ENA 0x0001 /* EQ4_ENA */

4237

#define WM5100_EQ4_ENA_MASK 0x0001 /* EQ4_ENA */

4238

#define WM5100_EQ4_ENA_SHIFT 0 /* EQ4_ENA */

4239

#define WM5100_EQ4_ENA_WIDTH 1 /* EQ4_ENA */

4240

4241

/*

4242

* R3667 (0xE53) - EQ4_2

4243

*/

4244

#define WM5100_EQ4_B4_GAIN_MASK 0xF800 /* EQ4_B4_GAIN - [15:11] */

4245

#define WM5100_EQ4_B4_GAIN_SHIFT 11 /* EQ4_B4_GAIN - [15:11] */

4246

#define WM5100_EQ4_B4_GAIN_WIDTH 5 /* EQ4_B4_GAIN - [15:11] */

4247

#define WM5100_EQ4_B5_GAIN_MASK 0x07C0 /* EQ4_B5_GAIN - [10:6] */

4248

#define WM5100_EQ4_B5_GAIN_SHIFT 6 /* EQ4_B5_GAIN - [10:6] */

4249

#define WM5100_EQ4_B5_GAIN_WIDTH 5 /* EQ4_B5_GAIN - [10:6] */

4250

4251

/*

4252

* R3668 (0xE54) - EQ4_3

4253

*/

4254

#define WM5100_EQ4_B1_A_MASK 0xFFFF /* EQ4_B1_A - [15:0] */

4255

#define WM5100_EQ4_B1_A_SHIFT 0 /* EQ4_B1_A - [15:0] */

4256

#define WM5100_EQ4_B1_A_WIDTH 16 /* EQ4_B1_A - [15:0] */

4257

4258

/*

4259

* R3669 (0xE55) - EQ4_4

4260

*/

4261

#define WM5100_EQ4_B1_B_MASK 0xFFFF /* EQ4_B1_B - [15:0] */

4262

#define WM5100_EQ4_B1_B_SHIFT 0 /* EQ4_B1_B - [15:0] */

4263

#define WM5100_EQ4_B1_B_WIDTH 16 /* EQ4_B1_B - [15:0] */

4264

4265

/*

4266

* R3670 (0xE56) - EQ4_5

4267

*/

4268

#define WM5100_EQ4_B1_PG_MASK 0xFFFF /* EQ4_B1_PG - [15:0] */

4269

#define WM5100_EQ4_B1_PG_SHIFT 0 /* EQ4_B1_PG - [15:0] */

4270

#define WM5100_EQ4_B1_PG_WIDTH 16 /* EQ4_B1_PG - [15:0] */

4271

4272

/*

4273

* R3671 (0xE57) - EQ4_6

4274

*/

4275

#define WM5100_EQ4_B2_A_MASK 0xFFFF /* EQ4_B2_A - [15:0] */

4276

#define WM5100_EQ4_B2_A_SHIFT 0 /* EQ4_B2_A - [15:0] */

4277

#define WM5100_EQ4_B2_A_WIDTH 16 /* EQ4_B2_A - [15:0] */

4278

4279

/*

4280

* R3672 (0xE58) - EQ4_7

4281

*/

4282

#define WM5100_EQ4_B2_B_MASK 0xFFFF /* EQ4_B2_B - [15:0] */

4283

#define WM5100_EQ4_B2_B_SHIFT 0 /* EQ4_B2_B - [15:0] */

4284

#define WM5100_EQ4_B2_B_WIDTH 16 /* EQ4_B2_B - [15:0] */

4285

4286

/*

4287

* R3673 (0xE59) - EQ4_8

4288

*/

4289

#define WM5100_EQ4_B2_C_MASK 0xFFFF /* EQ4_B2_C - [15:0] */

4290

#define WM5100_EQ4_B2_C_SHIFT 0 /* EQ4_B2_C - [15:0] */

4291

#define WM5100_EQ4_B2_C_WIDTH 16 /* EQ4_B2_C - [15:0] */

4292

4293

/*

4294

* R3674 (0xE5A) - EQ4_9

4295

*/

4296

#define WM5100_EQ4_B2_PG_MASK 0xFFFF /* EQ4_B2_PG - [15:0] */

4297

#define WM5100_EQ4_B2_PG_SHIFT 0 /* EQ4_B2_PG - [15:0] */

4298

#define WM5100_EQ4_B2_PG_WIDTH 16 /* EQ4_B2_PG - [15:0] */

4299

4300

/*

4301

* R3675 (0xE5B) - EQ4_10

4302

*/

4303

#define WM5100_EQ4_B3_A_MASK 0xFFFF /* EQ4_B3_A - [15:0] */

4304

#define WM5100_EQ4_B3_A_SHIFT 0 /* EQ4_B3_A - [15:0] */

4305

#define WM5100_EQ4_B3_A_WIDTH 16 /* EQ4_B3_A - [15:0] */

4306

4307

/*

4308

* R3676 (0xE5C) - EQ4_11

4309

*/

4310

#define WM5100_EQ4_B3_B_MASK 0xFFFF /* EQ4_B3_B - [15:0] */

4311

#define WM5100_EQ4_B3_B_SHIFT 0 /* EQ4_B3_B - [15:0] */

4312

#define WM5100_EQ4_B3_B_WIDTH 16 /* EQ4_B3_B - [15:0] */

4313

4314

/*

4315

* R3677 (0xE5D) - EQ4_12

4316

*/

4317

#define WM5100_EQ4_B3_C_MASK 0xFFFF /* EQ4_B3_C - [15:0] */

4318

#define WM5100_EQ4_B3_C_SHIFT 0 /* EQ4_B3_C - [15:0] */

4319

#define WM5100_EQ4_B3_C_WIDTH 16 /* EQ4_B3_C - [15:0] */

4320

4321

/*

4322

* R3678 (0xE5E) - EQ4_13

4323

*/

4324

#define WM5100_EQ4_B3_PG_MASK 0xFFFF /* EQ4_B3_PG - [15:0] */

4325

#define WM5100_EQ4_B3_PG_SHIFT 0 /* EQ4_B3_PG - [15:0] */

4326

#define WM5100_EQ4_B3_PG_WIDTH 16 /* EQ4_B3_PG - [15:0] */

4327

4328

/*

4329

* R3679 (0xE5F) - EQ4_14

4330

*/

4331

#define WM5100_EQ4_B4_A_MASK 0xFFFF /* EQ4_B4_A - [15:0] */

4332

#define WM5100_EQ4_B4_A_SHIFT 0 /* EQ4_B4_A - [15:0] */

4333

#define WM5100_EQ4_B4_A_WIDTH 16 /* EQ4_B4_A - [15:0] */

4334

4335

/*

4336

* R3680 (0xE60) - EQ4_15

4337

*/

4338

#define WM5100_EQ4_B4_B_MASK 0xFFFF /* EQ4_B4_B - [15:0] */

4339

#define WM5100_EQ4_B4_B_SHIFT 0 /* EQ4_B4_B - [15:0] */

4340

#define WM5100_EQ4_B4_B_WIDTH 16 /* EQ4_B4_B - [15:0] */

4341

4342

/*

4343

* R3681 (0xE61) - EQ4_16

4344

*/

4345

#define WM5100_EQ4_B4_C_MASK 0xFFFF /* EQ4_B4_C - [15:0] */

4346

#define WM5100_EQ4_B4_C_SHIFT 0 /* EQ4_B4_C - [15:0] */

4347

#define WM5100_EQ4_B4_C_WIDTH 16 /* EQ4_B4_C - [15:0] */

4348

4349

/*

4350

* R3682 (0xE62) - EQ4_17

4351

*/

4352

#define WM5100_EQ4_B4_PG_MASK 0xFFFF /* EQ4_B4_PG - [15:0] */

4353

#define WM5100_EQ4_B4_PG_SHIFT 0 /* EQ4_B4_PG - [15:0] */

4354

#define WM5100_EQ4_B4_PG_WIDTH 16 /* EQ4_B4_PG - [15:0] */

4355

4356

/*

4357

* R3683 (0xE63) - EQ4_18

4358

*/

4359

#define WM5100_EQ4_B5_A_MASK 0xFFFF /* EQ4_B5_A - [15:0] */

4360

#define WM5100_EQ4_B5_A_SHIFT 0 /* EQ4_B5_A - [15:0] */

4361

#define WM5100_EQ4_B5_A_WIDTH 16 /* EQ4_B5_A - [15:0] */

4362

4363

/*

4364

* R3684 (0xE64) - EQ4_19

4365

*/

4366

#define WM5100_EQ4_B5_B_MASK 0xFFFF /* EQ4_B5_B - [15:0] */

4367

#define WM5100_EQ4_B5_B_SHIFT 0 /* EQ4_B5_B - [15:0] */

4368

#define WM5100_EQ4_B5_B_WIDTH 16 /* EQ4_B5_B - [15:0] */

4369

4370

/*

4371

* R3685 (0xE65) - EQ4_20

4372

*/

4373

#define WM5100_EQ4_B5_PG_MASK 0xFFFF /* EQ4_B5_PG - [15:0] */

4374

#define WM5100_EQ4_B5_PG_SHIFT 0 /* EQ4_B5_PG - [15:0] */

4375

#define WM5100_EQ4_B5_PG_WIDTH 16 /* EQ4_B5_PG - [15:0] */

4376

4377

/*

4378

* R3712 (0xE80) - DRC1 ctrl1

4379

*/

4380

#define WM5100_DRC_SIG_DET_RMS_MASK 0xF800 /* DRC_SIG_DET_RMS - [15:11] */

4381

#define WM5100_DRC_SIG_DET_RMS_SHIFT 11 /* DRC_SIG_DET_RMS - [15:11] */

4382

#define WM5100_DRC_SIG_DET_RMS_WIDTH 5 /* DRC_SIG_DET_RMS - [15:11] */

4383

#define WM5100_DRC_SIG_DET_PK_MASK 0x0600 /* DRC_SIG_DET_PK - [10:9] */

4384

#define WM5100_DRC_SIG_DET_PK_SHIFT 9 /* DRC_SIG_DET_PK - [10:9] */

4385

#define WM5100_DRC_SIG_DET_PK_WIDTH 2 /* DRC_SIG_DET_PK - [10:9] */

4386

#define WM5100_DRC_NG_ENA 0x0100 /* DRC_NG_ENA */

4387

#define WM5100_DRC_NG_ENA_MASK 0x0100 /* DRC_NG_ENA */

4388

#define WM5100_DRC_NG_ENA_SHIFT 8 /* DRC_NG_ENA */

4389

#define WM5100_DRC_NG_ENA_WIDTH 1 /* DRC_NG_ENA */

4390

#define WM5100_DRC_SIG_DET_MODE 0x0080 /* DRC_SIG_DET_MODE */

4391

#define WM5100_DRC_SIG_DET_MODE_MASK 0x0080 /* DRC_SIG_DET_MODE */

4392

#define WM5100_DRC_SIG_DET_MODE_SHIFT 7 /* DRC_SIG_DET_MODE */

4393

#define WM5100_DRC_SIG_DET_MODE_WIDTH 1 /* DRC_SIG_DET_MODE */

4394

#define WM5100_DRC_SIG_DET 0x0040 /* DRC_SIG_DET */

4395

#define WM5100_DRC_SIG_DET_MASK 0x0040 /* DRC_SIG_DET */

4396

#define WM5100_DRC_SIG_DET_SHIFT 6 /* DRC_SIG_DET */

4397

#define WM5100_DRC_SIG_DET_WIDTH 1 /* DRC_SIG_DET */

4398

#define WM5100_DRC_KNEE2_OP_ENA 0x0020 /* DRC_KNEE2_OP_ENA */

4399

#define WM5100_DRC_KNEE2_OP_ENA_MASK 0x0020 /* DRC_KNEE2_OP_ENA */

4400

#define WM5100_DRC_KNEE2_OP_ENA_SHIFT 5 /* DRC_KNEE2_OP_ENA */

4401

#define WM5100_DRC_KNEE2_OP_ENA_WIDTH 1 /* DRC_KNEE2_OP_ENA */

4402

#define WM5100_DRC_QR 0x0010 /* DRC_QR */

4403

#define WM5100_DRC_QR_MASK 0x0010 /* DRC_QR */

4404

#define WM5100_DRC_QR_SHIFT 4 /* DRC_QR */

4405

#define WM5100_DRC_QR_WIDTH 1 /* DRC_QR */

4406

#define WM5100_DRC_ANTICLIP 0x0008 /* DRC_ANTICLIP */

4407

#define WM5100_DRC_ANTICLIP_MASK 0x0008 /* DRC_ANTICLIP */

4408

#define WM5100_DRC_ANTICLIP_SHIFT 3 /* DRC_ANTICLIP */

4409

#define WM5100_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */

4410

#define WM5100_DRCL_ENA 0x0002 /* DRCL_ENA */

4411

#define WM5100_DRCL_ENA_MASK 0x0002 /* DRCL_ENA */

4412

#define WM5100_DRCL_ENA_SHIFT 1 /* DRCL_ENA */

4413

#define WM5100_DRCL_ENA_WIDTH 1 /* DRCL_ENA */

4414

#define WM5100_DRCR_ENA 0x0001 /* DRCR_ENA */

4415

#define WM5100_DRCR_ENA_MASK 0x0001 /* DRCR_ENA */

4416

#define WM5100_DRCR_ENA_SHIFT 0 /* DRCR_ENA */

4417

#define WM5100_DRCR_ENA_WIDTH 1 /* DRCR_ENA */

4418

4419

/*

4420

* R3713 (0xE81) - DRC1 ctrl2

4421

*/

4422

#define WM5100_DRC_ATK_MASK 0x1E00 /* DRC_ATK - [12:9] */

4423

#define WM5100_DRC_ATK_SHIFT 9 /* DRC_ATK - [12:9] */

4424

#define WM5100_DRC_ATK_WIDTH 4 /* DRC_ATK - [12:9] */

4425

#define WM5100_DRC_DCY_MASK 0x01E0 /* DRC_DCY - [8:5] */

4426

#define WM5100_DRC_DCY_SHIFT 5 /* DRC_DCY - [8:5] */

4427

#define WM5100_DRC_DCY_WIDTH 4 /* DRC_DCY - [8:5] */

4428

#define WM5100_DRC_MINGAIN_MASK 0x001C /* DRC_MINGAIN - [4:2] */

4429

#define WM5100_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [4:2] */

4430

#define WM5100_DRC_MINGAIN_WIDTH 3 /* DRC_MINGAIN - [4:2] */

4431

#define WM5100_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */

4432

#define WM5100_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */

4433

#define WM5100_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */

4434

4435

/*

4436

* R3714 (0xE82) - DRC1 ctrl3

4437

*/

4438

#define WM5100_DRC_NG_MINGAIN_MASK 0xF000 /* DRC_NG_MINGAIN - [15:12] */

4439

#define WM5100_DRC_NG_MINGAIN_SHIFT 12 /* DRC_NG_MINGAIN - [15:12] */

4440

#define WM5100_DRC_NG_MINGAIN_WIDTH 4 /* DRC_NG_MINGAIN - [15:12] */

4441

#define WM5100_DRC_NG_EXP_MASK 0x0C00 /* DRC_NG_EXP - [11:10] */

4442

#define WM5100_DRC_NG_EXP_SHIFT 10 /* DRC_NG_EXP - [11:10] */

4443

#define WM5100_DRC_NG_EXP_WIDTH 2 /* DRC_NG_EXP - [11:10] */

4444

#define WM5100_DRC_QR_THR_MASK 0x0300 /* DRC_QR_THR - [9:8] */

4445

#define WM5100_DRC_QR_THR_SHIFT 8 /* DRC_QR_THR - [9:8] */

4446

#define WM5100_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [9:8] */

4447

#define WM5100_DRC_QR_DCY_MASK 0x00C0 /* DRC_QR_DCY - [7:6] */

4448

#define WM5100_DRC_QR_DCY_SHIFT 6 /* DRC_QR_DCY - [7:6] */

4449

#define WM5100_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [7:6] */

4450

#define WM5100_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */

4451

#define WM5100_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */

4452

#define WM5100_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */

4453

#define WM5100_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */

4454

#define WM5100_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */

4455

#define WM5100_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */

4456

4457

/*

4458

* R3715 (0xE83) - DRC1 ctrl4

4459

*/

4460

#define WM5100_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */

4461

#define WM5100_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */

4462

#define WM5100_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */

4463

#define WM5100_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */

4464

#define WM5100_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */

4465

#define WM5100_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */

4466

4467

/*

4468

* R3716 (0xE84) - DRC1 ctrl5

4469

*/

4470

#define WM5100_DRC_KNEE2_IP_MASK 0x03E0 /* DRC_KNEE2_IP - [9:5] */

4471

#define WM5100_DRC_KNEE2_IP_SHIFT 5 /* DRC_KNEE2_IP - [9:5] */

4472

#define WM5100_DRC_KNEE2_IP_WIDTH 5 /* DRC_KNEE2_IP - [9:5] */

4473

#define WM5100_DRC_KNEE2_OP_MASK 0x001F /* DRC_KNEE2_OP - [4:0] */

4474

#define WM5100_DRC_KNEE2_OP_SHIFT 0 /* DRC_KNEE2_OP - [4:0] */

4475

#define WM5100_DRC_KNEE2_OP_WIDTH 5 /* DRC_KNEE2_OP - [4:0] */

4476

4477

/*

4478

* R3776 (0xEC0) - HPLPF1_1

4479

*/

4480

#define WM5100_LHPF1_MODE 0x0002 /* LHPF1_MODE */

4481

#define WM5100_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */

4482

#define WM5100_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */

4483

#define WM5100_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */

4484

#define WM5100_LHPF1_ENA 0x0001 /* LHPF1_ENA */

4485

#define WM5100_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */

4486

#define WM5100_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */

4487

#define WM5100_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */

4488

4489

/*

4490

* R3777 (0xEC1) - HPLPF1_2

4491

*/

4492

#define WM5100_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */

4493

#define WM5100_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */

4494

#define WM5100_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */

4495

4496

/*

4497

* R3780 (0xEC4) - HPLPF2_1

4498

*/

4499

#define WM5100_LHPF2_MODE 0x0002 /* LHPF2_MODE */

4500

#define WM5100_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */

4501

#define WM5100_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */

4502

#define WM5100_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */

4503

#define WM5100_LHPF2_ENA 0x0001 /* LHPF2_ENA */

4504

#define WM5100_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */

4505

#define WM5100_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */

4506

#define WM5100_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */

4507

4508

/*

4509

* R3781 (0xEC5) - HPLPF2_2

4510

*/

4511

#define WM5100_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */

4512

#define WM5100_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */

4513

#define WM5100_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */

4514

4515

/*

4516

* R3784 (0xEC8) - HPLPF3_1

4517

*/

4518

#define WM5100_LHPF3_MODE 0x0002 /* LHPF3_MODE */

4519

#define WM5100_LHPF3_MODE_MASK 0x0002 /* LHPF3_MODE */

4520

#define WM5100_LHPF3_MODE_SHIFT 1 /* LHPF3_MODE */

4521

#define WM5100_LHPF3_MODE_WIDTH 1 /* LHPF3_MODE */

4522

#define WM5100_LHPF3_ENA 0x0001 /* LHPF3_ENA */

4523

#define WM5100_LHPF3_ENA_MASK 0x0001 /* LHPF3_ENA */

4524

#define WM5100_LHPF3_ENA_SHIFT 0 /* LHPF3_ENA */

4525

#define WM5100_LHPF3_ENA_WIDTH 1 /* LHPF3_ENA */

4526

4527

/*

4528

* R3785 (0xEC9) - HPLPF3_2

4529

*/

4530

#define WM5100_LHPF3_COEFF_MASK 0xFFFF /* LHPF3_COEFF - [15:0] */

4531

#define WM5100_LHPF3_COEFF_SHIFT 0 /* LHPF3_COEFF - [15:0] */

4532

#define WM5100_LHPF3_COEFF_WIDTH 16 /* LHPF3_COEFF - [15:0] */

4533

4534

/*

4535

* R3788 (0xECC) - HPLPF4_1

4536

*/

4537

#define WM5100_LHPF4_MODE 0x0002 /* LHPF4_MODE */

4538

#define WM5100_LHPF4_MODE_MASK 0x0002 /* LHPF4_MODE */

4539

#define WM5100_LHPF4_MODE_SHIFT 1 /* LHPF4_MODE */

4540

#define WM5100_LHPF4_MODE_WIDTH 1 /* LHPF4_MODE */

4541

#define WM5100_LHPF4_ENA 0x0001 /* LHPF4_ENA */

4542

#define WM5100_LHPF4_ENA_MASK 0x0001 /* LHPF4_ENA */

4543

#define WM5100_LHPF4_ENA_SHIFT 0 /* LHPF4_ENA */

4544

#define WM5100_LHPF4_ENA_WIDTH 1 /* LHPF4_ENA */

4545

4546

/*

4547

* R3789 (0xECD) - HPLPF4_2

4548

*/

4549

#define WM5100_LHPF4_COEFF_MASK 0xFFFF /* LHPF4_COEFF - [15:0] */

4550

#define WM5100_LHPF4_COEFF_SHIFT 0 /* LHPF4_COEFF - [15:0] */

4551

#define WM5100_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */

4552

4553

/*

4554

* R16384 (0x4000) - DSP1 DM 0

4555

*/

4556

#define WM5100_DSP1_DM_START_1_MASK 0x00FF /* DSP1_DM_START - [7:0] */

4557

#define WM5100_DSP1_DM_START_1_SHIFT 0 /* DSP1_DM_START - [7:0] */

4558

#define WM5100_DSP1_DM_START_1_WIDTH 8 /* DSP1_DM_START - [7:0] */

4559

4560

/*

4561

* R16385 (0x4001) - DSP1 DM 1

4562

*/

4563

#define WM5100_DSP1_DM_START_MASK 0xFFFF /* DSP1_DM_START - [15:0] */

4564

#define WM5100_DSP1_DM_START_SHIFT 0 /* DSP1_DM_START - [15:0] */

4565

#define WM5100_DSP1_DM_START_WIDTH 16 /* DSP1_DM_START - [15:0] */

4566

4567

/*

4568

* R16386 (0x4002) - DSP1 DM 2

4569

*/

4570

#define WM5100_DSP1_DM_1_1_MASK 0x00FF /* DSP1_DM_1 - [7:0] */

4571

#define WM5100_DSP1_DM_1_1_SHIFT 0 /* DSP1_DM_1 - [7:0] */

4572

#define WM5100_DSP1_DM_1_1_WIDTH 8 /* DSP1_DM_1 - [7:0] */

4573

4574

/*

4575

* R16387 (0x4003) - DSP1 DM 3

4576

*/

4577

#define WM5100_DSP1_DM_1_MASK 0xFFFF /* DSP1_DM_1 - [15:0] */

4578

#define WM5100_DSP1_DM_1_SHIFT 0 /* DSP1_DM_1 - [15:0] */

4579

#define WM5100_DSP1_DM_1_WIDTH 16 /* DSP1_DM_1 - [15:0] */

4580

4581

/*

4582

* R16892 (0x41FC) - DSP1 DM 508

4583

*/

4584

#define WM5100_DSP1_DM_254_1_MASK 0x00FF /* DSP1_DM_254 - [7:0] */

4585

#define WM5100_DSP1_DM_254_1_SHIFT 0 /* DSP1_DM_254 - [7:0] */

4586

#define WM5100_DSP1_DM_254_1_WIDTH 8 /* DSP1_DM_254 - [7:0] */

4587

4588

/*

4589

* R16893 (0x41FD) - DSP1 DM 509

4590

*/

4591

#define WM5100_DSP1_DM_254_MASK 0xFFFF /* DSP1_DM_254 - [15:0] */

4592

#define WM5100_DSP1_DM_254_SHIFT 0 /* DSP1_DM_254 - [15:0] */

4593

#define WM5100_DSP1_DM_254_WIDTH 16 /* DSP1_DM_254 - [15:0] */

4594

4595

/*

4596

* R16894 (0x41FE) - DSP1 DM 510

4597

*/

4598

#define WM5100_DSP1_DM_END_1_MASK 0x00FF /* DSP1_DM_END - [7:0] */

4599

#define WM5100_DSP1_DM_END_1_SHIFT 0 /* DSP1_DM_END - [7:0] */

4600

#define WM5100_DSP1_DM_END_1_WIDTH 8 /* DSP1_DM_END - [7:0] */

4601

4602

/*

4603

* R16895 (0x41FF) - DSP1 DM 511

4604

*/

4605

#define WM5100_DSP1_DM_END_MASK 0xFFFF /* DSP1_DM_END - [15:0] */

4606

#define WM5100_DSP1_DM_END_SHIFT 0 /* DSP1_DM_END - [15:0] */

4607

#define WM5100_DSP1_DM_END_WIDTH 16 /* DSP1_DM_END - [15:0] */

4608

4609

/*

4610

* R18432 (0x4800) - DSP1 PM 0

4611

*/

4612

#define WM5100_DSP1_PM_START_2_MASK 0x00FF /* DSP1_PM_START - [7:0] */

4613

#define WM5100_DSP1_PM_START_2_SHIFT 0 /* DSP1_PM_START - [7:0] */

4614

#define WM5100_DSP1_PM_START_2_WIDTH 8 /* DSP1_PM_START - [7:0] */

4615

4616

/*

4617

* R18433 (0x4801) - DSP1 PM 1

4618

*/

4619

#define WM5100_DSP1_PM_START_1_MASK 0xFFFF /* DSP1_PM_START - [15:0] */

4620

#define WM5100_DSP1_PM_START_1_SHIFT 0 /* DSP1_PM_START - [15:0] */

4621

#define WM5100_DSP1_PM_START_1_WIDTH 16 /* DSP1_PM_START - [15:0] */

4622

4623

/*

4624

* R18434 (0x4802) - DSP1 PM 2

4625

*/

4626

#define WM5100_DSP1_PM_START_MASK 0xFFFF /* DSP1_PM_START - [15:0] */

4627

#define WM5100_DSP1_PM_START_SHIFT 0 /* DSP1_PM_START - [15:0] */

4628

#define WM5100_DSP1_PM_START_WIDTH 16 /* DSP1_PM_START - [15:0] */

4629

4630

/*

4631

* R18435 (0x4803) - DSP1 PM 3

4632

*/

4633

#define WM5100_DSP1_PM_1_2_MASK 0x00FF /* DSP1_PM_1 - [7:0] */

4634

#define WM5100_DSP1_PM_1_2_SHIFT 0 /* DSP1_PM_1 - [7:0] */

4635

#define WM5100_DSP1_PM_1_2_WIDTH 8 /* DSP1_PM_1 - [7:0] */

4636

4637

/*

4638

* R18436 (0x4804) - DSP1 PM 4

4639

*/

4640

#define WM5100_DSP1_PM_1_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */

4641

#define WM5100_DSP1_PM_1_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */

4642

#define WM5100_DSP1_PM_1_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */

4643

4644

/*

4645

* R18437 (0x4805) - DSP1 PM 5

4646

*/

4647

#define WM5100_DSP1_PM_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */

4648

#define WM5100_DSP1_PM_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */

4649

#define WM5100_DSP1_PM_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */

4650

4651

/*

4652

* R19962 (0x4DFA) - DSP1 PM 1530

4653

*/

4654

#define WM5100_DSP1_PM_510_2_MASK 0x00FF /* DSP1_PM_510 - [7:0] */

4655

#define WM5100_DSP1_PM_510_2_SHIFT 0 /* DSP1_PM_510 - [7:0] */

4656

#define WM5100_DSP1_PM_510_2_WIDTH 8 /* DSP1_PM_510 - [7:0] */

4657

4658

/*

4659

* R19963 (0x4DFB) - DSP1 PM 1531

4660

*/

4661

#define WM5100_DSP1_PM_510_1_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */

4662

#define WM5100_DSP1_PM_510_1_SHIFT 0 /* DSP1_PM_510 - [15:0] */

4663

#define WM5100_DSP1_PM_510_1_WIDTH 16 /* DSP1_PM_510 - [15:0] */

4664

4665

/*

4666

* R19964 (0x4DFC) - DSP1 PM 1532

4667

*/

4668

#define WM5100_DSP1_PM_510_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */

4669

#define WM5100_DSP1_PM_510_SHIFT 0 /* DSP1_PM_510 - [15:0] */

4670

#define WM5100_DSP1_PM_510_WIDTH 16 /* DSP1_PM_510 - [15:0] */

4671

4672

/*

4673

* R19965 (0x4DFD) - DSP1 PM 1533

4674

*/

4675

#define WM5100_DSP1_PM_END_2_MASK 0x00FF /* DSP1_PM_END - [7:0] */

4676

#define WM5100_DSP1_PM_END_2_SHIFT 0 /* DSP1_PM_END - [7:0] */

4677

#define WM5100_DSP1_PM_END_2_WIDTH 8 /* DSP1_PM_END - [7:0] */

4678

4679

/*

4680

* R19966 (0x4DFE) - DSP1 PM 1534

4681

*/

4682

#define WM5100_DSP1_PM_END_1_MASK 0xFFFF /* DSP1_PM_END - [15:0] */

4683

#define WM5100_DSP1_PM_END_1_SHIFT 0 /* DSP1_PM_END - [15:0] */

4684

#define WM5100_DSP1_PM_END_1_WIDTH 16 /* DSP1_PM_END - [15:0] */

4685

4686

/*

4687

* R19967 (0x4DFF) - DSP1 PM 1535

4688

*/

4689

#define WM5100_DSP1_PM_END_MASK 0xFFFF /* DSP1_PM_END - [15:0] */

4690

#define WM5100_DSP1_PM_END_SHIFT 0 /* DSP1_PM_END - [15:0] */

4691

#define WM5100_DSP1_PM_END_WIDTH 16 /* DSP1_PM_END - [15:0] */

4692

4693

/*

4694

* R20480 (0x5000) - DSP1 ZM 0

4695

*/

4696

#define WM5100_DSP1_ZM_START_1_MASK 0x00FF /* DSP1_ZM_START - [7:0] */

4697

#define WM5100_DSP1_ZM_START_1_SHIFT 0 /* DSP1_ZM_START - [7:0] */

4698

#define WM5100_DSP1_ZM_START_1_WIDTH 8 /* DSP1_ZM_START - [7:0] */

4699

4700

/*

4701

* R20481 (0x5001) - DSP1 ZM 1

4702

*/

4703

#define WM5100_DSP1_ZM_START_MASK 0xFFFF /* DSP1_ZM_START - [15:0] */

4704

#define WM5100_DSP1_ZM_START_SHIFT 0 /* DSP1_ZM_START - [15:0] */

4705

#define WM5100_DSP1_ZM_START_WIDTH 16 /* DSP1_ZM_START - [15:0] */

4706

4707

/*

4708

* R20482 (0x5002) - DSP1 ZM 2

4709

*/

4710

#define WM5100_DSP1_ZM_1_1_MASK 0x00FF /* DSP1_ZM_1 - [7:0] */

4711

#define WM5100_DSP1_ZM_1_1_SHIFT 0 /* DSP1_ZM_1 - [7:0] */

4712

#define WM5100_DSP1_ZM_1_1_WIDTH 8 /* DSP1_ZM_1 - [7:0] */

4713

4714

/*

4715

* R20483 (0x5003) - DSP1 ZM 3

4716

*/

4717

#define WM5100_DSP1_ZM_1_MASK 0xFFFF /* DSP1_ZM_1 - [15:0] */

4718

#define WM5100_DSP1_ZM_1_SHIFT 0 /* DSP1_ZM_1 - [15:0] */

4719

#define WM5100_DSP1_ZM_1_WIDTH 16 /* DSP1_ZM_1 - [15:0] */

4720

4721

/*

4722

* R22524 (0x57FC) - DSP1 ZM 2044

4723

*/

4724

#define WM5100_DSP1_ZM_1022_1_MASK 0x00FF /* DSP1_ZM_1022 - [7:0] */

4725

#define WM5100_DSP1_ZM_1022_1_SHIFT 0 /* DSP1_ZM_1022 - [7:0] */

4726

#define WM5100_DSP1_ZM_1022_1_WIDTH 8 /* DSP1_ZM_1022 - [7:0] */

4727

4728

/*

4729

* R22525 (0x57FD) - DSP1 ZM 2045

4730

*/

4731

#define WM5100_DSP1_ZM_1022_MASK 0xFFFF /* DSP1_ZM_1022 - [15:0] */

4732

#define WM5100_DSP1_ZM_1022_SHIFT 0 /* DSP1_ZM_1022 - [15:0] */

4733

#define WM5100_DSP1_ZM_1022_WIDTH 16 /* DSP1_ZM_1022 - [15:0] */

4734

4735

/*

4736

* R22526 (0x57FE) - DSP1 ZM 2046

4737

*/

4738

#define WM5100_DSP1_ZM_END_1_MASK 0x00FF /* DSP1_ZM_END - [7:0] */

4739

#define WM5100_DSP1_ZM_END_1_SHIFT 0 /* DSP1_ZM_END - [7:0] */

4740

#define WM5100_DSP1_ZM_END_1_WIDTH 8 /* DSP1_ZM_END - [7:0] */

4741

4742

/*

4743

* R22527 (0x57FF) - DSP1 ZM 2047

4744

*/

4745

#define WM5100_DSP1_ZM_END_MASK 0xFFFF /* DSP1_ZM_END - [15:0] */

4746

#define WM5100_DSP1_ZM_END_SHIFT 0 /* DSP1_ZM_END - [15:0] */

4747

#define WM5100_DSP1_ZM_END_WIDTH 16 /* DSP1_ZM_END - [15:0] */

4748

4749

/*

4750

* R24576 (0x6000) - DSP2 DM 0

4751

*/

4752

#define WM5100_DSP2_DM_START_1_MASK 0x00FF /* DSP2_DM_START - [7:0] */

4753

#define WM5100_DSP2_DM_START_1_SHIFT 0 /* DSP2_DM_START - [7:0] */

4754

#define WM5100_DSP2_DM_START_1_WIDTH 8 /* DSP2_DM_START - [7:0] */

4755

4756

/*

4757

* R24577 (0x6001) - DSP2 DM 1

4758

*/

4759

#define WM5100_DSP2_DM_START_MASK 0xFFFF /* DSP2_DM_START - [15:0] */

4760

#define WM5100_DSP2_DM_START_SHIFT 0 /* DSP2_DM_START - [15:0] */

4761

#define WM5100_DSP2_DM_START_WIDTH 16 /* DSP2_DM_START - [15:0] */

4762

4763

/*

4764

* R24578 (0x6002) - DSP2 DM 2

4765

*/

4766

#define WM5100_DSP2_DM_1_1_MASK 0x00FF /* DSP2_DM_1 - [7:0] */

4767

#define WM5100_DSP2_DM_1_1_SHIFT 0 /* DSP2_DM_1 - [7:0] */

4768

#define WM5100_DSP2_DM_1_1_WIDTH 8 /* DSP2_DM_1 - [7:0] */

4769

4770

/*

4771

* R24579 (0x6003) - DSP2 DM 3

4772

*/

4773

#define WM5100_DSP2_DM_1_MASK 0xFFFF /* DSP2_DM_1 - [15:0] */

4774

#define WM5100_DSP2_DM_1_SHIFT 0 /* DSP2_DM_1 - [15:0] */

4775

#define WM5100_DSP2_DM_1_WIDTH 16 /* DSP2_DM_1 - [15:0] */

4776

4777

/*

4778

* R25084 (0x61FC) - DSP2 DM 508

4779

*/

4780

#define WM5100_DSP2_DM_254_1_MASK 0x00FF /* DSP2_DM_254 - [7:0] */

4781

#define WM5100_DSP2_DM_254_1_SHIFT 0 /* DSP2_DM_254 - [7:0] */

4782

#define WM5100_DSP2_DM_254_1_WIDTH 8 /* DSP2_DM_254 - [7:0] */

4783

4784

/*

4785

* R25085 (0x61FD) - DSP2 DM 509

4786

*/

4787

#define WM5100_DSP2_DM_254_MASK 0xFFFF /* DSP2_DM_254 - [15:0] */

4788

#define WM5100_DSP2_DM_254_SHIFT 0 /* DSP2_DM_254 - [15:0] */

4789

#define WM5100_DSP2_DM_254_WIDTH 16 /* DSP2_DM_254 - [15:0] */

4790

4791

/*

4792

* R25086 (0x61FE) - DSP2 DM 510

4793

*/

4794

#define WM5100_DSP2_DM_END_1_MASK 0x00FF /* DSP2_DM_END - [7:0] */

4795

#define WM5100_DSP2_DM_END_1_SHIFT 0 /* DSP2_DM_END - [7:0] */

4796

#define WM5100_DSP2_DM_END_1_WIDTH 8 /* DSP2_DM_END - [7:0] */

4797

4798

/*

4799

* R25087 (0x61FF) - DSP2 DM 511

4800

*/

4801

#define WM5100_DSP2_DM_END_MASK 0xFFFF /* DSP2_DM_END - [15:0] */

4802

#define WM5100_DSP2_DM_END_SHIFT 0 /* DSP2_DM_END - [15:0] */

4803

#define WM5100_DSP2_DM_END_WIDTH 16 /* DSP2_DM_END - [15:0] */

4804

4805

/*

4806

* R26624 (0x6800) - DSP2 PM 0

4807

*/

4808

#define WM5100_DSP2_PM_START_2_MASK 0x00FF /* DSP2_PM_START - [7:0] */

4809

#define WM5100_DSP2_PM_START_2_SHIFT 0 /* DSP2_PM_START - [7:0] */

4810

#define WM5100_DSP2_PM_START_2_WIDTH 8 /* DSP2_PM_START - [7:0] */

4811

4812

/*

4813

* R26625 (0x6801) - DSP2 PM 1

4814

*/

4815

#define WM5100_DSP2_PM_START_1_MASK 0xFFFF /* DSP2_PM_START - [15:0] */

4816

#define WM5100_DSP2_PM_START_1_SHIFT 0 /* DSP2_PM_START - [15:0] */

4817

#define WM5100_DSP2_PM_START_1_WIDTH 16 /* DSP2_PM_START - [15:0] */

4818

4819

/*

4820

* R26626 (0x6802) - DSP2 PM 2

4821

*/

4822

#define WM5100_DSP2_PM_START_MASK 0xFFFF /* DSP2_PM_START - [15:0] */

4823

#define WM5100_DSP2_PM_START_SHIFT 0 /* DSP2_PM_START - [15:0] */

4824

#define WM5100_DSP2_PM_START_WIDTH 16 /* DSP2_PM_START - [15:0] */

4825

4826

/*

4827

* R26627 (0x6803) - DSP2 PM 3

4828

*/

4829

#define WM5100_DSP2_PM_1_2_MASK 0x00FF /* DSP2_PM_1 - [7:0] */

4830

#define WM5100_DSP2_PM_1_2_SHIFT 0 /* DSP2_PM_1 - [7:0] */

4831

#define WM5100_DSP2_PM_1_2_WIDTH 8 /* DSP2_PM_1 - [7:0] */

4832

4833

/*

4834

* R26628 (0x6804) - DSP2 PM 4

4835

*/

4836

#define WM5100_DSP2_PM_1_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */

4837

#define WM5100_DSP2_PM_1_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */

4838

#define WM5100_DSP2_PM_1_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */

4839

4840

/*

4841

* R26629 (0x6805) - DSP2 PM 5

4842

*/

4843

#define WM5100_DSP2_PM_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */

4844

#define WM5100_DSP2_PM_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */

4845

#define WM5100_DSP2_PM_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */

4846

4847

/*

4848

* R28154 (0x6DFA) - DSP2 PM 1530

4849

*/

4850

#define WM5100_DSP2_PM_510_2_MASK 0x00FF /* DSP2_PM_510 - [7:0] */

4851

#define WM5100_DSP2_PM_510_2_SHIFT 0 /* DSP2_PM_510 - [7:0] */

4852

#define WM5100_DSP2_PM_510_2_WIDTH 8 /* DSP2_PM_510 - [7:0] */

4853

4854

/*

4855

* R28155 (0x6DFB) - DSP2 PM 1531

4856

*/

4857

#define WM5100_DSP2_PM_510_1_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */

4858

#define WM5100_DSP2_PM_510_1_SHIFT 0 /* DSP2_PM_510 - [15:0] */

4859

#define WM5100_DSP2_PM_510_1_WIDTH 16 /* DSP2_PM_510 - [15:0] */

4860

4861

/*

4862

* R28156 (0x6DFC) - DSP2 PM 1532

4863

*/

4864

#define WM5100_DSP2_PM_510_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */

4865

#define WM5100_DSP2_PM_510_SHIFT 0 /* DSP2_PM_510 - [15:0] */

4866

#define WM5100_DSP2_PM_510_WIDTH 16 /* DSP2_PM_510 - [15:0] */

4867

4868

/*

4869

* R28157 (0x6DFD) - DSP2 PM 1533

4870

*/

4871

#define WM5100_DSP2_PM_END_2_MASK 0x00FF /* DSP2_PM_END - [7:0] */

4872

#define WM5100_DSP2_PM_END_2_SHIFT 0 /* DSP2_PM_END - [7:0] */

4873

#define WM5100_DSP2_PM_END_2_WIDTH 8 /* DSP2_PM_END - [7:0] */

4874

4875

/*

4876

* R28158 (0x6DFE) - DSP2 PM 1534

4877

*/

4878

#define WM5100_DSP2_PM_END_1_MASK 0xFFFF /* DSP2_PM_END - [15:0] */

4879

#define WM5100_DSP2_PM_END_1_SHIFT 0 /* DSP2_PM_END - [15:0] */

4880

#define WM5100_DSP2_PM_END_1_WIDTH 16 /* DSP2_PM_END - [15:0] */

4881

4882

/*

4883

* R28159 (0x6DFF) - DSP2 PM 1535

4884

*/

4885

#define WM5100_DSP2_PM_END_MASK 0xFFFF /* DSP2_PM_END - [15:0] */

4886

#define WM5100_DSP2_PM_END_SHIFT 0 /* DSP2_PM_END - [15:0] */

4887

#define WM5100_DSP2_PM_END_WIDTH 16 /* DSP2_PM_END - [15:0] */

4888

4889

/*

4890

* R28672 (0x7000) - DSP2 ZM 0

4891

*/

4892

#define WM5100_DSP2_ZM_START_1_MASK 0x00FF /* DSP2_ZM_START - [7:0] */

4893

#define WM5100_DSP2_ZM_START_1_SHIFT 0 /* DSP2_ZM_START - [7:0] */

4894

#define WM5100_DSP2_ZM_START_1_WIDTH 8 /* DSP2_ZM_START - [7:0] */

4895

4896

/*

4897

* R28673 (0x7001) - DSP2 ZM 1

4898

*/

4899

#define WM5100_DSP2_ZM_START_MASK 0xFFFF /* DSP2_ZM_START - [15:0] */

4900

#define WM5100_DSP2_ZM_START_SHIFT 0 /* DSP2_ZM_START - [15:0] */

4901

#define WM5100_DSP2_ZM_START_WIDTH 16 /* DSP2_ZM_START - [15:0] */

4902

4903

/*

4904

* R28674 (0x7002) - DSP2 ZM 2

4905

*/

4906

#define WM5100_DSP2_ZM_1_1_MASK 0x00FF /* DSP2_ZM_1 - [7:0] */

4907

#define WM5100_DSP2_ZM_1_1_SHIFT 0 /* DSP2_ZM_1 - [7:0] */

4908

#define WM5100_DSP2_ZM_1_1_WIDTH 8 /* DSP2_ZM_1 - [7:0] */

4909

4910

/*

4911

* R28675 (0x7003) - DSP2 ZM 3

4912

*/

4913

#define WM5100_DSP2_ZM_1_MASK 0xFFFF /* DSP2_ZM_1 - [15:0] */

4914

#define WM5100_DSP2_ZM_1_SHIFT 0 /* DSP2_ZM_1 - [15:0] */

4915

#define WM5100_DSP2_ZM_1_WIDTH 16 /* DSP2_ZM_1 - [15:0] */

4916

4917

/*

4918

* R30716 (0x77FC) - DSP2 ZM 2044

4919

*/

4920

#define WM5100_DSP2_ZM_1022_1_MASK 0x00FF /* DSP2_ZM_1022 - [7:0] */

4921

#define WM5100_DSP2_ZM_1022_1_SHIFT 0 /* DSP2_ZM_1022 - [7:0] */

4922

#define WM5100_DSP2_ZM_1022_1_WIDTH 8 /* DSP2_ZM_1022 - [7:0] */

4923

4924

/*

4925

* R30717 (0x77FD) - DSP2 ZM 2045

4926

*/

4927

#define WM5100_DSP2_ZM_1022_MASK 0xFFFF /* DSP2_ZM_1022 - [15:0] */

4928

#define WM5100_DSP2_ZM_1022_SHIFT 0 /* DSP2_ZM_1022 - [15:0] */

4929

#define WM5100_DSP2_ZM_1022_WIDTH 16 /* DSP2_ZM_1022 - [15:0] */

4930

4931

/*

4932

* R30718 (0x77FE) - DSP2 ZM 2046

4933

*/

4934

#define WM5100_DSP2_ZM_END_1_MASK 0x00FF /* DSP2_ZM_END - [7:0] */

4935

#define WM5100_DSP2_ZM_END_1_SHIFT 0 /* DSP2_ZM_END - [7:0] */

4936

#define WM5100_DSP2_ZM_END_1_WIDTH 8 /* DSP2_ZM_END - [7:0] */

4937

4938

/*

4939

* R30719 (0x77FF) - DSP2 ZM 2047

4940

*/

4941

#define WM5100_DSP2_ZM_END_MASK 0xFFFF /* DSP2_ZM_END - [15:0] */

4942

#define WM5100_DSP2_ZM_END_SHIFT 0 /* DSP2_ZM_END - [15:0] */

4943

#define WM5100_DSP2_ZM_END_WIDTH 16 /* DSP2_ZM_END - [15:0] */

4944

4945

/*

4946

* R32768 (0x8000) - DSP3 DM 0

4947

*/

4948

#define WM5100_DSP3_DM_START_1_MASK 0x00FF /* DSP3_DM_START - [7:0] */

4949

#define WM5100_DSP3_DM_START_1_SHIFT 0 /* DSP3_DM_START - [7:0] */

4950

#define WM5100_DSP3_DM_START_1_WIDTH 8 /* DSP3_DM_START - [7:0] */

4951

4952

/*

4953

* R32769 (0x8001) - DSP3 DM 1

4954

*/

4955

#define WM5100_DSP3_DM_START_MASK 0xFFFF /* DSP3_DM_START - [15:0] */

4956

#define WM5100_DSP3_DM_START_SHIFT 0 /* DSP3_DM_START - [15:0] */

4957

#define WM5100_DSP3_DM_START_WIDTH 16 /* DSP3_DM_START - [15:0] */

4958

4959

/*

4960

* R32770 (0x8002) - DSP3 DM 2

4961

*/

4962

#define WM5100_DSP3_DM_1_1_MASK 0x00FF /* DSP3_DM_1 - [7:0] */

4963

#define WM5100_DSP3_DM_1_1_SHIFT 0 /* DSP3_DM_1 - [7:0] */

4964

#define WM5100_DSP3_DM_1_1_WIDTH 8 /* DSP3_DM_1 - [7:0] */

4965

4966

/*

4967

* R32771 (0x8003) - DSP3 DM 3

4968

*/

4969

#define WM5100_DSP3_DM_1_MASK 0xFFFF /* DSP3_DM_1 - [15:0] */

4970

#define WM5100_DSP3_DM_1_SHIFT 0 /* DSP3_DM_1 - [15:0] */

4971

#define WM5100_DSP3_DM_1_WIDTH 16 /* DSP3_DM_1 - [15:0] */

4972

4973

/*

4974

* R33276 (0x81FC) - DSP3 DM 508

4975

*/

4976

#define WM5100_DSP3_DM_254_1_MASK 0x00FF /* DSP3_DM_254 - [7:0] */

4977

#define WM5100_DSP3_DM_254_1_SHIFT 0 /* DSP3_DM_254 - [7:0] */

4978

#define WM5100_DSP3_DM_254_1_WIDTH 8 /* DSP3_DM_254 - [7:0] */

4979

4980

/*

4981

* R33277 (0x81FD) - DSP3 DM 509

4982

*/

4983

#define WM5100_DSP3_DM_254_MASK 0xFFFF /* DSP3_DM_254 - [15:0] */

4984

#define WM5100_DSP3_DM_254_SHIFT 0 /* DSP3_DM_254 - [15:0] */

4985

#define WM5100_DSP3_DM_254_WIDTH 16 /* DSP3_DM_254 - [15:0] */

4986

4987

/*

4988

* R33278 (0x81FE) - DSP3 DM 510

4989

*/

4990

#define WM5100_DSP3_DM_END_1_MASK 0x00FF /* DSP3_DM_END - [7:0] */

4991

#define WM5100_DSP3_DM_END_1_SHIFT 0 /* DSP3_DM_END - [7:0] */

4992

#define WM5100_DSP3_DM_END_1_WIDTH 8 /* DSP3_DM_END - [7:0] */

4993

4994

/*

4995

* R33279 (0x81FF) - DSP3 DM 511

4996

*/

4997

#define WM5100_DSP3_DM_END_MASK 0xFFFF /* DSP3_DM_END - [15:0] */

4998

#define WM5100_DSP3_DM_END_SHIFT 0 /* DSP3_DM_END - [15:0] */

4999

#define WM5100_DSP3_DM_END_WIDTH 16 /* DSP3_DM_END - [15:0] */

5000

5001

/*

5002

* R34816 (0x8800) - DSP3 PM 0

5003

*/

5004

#define WM5100_DSP3_PM_START_2_MASK 0x00FF /* DSP3_PM_START - [7:0] */

5005

#define WM5100_DSP3_PM_START_2_SHIFT 0 /* DSP3_PM_START - [7:0] */

5006

#define WM5100_DSP3_PM_START_2_WIDTH 8 /* DSP3_PM_START - [7:0] */

5007

5008

/*

5009

* R34817 (0x8801) - DSP3 PM 1

5010

*/

5011

#define WM5100_DSP3_PM_START_1_MASK 0xFFFF /* DSP3_PM_START - [15:0] */

5012

#define WM5100_DSP3_PM_START_1_SHIFT 0 /* DSP3_PM_START - [15:0] */

5013

#define WM5100_DSP3_PM_START_1_WIDTH 16 /* DSP3_PM_START - [15:0] */

5014

5015

/*

5016

* R34818 (0x8802) - DSP3 PM 2

5017

*/

5018

#define WM5100_DSP3_PM_START_MASK 0xFFFF /* DSP3_PM_START - [15:0] */

5019

#define WM5100_DSP3_PM_START_SHIFT 0 /* DSP3_PM_START - [15:0] */

5020

#define WM5100_DSP3_PM_START_WIDTH 16 /* DSP3_PM_START - [15:0] */

5021

5022

/*

5023

* R34819 (0x8803) - DSP3 PM 3

5024

*/

5025

#define WM5100_DSP3_PM_1_2_MASK 0x00FF /* DSP3_PM_1 - [7:0] */

5026

#define WM5100_DSP3_PM_1_2_SHIFT 0 /* DSP3_PM_1 - [7:0] */

5027

#define WM5100_DSP3_PM_1_2_WIDTH 8 /* DSP3_PM_1 - [7:0] */

5028

5029

/*

5030

* R34820 (0x8804) - DSP3 PM 4

5031

*/

5032

#define WM5100_DSP3_PM_1_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */

5033

#define WM5100_DSP3_PM_1_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */

5034

#define WM5100_DSP3_PM_1_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */

5035

5036

/*

5037

* R34821 (0x8805) - DSP3 PM 5

5038

*/

5039

#define WM5100_DSP3_PM_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */

5040

#define WM5100_DSP3_PM_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */

5041

#define WM5100_DSP3_PM_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */

5042

5043

/*

5044

* R36346 (0x8DFA) - DSP3 PM 1530

5045

*/

5046

#define WM5100_DSP3_PM_510_2_MASK 0x00FF /* DSP3_PM_510 - [7:0] */

5047

#define WM5100_DSP3_PM_510_2_SHIFT 0 /* DSP3_PM_510 - [7:0] */

5048

#define WM5100_DSP3_PM_510_2_WIDTH 8 /* DSP3_PM_510 - [7:0] */

5049

5050

/*

5051

* R36347 (0x8DFB) - DSP3 PM 1531

5052

*/

5053

#define WM5100_DSP3_PM_510_1_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */

5054

#define WM5100_DSP3_PM_510_1_SHIFT 0 /* DSP3_PM_510 - [15:0] */

5055

#define WM5100_DSP3_PM_510_1_WIDTH 16 /* DSP3_PM_510 - [15:0] */

5056

5057

/*

5058

* R36348 (0x8DFC) - DSP3 PM 1532

5059

*/

5060

#define WM5100_DSP3_PM_510_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */

5061

#define WM5100_DSP3_PM_510_SHIFT 0 /* DSP3_PM_510 - [15:0] */

5062

#define WM5100_DSP3_PM_510_WIDTH 16 /* DSP3_PM_510 - [15:0] */

5063

5064

/*

5065

* R36349 (0x8DFD) - DSP3 PM 1533

5066

*/

5067

#define WM5100_DSP3_PM_END_2_MASK 0x00FF /* DSP3_PM_END - [7:0] */

5068

#define WM5100_DSP3_PM_END_2_SHIFT 0 /* DSP3_PM_END - [7:0] */

5069

#define WM5100_DSP3_PM_END_2_WIDTH 8 /* DSP3_PM_END - [7:0] */

5070

5071

/*

5072

* R36350 (0x8DFE) - DSP3 PM 1534

5073

*/

5074

#define WM5100_DSP3_PM_END_1_MASK 0xFFFF /* DSP3_PM_END - [15:0] */

5075

#define WM5100_DSP3_PM_END_1_SHIFT 0 /* DSP3_PM_END - [15:0] */

5076

#define WM5100_DSP3_PM_END_1_WIDTH 16 /* DSP3_PM_END - [15:0] */

5077

5078

/*

5079

* R36351 (0x8DFF) - DSP3 PM 1535

5080

*/

5081

#define WM5100_DSP3_PM_END_MASK 0xFFFF /* DSP3_PM_END - [15:0] */

5082

#define WM5100_DSP3_PM_END_SHIFT 0 /* DSP3_PM_END - [15:0] */

5083

#define WM5100_DSP3_PM_END_WIDTH 16 /* DSP3_PM_END - [15:0] */

5084

5085

/*

5086

* R36864 (0x9000) - DSP3 ZM 0

5087

*/

5088

#define WM5100_DSP3_ZM_START_1_MASK 0x00FF /* DSP3_ZM_START - [7:0] */

5089

#define WM5100_DSP3_ZM_START_1_SHIFT 0 /* DSP3_ZM_START - [7:0] */

5090

#define WM5100_DSP3_ZM_START_1_WIDTH 8 /* DSP3_ZM_START - [7:0] */

5091

5092

/*

5093

* R36865 (0x9001) - DSP3 ZM 1

5094

*/

5095

#define WM5100_DSP3_ZM_START_MASK 0xFFFF /* DSP3_ZM_START - [15:0] */

5096

#define WM5100_DSP3_ZM_START_SHIFT 0 /* DSP3_ZM_START - [15:0] */

5097

#define WM5100_DSP3_ZM_START_WIDTH 16 /* DSP3_ZM_START - [15:0] */

5098

5099

/*

5100

* R36866 (0x9002) - DSP3 ZM 2

5101

*/

5102

#define WM5100_DSP3_ZM_1_1_MASK 0x00FF /* DSP3_ZM_1 - [7:0] */

5103

#define WM5100_DSP3_ZM_1_1_SHIFT 0 /* DSP3_ZM_1 - [7:0] */

5104

#define WM5100_DSP3_ZM_1_1_WIDTH 8 /* DSP3_ZM_1 - [7:0] */

5105

5106

/*

5107

* R36867 (0x9003) - DSP3 ZM 3

5108

*/

5109

#define WM5100_DSP3_ZM_1_MASK 0xFFFF /* DSP3_ZM_1 - [15:0] */

5110

#define WM5100_DSP3_ZM_1_SHIFT 0 /* DSP3_ZM_1 - [15:0] */

5111

#define WM5100_DSP3_ZM_1_WIDTH 16 /* DSP3_ZM_1 - [15:0] */

5112

5113

/*

5114

* R38908 (0x97FC) - DSP3 ZM 2044

5115

*/

5116

#define WM5100_DSP3_ZM_1022_1_MASK 0x00FF /* DSP3_ZM_1022 - [7:0] */

5117

#define WM5100_DSP3_ZM_1022_1_SHIFT 0 /* DSP3_ZM_1022 - [7:0] */

5118

#define WM5100_DSP3_ZM_1022_1_WIDTH 8 /* DSP3_ZM_1022 - [7:0] */

5119

5120

/*

5121

* R38909 (0x97FD) - DSP3 ZM 2045

5122

*/

5123

#define WM5100_DSP3_ZM_1022_MASK 0xFFFF /* DSP3_ZM_1022 - [15:0] */

5124

#define WM5100_DSP3_ZM_1022_SHIFT 0 /* DSP3_ZM_1022 - [15:0] */

5125

#define WM5100_DSP3_ZM_1022_WIDTH 16 /* DSP3_ZM_1022 - [15:0] */

5126

5127

/*

5128

* R38910 (0x97FE) - DSP3 ZM 2046

5129

*/

5130

#define WM5100_DSP3_ZM_END_1_MASK 0x00FF /* DSP3_ZM_END - [7:0] */

5131

#define WM5100_DSP3_ZM_END_1_SHIFT 0 /* DSP3_ZM_END - [7:0] */

5132

#define WM5100_DSP3_ZM_END_1_WIDTH 8 /* DSP3_ZM_END - [7:0] */

5133

5134

/*

5135

* R38911 (0x97FF) - DSP3 ZM 2047

5136

*/

5137

#define WM5100_DSP3_ZM_END_MASK 0xFFFF /* DSP3_ZM_END - [15:0] */

5138

#define WM5100_DSP3_ZM_END_SHIFT 0 /* DSP3_ZM_END - [15:0] */

5139

#define WM5100_DSP3_ZM_END_WIDTH 16 /* DSP3_ZM_END - [15:0] */

5140

5141

int wm5100_readable_register(struct snd_soc_codec *codec, unsigned int reg);

5142

int wm5100_volatile_register(struct snd_soc_codec *codec, unsigned int reg);

5143

5144

extern u16 wm5100_reg_defaults[WM5100_MAX_REGISTER + 1];

5145

5146

#endif